Semiconductor device having gate electrode layer with reduced height

Abstract

The present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. In an example, a semiconductor device (100) includes a substrate (130), a gate dielectric layer (140, 142), a gate electrode layer (144, 146), a doped source / drain region (168, 166), and a dielectric layer (182). The gate dielectric layer (140, 142) is on a surface of the substrate (130). The gate electrode layer (144, 146) is on the gate dielectric layer (140, 142). The doped source / drain region (168, 166) is in the substrate (130) and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate (130). The metallurgical junction extends to a first vertical distance (192) from the surface of the substrate (130). The gate electrode layer (144, 146) has a top surface at a second vertical distance (190) from the surface of the substrate (130). The second vertical distance (190) is equal to or less than half of the first vertical distance (192). The dielectric layer (182) is over the substrate (130) and the gate electrode layers (144, 146).

Description

Technical Field

[0001] The present disclosure relates generally, but not exclusively, to a semiconductor device having a gate electrode layer with reduced height. Background Art

[0002] Transistors, such as field effect transistors (FETs), are ubiquitous in today's world. Various electronic devices rely on transistors to achieve proper functionality. In some forms, transistors are constantly evolving and improving. With the continuous advancement of integrated circuit design and semiconductor manufacturing, there is also a search for improvements in semiconductor devices that include power FETs. Summary of the invention

[0003] The example described herein is a semiconductor device. The semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source / drain region, and a dielectric layer. The substrate includes a semiconductor material. The gate dielectric layer is on a surface of the substrate. The gate electrode layer is on the gate dielectric layer. The doped source / drain region is in the substrate. The doped source / drain region has a metallurgical junction in the substrate, and the metallurgical junction is parallel to a plane coplanar with the substrate surface. The metallurgical junction extends to a first vertical distance from the substrate surface. The gate electrode layer has a top surface away from the substrate. The top surface of the gate electrode layer is at a second vertical distance from the surface of the substrate. The second vertical distance is equal to or less than half of the first vertical distance. The dielectric layer is above the substrate and the gate electrode layer.

[0004] Another example is a method. A gate stack is formed on a gate dielectric layer disposed on a surface of a semiconductor substrate. The gate stack includes a gate electrode layer and a hard mask layer above the gate electrode layer. When the hard mask layer is above the gate electrode layer, a source / drain region is formed in the semiconductor substrate. Forming the source / drain region includes implanting a dopant into the semiconductor substrate. After implanting the dopant, a dielectric layer is formed above the gate electrode layer.

[0005] Another example is a semiconductor device. The semiconductor device includes a transistor and a dielectric layer above the transistor. The transistor includes a first source / drain region, a second source / drain region, and a gate electrode layer. The first source / drain region is in a semiconductor substrate, and the second source / drain region is in the semiconductor substrate. The gate electrode layer is above the semiconductor substrate and laterally between the first source / drain region and the second source / drain region. The top surface of the semiconductor material of the semiconductor substrate is located below the gate electrode layer. The first source / drain region has a metallurgical junction in the semiconductor substrate, and the metallurgical junction is parallel to a plane coplanar with the top surface. The metallurgical junction extends to a first vertical distance from the top surface. The gate electrode layer has a top surface away from the semiconductor substrate. The top surface of the gate electrode layer is a second vertical distance from the top surface. The second vertical distance is equal to or less than half of the first vertical distance.

[0006] The foregoing summary of the invention has been quite extensively summarized various features of the examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of these examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to understand the above features in detail, reference is made to the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1 is a cross-sectional view of an integrated circuit (IC) structure according to some examples.

[0009] Figure 2 , 3 , 4, 5, 6, 7, 8, 9, 10, 11 and 12 are according to some examples Figure 1 Cross-sectional views of an IC structure at various manufacturing stages.

[0010] The drawings and accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples shown in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements that are shared among the drawings. The drawings are drawn to clearly illustrate related elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0011] Various features will be described below with reference to the drawings. Other examples may include any arrangement of the described inclusion or exclusion aspects or features. The illustrated example may not have all aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example, even if not shown or not explicitly described as such. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0012] The present disclosure generally, but not exclusively, relates to a semiconductor device having a gate electrode layer with reduced height. In some examples, the semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, and a doped source / drain region. The gate dielectric layer is on the surface of the substrate, and the gate electrode layer is on the gate dielectric layer. The doped source / drain region is in the substrate. The doped source / drain region has a metallurgical junction in the substrate, and the metallurgical junction is parallel to a plane coplanar with the substrate surface. The metallurgical junction is at a certain depth from the substrate surface. The gate electrode layer has a top surface away from the substrate, and the top surface is at a certain height from the substrate surface. The dielectric layer is above the substrate and the gate electrode layer. In these examples, the height of the gate electrode layer can be reduced, which can reduce the sidewall surface area of ​​the gate electrode layer. For example, the height can be equal to or less than half the depth of the metallurgical junction. The reduced sidewall surface area can reduce parasitic capacitance, such as parasitic capacitance between a gate electrode layer and a contact electrically connected to a doped source / drain region, parasitic capacitance between a gate electrode layer and a doped source / drain region, and / or parasitic capacitance between a gate electrode layer and another gate electrode layer. With reduced parasitic capacitance, the operating speed of the semiconductor device can be increased due to a reduced resistance-capacitance (RC) time constant. Other benefits and advantages can also be achieved.

[0013] Various examples are then described.While a particular example may illustrate various aspects of the features generally described above, an example may incorporate any combination of the features generally described above (which are described in more detail in the examples below).

[0014] Figure 1 A cross-sectional view of an integrated circuit (IC) structure 100 is shown according to some examples. The IC includes the IC structure 100. The IC structure 100 includes a p-type field effect transistor (pFET) region 110 in which one or more types of pFETs may be formed. For example, the pFET region 110 may include a logic pFET 112 and a static random access memory (SRAM) pFET 114, such as Figure 1 As shown. IC structure 100 also includes an n-type field effect transistor (nFET) region 120, in which one or more types of nFETs may be formed. For example, nFET region 120 may include logic nFET 122 and SRAM nFET 124, such as Figure 1 The pFETs 112, 114 and the nFETs 122, 124 are each example semiconductor devices according to various examples.

[0015] The IC structure 100 includes a semiconductor substrate 130. The semiconductor substrate 130 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. The semiconductor substrate 130 may also include a support (or handle) substrate and an epitaxial layer epitaxially grown on the support substrate. In some examples, the semiconductor substrate 130 is or includes a silicon substrate (which may be singulated from a bulk silicon wafer at the end of semiconductor processing). In other examples, the semiconductor substrate 130 includes a silicon substrate with an epitaxial silicon layer grown thereon. The semiconductor substrate 130 is or includes a semiconductor material in and / or on which devices, such as the pFETs 112, 114 and the nFETs 122, 124, are formed. In some examples, the semiconductor material is or includes silicon (Si), and in other examples, the semiconductor material may be or include silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), etc., or a combination thereof. The semiconductor substrate 130 has a top major surface in and / or on which devices (eg, pFETs 112 , 114 and nFETs 122 , 124 ) are formed.

[0016] The isolation structure 132 is on the semiconductor substrate 130. In the example shown, the isolation structure 132 is a shallow trench isolation structure (STI) extending from the top major surface of the semiconductor substrate 130 into the semiconductor substrate 130. The isolation structure 132 may include, for example, a silicon nitride layer conformal along the surface of the corresponding trench in the semiconductor substrate 130 and a silicon oxide layer above and on the silicon nitride layer. In other examples, the isolation structure 132 may be a field oxide structure at the top major surface of the semiconductor substrate 130, such as a local oxidation of silicon (LOCOS) structure. The isolation structure 132 laterally defines an active area in the semiconductor substrate 130, in which the corresponding pFETs 112, 114 and nFETs 122, 124 are formed.

[0017] In the example shown, the semiconductor material of the semiconductor substrate 130 is p-doped. Therefore, an n-type doped well 134 is in the semiconductor substrate 130 in the pFET region 110. The concentration of the n-type dopant of the n-type dopant well 134 is greater than the concentration of the p-type dopant of the p-type doped semiconductor substrate 130. In some examples, the semiconductor substrate 130 is p-doped with a concentration of 1×10 14 cm -3 to 1×10 15 cm -3 The n-type dopant 134 is doped with a concentration of 1×10 15 cm -3 to 1×1016 cm -3 The semiconductor material of the semiconductor substrate 130 may be n-doped, and a p-type doped well may be in the semiconductor substrate 130 in the nFET region 120.

[0018] The respective gate dielectric layers 140 are above and on the top major surface of the semiconductor substrate 130 in the pFET region 110 in the active area, and the respective gate dielectric layers 142 are above and on the top major surface of the semiconductor substrate 130 in the nFET region 120 in the active area. The gate dielectric layers 140, 142 may be or include silicon oxide, silicon nitride, hafnium oxide, etc., or a combination thereof. In some examples, the gate dielectric layer 140 may be or include a material that is a high-k dielectric material, for example, having a dielectric constant (k) greater than the dielectric constant of silicon dioxide (SiO2). In some examples, the respective thicknesses of the gate dielectric layers 140, 142 may be between 10 angstroms and 100 angstroms. arrive within the range.

[0019] The respective gate electrode layer 144 is above and on the gate dielectric layer 140, and the respective gate electrode layer 146 is above and on the gate dielectric layer 142. In some examples, the gate electrode layers 144, 146 are or include silicon, such as doped polysilicon. In examples where the gate electrode layers 144, 146 are doped polysilicon, the gate electrode layer 144 may be p-doped with a concentration of 1×10 20 cm -3 to 5×10 21 cm -3 The gate electrode layer 146 may be n-doped with a concentration of 1×10 20 cm -3 to 5×10 21 cm -3 range of n-type dopants.

[0020] The first gate spacer 148 is on the sidewall surface of the gate electrode layer 144, and the first gate spacer 150 is on the sidewall surface of the gate electrode layer 146. The first gate spacers 148 and 150 may be or include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc., or a combination thereof.

[0021] A p-type lightly doped drain region (LDD) 160 is in the semiconductor substrate 130 in the active area in the pFET region 110, and an n-type LDD 162 is in the semiconductor substrate 130 in the active area in the nFET region 120. For each of the pFETs 112, 114, the first and second p-type LDDs 160 are on opposite lateral sides of the respective gate dielectric layer 140 and gate electrode layer 144. The p-type LDD 160 may be partially located below the gate dielectric layer 140 and gate electrode layer 144 and extend laterally away from the gate dielectric layer 140 and gate electrode layer 144 in the semiconductor substrate 130. For each of the nFETs 122, 124, the first and second n-type LDDs 162 are on opposite lateral sides of the respective gate dielectric layer 142 and gate electrode layer 146. The n-type LDD 162 may be partially located below the gate dielectric layer 142 and the gate electrode layer 146 and extend laterally away from the gate dielectric layer 142 and the gate electrode layer 146 in the semiconductor substrate 130. The p-type dopant concentration of the p-type LDD 160 is greater than the n-type dopant concentration of the n-type dopant of the n-type doping well 134, and the n-type dopant concentration of the n-type LDD 162 is greater than the p-type dopant concentration of the p-type dopant of the p-doped semiconductor substrate 130. In some examples, the p-type LDD 160 is p-doped with a concentration of 1×10 19 cm -3 to 1×10 21 cm -3 The n-type LDD 162 is doped with a p-type dopant in the range of 1×10 19 cm -3 to 1×10 21 cm -3 Other doping concentrations may be implemented.

[0022] The embedded stressors 164 are in the semiconductor substrate 130 in the active area in the pFET region 110. For each of the pFETs 112, 114, a pair of embedded stressors 164 are on opposite lateral sides of the respective gate dielectric layer 140 and gate electrode layer 144. The embedded stressors 164 extend laterally away from the gate dielectric layer 140 and gate electrode layer 144 in the semiconductor substrate 130. In some examples, such as when the semiconductor substrate 130 is silicon, the embedded stressors 164 may be silicon germanium (SiGe) or another stressor material epitaxially grown in a recess in the semiconductor substrate 130. The embedded stressors 164 are at least partially doped with p-type dopants, which may form p-type source / drain regions 168 of the pFETs 112, 114. In some examples, the p-type source / drain regions 168 are in the embedded stressors 164. In some examples, the p-type source / drain region 168 is partially within the embedded stressor 164 and extends below the embedded stressor 164 into the semiconductor material of the semiconductor substrate 130 , such as Figure 1 The p-type dopant concentration of the p-type source / drain region 168 is greater than the p-type dopant concentration of the p-type LDD 160 and greater than the n-type dopant concentration of the n-type dopant well 134. In some examples, the p-type source / drain region 168 is p-doped with a concentration of 1×10 20 cm -3 to 1×10 22 cm -3 Other doping concentrations may be implemented.

[0023] The n-type source / drain regions 166 are in the semiconductor substrate 130 in the active area in the nFET region 120. For each of the nFETs 122, 124, the first and second n-type source / drain regions 166 are on opposite lateral sides of the respective gate dielectric layer 142 and gate electrode layer 146. The n-type source / drain regions 166 extend laterally away from the gate dielectric layer 142 and gate electrode layer 146 in the semiconductor substrate 130. The concentration of the n-type dopant of the n-type source / drain regions 166 is greater than the concentration of the n-type dopant of the n-type LDD 162 and greater than the concentration of the p-type dopant of the p-doped semiconductor substrate 130. In some examples, the n-type source / drain regions 166 are doped with a concentration of 1×10 19 cm -3 to 1×10 22 cm -3 Other doping concentrations may be implemented.

[0024] The second gate spacers 170 are along the sidewall surfaces of the corresponding first gate spacers 148, and the second gate spacers 172 are along the sidewall surfaces of the corresponding first gate spacers 150. The first gate spacers 148 are disposed between the corresponding second gate spacers 170 and the gate electrode layer 144, and the first gate spacers 150 are disposed between the corresponding second gate spacers 172 and the gate electrode layer 146. The second gate spacers 170, 172 may be or include silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc., or a combination thereof.

[0025] As shown, metal-semiconductor compound 174 is on the respective top surface of gate electrode layer 144, and metal-semiconductor compound 176 is on the respective top surface of gate electrode layer 146. When gate electrode layers 144, 146 are or include semiconductor materials, such as silicon (e.g., polysilicon), metal-semiconductor compounds 174, 176 may be formed on the top surface of gate electrode layers 144, 146. Metal-semiconductor compounds 174, 176 may be silicides (e.g., TiSix, CoSix, NiSix, PtSix), germanides, etc. In some examples, metal-semiconductor compounds 174, 176 may be omitted. Metal-semiconductor compound 178 is on the respective top surface of embedded stressor 164, and metal-semiconductor compound 180 is located on the top major surface of semiconductor substrate 130 at n-type source / drain region 166. The metal-semiconductor compounds 178 , 180 may be silicides (eg, TiSix, CoSix, NiSix, PtSix), germanides, etc. In some examples, the metal-semiconductor compounds 178 , 180 may be omitted.

[0026] Conformal dielectric layer 182 is over semiconductor substrate 130. Conformal dielectric layer 182 is conformally over and on isolation structure 132, metal-semiconductor compounds 174, 176, 178, 180, first gate spacers 148, 150, and second gate spacers 170, 172. Conformal dielectric layer 182 may be or include silicon nitride, silicon oxynitride, or another dielectric layer. Conformal dielectric layer 182 may be a stressor layer, an etch stop layer, etc. Dielectric layer 184 is over and on conformal dielectric layer 182. Dielectric layer 184 may be or include silicon oxide, silicon nitride, etc. Dielectric layer 184 may be a pre-metal dielectric (PMD), an inter-layer dielectric (ILD), etc.

[0027] Contacts 186 extend through dielectric layer 184 and conformal dielectric layer 182 and contact respective metal-semiconductor compounds 174, 176, 178, 180. Contacts 186 may each include one or more barriers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conformally disposed in respective openings through dielectric layer 184 and conformal dielectric layer 182, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) over and / or on the barriers and / or adhesion layers.

[0028] In general, as shown, each pFET 112, 114 includes a gate structure, wherein the gate structure includes a gate dielectric layer 140, a gate electrode layer 144 on the gate dielectric layer 140, and a metal-semiconductor compound 174 on the gate electrode layer 144. Each pFET 112, 114 includes a gate spacer structure on opposite sides of the gate structure, wherein the gate spacer structure includes a first gate spacer 148 on a sidewall surface of the gate structure and a second gate spacer 170 on the first gate spacer 148. Each pFET 112, 114 includes a first p-type LDD 160 and a second p-type LDD 160 in a semiconductor substrate 130. The first and second p-type LDDs 160 are on opposite lateral sides of the gate structure, and a channel region in the semiconductor substrate 130 located below the gate structure (e.g., below the gate dielectric layer 140) is between the first p-type LDD 160 and the second p-type LDD 160. In addition, each pFET 112, 114 includes a first p-type source / drain region 168 and a second p-type source / drain region 168. Each p-type source / drain region 168 is at least partially in a corresponding embedded stressor 164 and may extend below the embedded stressor 164 into the semiconductor substrate 130. Each p-type source / drain region 168 extends laterally from a corresponding p-type LDD 160 away from the gate structure. Thus, the p-type LDD 160 and the channel region are disposed between the p-type source / drain regions 168.

[0029] In general, as shown, each nFET 122, 124 includes a gate structure, wherein the gate structure includes a gate dielectric layer 142, a gate electrode layer 146 on the gate dielectric layer 142, and a metal-semiconductor compound 176 on the gate electrode layer 146. Each nFET 122, 124 includes a gate spacer structure on opposite sides of the gate structure, wherein the gate spacer structure includes a first gate spacer 150 on a sidewall surface of the gate structure and a second gate spacer 172 on the first gate spacer 150. Each nFET 122, 124 includes a first n-type LDD 162 and a second n-type LDD 162 in a semiconductor substrate 130. The first and second n-type LDDs 162 are on opposite lateral sides of the gate structure, and a channel region in the semiconductor substrate 130 located below the gate structure (e.g., below the gate dielectric layer 142) is between the first n-type LDD 162 and the second n-type LDD 162. In addition, each nFET 122, 124 includes a first n-type source / drain region 166 and a second n-type source / drain region 166. Each n-type source / drain region 166 extends laterally away from the gate structure from a corresponding n-type LDD 162. Thus, the n-type LDD 162 and the channel region are disposed between the n-type source / drain regions 166.

[0030] For any of the pFETs 112, 114 and the nFETs 122, 124, the gate electrode layer 144, 146 has a top surface at a first dimension 190 (e.g., vertical distance or height) away from the top major surface of the semiconductor substrate 130 (e.g., located below and / or interfacing with the gate dielectric layer 140, 142). The p-type source / drain region 168 or the n-type source / drain region 166 each partially forms a metallurgical (e.g., pn) junction at a second dimension 192 (e.g., vertical distance or depth) from the top major surface of the semiconductor substrate 130, the metallurgical junction being parallel to a plane coplanar with the top major surface of the semiconductor substrate 130. For the pFETs 112, 114, the p-type source / drain region 168 is a p-type region of the metallurgical junction, and the n-type doped well 134 is an n-type region of the metallurgical junction. A metallurgical junction is formed, wherein the p-type dopant concentration of the p-type source / drain region 168 becomes equal to the n-type dopant concentration in the n-type doped well 134. For the nFETs 122, 124, the n-type source / drain region 166 is the n-type region of the metallurgical junction, and the p-type doped semiconductor material of the semiconductor substrate 130 is the p-type region of the metallurgical junction. A metallurgical junction is formed, wherein the n-type dopant concentration of the n-type source / drain region 166 becomes equal to the p-type dopant concentration in the p-type doped semiconductor material of the semiconductor substrate 130.

[0031] In some examples, the first dimension 190 is smaller than the second dimension 192. More specifically, in some examples, the first dimension 190 is equal to or less than half of the second dimension 192. In some examples, the first dimension 190 is equal to or less than and more specifically equal to or less than In some examples, the second dimension 192 is equal to or greater than and more specifically equal to or greater than

[0032] According to some examples, the gate electrode layers 144, 146 may be implanted with dopants (e.g., p-type or n-type dopants) that are implanted to form corresponding source / drain regions of the pFETs 112, 114 or nFETs 122, 124. During the implantation, a hard mask layer is above and on the gate electrode layers 144, 146, which may be thick enough to prevent a significant amount of dopants from being implanted into the channel region of the semiconductor substrate 130 below the gate electrode layers 144, 146, even though, for example, the first dimension 190 is less than the depth (e.g., the second dimension 192) at which the source / drain regions are formed. Therefore, according to some examples, the channel region below the gate structure is substantially free of dopants (e.g., to exclude possible diffusion of dopants) that are implanted into the gate electrode layers 144, 146 of the gate structure and into the semiconductor substrate 130 to form corresponding source / drain regions.

[0033] Some examples may achieve a reduced first dimension 190 for a given technology node while maintaining other dimensions (e.g., metallurgical junction depth of source / drain regions, distance between LDD regions below the gate structure (which may be referred to as channel length), lateral width dimension of the gate structure) for a given technology node, which may result in reduced parasitic capacitance. Parasitic capacitance may form between sidewall surfaces of the gate electrode layers 144, 146 and the contacts 186, between sidewall surfaces of the gate electrode layers 144, 146 and the source / drain regions, and between sidewall surfaces of the gate electrode layers 144, 146 and sidewall surfaces of another gate electrode layer 144, 146. Reducing the dimensions (e.g., height) of the gate electrode layers 144, 146 reduces the area of ​​the sidewall surfaces of the gate electrode layers 144, 146 used to form parasitic capacitance. Since parasitic capacitance is generally a function of the area of ​​the sidewall surfaces of the gate electrode layers 144, 146, the parasitic capacitance can be reduced by reducing the area of ​​the sidewall surfaces of the gate electrode layers 144, 146. Reducing parasitic capacitance reduces the resistance-capacitance (RC) time constant, which can allow the speed of the FET to be increased.

[0034] In some examples, the gate electrode layers 144, 146 have a third dimension 194 (e.g., a lateral dimension or width) between opposing sidewall surfaces of the gate electrode layers 144, 146. The third dimension 194 is the width of the gate electrode layers 144, 146, which is parallel to the channel length direction of the channel region located below the gate electrode layers 144, 146. In some examples, the third dimension 194 can be in the range of 25nm to 1μm. According to some examples, the first dimension 190 is less than or equal to twice the third dimension 194, and more specifically in the range of one to two times the third dimension 194. As shown subsequently, the first dimension 190 can be reduced for a given technology node, while the third dimension 194 is maintained for a given technology node, which can be determined by the channel length requirements of the given technology node, such as the target channel length.

[0035] In some examples, the gate spacer structure (e.g., including the first gate spacers 148, 150 and the second gate spacers 170, 172) on the sidewall surface of the gate structure has a fourth dimension 196 (e.g., a lateral dimension or width) in a lateral direction perpendicular to the sidewall surface of the gate structure. The fourth dimension 196 may be the cumulative thickness of the first gate spacers 148, 150 and the second gate spacers 170, 172 in the lateral direction. The thickness of the first gate spacers 148, 150 may be in the range of 2nm to 10nm, and the thickness of the second gate spacers 170, 172 may be in the range of 3nm to 40nm. In some examples, the fourth dimension 196 may be in the range of 5nm to 50nm. According to some examples, the first dimension 190 is less than or equal to the fourth dimension 196, for example, in the range of half to one times the fourth dimension 196.

[0036] In some examples, the p-type source / drain region 168 or the n-type source / drain region 166 each partially forms a metallurgical (e.g., pn) junction at a fifth dimension 198 (e.g., lateral distance) from the closest sidewall surface of the gate structure, the metallurgical junction being perpendicular to a plane coplanar with the top major surface of the semiconductor substrate 130. As described above, for the pFETs 112, 114, the p-type source / drain region 168 is the p-type region of the metallurgical junction, and the n-type doped well 134 is the n-type region of the metallurgical junction. For the nFETs 122, 124, the n-type source / drain region 166 is the n-type region of the metallurgical junction, and the p-type doped semiconductor material of the semiconductor substrate 130 is the p-type region of the metallurgical junction. The p-type source / drain region 168 or the n-type source / drain region 166 does not extend below the corresponding gate structure (eg, the gate dielectric layer 140, 142 and the gate electrode layer 144, 146). In some examples, the fifth dimension 198 is arrive As described later, an intermediate gate spacer may be implemented to control a fifth dimension 198 independently of the fourth dimension 196. Based on the size of the intermediate gate spacer, the source / drain region may occupy below the corresponding gate spacer structure. Thus, an example may implement a fifth dimension 198 such that a target channel length for a given technology node may be implemented. This may allow a target channel leakage for a technology node to be achieved.

[0037] Figures 2 to 12 Showing some examples Figure 1 The IC structure 100 is a cross-sectional view at various stages of manufacture. Figure 2 , an isolation structure 132 is formed in the semiconductor substrate 130. In the example shown, a corresponding trench is formed in the semiconductor substrate 130, for example, by using appropriate photolithography and etching processes. A dielectric liner, such as silicon nitride, is conformally deposited in the trench, such as by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. An isolation material, such as silicon oxide, is deposited on the dielectric liner in the trench, such as by flowable CVD (FCVD), etc. A planarization process, such as chemical mechanical polishing (CMP), can remove any dielectric liner and isolation material on the top major surface of the semiconductor substrate 130. In other examples, a LOCOS process can be used to form the isolation structure 132.

[0038] An n-type doped well 134 is formed in the semiconductor substrate 130 in the pFET region 110. The n-type doped well 134 may be formed by masking the nFET region 120 and implanting n-type dopants into the semiconductor substrate 130 in the pFET region 110. The nFET region 120 may be masked using a photoresist patterned to remain over the nFET region 120. After implantation, the photoresist may be removed, for example, by ashing.

[0039] A blanket gate dielectric layer 202 is formed over and on the top major surface of semiconductor substrate 130. Blanket gate dielectric layer 202 may be any material described above for gate dielectric layers 140, 142. Blanket gate dielectric layer 202 may be formed by oxidation or deposited by CVD, ALD, or the like.

[0040] A blanket gate electrode layer 204 is formed over and on the blanket gate dielectric layer 202. In some examples, the blanket gate electrode layer 204 is a silicon layer (e.g., polysilicon). In such examples, the silicon blanket gate electrode layer 204 is doped with a substantially uniform concentration of a p-type dopant. In some such examples, the silicon blanket gate electrode layer 204 is p-doped in situ during deposition, and in other such examples, the silicon blanket gate electrode layer 204 is blanket implanted with a p-type dopant after deposition. After deposition and / or implantation, the concentration of the p-type dopant in the silicon blanket gate electrode layer 204 may be between 1×10 19 cm-3 to 1×10 21 cm -3 In other examples, different materials may be used.

[0041] refer to Figure 3 , the blanket gate electrode layer 204 in the nFET region 120 is implanted with an n-type dopant to form a differentially doped blanket gate electrode layer 302. A photoresist 304 is formed over the pFET region 110. The photoresist 304 is deposited (e.g., by spin coating) on ​​or over the blanket gate electrode layer 204 and patterned using photolithography. The photoresist 304 is patterned to remain in the pFET region 110. With the patterned photoresist 304 used as a mask, an implantation is performed to implant an n-type dopant into the blanket gate electrode layer 204 to form the differentially doped blanket gate electrode layer 302. After the implantation, the photoresist 304 is removed, for example, by ashing. The concentration of the n-type dopant in the differentially doped blanket gate electrode layer 302 in the nFET region 120 is greater than the concentration of the p-type dopant in the differentially doped blanket gate electrode layer 302 in the pFET region 110. After implantation, the concentration of n-type dopant in the differentially doped blanket gate electrode layer 302 in the nFET region 120 may be between 5×10 19 cm -3 to 5×10 21 cm -3 Continuing with the example where blanket gate electrode layer 204 is silicon and p-doped, the implant may implant n-type dopants into differentially doped blanket gate electrode layer 302 at a concentration greater than the concentration of p-type dopants with which the silicon blanket gate electrode layer 204 is doped. Thus, in such examples, the silicon differentially doped blanket gate electrode layer 302 is p-doped in pFET region 110 and n-doped in nFET region 120.

[0042] refer to Figure 4 , a blanket hard mask layer 402 is formed on the differentially doped blanket gate electrode layer 302. The blanket hard mask layer 402 may be or include silicon nitride, silicon oxynitride, etc. or a combination thereof. The blanket hard mask layer 402 may be deposited by CVD, physical vapor deposition (PVD), etc. The blanket hard mask layer 402 may be formed with arrive Thickness within the range.

[0043] refer to Figure 5, the blanket hard mask layer 402, the differentially doped blanket gate electrode layer 302, and the blanket gate dielectric layer 202 are patterned into hard mask layers 506, 508, intermediate gate electrode layers 502, 504, and gate dielectric layers 140, 142. The patterning may be performed using photolithography and etching processes. The intermediate gate electrode layer 502 is subsequently formed into the gate electrode layer 144, and the intermediate gate electrode layer 504 is subsequently formed into the gate electrode layer 146. Continuing with the example where the blanket gate electrode layer 204 is silicon, according to Figure 2 and 3 The middle gate electrode layer 502 is p-doped, and the middle gate electrode layer 504 is n-doped.

[0044] The first gate spacers 148, 150 are formed along the sidewall surfaces of the intermediate gate electrode layers 502, 504 and the hard mask layers 506, 508. The first gate spacers 148, 150 may be formed by oxidizing the sidewall surfaces or by conformally depositing a material layer of the first gate spacers 148, 150 over the semiconductor substrate 130 and anisotropically etching the layer so that the first gate spacers 148, 150 remain.

[0045] The p-type LDD 160 and the n-type LDD 162 are formed in the semiconductor substrate 130. The p-type LDD 160 may be formed by masking the nFET region 120 and implanting a p-type dopant into the semiconductor substrate 130 in the pFET region 110. The nFET region 120 may be masked by using a photoresist patterned to remain over the nFET region 120. After implantation, the photoresist may be removed, for example, by ashing. The n-type LDD 162 may be formed by masking the pFET region 110 and implanting an n-type dopant into the semiconductor substrate 130 in the nFET region 120. The pFET region 110 may be masked by using a photoresist patterned to remain over the pFET region 110. After implantation, the photoresist may be removed, for example, by ashing.

[0046] refer to Figure 6 , a conformal hard mask layer 602 is formed over the semiconductor substrate 130 in the nFET region 120. The conformal hard mask layer 602 is conformally located above and on the top major surface of the semiconductor substrate 130 in the nFET region 120, along the sidewalls and top surface of the first gate spacer 150, and above and on the top surface of the hard mask layer 508. The conformal hard mask layer 602 may be or include silicon nitride, silicon oxynitride, etc. or a combination thereof. The conformal hard mask layer 602 may be formed by conformally depositing and patterning the conformal hard mask layer 602. The conformal hard mask layer 602 may be deposited by CVD, plasma enhanced CVD (PECVD), ALD, etc. The conformal hard mask layer 602 may be patterned using photolithography and etching processes.

[0047] The stressor recess 604 is formed in the semiconductor substrate 130 in the pFET region 110. The stressor recess 604 is etched in the semiconductor substrate 130 at the location where the embedded stressor is to be formed. The stressor recess 604 can be formed using any suitable etching process, which can be a wet or dry etching process. As shown, the etching process can be anisotropic and selective to (e.g., preferentially etches) a crystal plane of the semiconductor substrate 130.

[0048] refer to Figure 7 , the embedded stressor 164 is formed in the stressor recess 604. The embedded stressor 164 may be formed using a selective epitaxial growth process. The embedded stressor 164 may be formed using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), or another epitaxial process. After forming the embedded stressor 164, the conformal hard mask layer 602 is removed. The conformal hard mask layer 602 may be removed by an etching process, which may be a wet or dry etching process.

[0049] refer to Figure 8, forming the intermediate second gate spacers 802, 804 along the sidewall surfaces of the first gate spacers 148, 150. The intermediate second gate spacers 802, 804 have a sixth dimension 806 in a lateral direction perpendicular to the sidewall surfaces of the gate structure (e.g., the intermediate gate electrode layers 502, 504). In addition, in combination, the first gate spacers 148 and the intermediate second gate spacers 802 have a seventh dimension 808 (e.g., a lateral dimension or width) in a lateral direction perpendicular to the sidewall surfaces of the gate structure (e.g., the intermediate gate electrode layers 502, 504). The intermediate second gate spacers 802, 804 may be or include silicon nitride, silicon oxynitride, etc. or a combination thereof. The intermediate second gate spacers 802, 804 may be formed by conformally depositing and anisotropically etching a material layer of the intermediate second gate spacers 802, 804. The layers of the intermediate second gate spacers 802, 804 may be deposited by CVD, PECVD, ALD, etc. In some examples, the material of the intermediate second gate spacers 802, 804 is the same as the material of the hard mask layers 506, 508. The layer of the intermediate second gate spacers 802, 804 may be deposited to have a thickness as the sixth dimension 806. The anisotropic etch may be a reactive ion etch (RIE) or the like. The combined size (e.g., total thickness) of the intermediate gate electrode layers 502, 504 and the hard mask layers 506, 508 allows the sixth dimension 806 to be large enough to achieve targeted alignment of the source / drain regions, as described in more detail later.

[0050] refer to Fig. 9 , implantation is performed in the nFET region 120 to form n-type source / drain regions 166 in the semiconductor material of the semiconductor substrate 130 laterally proximate to the intermediate gate electrode layer 504 (which corresponds to the gate electrode layer 146). A photoresist 902 is formed over the pFET region 110. The photoresist 902 is deposited (e.g., by spin coating) on ​​or over the semiconductor substrate 130 and patterned using photolithography. The photoresist 902 is patterned to remain in the pFET region 110. With the patterned photoresist 902 used as a mask, an implantation is performed to implant n-type dopants into the semiconductor substrate 130 to form the n-type source / drain regions 166. After the implantation, the n-type source / drain regions 166 have the concentration of the n-type dopant described above. After the implantation, the photoresist 902 is removed, for example, by ashing.

[0051] exist Fig. 9 During the implantation of , the hard mask layer 508 is above and on the intermediate gate electrode layer 504 . Fig. 9 The implantation of n-type dopants (to form n-type source / drain regions 166) may also implant n-type dopants into the intermediate gate electrode layer 504 and the hard mask layer 508. Implanting n-type dopants into the intermediate gate electrode layer 504 produces the gate electrode layer 146, which is formed as described above with respect to Figure 1 The n-type dopant concentrations described are used for doping. Fig. 9 During the implantation of the gate dielectric layer 142, the intermediate gate electrode layer 504, and the hard mask layer 508, the stacks each including the gate dielectric layer 142, the intermediate gate electrode layer 504, and the hard mask layer 508 have an eighth dimension 904 from the top major surface of the semiconductor substrate 130 to the top surface of the corresponding stack (e.g., the top surface of the hard mask layer 508). The eighth dimension 904 is equal to or greater than the second dimension 192. Therefore, the stack (e.g., including the hard mask layer 508) has a sufficient eighth dimension 904 (e.g., thickness) to block or prevent Fig. 9 The implanted dopants reach the semiconductor substrate 130 in the channel region below the corresponding stack. The channel region below the gate electrode layer 146 and the gate dielectric layer 142 may thus be substantially free of dopants for forming the n-type source / drain region 166. For example, if Fig. 9 If, for example, a shorter stack of only the intermediate gate electrode layer 504 and the gate dielectric layer 142 is implemented during the implantation (e.g., without a hard mask layer), the channel region may be implanted with dopants, rendering the nFETs 122, 124 inoperable, and / or the metallurgical junctions may not be deep enough (e.g., if the implantation energy is reduced to avoid implanting the channel region), resulting in the nFETs 122, 124 having undesirable characteristics, such as higher resistance, lower on-state current, etc.

[0052] In addition, when the middle second gate spacer 804 has a sixth size 806, performing Fig. 9 The implantation may be performed perpendicular to the top main surface of the semiconductor substrate 130 or at a small angle (e.g., within 5°) relative to the top main surface of the semiconductor substrate 130. Therefore, the metallurgical (e.g., pn) junction of the n-type source / drain region 166 perpendicular to the plane coplanar with the top main surface of the semiconductor substrate 130 is generally aligned with or corresponds to the outer sidewall surface of the corresponding middle second gate spacer 804 to control the reference Figure 1 Due to the eighth dimension 904 of the stack, the middle second gate spacer 804 can be formed with a sixth dimension 806, which can be Fig. 9 The sixth dimension 806 may allow the n-type source / drain regions 166 to be formed so that the n-type source / drain regions 166 do not extend under the gate structure (e.g., far enough away from the gate structure), which may allow a target channel length and channel leakage for a given technology node to be achieved. For example, if Fig. 9 If a shorter stack (e.g., without a hard mask layer) is implemented during implantation of, for example, only the intermediate gate electrode layer 504 and the gate dielectric layer 142, the stack may not be able to support spacers of sufficient thickness to obtain the target channel length, which may result in undesirable channel leakage, etc.

[0053] refer to Fig.10 , implantation is performed in the pFET region 110 to form p-type source / drain regions 168 in the embedded stressor 164 and in the semiconductor material of the semiconductor substrate 130 laterally proximate to the intermediate gate electrode layer 502 (which corresponds to the gate electrode layer 144). A photoresist 1002 is formed over the nFET region 120. The photoresist 1002 is deposited (e.g., by spin coating) on ​​or over the semiconductor substrate 130 and patterned using photolithography. The photoresist 1002 is patterned to remain in the nFET region 120. With the patterned photoresist 1002 used as a mask, an implantation is performed to implant a p-type dopant into the semiconductor substrate 130 to form the p-type source / drain region 168. After the implantation, the p-type source / drain region 168 has the concentration of the p-type dopant described above. After the implantation, the photoresist 1002 is removed, for example, by ashing.

[0054] exist Fig.10 During the implantation of , the hard mask layer 506 is above and on the intermediate gate electrode layer 502 . Fig.10 The implantation of p-type dopants (to form p-type source / drain regions 168) may also implant p-type dopants into the intermediate gate electrode layer 502 and the hard mask layer 506. Implanting p-type dopants into the intermediate gate electrode layer 502 produces the gate electrode layer 144, which is formed as described above with respect to Figure 1 The p-type dopant concentration is described. Fig.10 During the implantation of the gate dielectric layer 140, the stacks each including the gate dielectric layer 140, the intermediate gate electrode layer 502, and the hard mask layer 506 have an eighth dimension 904 from the top major surface of the semiconductor substrate 130 to the top surface of the corresponding stack (e.g., the top surface of the hard mask layer 506), as described above. Therefore, the stack (e.g., including the hard mask layer 506) has a sufficient eighth dimension 904 (e.g., thickness) to block or prevent Fig.10 The implanted dopants reach the semiconductor substrate 130 in the channel region below the corresponding stack. The channel region below the gate electrode layer 144 and the gate dielectric layer 140 may therefore be substantially free of dopants for forming the p-type source / drain region 168. For example, if Fig.10 If, for example, a shorter stack of only the intermediate gate electrode layer 502 and the gate dielectric layer 140 is implemented during the implantation (e.g., without a hard mask layer), the channel region may be implanted with dopants, rendering the pFETs 112, 114 inoperable, and / or the metallurgical junctions may not be deep enough (e.g., if the implantation energy is reduced to avoid implanting the channel region), resulting in the pFETs 112, 114 having undesirable characteristics, such as higher resistance, lower on-state current, etc.

[0055] Additionally, when the middle second gate spacer 802 has a sixth dimension 806 (eg, a lateral dimension or width), performing Fig.10 The implantation may be performed perpendicular to the top main surface of the semiconductor substrate 130 or at a small angle (e.g., within 5°) relative to the top main surface of the semiconductor substrate 130. Therefore, the metallurgical (e.g., pn) junction of the p-type source / drain region 168 perpendicular to the plane coplanar with the top main surface of the semiconductor substrate 130 is generally aligned with or corresponds to the outer sidewall surface of the corresponding middle second gate spacer 802 to control the reference Figure 1 Due to the eighth dimension 904 of the stack, the middle second gate spacer 802 can be formed with a sixth dimension 806, which can be Fig.10 The sixth dimension 806 may allow the p-type source / drain region 168 to be formed so that the p-type source / drain region 168 does not extend under the gate structure (e.g., is far enough away from the gate structure), which may allow a target channel length and channel leakage for a given technology node to be achieved. For example, if Fig.10 If a shorter stack (e.g., without a hard mask layer) is implemented during implantation of, for example, only the intermediate gate electrode layer 502 and the gate dielectric layer 140, the stack may not be able to support spacers of sufficient thickness to obtain a target channel length, which may result in undesirable channel leakage, etc.

[0056] refer to Fig.11 , removing the hard mask layers 506, 508. The hard mask layers 506, 508 may be removed using an etch that is selective to (eg, preferentially etches) the hard mask layers 506, 508, and the etch may be a wet etch.

[0057] In some examples, the intermediate second gate spacers 802, 804 are thinned (e.g., reduced in lateral thickness) to produce the second gate spacers 170, 172. The thinning may be performed by a timed isotropic etch that is selective (e.g., preferentially etches) to the material of the intermediate second gate spacers 802, 804. The intermediate second gate spacers 802, 804 are thinned to obtain the second gate spacers 170, 172 such that the reference Figure 1 The depicted fourth dimension 196 is less than the seventh dimension 808. Thinning of the intermediate gate spacers 802, 804 may produce thinner gate spacer structures that may be somewhat decoupled from the sixth dimension 806, which may be implemented to allow source / drain regions to be formed without extending under respective gate structures.

[0058] In some examples, the middle second gate spacers 802, 804 are removed, and the second gate spacers 170, 172 are subsequently formed. In some examples, the middle second gate spacers 802, 804 are removed simultaneously with the hard mask layers 506, 508 (e.g., by the same etching). The middle second gate spacers 802, 804 may be removed by etching that is selective (e.g., preferentially etching) to the material of the middle second gate spacers 802, 804 (and the material of the hard mask layers 506, 508). The second gate spacers 170, 172 may be formed by conformally depositing and anisotropically etching a material layer of the second gate spacers 170, 172. The layers of the second gate spacers 170, 172 may be deposited by CVD, PECVD, ALD, etc. The layers of the second gate spacers 170, 172 may be deposited to have a thickness less than the sixth dimension 806. The anisotropic etching may be RIE, etc. The thinner second gate spacers 170, 172 (e.g., relative to the intermediate second gate spacers 802, 804) cause the fourth dimension 196 to be smaller than the seventh dimension 808. Removal of the intermediate gate spacers 802, 804 and subsequent formation of the second gate spacers 170, 172 can produce a thinner gate spacer structure that can be decoupled to some extent from the sixth dimension 806, which can be implemented to allow source / drain regions to be formed without extending under the respective gate structures.

[0059] refer to Fig.12 , forming metal-semiconductor compounds 174, 176, 178, 180. The metal-semiconductor compounds 174, 176, 178, 180 may be formed by depositing a metal (e.g., Ti, Co, Ni, Pt) over the semiconductor substrate 130 (e.g., by CVD, PVD, etc.). The metal is reacted with a semiconductor material, such as a semiconductor material (e.g., silicon) of the semiconductor substrate 130 and a semiconductor material (e.g., silicon, such as polysilicon) of the gate electrode layers 144, 146. An annealing process may be used to react the metal with the semiconductor material. Any unreacted metal may be removed, such as by an etch that is selective (e.g., preferentially etches) to the metal.

[0060] refer to Figure 1 , a conformal dielectric layer 182 is formed over the semiconductor substrate 130. The conformal dielectric layer 182 may be conformally deposited using CVD, PECVD, ALD, etc. Subsequently, a dielectric layer 184 is formed over the conformal dielectric layer 182. The dielectric layer 184 may be deposited using any suitable deposition process, such as PECVD, etc. The dielectric layer 184 may be planarized, for example, by CMP.

[0061] Contacts 186 are formed through dielectric layer 184 and conformal dielectric layer 182 to the respective metal-semiconductor compounds 174, 176, 178, 180. Appropriate photolithography and etching processes may be used to form respective openings through dielectric layer 184 and conformal dielectric layer 182 to metal-semiconductor compounds 174, 176, 178, 180. The metal of contact 186 is deposited in the openings through dielectric layer 184 and conformal dielectric layer 182. The metal may be deposited using an appropriate deposition process, such as CVD, PVD, etc. Any excess metal may be removed, for example, by CMP and / or by patterning using photolithography and etching processes.

[0062] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations could be made thereto without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate comprising a semiconductor material; a gate dielectric layer disposed on a surface of the substrate; a gate electrode layer located on the gate dielectric layer; doped source / drain regions in the substrate, wherein: The doped source / drain regions have metallurgical junctions in the substrate, the metallurgical junctions being parallel to a plane coplanar with the surface of the substrate; the metallurgical junction extending to a first vertical distance from the surface of the substrate; The gate electrode layer has a top surface away from the substrate; The top surface of the gate electrode layer is a second vertical distance from the surface of the substrate; and The second vertical distance is equal to or less than half of the first vertical distance; as well as A dielectric layer is located above the substrate and the gate electrode layer. 2 . The semiconductor device according to claim 1 , further comprising a silicide, wherein the gate electrode layer comprises a polysilicon layer on the gate dielectric layer, and the silicide is on the polysilicon layer.

3. The semiconductor device according to claim 1, wherein the second vertical distance is less than 600 angstroms. 4 . The semiconductor device of claim 1 , wherein a portion of the semiconductor material beneath the gate dielectric layer is substantially free of dopants of the doped source / drain regions.

5. The semiconductor device of claim 1, wherein the gate dielectric layer has a dielectric constant greater than that of silicon dioxide (SiO2). 6 . The semiconductor device of claim 1 , wherein the gate electrode layer has a lateral dimension parallel to a channel length direction starting from the doped source / drain region, and the second vertical distance is less than or equal to twice the lateral dimension.

7. The semiconductor device according to claim 1, further comprising a gate spacer structure along a sidewall surface of the gate electrode layer, wherein: The gate spacer structure has a lateral width in a direction perpendicular to the sidewall surface of the gate electrode layer; and The second vertical distance is less than or equal to the lateral width.

8. The semiconductor device of claim 1, wherein the doped source / drain regions are in the semiconductor material of the substrate, and the metallurgical junction is in the semiconductor material of the substrate.

9. The semiconductor device according to claim 1, wherein: The substrate comprises a stressor material; and The doped source / drain regions are in the stressor material and the semiconductor material of the substrate, and the metallurgical junction is in the semiconductor material of the substrate.

10. A method comprising: forming a gate stack on a gate dielectric layer disposed on a surface of a semiconductor substrate, the gate stack comprising a gate electrode layer and a hard mask layer over the gate electrode layer; When the hard mask layer is above the gate electrode layer, forming a source / drain region in the semiconductor substrate, the forming of the source / drain region comprising implanting a dopant into the semiconductor substrate; as well as After implanting the dopant, a dielectric layer is formed over the gate electrode layer.

11. The method according to claim 10, further comprising: Before forming the source / drain regions, forming gate spacers along sidewall surfaces of the gate stack; as well as After forming the source / drain regions, the lateral thickness of the gate spacers is reduced.

12. The method according to claim 10, further comprising: Before forming the source / drain region, forming a first gate spacer along the sidewall surface of the gate stack; After forming the source / drain regions, removing the first gate spacer; as well as A second gate spacer is formed along the sidewall surface of the gate stack.

13. The method of claim 10, wherein: The semiconductor substrate includes a semiconductor material, at least a portion of the semiconductor material being below the gate dielectric layer and the gate stack; and Implanting the dopant into the semiconductor substrate includes implanting the dopant into the semiconductor material of the semiconductor substrate laterally proximate to the gate stack.

14. The method of claim 10, further comprising forming a stressor material in the semiconductor substrate laterally proximate to the gate stack, wherein: The semiconductor substrate includes a semiconductor material, at least a portion of the semiconductor material being below the gate dielectric layer and the gate stack; and Implanting the dopant into the semiconductor substrate includes implanting the dopant into the stressor material and the semiconductor material of the semiconductor substrate laterally proximate to the gate stack.

15. The method of claim 10, further comprising removing the hard mask layer before forming the dielectric layer. 16 . The method of claim 15 , wherein removing the hard mask layer comprises removing gate spacers along sidewall surfaces of the gate stack.

17. The method of claim 10, wherein after forming the dielectric layer: The source / drain region has a metallurgical junction in the semiconductor substrate, wherein the metallurgical junction is parallel to a plane coplanar with the surface of the semiconductor substrate; the metallurgical junction extending to a first vertical distance from the surface of the semiconductor substrate; The gate electrode layer has a top surface away from the semiconductor substrate; The top surface of the gate electrode layer is a second vertical distance from the surface of the semiconductor substrate; and The second vertical distance is equal to or less than half of the first vertical distance.

18. A semiconductor device comprising: A transistor comprising: a first source / drain region located in the semiconductor substrate; a second source / drain region located in the semiconductor substrate; as well as a gate electrode layer located above the semiconductor substrate and laterally between the first source / drain region and the second source / drain region, wherein: A top surface of the semiconductor material of the semiconductor substrate is located below the gate electrode layer; The first source / drain region has a metallurgical junction in the semiconductor substrate, the metallurgical junction being parallel to a plane coplanar with the top surface; the metallurgical junction extending to a first vertical distance from the top surface; The gate electrode layer has a top surface away from the semiconductor substrate; The top surface of the gate electrode layer is a second vertical distance from the top surface; and The second vertical distance is equal to or less than half of the first vertical distance; as well as A dielectric layer is located above the transistor.

19. The semiconductor device according to claim 18, wherein the second vertical distance is less than 600 angstroms. 20 . The semiconductor device of claim 18 , wherein the gate electrode layer has a lateral distance parallel to a direction from the first source / drain region to the second source / drain region, and the second vertical distance is less than or equal to twice the lateral distance.

21. The semiconductor device according to claim 18, further comprising a gate spacer along a sidewall surface of the gate electrode layer, wherein: The gate spacer has a lateral width in a direction perpendicular to the sidewall surface of the gate electrode layer; and The second vertical distance is less than or equal to the lateral width. 22 . The semiconductor device according to claim 18 , further comprising silicide, wherein the gate electrode layer comprises a polysilicon layer above the semiconductor substrate, and the silicide is on the polysilicon layer.

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