Solar cell, preparation method thereof and solar cell module

Abstract

The invention discloses a solar cell and a preparation method thereof and a solar cell module, the solar cell comprises a semiconductor substrate, the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the semiconductor substrate, the first surface of the semiconductor substrate is sequentially provided with a tunneling oxide layer, a doped polycrystalline silicon layer, a first transparent conductive layer and a first electrode, and the second surface of the semiconductor substrate is provided with a second transparent conductive layer; the second surface of the semiconductor substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous silicon layer, a second transparent conductive layer and a second electrode, the thickness of the doped polycrystalline silicon layer is less than 10nm, and the doped polycrystalline silicon layer is subjected to hydrogen passivation. The thickness of the ultra-thin doped polycrystalline silicon layer is smaller than 10 nm, the parasitic absorption problem of the doped polycrystalline silicon layer can be remarkably reduced, meanwhile, the carrier transmission resistance is reduced, meanwhile, the doped polycrystalline silicon layer is subjected to hydrogen passivation, the passivation effect of the ultra-thin doped polycrystalline silicon layer can be remarkably improved, and the service life of the ultra-thin doped polycrystalline silicon layer is prolonged. The passivation effect of the doped polycrystalline silicon layer does not need to be improved by increasing the thickness of the doped polycrystalline silicon layer.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a solar cell module. Background Art

[0002] The pursuit of more efficient solar cells has always been a hot topic in industry research. As a highly efficient passivation structure, tunneling oxide passivation contact has been widely studied in recent years. It consists of an ultra-thin silicon oxide layer and a doped polysilicon layer, which can significantly reduce the recombination of electrons and holes, thereby improving the performance of solar cells.

[0003] In order to achieve a better passivation effect, the traditional tunneling oxide passivation contact cell often has a thicker polysilicon film layer, which causes the incident light, especially short-wavelength light, to be absorbed by the polysilicon layer, reducing the effective amount of light reaching the silicon substrate, thereby reducing the short-circuit current of the solar cell. Ultra-thin polysilicon layers can significantly reduce parasitic absorption problems while reducing carrier transfer resistance, but correspondingly, their passivation effect is greatly weakened. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present application is to propose a solar cell and a method for preparing the same and a solar cell module. The thickness of the ultra-thin doped polysilicon layer of the present application is less than 10 nm, which can significantly reduce the parasitic absorption problem of the doped polysilicon layer and reduce the carrier transfer resistance. At the same time, the doped polysilicon layer is hydrogen passivated, which can significantly improve the passivation effect of the ultra-thin doped polysilicon layer. There is no need to increase the thickness of the doped polysilicon layer to improve its passivation effect, thereby avoiding the parasitic absorption problem caused by the excessive thickness of the doped polysilicon layer. As a result, the short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF of the solar cell can be improved at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0005] In a first aspect of the present application, a solar cell is provided. According to an embodiment of the present application, the solar cell comprises:

[0006] A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other along a thickness direction thereof;

[0007] A tunneling oxide layer, wherein the tunneling oxide layer is disposed on the first surface of the semiconductor substrate;

[0008] A doped polysilicon layer, wherein the doped polysilicon layer is disposed on a side of the tunneling oxide layer away from the semiconductor substrate, the thickness of the doped polysilicon layer is less than 10 nm, and the doped polysilicon layer is hydrogen passivated;

[0009] a first transparent conductive layer, wherein the first transparent conductive layer is disposed on a side of the doped polysilicon layer away from the semiconductor substrate;

[0010] a first electrode, the first electrode being disposed on a side of the first transparent conductive layer away from the doped polysilicon layer;

[0011] An intrinsic amorphous silicon layer, wherein the intrinsic amorphous silicon layer is disposed on the second surface of the semiconductor substrate;

[0012] A doped amorphous silicon layer, wherein the doped amorphous silicon layer is disposed on a side of the intrinsic amorphous silicon layer away from the semiconductor substrate;

[0013] a second transparent conductive layer, wherein the second transparent conductive layer is disposed on a side of the doped amorphous silicon layer away from the semiconductor substrate;

[0014] The second electrode is arranged on a side of the second transparent conductive layer away from the semiconductor substrate.

[0015] According to the solar cell of the above embodiment of the present application, the thickness of the ultra-thin doped polysilicon layer of the present application is less than 10nm, which can significantly reduce the parasitic absorption problem of the doped polysilicon layer and reduce the carrier transfer resistance. At the same time, the doped polysilicon layer is hydrogen passivated, which can significantly improve the passivation effect of the ultra-thin doped polysilicon layer. It is not necessary to increase the thickness of the doped polysilicon layer to improve its passivation effect, thereby avoiding the parasitic absorption problem caused by the excessive thickness of the doped polysilicon layer. As a result, the short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF of the solar cell can be improved at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0016] In addition, the solar cell according to the above embodiment of the present application may also have the following additional technical features:

[0017] In some embodiments of the present application, the concentration of hydrogen atoms in the doped polysilicon layer is 10 18 ~10 22 / cm 3 .

[0018] In some embodiments of the present application, the concentration of hydrogen atoms in the doped polysilicon layer is 10 19 ~10 21 / cm 3 .

[0019] In some embodiments of the present application, the thickness of the doped polysilicon layer is 2 nm to 6 nm.

[0020] In some embodiments of the present application, the solar cell further includes: an aluminum oxide layer, wherein the aluminum oxide layer is disposed between the doped polysilicon layer and the first transparent conductive layer.

[0021] In some embodiments of the present application, the thickness of the aluminum oxide layer is 1 nm to 20 nm.

[0022] In some embodiments of the present application, the solar cell further includes: a silicon nitride layer, wherein the silicon nitride layer is disposed between the doped polysilicon layer and the first transparent conductive layer.

[0023] In some embodiments of the present application, the thickness of the silicon nitride layer is 10 nm to 120 nm.

[0024] In some embodiments of the present application, the solar cell also includes: an aluminum oxide layer and a silicon nitride layer, the aluminum oxide layer is arranged on a side of the doped polysilicon layer away from the semiconductor substrate, the silicon nitride layer is arranged on a side of the aluminum oxide layer away from the semiconductor substrate, and the first transparent conductive layer is arranged on a side of the silicon nitride layer away from the semiconductor substrate.

[0025] In some embodiments of the present application, the thickness of the aluminum oxide layer is 1 nm to 20 nm, the thickness of the silicon nitride layer is 10 nm to 120 nm, and the total thickness of the aluminum oxide layer and the silicon nitride layer is 10 nm to 140 nm.

[0026] In some embodiments of the present application, the semiconductor substrate is an N-type silicon wafer, the doped polysilicon layer is an N-type doped polysilicon layer, and the doped amorphous silicon layer is a P-type doped amorphous silicon layer; or, the semiconductor substrate is an N-type silicon wafer, the doped polysilicon layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer is an N-type doped amorphous silicon layer; or, the semiconductor substrate is a P-type silicon wafer, the doped polysilicon layer is an N-type doped polysilicon layer, and the doped amorphous silicon layer is a P-type doped amorphous silicon layer; or, the semiconductor substrate is a P-type silicon wafer, the doped polysilicon layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer is an N-type doped amorphous silicon layer.

[0027] In some embodiments of the present application, the thickness of the tunneling oxide layer is 1.2nm~2.5nm; and / or the thickness of the intrinsic amorphous silicon layer is 2nm~30nm; and / or the thickness of the doped amorphous silicon layer is 2nm~60nm; and / or the thickness of the first transparent conductive layer and the second transparent conductive layer are 10nm~200nm respectively.

[0028] In a second aspect of the present application, a method for preparing a solar cell is provided. According to an embodiment of the present application, the method comprises:

[0029] Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other along a thickness direction thereof;

[0030] forming a tunneling oxide layer and a doped polysilicon layer in sequence on the first surface;

[0031] Performing hydrogen implantation on the surface of the doped polysilicon layer;

[0032] sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface;

[0033] forming a first transparent conductive layer on the surface of the doped polysilicon layer after hydrogen injection, and forming a second transparent conductive layer on the surface of the doped amorphous silicon layer;

[0034] A first electrode is formed on the surface of the first transparent conductive layer, and a second electrode is formed on the surface of the second transparent conductive layer.

[0035] According to the method for preparing a solar cell of the above embodiment of the present application, hydrogen is injected into the ultra-thin doped polysilicon layer by performing hydrogen injection treatment on the surface of the ultra-thin doped polysilicon layer, passivating the defect centers in the doped polysilicon layer, and reducing the interface state density, which can significantly improve the passivation effect of the ultra-thin doped polysilicon layer, and there is no need to increase the thickness of the doped polysilicon layer to improve its passivation effect, thereby avoiding the parasitic absorption problem caused by the excessive thickness of the doped polysilicon layer. As a result, the short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF of the solar cell can be improved at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0036] In addition, the method according to the above embodiment of the present application may also have the following additional technical features:

[0037] In some embodiments of the present application, the above method further includes: forming an aluminum oxide layer and / or a silicon nitride layer on the surface of the doped polysilicon layer, and annealing to achieve hydrogen injection into the doped polysilicon layer.

[0038] In some embodiments of the present application, the annealing temperature is 300° C. to 700° C., and the annealing time is 10 min to 60 min.

[0039] In some embodiments of the present application, hydrogen plasma is used to perform hydrogen implantation on the surface of the doped polysilicon layer.

[0040] In some embodiments of the present application, the flow rate of the hydrogen plasma is 500 sccm to 3000 sccm, and the processing time is 30 s to 300 s.

[0041] In the third aspect of the present application, a solar cell assembly is provided. According to an embodiment of the present application, the solar cell assembly has the solar cell of the above embodiment. As a result, the solar cell in the solar cell assembly has a high short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0042] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0044] Figure 1 is a schematic structural diagram of a solar cell according to some embodiments of the present application;

[0045] Figure 2 is a schematic structural diagram of a solar cell according to some further embodiments of the present application;

[0046] Figure 3 is a schematic structural diagram of a solar cell according to some other embodiments of the present application;

[0047] Figure 4 is a schematic structural diagram of a solar cell according to some other embodiments of the present application;

[0048] Figure 5 The present invention is a flow chart of a method for preparing a solar cell according to some embodiments of the present application.

[0049] Reference numerals:

[0050] 101-semiconductor substrate, 101-1-first surface, 101-2-second surface, 102-tunneling oxide layer, 103-doped polysilicon layer, 104-first transparent conductive layer, 105-first electrode, 106-intrinsic amorphous silicon layer, 107-doped amorphous silicon layer, 108-second transparent conductive layer, 109-second electrode, 110-aluminum oxide layer, 111-silicon nitride layer. DETAILED DESCRIPTION

[0051] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0052] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred elements must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present application.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0054] In this application, unless otherwise clearly specified and limited, the terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0055] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0056] In a first aspect of the present application, a solar cell is provided. According to an embodiment of the present application, referring to the attached Figure 1The solar cell comprises: a semiconductor substrate 101, the semiconductor substrate 101 comprises a first surface 101-1 and a second surface 101-2 arranged opposite to each other along the thickness direction thereof; a tunneling oxide layer 102, the tunneling oxide layer 102 is arranged on the first surface 101-1 of the semiconductor substrate 101; a doped polysilicon layer 103, the doped polysilicon layer 103 is arranged on a side of the tunneling oxide layer 102 away from the semiconductor substrate 101, the thickness of the doped polysilicon layer 103 is less than 10nm, and the doped polysilicon layer 103 is hydrogen passivated; a first transparent conductive layer 104, the first transparent conductive layer 104 is arranged on a side of the doped polysilicon layer 103 away from the semiconductor substrate 101 one side; a first electrode 105, the first electrode 105 is arranged on a side of the first transparent conductive layer 104 away from the doped polysilicon layer 103; an intrinsic amorphous silicon layer 106, the intrinsic amorphous silicon layer 106 is arranged on the second side 101-2 of the semiconductor substrate 101; a doped amorphous silicon layer 107, the doped amorphous silicon layer 107 is arranged on a side of the intrinsic amorphous silicon layer 106 away from the semiconductor substrate 101; a second transparent conductive layer 108, the second transparent conductive layer 108 is arranged on a side of the doped amorphous silicon layer 107 away from the semiconductor substrate 101; a second electrode 109, the second electrode 109 is arranged on a side of the second transparent conductive layer 108 away from the semiconductor substrate 101.

[0057] The beneficial effects that can be achieved by the solar cell proposed in this application are described in detail below:

[0058] The present application combines the advantages of TOPCon cells and HJT cells to provide a hybrid solar cell with a TOPCon tunneling structure on the light-facing side and a HJT structure on the backlight side, so that the cell surface obtains a stable passivation effect. The thickness of the ultra-thin doped polysilicon layer 103 of the present application is less than 10nm, which can significantly reduce the parasitic absorption problem of the doped polysilicon layer 103 and reduce the carrier transfer resistance. At the same time, the doped polysilicon layer 103 is hydrogen passivated, which can significantly improve the passivation effect of the ultra-thin doped polysilicon layer 103. There is no need to increase the thickness of the doped polysilicon layer 103 to improve its passivation effect, avoiding the parasitic absorption problem caused by the excessive thickness of the doped polysilicon layer 103. As a result, the short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF of the solar cell can be improved at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0059] According to some specific embodiments of the present application, the concentration of hydrogen atoms in the doped polysilicon layer 103 is 10 18 ~10 22 / cm 3 , for example, it can be 10 18 / cm 3 , 10 19 / cm 3 , 10 20 / cm3 , 10 21 / cm 3 , 10 22 / cm 3 , thereby further ensuring the passivation of defect centers in the doped polysilicon layer 103, reducing the interface state density, and further ensuring the passivation effect of the ultra-thin doped polysilicon layer 103. Preferably, the hydrogen atom concentration in the doped polysilicon layer 103 is 10 19 ~10 21 / cm 3 .

[0060] In the embodiment of the present application, secondary ion mass spectrometry (SIMS) may be used to test the concentration of hydrogen atoms in the doped polysilicon layer 103 .

[0061] According to some further specific embodiments of the present application, the thickness of the doped polysilicon layer 103 is 2nm to 6nm, for example, it can be 2nm, 3nm, 4nm, 5nm, 6nm, etc., thereby further ensuring that the thickness of the doped polysilicon layer 103 is small, thereby further reducing the parasitic absorption problem of the doped polysilicon layer 103 and reducing the carrier transfer resistance.

[0062] According to some other specific embodiments of the present application, refer to the attached Figure 2 The solar cell further comprises: an aluminum oxide layer 110, wherein the aluminum oxide layer 110 is disposed between the doped polysilicon layer 103 and the first transparent conductive layer 104, thereby effectively injecting hydrogen into the ultra-thin doped polysilicon layer 103, passivating the defect centers of the doped polysilicon layer 103, reducing the interface state density, and improving the performance of the solar cell.

[0063] According to some other specific embodiments of the present application, the thickness of the aluminum oxide layer 110 is 1nm to 20nm, for example, it can be 1nm, 2nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, etc., thereby further ensuring that hydrogen is injected into the ultra-thin doped polysilicon layer 103, passivating the defect centers of the doped polysilicon layer 103, reducing the interface state density, and improving the performance of the solar cell.

[0064] According to some other specific embodiments of the present application, refer to the attached Figure 3 The above-mentioned solar cell also includes: a silicon nitride layer 111, and the silicon nitride layer 110 is arranged between the doped polysilicon layer 103 and the first transparent conductive layer 104, thereby effectively injecting hydrogen into the ultra-thin doped polysilicon layer 103, passivating the defect centers of the doped polysilicon layer 103, reducing the interface state density, and improving the performance of the solar cell.

[0065] According to some other specific embodiments of the present application, the thickness of the silicon nitride layer 111 is 10nm to 120nm, for example, it can be 10nm, 20nm, 40nm, 60nm, 80nm, 100nm, 120nm, etc., thereby further ensuring that hydrogen is injected into the ultra-thin doped polysilicon layer 103, passivating the defect centers of the doped polysilicon layer 103, reducing the interface state density, and improving the performance of the solar cell.

[0066] According to some other specific embodiments of the present application, refer to the attached Figure 4 The solar cell further comprises: an aluminum oxide layer 110 and a silicon nitride layer 111, wherein the aluminum oxide layer 110 is arranged on a side of the doped polysilicon layer 103 away from the semiconductor substrate 101, the silicon nitride layer 111 is arranged on a side of the aluminum oxide layer 110 away from the semiconductor substrate 101, and the first transparent conductive layer 104 is arranged on a side of the silicon nitride layer 111 away from the semiconductor substrate 101, thereby effectively injecting hydrogen into the ultra-thin doped polysilicon layer 103, passivating the defect centers of the doped polysilicon layer 103, reducing the interface state density, and improving the performance of the solar cell.

[0067] According to some other specific embodiments of the present application, the thickness of the aluminum oxide layer 110 is 1nm to 20nm, the thickness of the silicon nitride layer 111 is 10nm to 120nm, and the total thickness of the aluminum oxide layer 110 and the silicon nitride layer 111 is 10nm to 140nm. Thus, it is further ensured that hydrogen is injected into the ultra-thin doped polysilicon layer 103, the defect centers of the doped polysilicon layer 103 are passivated, the interface state density is reduced, and the efficiency of the solar cell is improved.

[0068] According to some specific embodiments of the present application, the semiconductor substrate 101 is an N-type silicon wafer, the doped polycrystalline silicon layer 103 is an N-type doped polycrystalline silicon layer (for example, a phosphorus-doped polycrystalline silicon layer), and the doped amorphous silicon layer 107 is a P-type doped amorphous silicon layer (for example, a boron-doped amorphous silicon layer). Therefore, a PN junction is formed between the semiconductor substrate 101 and the doped amorphous silicon layer 107, that is, the PN junction is arranged on the back side of the battery.

[0069] According to some further specific embodiments of the present application, the semiconductor substrate 101 is an N-type silicon wafer, the doped polysilicon layer 103 is a P-type doped polysilicon layer (for example, a boron-doped polysilicon layer), and the doped amorphous silicon layer 107 is an N-type doped amorphous silicon layer (for example, a phosphorus-doped amorphous silicon layer). Therefore, a PN junction is formed between the semiconductor substrate 101 and the doped polysilicon layer 103, that is, the PN junction is arranged on the front side of the battery.

[0070] According to some other specific embodiments of the present application, the semiconductor substrate 101 is a P-type silicon wafer, the doped polysilicon layer 103 is an N-type doped polysilicon layer (for example, a phosphorus-doped polysilicon layer), and the doped amorphous silicon layer 107 is a P-type doped amorphous silicon layer (for example, a boron-doped amorphous silicon layer). Therefore, a PN junction is formed between the semiconductor substrate 101 and the doped polysilicon layer 103, that is, the PN junction is arranged on the front side of the battery.

[0071] According to some other specific embodiments of the present application, the semiconductor substrate 101 is a P-type silicon wafer, the doped polycrystalline silicon layer 103 is a P-type doped polycrystalline silicon layer (for example, a boron-doped polycrystalline silicon layer), and the doped amorphous silicon layer 107 is an N-type doped amorphous silicon layer (for example, a phosphorus-doped amorphous silicon layer). Therefore, a PN junction is formed between the semiconductor substrate 101 and the doped amorphous silicon layer 107, that is, the PN junction is arranged on the back side of the battery.

[0072] According to some specific embodiments of the present application, the thickness of the tunnel oxide layer 102 is 1.2nm to 2.5nm, for example, it can be 1.2nm, 1.5nm, 1.8nm, 2.0nm, 2.2nm, 2.5nm, etc., thereby further ensuring its good passivation contact effect and further ensuring the multi-sub tunneling effect. The specific type of the above-mentioned tunnel oxide layer 102 is not particularly limited, and those skilled in the art can select it according to actual needs. As some specific examples, the tunnel oxide layer 102 is a tunnel SiO 2 layer.

[0073] According to some other specific embodiments of the present application, the thickness of the intrinsic amorphous silicon layer 106 is 2nm to 30nm, for example, it can be 2nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, etc., thereby further ensuring the passivation contact effect of the intrinsic amorphous silicon layer 106 on the semiconductor substrate 101.

[0074] According to some further specific embodiments of the present application, the thickness of the doped amorphous silicon layer 107 is 2 nm to 60 nm, for example, 2 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, etc.

[0075] According to some further specific embodiments of the present application, the thickness of the first transparent conductive layer 104 and the second transparent conductive layer 108 are respectively 10 nm to 200 nm, for example, they may be 10 nm, 20 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0076] In the embodiments of the present invention, the materials of the first transparent conductive layer 104 and the second transparent conductive layer 108 are not particularly limited. As some specific examples, the materials of the first transparent conductive layer 104 and the second transparent conductive layer 108 respectively include at least one of transparent conductive materials such as ZnO, InO, SnO, etc., and these materials may be doped with at least one of elements such as Ga, Sn, Mo, Ce, F, W, Al, etc.

[0077] In an embodiment of the present invention, the materials of the first electrode 105 (e.g., gate line electrode) and the second electrode 109 (e.g., gate line electrode) are not particularly limited. As some specific examples, the materials of the first electrode 105 and the second electrode 109 include, but are not limited to, at least one of silver, copper, gold, aluminum, tin, titanium, silver-containing compounds, copper-containing compounds, gold-containing compounds, aluminum-containing compounds, tin-containing compounds and titanium-containing compounds.

[0078] In an embodiment of the present invention, the material of the semiconductor substrate 101 can be selected from materials such as silicon (Si), germanium (Ge) or gallium arsenide (GaAs), preferably silicon. In terms of conductivity type, the semiconductor substrate 101 can be an N-type semiconductor substrate 101 or a P-type semiconductor substrate 101, preferably an N-type silicon wafer. It should be noted that the first surface 101-1 of the semiconductor substrate 101 is on the light-facing side of the solar cell, and the second surface 101-2 of the semiconductor substrate 101 is on the backlight side of the solar cell. As some preferred solutions, the thickness of the semiconductor substrate 101 layer can be 80μm-250μm (for example, 80μm, 100μm, 120μm, 140μm, 150μm, 180μm, 200μm, 220μm, 250μm, etc.), preferably 100μm-200μm.

[0079] In the second aspect of the present application, a method for preparing the above-mentioned solar cell is proposed. According to the embodiment of the present application, referring to the attached Figure 5 , the method comprising:

[0080] S100: providing a semiconductor substrate;

[0081] In this step, a semiconductor substrate 101 is provided. The semiconductor substrate 101 includes a first surface 101 - 1 and a second surface 101 - 2 disposed opposite to each other along a thickness direction thereof.

[0082] S200: forming a tunneling oxide layer and a doped polysilicon layer in sequence on the first surface;

[0083] In this step, a tunnel oxide layer 102 is formed on the first surface 101 - 1 , and a doped polysilicon layer 103 is formed on a side of the tunnel oxide layer 102 away from the semiconductor substrate 101 .

[0084] In the embodiment of the present application, the method of forming the tunnel oxide layer 102 includes a thermal oxidation method, a PECVD (plasma enhanced chemical vapor deposition) method, a wet chemical method, and the like.

[0085] In the embodiment of the present application, the method for forming the polysilicon layer is LPCVD (low pressure chemical vapor deposition) method or PECVD (plasma enhanced chemical vapor deposition) method. The doping method of the polysilicon layer includes in-situ doping or non-in-situ doping. Taking PECVD in-situ doping as an example, firstly, a doped microcrystalline silicon layer is formed on the tunneling oxide layer 102 by the PECVD method. The doping source can be an N-type doping source, such as phosphorus, and then it is converted into a doped polysilicon layer under annealing at a high temperature of 900-930°C for several minutes.

[0086] S300: performing hydrogen implantation treatment on the surface of the doped polysilicon layer;

[0087] In this step, hydrogen implantation is performed on the surface of the doped polysilicon layer 103 so as to implant hydrogen into the ultra-thin doped polysilicon layer 103 to passivate defect centers in the doped polysilicon layer 103, reduce interface state density, and improve the efficiency of the solar cell.

[0088] In an embodiment of the present application, a method for performing hydrogen implantation on the surface of the doped polysilicon layer 103 includes:

[0089] Method 1: depositing an aluminum oxide layer 110 and / or a silicon nitride layer 111 on the surface of the doped polysilicon layer 103, and then performing an annealing process to implant hydrogen into the doped polysilicon layer 103 to achieve hydrogen passivation activation.

[0090] According to some specific embodiments of the present application, the annealing temperature is 300°C to 700°C (for example, 300°C, 400°C, 500°C, 600°C, 700°C, etc.), and the annealing time is 10min to 60min (for example, 10min, 20min, 30min, 40min, 50min, 60min, etc.). Thus, hydrogen can be effectively injected into the doped polysilicon layer 103 to achieve hydrogen passivation activation.

[0091] Method 2: Using hydrogen plasma to perform hydrogen implantation treatment on the surface of the doped polysilicon layer 103 to implant hydrogen into the doped polysilicon layer 103 and achieve hydrogen passivation activation.

[0092] The above two hydrogen injection treatment methods are highly compatible with the production line process and are conducive to actual production.

[0093] According to some specific embodiments of the present application, the flow rate of hydrogen plasma is 500sccm~3000sccm (for example, it can be 500sccm, 1000sccm, 1500sccm, 2000sccm, 2500sccm, 3000sccm, etc.), and the processing time is 30s~300s (for example, it can be 30s, 50s, 100s, 150s, 200s, 250s, 300s, etc.), thereby effectively injecting hydrogen into the doped polysilicon layer 103 to achieve hydrogen passivation activation.

[0094] In the embodiment of the present application, the process gas for the hydrogen plasma treatment may be hydrogen, a mixture of hydrogen and other gases, and other hydrogen sources that can be ionized to obtain hydrogen plasma.

[0095] In the embodiment of the present application, the concentration of hydrogen atoms in the doped polysilicon layer 103 after hydrogen implantation can reach 10 18 ~10 22 / cm 3 , thereby further ensuring the passivation of defect centers in the doped polysilicon layer 103, reducing the interface state density, and further ensuring the passivation effect of the ultra-thin doped polysilicon layer 103. Preferably, the hydrogen atom concentration in the doped polysilicon layer 103 is 10 19 ~10 21 / cm 3 .

[0096] S400: forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer in sequence on the second surface;

[0097] In this step, an intrinsic amorphous silicon layer 106 is formed on the second surface 101 - 2 , and a doped amorphous silicon layer 107 is formed on a side of the intrinsic amorphous silicon layer 106 away from the semiconductor substrate 101 .

[0098] In the embodiment of the present application, the intrinsic amorphous silicon layer 106 may be deposited by a CVD (chemical vapor deposition) method, and then the doped amorphous silicon layer 107 may be deposited on the intrinsic amorphous silicon layer 106 .

[0099] S500: forming a first transparent conductive layer on the surface of the hydrogen-implanted doped polysilicon layer, and forming a second transparent conductive layer on the surface of the doped amorphous silicon layer;

[0100] In this step, a PVD method may be used to form a first transparent conductive layer 104 on the surface of the doped polysilicon layer 103 after hydrogen implantation, and a second transparent conductive layer 108 on the surface of the doped amorphous silicon layer 107 .

[0101] S600: forming a first electrode on a surface of the first transparent conductive layer, and forming a second electrode on a surface of the second transparent conductive layer.

[0102] In this step, the first electrode 105 can be formed on the surface of the first transparent conductive layer 104, and the second electrode 109 can be formed on the surface of the second transparent conductive layer 108 by electroplating. The electroplating method includes but is not limited to at least one of electrodeposition, light-induced deposition, and chemical deposition. In addition, the first electrode 105 and the second electrode 109 can also be formed by screen printing.

[0103] It should be noted that steps S100-S600 are not intended to limit the method for preparing a solar cell to a single preparation sequence, and the method of the present application may also adopt other possible reasonable sequences.

[0104] According to the method for preparing a solar cell of the above embodiment of the present application, hydrogen is injected into the ultra-thin doped polysilicon layer by performing hydrogen injection treatment on the surface of the ultra-thin doped polysilicon layer, passivating the defect centers in the doped polysilicon layer, and reducing the interface state density, which can significantly improve the passivation effect of the ultra-thin doped polysilicon layer, and there is no need to increase the thickness of the doped polysilicon layer to improve its passivation effect, thereby avoiding the parasitic absorption problem caused by the excessive thickness of the doped polysilicon layer. As a result, the short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF of the solar cell can be improved at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0105] In the third aspect of the present application, a solar cell assembly is provided. According to an embodiment of the present application, the solar cell assembly has the solar cell of the above embodiment. As a result, the solar cell in the solar cell assembly has a high short-circuit current density Jsc, open-circuit voltage Voc and fill factor FF at the same time, thereby improving the photoelectric conversion efficiency PCE of the solar cell.

[0106] A battery module is a finished module with power generation output function produced by connecting multiple of the above-mentioned solar cells in series and / or in parallel, and undergoing processes such as lamination and packaging. Specifically, the battery module includes photovoltaic glass, packaging film, battery cells, packaging film, backplane, etc.

[0107] The embodiments of the present application are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, unless otherwise explicitly stated, all reagents used in the following embodiments are commercially available or can be synthesized according to this article or known methods, and the reaction conditions not listed are also easily available to those skilled in the art.

[0108] Example 1

[0109] This embodiment provides a solar cell, and the preparation method thereof is as follows:

[0110] (S1) Providing an initial N-type silicon wafer, cleaning and texturing the N-type silicon wafer, and obtaining an N-type silicon wafer substrate with a thickness of 130 μm.

[0111] (S2) Using PECVD method, a 2nm thick tunneling SiO2 is deposited in situ on the front side of the N-type silicon wafer. 2 A layer and an ultra-thin phosphorus-doped amorphous silicon layer with a thickness of 6 nm are formed, and an ultra-thin phosphorus-doped polycrystalline silicon layer is obtained after annealing.

[0112] (S3) feeding a silicon wafer having an ultra-thin phosphorus-doped polysilicon layer on the front side into a plate-type ALD device, with the side of the ultra-thin phosphorus-doped polysilicon layer away from the substrate facing upward, and cyclically feeding TMA and H into the ALD device. 2 O, a 10 nm thick aluminum oxide film is deposited on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0113] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 2E10 20 / cm 3 .

[0114] (S5) A 15 nm thick intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer substrate using a CVD method, and a 40 nm thick boron-doped amorphous silicon layer is deposited on the intrinsic amorphous silicon layer.

[0115] (S6) A 60 nm transparent conductive oxide layer is deposited on the aluminum oxide using a PVD method. The material is aluminum-doped zinc oxide.

[0116] (S7) Depositing a 100 nm transparent conductive oxide layer on the boron-doped amorphous silicon layer using a PVD method. The material is tin-doped indium oxide.

[0117] (S8) Electroplating the first gate line electrode and the second gate line electrode on the front and back sides respectively by chemical deposition, wherein the electroplating metal material includes Ni, Cu and Ag.

[0118] Example 2

[0119] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0120] (S3) depositing an aluminum oxide film with a thickness of 1 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0121] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 2E10 19 / cm3 .

[0122] Example 3

[0123] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0124] (S3) depositing an aluminum oxide film with a thickness of 5 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0125] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 5E10 19 / cm 3 .

[0126] Example 4

[0127] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0128] (S3) depositing an aluminum oxide film with a thickness of 15 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0129] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 3E10 20 / cm 3 .

[0130] Example 5

[0131] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0132] (S3) depositing an aluminum oxide film with a thickness of 20 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0133] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 4E10 20 / cm 3 .

[0134] Example 6

[0135] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0136] (S4) The silicon wafer is taken out of the ALD equipment and sent into an annealing furnace, where it is annealed at 300°C for 60 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 2E10 19 / cm 3 .

[0137] Example 7

[0138] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0139] (S4) The silicon wafer is taken out of the ALD device and sent into an annealing furnace, where it is annealed at 700°C for 10 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS tests show that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 2E10 20 / cm 3 .

[0140] Example 8

[0141] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0142] The step (S3) is replaced by: depositing a silicon nitride layer with a thickness of 10 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0143] (S4) The silicon wafer is sent to an annealing furnace and annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 8E10 19 / cm 3 .

[0144] Example 9

[0145] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 8 is that:

[0146] (S3) depositing a 50 nm thick silicon nitride layer on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0147] (S4) The silicon wafer is sent to an annealing furnace and annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 2E10 20 / cm 3 .

[0148] Example 10

[0149] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 8 is that:

[0150] (S3) depositing a silicon nitride layer with a thickness of 80 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0151] (S4) The silicon wafer is sent to an annealing furnace and annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 4E10 20 / cm 3 .

[0152] Embodiment 11

[0153] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 8 is that:

[0154] (S3) depositing a silicon nitride layer with a thickness of 120 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer.

[0155] (S4) The silicon wafer is sent to an annealing furnace and annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 7E10 20 / cm 3 .

[0156] Example 12

[0157] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0158] (S3) firstly depositing an aluminum oxide film with a thickness of 10 nm on the surface of the ultra-thin phosphorus-doped polysilicon layer, and then depositing a silicon nitride layer with a thickness of 50 nm on the surface of the aluminum oxide film.

[0159] (S4) The silicon wafer is sent to an annealing furnace and annealed at 500°C for 30 minutes in a nitrogen atmosphere to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 3E10 20 / cm 3 .

[0160] Embodiment 13

[0161] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0162] Replace (S3) and (S4) with:

[0163] Hydrogen plasma (process gas is hydrogen) is used to inject hydrogen on the surface of the ultra-thin phosphorus-doped polysilicon layer. The flow rate of hydrogen plasma is 1500sccm and the processing time is 150s to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface of the doped polysilicon layer is about 7E10 20 / cm3 .

[0164] Embodiment 14

[0165] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0166] Replace (S3) and (S4) with:

[0167] Hydrogen plasma (process gas is hydrogen) is used to inject hydrogen into the surface of the ultra-thin phosphorus-doped polysilicon layer. The flow rate of hydrogen plasma is 500sccm and the processing time is 300s to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface of the doped polysilicon layer is about 5E10 20 / cm 3 .

[0168] Embodiment 15

[0169] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0170] Replace (S3) and (S4) with:

[0171] Hydrogen plasma (process gas is hydrogen) is used to inject hydrogen into the surface of the ultra-thin phosphorus-doped polysilicon layer. The flow rate of hydrogen plasma is 3000sccm and the processing time is 30s to achieve hydrogen passivation activation. SIMS test shows that the concentration of hydrogen atoms in the surface of the doped polysilicon layer is about 2E10 20 / cm 3 .

[0172] Example 16

[0173] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0174] (S2) Using PECVD method, a 2nm thick tunneling SiO2 is deposited in situ on the front side of the N-type silicon wafer. 2 A layer and an ultra-thin phosphorus-doped amorphous silicon layer with a thickness of 2 nm are formed, and an ultra-thin phosphorus-doped polycrystalline silicon layer is obtained after annealing.

[0175] (S4) SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 4E10 20 / cm 3 .

[0176] Embodiment 17

[0177] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0178] (S2) Using PECVD method, a 2nm thick tunneling SiO2 is deposited in situ on the front side of the N-type silicon wafer. 2 A layer and an ultra-thin phosphorus-doped amorphous silicon layer with a thickness of 4 nm are formed, and an ultra-thin phosphorus-doped polycrystalline silicon layer is obtained after annealing.

[0179] (S4) SIMS test shows that the concentration of hydrogen atoms in the surface layer of the doped polysilicon layer is about 3E10 20 / cm 3 .

[0180] Comparative Example 1

[0181] This comparative example provides a solar cell, and the difference between this comparative example and Example 1 is only that:

[0182] (S2) The thickness of the phosphorus-doped polysilicon layer is 110 nm.

[0183] Comparative Example 2

[0184] This comparative example provides a solar cell, and the difference between this comparative example and Example 1 is only that:

[0185] Steps (S3) and (S4) are not included, that is, this comparative example does not perform hydrogen implantation treatment on the phosphorus-doped polysilicon layer.

[0186] The performance of the solar cells of Examples 1 to 17 and Comparative Examples 1 to 2 were tested respectively to obtain the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE of the corresponding cells. The results are shown in Table 1.

[0187] Table 1

[0188]

[0189]

[0190] It can be seen from Table 1 that compared with Comparative Example 1, the short-circuit current density Jsc, fill factor FF and photoelectric conversion efficiency PCE of Examples 1 to 17 are significantly improved. It can be seen that the ultra-thin doped polysilicon layer can significantly reduce the parasitic absorption problem of the doped polysilicon layer, thereby effectively improving the short-circuit current density Jsc, fill factor FF and photoelectric conversion efficiency PCE of the battery.

[0191] It can be seen from Table 1 that compared with Comparative Example 2, the open circuit voltage Voc, fill factor FF and photoelectric conversion efficiency PCE of Examples 1 to 17 are significantly improved. It can be seen that the ultra-thin doped polycrystalline silicon layer is hydrogen passivated, which can significantly improve the passivation effect of the ultra-thin doped polycrystalline silicon layer, thereby effectively improving the open circuit voltage Voc, fill factor FF and photoelectric conversion efficiency PCE of the battery.

[0192] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0193] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other along a thickness direction thereof; A tunneling oxide layer, wherein the tunneling oxide layer is disposed on the first surface of the semiconductor substrate; A doped polysilicon layer, wherein the doped polysilicon layer is disposed on a side of the tunneling oxide layer away from the semiconductor substrate, the thickness of the doped polysilicon layer is less than 10 nm, and the doped polysilicon layer is hydrogen passivated; a first transparent conductive layer, wherein the first transparent conductive layer is disposed on a side of the doped polysilicon layer away from the semiconductor substrate; a first electrode, the first electrode being disposed on a side of the first transparent conductive layer away from the doped polysilicon layer; An intrinsic amorphous silicon layer, wherein the intrinsic amorphous silicon layer is disposed on the second surface of the semiconductor substrate; A doped amorphous silicon layer, wherein the doped amorphous silicon layer is disposed on a side of the intrinsic amorphous silicon layer away from the semiconductor substrate; a second transparent conductive layer, wherein the second transparent conductive layer is disposed on a side of the doped amorphous silicon layer away from the semiconductor substrate; The second electrode is arranged on a side of the second transparent conductive layer away from the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that The concentration of hydrogen atoms in the doped polysilicon layer is 10 18 ~10 22 / cm 3 .

3. The solar cell according to claim 1, characterized in that The concentration of hydrogen atoms in the doped polysilicon layer is 10 19 ~10 21 / cm 3 .

4. The solar cell according to claim 1, characterized in that The thickness of the doped polysilicon layer is 2nm-6nm.

5. The solar cell according to claim 1, characterized in that: Also includes: An aluminum oxide layer is disposed between the doped polysilicon layer and the first transparent conductive layer.

6. The solar cell according to claim 5, characterized in that: The thickness of the aluminum oxide layer is 1 nm to 20 nm.

7. The solar cell according to claim 1, characterized in that Also includes: A silicon nitride layer is provided between the doped polysilicon layer and the first transparent conductive layer.

8. The solar cell according to claim 7, characterized in that: The thickness of the silicon nitride layer is 10 nm to 120 nm.

9. The solar cell according to claim 1, characterized in that: Also includes: An aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer is arranged on a side of the doped polysilicon layer away from the semiconductor substrate, the silicon nitride layer is arranged on a side of the aluminum oxide layer away from the semiconductor substrate, and the first transparent conductive layer is arranged on a side of the silicon nitride layer away from the semiconductor substrate.

10. The solar cell according to claim 9, characterized in that: The thickness of the aluminum oxide layer is 1 nm to 20 nm, the thickness of the silicon nitride layer is 10 nm to 120 nm, and the total thickness of the aluminum oxide layer and the silicon nitride layer is 10 nm to 140 nm.

11. The solar cell according to any one of claims 1 to 10, characterized in that: The semiconductor substrate is an N-type silicon wafer, the doped polysilicon layer is an N-type doped polysilicon layer, and the doped amorphous silicon layer is a P-type doped amorphous silicon layer; Alternatively, the semiconductor substrate is an N-type silicon wafer, the doped polysilicon layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer is an N-type doped amorphous silicon layer; Alternatively, the semiconductor substrate is a P-type silicon wafer, the doped polysilicon layer is an N-type doped polysilicon layer, and the doped amorphous silicon layer is a P-type doped amorphous silicon layer; Alternatively, the semiconductor substrate is a P-type silicon wafer, the doped polysilicon layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer is an N-type doped amorphous silicon layer.

12. The solar cell according to any one of claims 1 to 10, characterized in that The thickness of the tunnel oxide layer is 1.2nm to 2.5nm; And / or, the thickness of the intrinsic amorphous silicon layer is 2nm to 30nm; And / or, the thickness of the doped amorphous silicon layer is 2 nm to 60 nm; And / or, the thickness of the first transparent conductive layer and the second transparent conductive layer are respectively 10 nm to 200 nm.

13. A method for preparing the solar cell according to any one of claims 1 to 12, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other along a thickness direction thereof; forming a tunneling oxide layer and a doped polysilicon layer in sequence on the first surface; Performing hydrogen implantation on the surface of the doped polysilicon layer; sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the second surface; forming a first transparent conductive layer on the surface of the doped polysilicon layer after hydrogen injection, and forming a second transparent conductive layer on the surface of the doped amorphous silicon layer; A first electrode is formed on the surface of the first transparent conductive layer, and a second electrode is formed on the surface of the second transparent conductive layer.

14. The method according to claim 13, characterized in that Also includes: An aluminum oxide layer and / or a silicon nitride layer is formed on the surface of the doped polysilicon layer and annealed to achieve hydrogen implantation into the doped polysilicon layer.

15. The method according to claim 14, characterized in that The annealing temperature is 300°C to 700°C, and the annealing time is 10min to 60min.

16. The method according to claim 13, characterized in that A hydrogen plasma is used to perform hydrogen implantation treatment on the surface of the doped polysilicon layer.

17. The method according to claim 16, characterized in that The flow rate of the hydrogen plasma is 500 sccm to 3000 sccm, and the processing time is 30 s to 300 s.

18. A solar cell module, characterized in that: A solar cell according to any one of claims 1 to 12 or a solar cell produced by the method according to any one of claims 13 to 17.

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