Preparation method of image sensor structure and image sensor structure

Abstract

The invention relates to a preparation method of an image sensor structure and the image sensor structure, and relates to the technical field of semiconductors. According to the preparation method of the image sensor structure, the photodiode and the common emitter triode are prepared at the same time and integrated on the same substrate, and miniaturization of the image sensor structure is achieved. A first doped region of a photodiode is connected with a base region of a common-emitter triode through a connecting structure, after the photodiode receives an optical signal, the optical signal is converted into an electric signal, then the electric signal is transmitted to the common-emitter triode through the connecting structure, and the common-emitter triode further amplifies the electric signal. The imaging quality of the image sensor can be improved when the electric signal is increased, and the image sensor structure can amplify the electric signal even if the received optical signal is weak and the electric signal generated by the photodiode is weak due to the existence of the common-emitter triode, so that the imaging quality of the image sensor in the dark environment is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an image sensor structure and an image sensor structure. Background Art

[0002] CMOS image sensor is a device that converts light signals into electrical signals and is widely used in digital photography, video communication and other fields.

[0003] The working principle of CMOS image sensor is to focus the incident light into the optical area of ​​the photodiode. After receiving the light signal, the photodiode converts it into an electrical signal, and then converts it into an image signal. As the size of existing CMOS image sensors is limited by the internal space of electronic products, the light signal incident on the photodiode becomes weaker, and the imaging quality of the image sensor is weakened.

[0004] Based on this, how to improve the imaging quality of image sensors has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing an image sensor structure and an image sensor structure in order to improve the imaging quality of the image sensor.

[0006] In order to achieve the above object, on the one hand, the present invention provides a method for preparing an image sensor structure, comprising:

[0007] providing a substrate;

[0008] A trench isolation structure is formed in the substrate, wherein two oppositely disposed sides of the trench isolation structure are respectively a first region and a second region;

[0009] A photodiode is formed in the first region, and a common emitter transistor is formed in the second region, wherein the photodiode includes a first doped region located in the substrate, and the common emitter transistor includes a base region located in the substrate, and the base region and the first doped region have the same conductivity type;

[0010] A connection structure connecting the first doped region and the base region is formed.

[0011] In one embodiment, the forming of a photodiode in the first region and the forming of a common emitter transistor in the second region include:

[0012] forming a first implantation barrier layer covering the substrate and the trench isolation structure;

[0013] Performing ion implantation of a first conductivity type into the substrate based on the first implantation barrier layer, so as to form the first doping region in the substrate in the first region and a base region in the substrate in the second region;

[0014] removing the first injection blocking layer;

[0015] forming a second injection barrier layer covering the substrate and the trench isolation structure;

[0016] Based on the second injection barrier layer, ions of the second conductivity type are implanted into the substrate to form a second doped region in the substrate in the first region, and a collector region and an emitter region in the substrate in the second region; the collector region and the emitter region are respectively located on both sides of the base region, and the second doped region is connected to the first doped region;

[0017] The second implantation blocking layer is removed.

[0018] In one embodiment, the forming of the photodiode in the first region and the forming of the common emitter transistor in the second region further comprises:

[0019] A base electrode is formed on the base region.

[0020] In one embodiment, after forming a photodiode in the first region and forming a common emitter transistor in the second region, the method further comprises:

[0021] A load resistor is formed on a side of the emitter region away from the base region.

[0022] In one embodiment, forming a load resistor on a side of the emitter region away from the base region includes:

[0023] forming a groove on a side of the common emitter transistor away from the trench isolation structure;

[0024] The load resistor is formed in the groove.

[0025] In one embodiment, the connection structure includes a first interconnection structure, a second interconnection structure and a connection portion; forming the connection structure includes:

[0026] forming a dielectric layer covering the substrate, the photodiode and the common emitter transistor;

[0027] forming a first interconnection hole, a second interconnection hole and a third interconnection hole in the dielectric layer;

[0028] Filling the first interconnection hole, the second interconnection hole and the third interconnection hole with a conductive material to form the first interconnection structure, the second interconnection structure and the third interconnection structure; the first interconnection structure is connected to the first doped region, the second interconnection structure is connected to the base region, and the third interconnection structure is connected to the load resistor;

[0029] The connecting portion is formed on the first interconnect structure, the second interconnect structure and the dielectric layer.

[0030] On the other hand, the present invention further provides an image sensor structure, comprising:

[0031] substrate;

[0032] A trench isolation structure, wherein the trench isolation structure is located in the substrate, and two oppositely disposed sides of the trench isolation structure are respectively a first region and a second region;

[0033] a photodiode, the photodiode being located on one side of the first region and comprising a first doped region located in the substrate;

[0034] A common emitter transistor, the common emitter transistor is located at one side of the second region, and the common emitter transistor includes a base region located in the substrate, and the base region has the same conductivity type as the first doped region;

[0035] A connection structure connects the first doped region and the base region.

[0036] In one embodiment, the photodiode further includes a second doping region, the second doping region is located in the substrate of the first region; the second doping region is connected to the first doping region;

[0037] The common emitter transistor further includes a collector region and an emitter region, wherein the collector region and the emitter region are located in the substrate of the second region, and the collector region and the emitter region are respectively located on both sides of the base region;

[0038] The common emitter transistor further includes a base electrode located on the base region.

[0039] In one embodiment, the image sensor further comprises:

[0040] A load resistor is located at a side of the emitter region away from the base region.

[0041] In one embodiment, the image sensor further comprises:

[0042] a dielectric layer, the dielectric layer covering the substrate, the photodiode and the common emitter transistor;

[0043] A connection structure located in the dielectric layer, the connection structure comprising: a first interconnection structure, a second interconnection structure and a connection portion; the first interconnection structure is connected to the first doped region, the second interconnection structure is connected to the base region, and the connection portion connects the first interconnection structure and the second interconnection structure;

[0044] A third interconnect structure is located in the dielectric layer, and the third interconnect structure is connected to the load resistor.

[0045] Compared with the prior art, the above technical solution has the following advantages:

[0046] In the preparation method of the image sensor structure, a substrate is first provided, and a trench isolation structure is formed in the substrate, wherein the trench isolation structure separates the substrate into a first region and a second region which are arranged opposite to each other. Then, a photodiode is formed in the first region, and a common emitter transistor is formed in the second region. The photodiode includes a first doping region located in the substrate, and the common emitter transistor includes a base region located in the substrate, wherein the base region and the first doping region have the same conductivity type. The photodiode and the common emitter transistor are formed simultaneously and integrated on the same substrate, thereby realizing the miniaturization of the image sensor structure. The first doping region of the photodiode is connected to the base region of the common emitter transistor through a connecting structure. When the photodiode receives an optical signal, the optical signal is converted into an electrical signal, and the electrical signal is transmitted to the common emitter transistor through the connecting structure, and the common emitter transistor further amplifies the electrical signal. The increase in the electrical signal will increase the imaging quality of the image sensor. Due to the existence of the common emitter transistor, even if the received optical signal is weak and the electrical signal generated by the photodiode is also weak, the image sensor structure will amplify the electrical signal, thereby improving the imaging quality of the image sensor in a dark environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic flow chart of a method for preparing an image sensor structure is provided for an embodiment of the present application;

[0049] Figure 2 A schematic diagram of an image sensor structure provided in an embodiment of the present application;

[0050] Figure 3 A circuit diagram of a common emitter transistor Q provided in an embodiment of the present application;

[0051] Figure 4-Figure 9 A partial structural diagram of an image sensor structure provided in an embodiment of the present application;

[0052] Fig.10 A schematic diagram of another part of the structure of an image sensor provided in an embodiment of the present application;

[0053] Fig.11 A schematic diagram of another part of the structure of an image sensor provided in an embodiment of the present application;

[0054] Fig.12 A schematic diagram of another part of the structure of an image sensor provided in an embodiment of the present application;

[0055] Figure 13-Figure 16 A schematic diagram of another part of the structure of an image sensor provided in an embodiment of the present application;

[0056] Fig.17 A schematic diagram of current flow in an image sensor structure provided in an embodiment of the present application.

[0057] Explanation of the figure numbers: 01-substrate; 02-trench isolation structure; 03-first region; 04-second region; 05-first doped region; 06-base region; 07-connection structure; 08-first injection blocking layer; 09-second injection blocking layer; 10-second doped region; 11-collector region; 12-emitter region; 13-base electrode; 14-load resistor; 15-groove; 16-dielectric layer; 17-first interconnection hole; 18-second interconnection hole; 19-third interconnection hole; 20-first interconnection structure; 21-second interconnection structure; 22-third interconnection structure; 23-connecting part. DETAILED DESCRIPTION

[0058] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0060] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0061] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0062] Based on the content in the background technology, a CMOS image sensor is a sensor that can convert the color and brightness of light captured by the lens into electronic signals and transmit them to a processor. CMOS image sensors can be divided into front side illumination (FSI) image sensors and back side illumination (BSI) image sensors. Back side illumination image sensors currently have great development advantages because they can capture a larger amount of incoming light and achieve higher quality images.

[0063] However, the size of back-illuminated image sensors is currently limited by the internal space of electronic products, and the size of a single pixel is also limited, resulting in a weakened light signal incident on the image sensor. The voltage converted from the weak light signal in a dark environment is not enough to reach the turn-on voltage of the transistor, resulting in unsatisfactory imaging quality of the image sensor under extreme dark light conditions.

[0064] Based on this, the present application provides a method for preparing an image sensor structure and an image sensor structure. In the method for preparing the image sensor structure, a substrate is first provided, and a trench isolation structure is formed in the substrate. The trench isolation structure separates the substrate into a first region and a second region that are relatively arranged. Then, a photodiode is formed in the first region, and a common emitter transistor is formed in the second region. The photodiode includes a first doped region located in the substrate, and the common emitter transistor includes a base region located in the substrate. The base region and the first doped region have the same conductivity type. The photodiode and the common emitter transistor are integrated on the same substrate to achieve miniaturization of the image sensor structure. The first doped region of the photodiode is connected to the base region of the common emitter transistor through a connecting structure. When the photodiode receives an optical signal, the optical signal is converted into an electrical signal, and the electrical signal is transmitted to the common emitter transistor through the connecting structure. The common emitter transistor further amplifies the electrical signal. The larger the electrical signal, the higher the imaging quality of the image sensor. Due to the presence of the common emitter transistor, even if the received light signal is weak and the electrical signal generated by the photodiode is also weak, the image sensor structure will amplify the electrical signal, thereby improving the imaging quality of the image sensor in a dark environment.

[0065] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0066] refer to Figure 1 , Figure 1 A schematic diagram of a method for preparing an image sensor structure is provided for reference. Figure 2 , Figure 2 A schematic diagram of an image sensor structure provided in an embodiment of the present application; comprising:

[0067] S101: providing a substrate 01.

[0068] S102 : forming a trench isolation structure 02 in the substrate 01 .

[0069] The two opposite sides of the trench isolation structure 02 are respectively the first region 03 and the second region 04 .

[0070] S103 : forming a photodiode D in the first region 03 , and forming a common emitter transistor Q in the second region 04 .

[0071] The photodiode D includes a first doping region 05 located in the substrate 01 , and the common emitter transistor Q includes a base region 06 located in the substrate 01 . The base region 06 and the first doping region 05 have the same conductivity type.

[0072] S104 : forming a connection structure 07 connecting the first doping region 05 and the base region 06 .

[0073] Specifically, in the embodiment of the present application, the substrate 01 provided in step S101 can be a silicon substrate 01, and there is no specific limitation on this, and it can be set as needed. In step S102, a trench isolation structure 02 is formed in the substrate 01, and the trench isolation structure 02 can be a shallow trench isolation, which is used to isolate the interference between components. The material of the trench isolation structure 02 can be an insulating material such as silicon dioxide. The trench isolation structure 02 divides the substrate 01 into a first area 03 and a second area 04 that are relatively arranged. In step S103, a photodiode D is formed in the first area 03 of the substrate 01, and a common emitter transistor Q is formed in the second area 04. The photodiode D and the common emitter transistor Q are integrated on the same substrate 01, thereby realizing the miniaturization of the image sensor structure. It should be noted that since the base region 06 and the first doping region 05 have the same conductivity type, they can be formed at the same time. In step S104 , the connection structure 07 connects the first doping region 05 of the photodiode D to the base region 06 of the common emitter transistor Q, so as to transmit the electrical signal to the common emitter transistor Q for amplification.

[0074] The preparation method of the image sensor structure provided by the present application integrates the photodiode D and the common emitter transistor Q on the same substrate 01, thereby realizing the miniaturization of the image sensor structure. The first doping region 05 of the photodiode D is connected to the base region 06 of the common emitter transistor Q through a connection structure 07. When the photodiode D receives a light signal, the light signal is converted into an electrical signal, and the electrical signal is transmitted to the common emitter transistor Q through the connection structure 07. The common emitter transistor Q further amplifies the electrical signal. The increase in the electrical signal will increase the imaging quality of the image sensor. Due to the presence of the common emitter transistor Q, even if the received light signal is weak, so that the electrical signal generated by the photodiode D is also weak, the image sensor structure will amplify the electrical signal, thereby improving the imaging quality of the image sensor in a dark environment.

[0075] It should be noted that the reference Figure 3 , Figure 3 A circuit diagram of a common emitter transistor Q provided in an embodiment of the present application; the common emitter transistor Q introduces a current in the base region 06 and then opens a channel from the collector to the emitter. This channel can pass a large current and the current is converged to the emitter to achieve amplification. The common emitter transistor Q can amplify not only current signals but also voltage signals. The amplification principle of existing transistors can only amplify voltage but not current. The common emitter transistor Q of the present application obviously has a better amplification effect. Figure 3 Vin represents the input terminal, Vout represents the output terminal, I Brepresents the base region 06 current, I E represents the emitter current, I C represents the collector current, R c Represents the intrinsic resistance of the collector. The transistor follows the following relationship: I E =I C +I B , and the amplification factor of the common emitter transistor Q is β, where I C =I B ×β.

[0076] Optionally, in another embodiment of the present application, refer to Figure 4-Figure 9 , Figure 4-Figure 9 This is a partial structural diagram of an image sensor structure provided by an embodiment of the present application; a photodiode D is formed in the first area 03, and a common emitter transistor Q is formed in the second area 04, including:

[0077] S201 : forming a first implantation blocking layer 08 covering the substrate 01 and the trench isolation structure 02 .

[0078] In this step, if Figure 4 As shown, the first injection blocking layer 08 covers the trench isolation structure 02 and a portion of the substrate 01 . The first injection blocking layer 08 may be a photoresist, which is not specifically limited and can block ion injection.

[0079] S202 : performing ion implantation of the first conductivity type into the substrate 01 based on the first implantation barrier layer 08 , forming a first doping region 05 in the substrate 01 in the first region 03 , and forming a base region 06 in the substrate 01 in the second region 04 .

[0080] In this step, if Figure 5 As shown, the area of ​​the substrate 01 not covered by the first injection barrier layer 08 is the area where ions need to be injected, and the first doped region 05 injected into the substrate 01 in the first area 03 and the base region 06 injected into the substrate 01 in the second area 04 are both P-type regions. It should be noted that the doped ions in the first doped region 05 can be phosphorus ions, arsenic ions, indium metal, gallium metal, etc., and are not specifically limited. The doped ions in the base region 06 can be boron ions, etc., which are only for example.

[0081] S203: removing the first injection blocking layer 08.

[0082] In this step, if Figure 6 As shown, after the first doping region 05 and the base region 06 are prepared, the first injection barrier layer 08 is removed. When the first injection barrier layer 08 is a photoresist, dry stripping or wet stripping can be used without specific limitation.

[0083] S204 : forming a second implantation blocking layer 09 covering the substrate 01 and the trench isolation structure 02 .

[0084] In this step, if Figure 7 As shown, the material of the second injection blocking layer 09 can be photoresist, and the second injection blocking layer 09 covers the trench isolation structure 02 and a portion of the substrate 01 , and at this time covers the first doped region 05 and the base region 06 to be formed.

[0085] S205: Based on the second injection barrier layer 09, ions of the second conductivity type are implanted into the substrate 01 to form a second doped region 10 in the substrate 01 in the first region 03, and a collector region 11 and an emitter region 12 in the substrate 01 in the second region 04; the collector region 11 and the emitter region 12 are respectively located on both sides of the base region 06, and the second doped region 10 is connected to the first doped region 05.

[0086] In this step, if Figure 8 As shown, the area of ​​the substrate 01 not covered by the second injection blocking layer 09 is the area where ions need to be injected. The second doped region 10 is injected into the substrate 01 of the first region 03. The second doped region 10 is connected to the first doped region 05. The second doped region 10 is an N-type region, and together with the first doped region 05, forms a PN junction of the photodiode D. The collector region 11 and the emitter region 12 are injected into the substrate 01 of the second region 04. The collector region 11 and the emitter region 12 are both N-type regions. It should be noted that the doped ions in the second doped region 10 can be phosphorus ions, arsenic ions, indium metal, gallium metal, etc., and are not specifically limited. The doped ions in the collector region 11 and the emitter region 12 can be boron ions, etc., which are only for example.

[0087] S206: removing the second injection blocking layer 09.

[0088] In this step, if Fig. 9 As shown, after the N-type region and the P-type region of the photodiode D and the common emitter transistor Q are doped and formed, the second injection blocking layer 09 is removed. When the second injection blocking layer 09 is a photoresist, dry stripping or wet stripping can be used without specific limitation.

[0089] In this embodiment, the P-type region of the photodiode D and the P-type region of the common emitter transistor Q are formed at the same time, and the N-type region of the photodiode D and the N-type region of the common emitter transistor Q are formed at the same time. That is to say, the photodiode D and the common emitter transistor Q are formed on the same substrate 01 at the same time, which increases the integration and realizes the miniaturization of the image sensor structure.

[0090] Optionally, in another embodiment of the present application, refer to Fig.10 , Fig.10This is another partial structural diagram of an image sensor structure provided by an embodiment of the present application; a photodiode D is formed in the first area 03, and a common emitter transistor Q is formed in the second area 04, and further includes:

[0091] A base electrode 13 is formed on the base region 06 .

[0092] Specifically, the common emitter transistor Q further includes a base electrode 13, which is located on the upper surface of the base region 06, and the connecting structure 07 is connected to the base region 06 through the base electrode 13. It should be noted that the base electrode 13 is a metal conductive material, and is not specifically limited. Forming the base electrode 13 on one side of the base region 06 can improve the conductivity.

[0093] Optionally, in another embodiment of the present application, refer to Fig.11 , Fig.11 This is another schematic diagram of a structure of an image sensor provided by an embodiment of the present application; after a photodiode D is formed in the first region 03 and a common emitter transistor Q is formed in the second region 04, the structure includes:

[0094] A load resistor 14 is formed on a side of the emitter region 12 away from the base region 06 .

[0095] Specifically, in the second region 04, a load resistor 14 is further provided, the load resistor 14 is located on the side of the emitter region 12 away from the base region 06, connected to the emitter, and the material of the load resistor 14 may be a copper-nickel alloy material. In this embodiment, the load resistor 14 is provided to protect the circuit.

[0096] Optionally, in another embodiment of the present application, refer to Fig.12 , Fig.12 This is another schematic diagram of a structure of an image sensor provided by an embodiment of the present application; a load resistor 14 is formed on a side of the emitter region 12 away from the base region 06, including:

[0097] S301 : forming a groove 15 on a side of the common emitter transistor Q away from the trench isolation structure 02 .

[0098] S302 : forming a load resistor 14 in the groove 15 .

[0099] Specifically, the load resistor 14 is formed by a physical vapor deposition (PVD) method. Fig.12 As shown, in step S301, a groove 15 is formed in the substrate 01 on the side of the common emitter transistor Q away from the trench isolation structure 02 in the second region 04, so as to provide a basis for the subsequent formation of the load resistor 14. Fig.11As shown, in step S302 , a copper-nickel alloy is deposited in the formed groove 15 to form a load resistor 14 .

[0100] Optionally, in another embodiment of the present application, refer to Figure 13-Figure 16 , Figure 13-Figure 16 This is another partial structural diagram of an image sensor structure provided in an embodiment of the present application; the connection structure 07 includes a first interconnection structure 20, a second interconnection structure 21 and a connection portion 23; forming the connection structure 07, including:

[0101] S401 : forming a dielectric layer 16 covering the substrate 01 , the photodiode D and the common emitter transistor Q.

[0102] In this step, if Fig.13 As shown, a dielectric layer 16 covering the substrate 01, the photodiode D and the common emitter transistor Q is formed by chemical vapor deposition (CVD). The dielectric layer 16 provides physical support for the image sensor structure and realizes electrical isolation.

[0103] S402 : forming a first interconnection hole 17 , a second interconnection hole 18 and a third interconnection hole 19 in the dielectric layer 16 .

[0104] In this step, if Fig.14 As shown, a first interconnection hole 17, a second interconnection hole 18 and a third interconnection hole 19 are formed in the dielectric layer 16 by dry etching. It should be noted that the first interconnection hole 17 penetrates the dielectric layer 16 and exposes the first doped region 05, the second interconnection hole 18 penetrates the dielectric layer 16 and exposes the base electrode 13, and the third interconnection hole 19 penetrates the dielectric layer 16 and exposes the load resistor 14.

[0105] S403: Filling the first interconnection hole 17, the second interconnection hole 18 and the third interconnection hole 19 with conductive material to form a first interconnection structure 20, a second interconnection structure 21 and a third interconnection structure 22; the first interconnection structure 20 is connected to the first doped region 05, the second interconnection structure 21 is connected to the base region 06, and the third interconnection structure 22 is connected to the load resistor 14.

[0106] In this step, if Fig.15As shown, the conductive material filled in the first interconnection hole 17, the second interconnection hole 18 and the third interconnection hole 19 can be a metal material, and is not specifically limited. After filling the metal, a first interconnection structure 20, a second interconnection structure 21 and a third interconnection structure 22 are formed. The first interconnection structure 20 is connected to the first doping region 05, the second interconnection structure 21 is connected to the base region 06, and the third interconnection structure 22 is connected to the load resistor 14. The first interconnection structure 20, the second interconnection structure 21 and the third interconnection structure 22 connect the element to the external upper layer circuit to realize the signal transmission of the image sensor.

[0107] S404 : forming a connection portion 23 on the first interconnect structure 20 , the second interconnect structure 21 and the dielectric layer 16 .

[0108] In this step, if Fig.16 As shown, the connection structure 07 further includes a connection portion 23 , and the connection portion 23 is used to connect the first interconnection structure 20 and the second interconnection structure 21 to achieve the connection between the photodiode D and the common emitter transistor Q.

[0109] In this embodiment, since the photodiode D and the common emitter transistor Q are located in the same substrate 01, the connection structure 07 connects the photodiode D and the common emitter transistor Q together, which increases the integration of the image sensor structure. At the same time, the electrical signal generated by the photodiode D is amplified by the common emitter transistor Q, thereby improving the imaging quality of the image sensor structure.

[0110] In the examples of this application, refer to Fig.17 , Fig.17 A schematic diagram of current flow in an image sensor structure provided by an embodiment of the present application; the photodiode D receives the light signal, performs photoelectric signal conversion, and then transmits the electrical signal to the base region 06 of the common emitter transistor Q, and then flows out from the load resistor 14. The signal amplification circuit implemented in the present application has a better amplification effect.

[0111] Based on the above-mentioned method for preparing the image sensor structure, the present application also provides an image sensor structure, which is prepared by the above-mentioned method for preparing the image sensor structure. The image sensor structure will be described below. Fig.17 As shown, the image sensor structure includes:

[0112] Substrate 01.

[0113] A trench isolation structure 02 is located in the substrate 01 , and two oppositely disposed sides of the trench isolation structure 02 are a first region 03 and a second region 04 .

[0114] The photodiode D is located at one side of the first region 03 , and includes a first doping region 05 located in the substrate 01 .

[0115] The common emitter transistor Q is located at one side of the second region 04 , and includes a base region 06 located in the substrate 01 , and the base region 06 and the first doped region 05 have the same conductivity type.

[0116] The connection structure 07 connects the first doping region 05 and the base region 06 .

[0117] Specifically, the substrate 01 may be a silicon substrate 01, and the trench isolation structure 02 may be a shallow trench isolation structure. In the present application, the trench isolation structure 02 separates the substrate 01 into a first region 03 and a second region 04 that are arranged opposite to each other. The first region 03 includes a photodiode D, and the second region 04 includes a common emitter transistor Q. The photodiode D includes a first doped region 05 located in the substrate 01, and the common emitter transistor Q includes a base region 06 located in the substrate 01. The base region 06 has the same conductivity type as the first doped region 05. The photodiode D and the common emitter transistor Q are integrated on the same substrate 01, thereby realizing the miniaturization of the image sensor structure.

[0118] The first doping region 05 of the photodiode D is connected to the base region 06 of the common emitter transistor Q through the connection structure 07. When the photodiode D receives the light signal, it converts the light signal into an electric signal, and transmits the electric signal to the common emitter transistor Q through the connection structure 07. The common emitter transistor Q further amplifies the electric signal. The larger the electric signal, the better the imaging quality of the image sensor. Due to the existence of the common emitter transistor Q, even if the received light signal is weak and the electric signal generated by the photodiode D is also weak, the image sensor structure will amplify the electric signal, thereby improving the imaging quality of the image sensor in a dark environment.

[0119] Optionally, in another embodiment of the present application, Fig. 9 As shown, the photodiode D further includes a second doping region 10, which is located in the substrate 01 of the first region 03; the second doping region 10 is connected to the first doping region 05;

[0120] The common emitter transistor Q further includes a collector region 11 and an emitter region 12, the collector region 11 and the emitter region 12 are located in the substrate 01 of the second region 04, and the collector region 11 and the emitter region 12 are located on both sides of the base region 06 respectively;

[0121] The common emitter transistor Q further includes a base electrode 13 located on the base region 06 .

[0122] Specifically, the first doping region 05 in the photodiode D is a P-type region, and the second doping region 10 is an N-type region. The base region 06 in the common emitter transistor Q is a P-type region, the collector region 11 and the emitter region 12 are N-type regions, and the base electrode 13 is a metal material. It should be noted that the photodiode D and the common emitter transistor Q are integrated on the same substrate 01, so that the image sensor structure is miniaturized.

[0123] Optionally, in another embodiment of the present application, Fig. 9 As shown, the image sensor structure also includes:

[0124] The load resistor 14 is located at a side of the emitter region 12 away from the base region 06 .

[0125] Specifically, the load resistor 14 is used to protect the circuit of the image sensor structure.

[0126] Optionally, in another embodiment of the present application, Fig. 9 As shown, the image sensor structure also includes:

[0127] The dielectric layer 16 covers the substrate 01 , the photodiode D and the common emitter transistor Q.

[0128] The connection structure 07 is located in the dielectric layer 16 , and the connection structure 07 includes: a first interconnection structure 20 , a second interconnection structure 21 and a connection portion 23 ; the first interconnection structure 20 is connected to the first doped region 05 , the second interconnection structure 21 is connected to the base region 06 , and the connection portion 23 connects the first interconnection structure 20 and the second interconnection structure 21 .

[0129] The third interconnect structure 22 is located in the dielectric layer 16 , and the third interconnect structure 22 is connected to the load resistor 14 .

[0130] Specifically, the dielectric layer 16 is formed by chemical vapor deposition, and a first interconnection structure 20, a second interconnection structure 21, a connection portion 23, and a third interconnection structure 22 are formed in the dielectric layer 16 by dry etching and deposition. The first interconnection structure 20 is connected to the first doping region 05, the second interconnection structure 21 is connected to the base region 06, and the third interconnection structure 22 is connected to the load resistor 14, and the connection portion 23 connects the first interconnection structure 20 and the second interconnection structure 21.

[0131] It should be noted that the first interconnection structure 20, the second interconnection structure 21 and the third interconnection structure 22 can be formed at the same time without specific limitation. The connection structure 07 realizes the connection between the photodiode D and the common emitter transistor Q, and the third interconnection structure 22 realizes the signal extraction of the load resistor 14.

[0132] In the above-mentioned image sensor structures, since they are all formed by the preparation method of the image sensor structure, they have the same technical effects as those thereof and will not be described in detail herein.

[0133] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0134] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing an image sensor structure, characterized in that: include: providing a substrate; A trench isolation structure is formed in the substrate, wherein two oppositely disposed sides of the trench isolation structure are respectively a first region and a second region; A photodiode is formed in the first region, and a common emitter transistor is formed in the second region, wherein the photodiode includes a first doped region located in the substrate, and the common emitter transistor includes a base region located in the substrate, and the base region and the first doped region have the same conductivity type; A connection structure connecting the first doped region and the base region is formed.

2. The method for preparing an image sensor structure according to claim 1, characterized in that: The method of forming a photodiode in the first region and forming a common emitter transistor in the second region includes: forming a first implantation barrier layer covering the substrate and the trench isolation structure; Performing ion implantation of a first conductivity type into the substrate based on the first implantation barrier layer, so as to form the first doping region in the substrate in the first region and a base region in the substrate in the second region; removing the first injection blocking layer; forming a second injection barrier layer covering the substrate and the trench isolation structure; Based on the second injection barrier layer, ions of the second conductivity type are implanted into the substrate to form a second doped region in the substrate in the first region, and a collector region and an emitter region in the substrate in the second region; the collector region and the emitter region are respectively located on both sides of the base region, and the second doped region is connected to the first doped region; The second implantation blocking layer is removed.

3. The method for preparing an image sensor structure according to claim 2, characterized in that: The method of forming a photodiode in the first region and forming a common emitter transistor in the second region further includes: A base electrode is formed on the base region.

4. The method for preparing an image sensor structure according to claim 2, characterized in that: After forming a photodiode in the first region and forming a common emitter transistor in the second region, the method comprises: A load resistor is formed on a side of the emitter region away from the base region.

5. The method for preparing an image sensor structure according to claim 4, characterized in that: The forming of a load resistor on a side of the emitter region away from the base region comprises: forming a groove on a side of the common emitter transistor away from the trench isolation structure; The load resistor is formed in the groove.

6. The method for preparing an image sensor structure according to claim 4, characterized in that: The connection structure includes a first interconnection structure, a second interconnection structure and a connection portion; forming the connection structure includes: forming a dielectric layer covering the substrate, the photodiode and the common emitter transistor; forming a first interconnection hole, a second interconnection hole and a third interconnection hole in the dielectric layer; Filling the first interconnection hole, the second interconnection hole and the third interconnection hole with a conductive material to form the first interconnection structure, the second interconnection structure and the third interconnection structure; the first interconnection structure is connected to the first doped region, the second interconnection structure is connected to the base region, and the third interconnection structure is connected to the load resistor; The connecting portion is formed on the first interconnect structure, the second interconnect structure and the dielectric layer.

7. An image sensor structure, characterized in that: include: substrate; A trench isolation structure, wherein the trench isolation structure is located in the substrate, and two oppositely disposed sides of the trench isolation structure are respectively a first region and a second region; a photodiode, the photodiode being located on one side of the first region and comprising a first doped region located in the substrate; A common emitter transistor, the common emitter transistor is located at one side of the second region, and the common emitter transistor includes a base region located in the substrate, and the base region has the same conductivity type as the first doped region; A connection structure connects the first doped region and the base region.

8. The image sensor structure according to claim 7, characterized in that: The photodiode further includes a second doping region, the second doping region is located in the substrate of the first region; the second doping region is connected to the first doping region; The common emitter transistor further includes a collector region and an emitter region, wherein the collector region and the emitter region are located in the substrate of the second region, and the collector region and the emitter region are respectively located on both sides of the base region; The common emitter transistor further includes a base electrode located on the base region.

9. The image sensor structure according to claim 8, characterized in that: The image sensor structure further includes: A load resistor is located at a side of the emitter region away from the base region.

10. The image sensor structure according to claim 9, characterized in that: The image sensor structure further includes: a dielectric layer, the dielectric layer covering the substrate, the photodiode and the common emitter transistor; A connection structure located in the dielectric layer, the connection structure comprising: a first interconnection structure, a second interconnection structure and a connection portion; the first interconnection structure is connected to the first doped region, the second interconnection structure is connected to the base region, and the connection portion connects the first interconnection structure and the second interconnection structure; A third interconnect structure is located in the dielectric layer, and the third interconnect structure is connected to the load resistor.

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