Pixel-level spectrum light splitting manufacturing method on CMOS (complementary metal oxide semiconductor) imaging chip

Abstract

The invention relates to the technical field of optical thin films, and particularly provides a pixel-level spectrum light splitting manufacturing method on a CMOS (Complementary Metal Oxide Semiconductor) imaging chip, which comprises the following steps of: cleaning a bare chip in the CMOS imaging chip, covering an electrode area on the surface of the bare chip by using negative photoresist, depositing a filter film stack in a photosensitive area on the surface of the bare chip, and forming a pixel-level spectrum light splitting film on the CMOS imaging chip. The light filtering film stack outside the single light splitting unit area is etched, the reserved light filtering film stack forms a spectrum channel, other spectrum channels are prepared in other light splitting units in the light sensing area respectively, and the processed bare chip is cleaned and packaged in the CMOS imaging chip again; the CMOS spectral imaging chip solves the problems of spectral crosstalk caused by alignment errors, Newton rings caused by air gaps between the chip and the optical filter and the like when the imaging chip and the pixel-level spectral optical filter are integrated, and the spectral imaging quality of the CMOS spectral imaging chip is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of optical thin films, and in particular relates to a method for manufacturing pixel-level spectral splitting on a CMOS imaging chip. Background Art

[0002] The imaging spectrometer with spectroscopy as the core combines imaging technology and spectroscopy technology. It can not only image the detection target, but also obtain its rich spectral information. It has been widely and deeply applied in the fields of agriculture / forestry monitoring, environmental monitoring, natural disaster assessment, mineral exploration, biomedical testing, security monitoring, and military target warning and identification. At present, imaging spectrometers are often used for remote sensing in the form of aviation, aerospace and drone payloads. Their size and weight are very critical. There is an urgent need for miniaturization and lightweight research on imaging spectrometers.

[0003] A pixel-level multi-channel filter is a filter with multiple spectral channels, each of which can correspond to a pixel of an imaging detector chip one-to-one. Integrating it as a spectroscopic element on the imaging detector chip can greatly optimize the structure of the spectroscopic system of the imaging spectrometer and realize the miniaturization and lightweight of the imaging spectrometer. However, there are two problems when integrating the pixel-level multi-channel filter with the imaging detector chip. First, when the spectral channel of the pixel-level multi-channel filter is aligned with the pixel of the detector imaging chip, there will be an air gap between the pixel surface and the filter surface. This air gap can easily lead to the formation of Newton rings, which has a serious impact on the imaging quality. Second, there will be an alignment error between the spectral channel and the chip pixel. The alignment error will also cause spectral crosstalk between the spectral channels, affecting the spectral purity of the imaging spectrum. Therefore, a new pixel-level spectral spectrometry production method is needed to solve the above problems. Summary of the invention

[0004] To achieve the above object, the technical solution created by the present invention is implemented as follows:

[0005] The present invention provides a method for manufacturing pixel-level spectral splitting on a CMOS imaging chip, comprising the following steps:

[0006] S1: taking out the bare die from the CMOS imaging chip, cleaning the bare die, designing a first mask according to the distribution of the electrode area and the photosensitive area on the surface of the bare die, wherein the first mask is designed to cover the photosensitive area on the surface of the bare die, covering the surface of the bare die with the first mask, covering the electrode area with negative photoresist using a photolithography process, and removing the first mask;

[0007] S2: dividing the surface of the photosensitive area into m×m periodically arranged light-splitting arrays, dividing each light-splitting array into n×n light-splitting units, each light-splitting unit corresponding to a×a pixels in the photosensitive area, wherein m, n and a are all integers greater than or equal to 1;

[0008] S3: Design a second mask, wherein the second mask is designed to cover the first light splitting unit in the first light splitting array in the photosensitive area, cover the second mask on the surface of the photosensitive area, deposit an etch stop layer on the surface of the photosensitive area covered with the second mask by a thin film deposition process, remove the second mask, and deposit a first filter film stack on the photosensitive area by a thin film deposition process, wherein the first filter film stack is formed by alternating high refractive index material films and low refractive index material films, and the total thickness of the first filter film stack is 1 μm to 10 μm;

[0009] S4: designing a third mask, wherein the third mask is designed to cover other photosensitive areas except the first light splitting unit in the first light splitting array, depositing a metal mask layer on the surface of the photosensitive area covering the third mask by using a thin film deposition process, then removing the third mask, etching the first filter film stack by using a chemical reaction ion beam etching process until the etching stops at the etching stop layer, removing the metal mask layer and the etching stop layer, and the first filter film stack left on the first light splitting unit constitutes a spectral channel;

[0010] S5: Repeat steps S3 to S4, repeat (n 2 -1) times, preparing spectral channels in other spectral units of the first spectral array, each spectral channel is used to pass light of a predetermined wavelength;

[0011] S6: Repeat steps S3 to S5, repeat (m 2 -1) times, preparing spectral channels in other spectroscopic arrays in the photosensitive area respectively, and the corresponding spectral channels in each spectroscopic array are arranged in the same manner;

[0012] S7: Use ethanol or acetone to clean the surface of the processed die, and encapsulate the die into a CMOS imaging chip.

[0013] Preferably, the photolithography process in S1 includes spin coating a negative photoresist on the surface of the die, pre-baking, exposing, post-baking and developing.

[0014] Preferably, the rotation speed of spin coating the negative photoresist is 1000 rpm to 5000 rpm, the pre-baking and post-baking temperatures are both 90° C. to 150° C., and the exposure time is 2s to 10s.

[0015] Preferably, the thin film deposition process in S3 is an electron beam evaporation thin film deposition process or a magnetron sputtering thin film deposition process.

[0016] Preferably, the etching stop layer in S3 is a metal film, the material of the metal film is chromium or aluminum, and the thickness of the metal film is 100 nm to 500 nm.

[0017] Preferably, the high refractive index material in S3 is Ta2O5 or TiO2 or HfO2, and the low refractive index material is SiO2 or Al2O3.

[0018] Preferably, the thickness of the metal mask layer in S4 is 100 nm to 500 nm.

[0019] Preferably, the gas used for etching in S4 is a sulfur-based gas such as SF6 or CF4 or CHF3, and the etching rate is 10 nm / min to 100 nm / min.

[0020] Compared with the prior art, the invention can achieve the following beneficial effects:

[0021] The present invention creates a method for manufacturing pixel-level spectral spectrometry on a CMOS imaging chip, which directly manufactures a spectral spectrometry channel in the photosensitive area on the surface of a bare chip in the CMOS imaging chip, thereby replacing the existing manufacturing method of integrating a CMOS imaging chip with a spectral filter, solving the spectral crosstalk caused by the alignment error when the imaging chip and the filter are spliced ​​and aligned, and solving the Newton ring problem caused by the air gap between the chip and the spectral filter, and can greatly improve the spectral imaging quality and product yield of the CMOS spectral imaging chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0023] Figure 1 This is a schematic diagram of the spectral channels of a die surface including 8×8 pixels in this application;

[0024] Figure 2 Schematic diagram of the light splitting array and the light splitting unit in the first embodiment of the present application.

[0025] Description of reference numerals:

[0026] 1. Pixel; 2. Electrode area; 3. Spectral channel; 10. First spectroscopic array; 101. First spectroscopic unit; 102. Second spectroscopic unit; 103. Third spectroscopic unit; 104. Fourth spectroscopic unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0029] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0030] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0031] The present invention provides a method for manufacturing pixel-level spectral splitting on a CMOS imaging chip, comprising the following steps:

[0032] S1: Take out the bare chip from the CMOS imaging chip, the surface of the bare chip includes a photosensitive area arranged in the middle and electrode areas 2 arranged around, the photosensitive area includes 1K×1K to 5K×5K (1K and 5K here represent 1000 and 5000 respectively) pixels 1, and the size of a single pixel 1 is (2μm~20μm)×(2μm~20μm), clean the bare chip, and according to the distribution of the electrode area 2 and the photosensitive area on the surface of the bare chip, design a first mask that can cover the photosensitive area on the surface of the bare chip and expose the electrode area 2, cover the first mask on the surface of the bare chip, use a photolithography process to cover the electrode area 2 with negative photoresist, and remove the first mask.

[0033] S2: The surface of the photosensitive area is divided into m×m periodically arranged splitting arrays, and each splitting array is divided into n×n splitting units. Each splitting unit in S2 corresponds to a×a pixels in the photosensitive area, where m, n and a are all integers greater than or equal to 1.

[0034] S3: Design a second mask, the second mask is designed to cover the first splitter unit in the first splitter array in the photosensitive area, cover the second mask on the surface of the photosensitive area, and use a thin film deposition process to deposit an etch stop layer on the surface of the photosensitive area covered with the second mask. The etch stop layer is a metal film with a thickness of 100nm to 500nm, and the material of the metal film is chromium or aluminum. Remove the second mask. At this time, all areas in the photosensitive area except the first splitter unit of the first splitter array are covered with the etch stop layer; use a thin film deposition process to deposit a first filter film stack in the photosensitive area, the first filter film stack is formed by alternating high refractive index material films and low refractive index material films, and the total thickness of the first filter film stack is 1μm to 10μm, wherein the high refractive index material is Ta2O5 or TiO2 or HfO2, and the low refractive index material is SiO2 or Al2O3, and the thin film deposition process is an electron beam evaporation thin film deposition process or a magnetron sputtering thin film deposition process.

[0035] S4: Design a third mask, which is designed to expose the first spectroscopic unit in the first spectroscopic array in the photosensitive area and cover other parts of the photosensitive area. Cover the third mask on the surface of the bare chip, and deposit a metal mask layer on the surface of the photosensitive area covered with the third mask by a thin film deposition process. Then remove the third mask, and the thickness of the deposited metal mask layer is 100nm to 500nm. Etch the first filter film stack by a chemical reaction ion beam etching process until it stops at the etching stop layer. The gas used for etching is sulfur-based gas such as SF6, CHF3, and CF4, and the etching rate is 10nm / min to 100nm / min. Due to the protection of the metal mask layer, the first filter film stack covering the first spectroscopic unit in the first spectroscopic array will not be etched. Then remove the metal mask layer and the etching stop layer. The first filter film stack retained on the first spectroscopic unit constitutes a spectral channel.

[0036] S5: Repeat steps S3 to S4, repeat (n 2 -1) times, corresponding spectral channels are respectively prepared in the remaining other spectral units of the first spectral array, and each spectral channel is used to pass light of a predetermined wavelength.

[0037] S6: Repeat steps S3 to S5, repeat (m 2 -1) times, spectral channels are prepared in other spectroscopic arrays in the photosensitive area respectively, and the corresponding spectral channels in each spectroscopic array are arranged in the same manner.

[0038] S7: Use ethanol or acetone to clean the surface of the processed bare chip and then package it.

[0039] The photolithography process in S1 includes spin coating negative photoresist on the surface of the die, pre-baking, exposure, development and post-baking.

[0040] Furthermore, in S1, the negative photoresist is spin-coated on the surface of the bare wafer at a rotation speed of 1000 rpm to 5000 rpm, the pre-baking and post-baking temperatures are both 90° C. to 150° C., and the exposure time is 2s to 10s.

[0041] like Figure 1 As shown, Figure 1 The figure shows the situation where the pixels are arranged in an 8×8 array, where m=4, n=2, a=1, and the pixel 1 is arranged in an 8×8 array in the middle of the die surface, and the electrode area 2 is spread over the four edge positions of the die. It can be seen from the figure that the spectral channels 3 are arranged in a 2×2 array on the die surface, and each spectral channel 3 passes light of a predetermined wavelength band.

[0042] Embodiment 1

[0043] A method for manufacturing pixel-level four-channel spectral splitting on a CMOS imaging chip specifically comprises the following steps:

[0044] S1: Select a CMOS imaging chip of model GSENSE400, the photosensitive area of ​​this chip is 22.528mm×22.528mm, take out the bare chip in the CMOS imaging chip, the surface of the bare chip includes the photosensitive area in the middle and the electrode area 2 distributed at the four edges of the bare chip, the layout of the electrode area 2 and the photosensitive area on the bare chip surface is the same as Figure 1 The layout shown is similar, the photosensitive area includes 2048×2048 pixels 1, and the side length of a single pixel 1 is 11μm×11μm. The bare chip is cleaned, and the first mask is designed according to the layout of the electrode area and the photosensitive area on the surface of the bare chip. The side length of the first mask is 3 inches and the surface is plated with a layer of chrome film. The first mask is designed to cover the photosensitive area on the surface of the bare chip and expose the electrode area 2. SU-8 type negative photoresist is spin-coated on the surface of the bare chip. Since the negative photoresist has strong corrosion resistance, strong heat stability and strong resistance to ion bombardment, this embodiment chooses to use negative photoresist. The speed of the coating machine during spin coating is 3000 rpm; the bare chip after spin coating with negative photoresist is placed on a hot plate for pre-baking, the baking temperature is 100°C, and the baking time is 3 minutes; the first mask is covered on the surface of the bare chip, and the bare chip is exposed, and the exposure dose is 60mJ / cm 2 The exposure time is 6s, the first mask is removed, and the exposed die is post-baked at a temperature of 100°C for 3min; the baked die is placed in a developer for development, and the electrode region 2 on the die surface is covered with a negative photoresist.

[0045] S2: In this embodiment, each spectroscopic unit corresponds to one pixel (ie, a=1), and each spectral channel corresponds to one spectroscopic unit, that is, the size of each spectral channel is 11 μm×11 μm, and four spectroscopic units are arranged in a 2×2 array (ie, n=2) to form a spectroscopic array.

[0046] The four light-splitting units in each light-splitting array can form four spectral channels after processing. The wavelength of light that can pass through each spectral channel is different. The light-splitting array on the surface of the entire photosensitive area is arranged periodically in a 1024×1024 array (i.e., m=1024). Figure 2 As shown, due to the excessive number of pixels on the entire die surface, the photosensitive area containing 64 pixels 1 is intercepted as an example, and the pixels 1 are arranged in an 8×8 array. Figure 2The figure is a schematic diagram of dividing the spectroscopic array and the spectroscopic unit on the surface of the bare chip under the conditions of n=2 and a=1. It can be seen from the figure that the spectroscopic array is arranged in an array, and each spectroscopic array includes four spectroscopic units (i.e., the first spectroscopic unit 101, the second spectroscopic unit 102, the third spectroscopic unit 103, and the fourth spectroscopic unit 104). A filter film stack can be deposited on each spectroscopic unit to form a spectral channel 3, and each spectral channel 3 passes light of a predetermined band.

[0047] S3: Design a second mask, which is designed to cover the first splitter unit 101 in the first splitter array 10 in the photosensitive area. Cover the second mask on the surface of the photosensitive area, and deposit an etch stop layer on the surface of the second mask using an electron beam evaporation thin film deposition process. The etch stop layer is a chromium thin film with a deposition rate of 0.2nm / s and a deposition thickness of 300nm. Remove the second mask. At this time, all areas in the photosensitive area except the first splitter unit 101 in the first splitter array 10 are covered with a chromium thin film. Deposit a first filter film stack in the photosensitive area using an electron beam evaporation thin film deposition process. The first filter film stack is formed by alternating Ta2O5 thin films and SiO2 thin films, with a total thickness of 3μm.

[0048] S4: Design a third mask, the third mask is designed to expose the first light splitting unit 101 in the first light splitting array 10 in the photosensitive area and cover other photosensitive areas except the first light splitting unit 101 in the first light splitting array 10, cover the third mask on the surface of the bare chip, deposit a chrome mask layer in the photosensitive area using an electron beam evaporation thin film deposition process, and then remove the third mask, the thickness of the chrome mask layer deposited in the photosensitive area is 300nm, and etch the first filter film stack using an inductively coupled ion beam etching process until the chrome film is etched. Under the protection of the chrome mask layer, the first filter film stack deposited on the first light splitting unit 101 will not be etched away, and the first filter film stacks in other areas will not be etched away. The optical film stacks are all etched away, leaving only a chromium film on the surface of the bare chip except for the first optical splitter unit 101 in the first optical splitter array 10. The gas used for etching is CF4 gas, and the etching rate is 50nm / min. Then, the chromium mask layer and the chromium film in other areas on the surface of the first optical splitter unit 101 in the first optical splitter array 10 are removed by an inductively coupled plasma etching process. A chlorine-based gas is selected as the etching gas. After removing the chromium mask layer and the chromium film, the surface of the photosensitive area except for the first optical splitter unit 101 in the first optical splitter array 10 is exposed to pixels, and the surface of the first optical splitter unit 101 in the first optical splitter array 10 is covered with the first filter film stack to form a spectral channel.

[0049] S5: Repeat steps S3 to S4, repeat 3 (i.e. n 2-1, n=2) times, spectral channels are prepared on the second spectral unit 102, the third spectral unit 103 and the fourth spectral unit 104 of the first spectral array, respectively, each spectral channel is used to pass light of a predetermined wavelength. In this embodiment, the wavelength of light that can be passed by each spectral channel is different.

[0050] S6: Repeat steps S3 to S5, repeat 1048575 (i.e. m 2 -1, m=1024) times, each spectroscopic unit in other spectroscopic arrays in the photosensitive area prepares a corresponding spectral channel respectively, and the corresponding spectral channels in each spectroscopic array are arranged in the same manner.

[0051] S7: Remove the negative photoresist in the electrode area, clean the surface of the processed die with ethanol or acetone, and repackage it in the CMOS imaging chip.

[0052] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for producing pixel-level spectral splitting on a CMOS imaging chip, characterized in that: The following steps are involved: S1: taking out the bare die from the CMOS imaging chip, cleaning the bare die, designing a first mask according to the distribution of the electrode area and the photosensitive area on the surface of the bare die, wherein the first mask is designed to cover the photosensitive area, covering the first mask on the surface of the bare die, covering the electrode area with negative photoresist using a photolithography process, and removing the first mask; S2: dividing the surface of the photosensitive area into m×m periodically arranged light-splitting arrays, dividing each light-splitting array into n×n light-splitting units, each light-splitting unit corresponding to a×a pixels in the photosensitive area, wherein m, n and a are all integers greater than or equal to 1; S3: Design a second mask, wherein the second mask is designed to cover the first light splitting unit in the first light splitting array in the photosensitive area, cover the second mask on the surface of the photosensitive area, deposit an etch stop layer on the surface of the photosensitive area covered with the second mask by a thin film deposition process, remove the second mask, and deposit a first filter film stack on the photosensitive area by a thin film deposition process, wherein the first filter film stack is formed by alternating high refractive index material films and low refractive index material films, and the total thickness of the first filter film stack is 1 μm to 10 μm; S4: designing a third mask, wherein the third mask is designed to cover other photosensitive areas except the first light splitting unit in the first light splitting array, depositing a metal mask layer on the surface of the photosensitive area covering the third mask by using a thin film deposition process, then removing the third mask, etching the first filter film stack by using a chemical reaction ion beam etching process until the etching stops at the etching stop layer, removing the metal mask layer and the etching stop layer, and the first filter film stack left on the first light splitting unit constitutes a first spectral channel; S5: Repeat steps S3 to S4, repeat (n 2 -1) times, preparing spectral channels in other spectral units of the first spectral array, each spectral channel is used to pass light of a predetermined wavelength; S6: Repeat steps S3 to S5, repeat (m 2 -1) times, preparing spectral channels in other spectroscopic arrays in the photosensitive area respectively, and the corresponding spectral channels in each spectroscopic array are arranged in the same manner; S7: removing the photoresist in the electrode area, cleaning the surface of the processed die, and packaging the processed die into a CMOS imaging chip.

2. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The photolithography process in S1 includes spin coating of negative photoresist on the surface of the die, pre-baking, exposure, post-baking and development.

3. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 2, characterized in that: The rotation speed of spin coating negative photoresist is 1000 rpm to 5000 rpm, the pre-baking and post-baking temperatures are both 90° C. to 150° C., and the exposure time is 2s to 10s.

4. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The thin film deposition process in S3 is an electron beam evaporation thin film deposition process or a magnetron sputtering thin film deposition process.

5. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The etching stop layer in S3 is a metal film, the material of the metal film is chromium or aluminum, and the thickness of the metal film is 100nm to 500nm.

6. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The high refractive index material in S3 is Ta2O5 or TiO2 or HfO2, and the low refractive index material is SiO2 or Al2O3.

7. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The thickness of the metal mask layer in S4 is 100 nm to 500 nm.

8. The method for manufacturing pixel-level spectral splitting on a CMOS imaging chip according to claim 1, characterized in that: The gas used for etching in S4 is sulfur-based gas such as SF6 or CF4 or CHF3, and the etching rate is 10nm / min to 100nm / min.

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