Method for preparing crystalline silicon bottom cell of perovskite crystalline silicon tandem solar cell and cell

Abstract

The application discloses a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and the cell, and relates to the technical field of solar cells. x The method comprises the following steps: polishing both sides of a silicon wafer, diffusing boron on the back side, removing a front BSG layer, preparing a tunneling silicon oxide layer and a phosphorus-doped poly-silicon layer on the front side, depositing a mask SiOx layer on the front side, preparing a laser texturing, removing damage by etching, removing excess layers, depositing a film layer on the back side, and printing electrodes and sintering. The application effectively solves the problems of poor passivation performance of the front surface of the TOPCON bottom cell, parasitic absorption, and the contradiction between the light trapping structure and passivation and perovskite superposition, and improves the cell performance, which has important significance in the technical field of perovskite laminated solar cells.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and the cell. BACKGROUND

[0002] In the field of high-efficiency crystalline silicon cells, the tunnel oxide passivated contact solar cell (TOPCon) is based on the selective carrier principle. The cell structure is an n-type silicon substrate cell. The passivation contact structure formed by the ultra-thin silicon oxide and the doped polysilicon thin layer on the back surface effectively reduces the surface recombination and metal contact recombination, has the advantages of high minority carrier lifetime, high metal contamination tolerance, low attenuation, low surface recombination rate, etc., and becomes an ideal choice for the silicon bottom cell in the laminated cell.

[0003] At present, the perovskite crystalline silicon laminated solar cell technology is mostly constructed in a series mode. The crystalline silicon cell is used as the bottom cell, the perovskite is used as the top cell, and the two are connected by a composite layer or a tunnel layer. Light is incident from the perovskite end. However, the typical perovskite / TOPCon laminated solar cell has many defects. When the poly-Si / SiOx contact structure of the TOPCON cell is placed on the front surface of the bottom cell, the optical absorption characteristics of the polysilicon layer cause significant parasitic absorption, which reduces the photo-generated current density of the crystalline silicon layer sub-cell. In order to improve the photo-generated current density, the thickness of the polysilicon film is reduced, which will also make the passivation performance of the polysilicon layer worse, and reduce the open voltage of the perovskite laminated crystalline silicon cell as a whole. In addition, when the textured structure is made to enhance the light trapping ability of the crystalline silicon cell, on the one hand, the textured structure has a large recombination, which requires a thicker poly-silicon layer for passivation, which is contrary to the requirement of reducing the thickness of the poly-silicon layer; on the other hand, the height of the textured pyramid is high, which increases the difficulty of the surface superposition of the perovskite. SUMMARY

[0004] The present application is aimed at the above problems, makes up for the deficiencies of the prior art, and provides a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell and the cell to solve the problems in the background art.

[0005] The technical scheme of the present application is as follows: a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell, comprising the following steps:

[0006] S1: double-sided polishing of an N-type silicon wafer;

[0007] S2: boron diffusion on the back surface of the silicon wafer to form a boron-doped single-crystal silicon layer;

[0008] S3: removing the BSG layer on the front surface of the silicon wafer;

[0009] S4: preparing a tunnel silicon oxide layer and a phosphorus-doped poly-silicon layer on the front surface of the silicon wafer;

[0010] S5: removing the PSG layer on the front surface of the silicon wafer;

[0011] S6: depositing a mask SiO x layer on the front surface of the silicon wafer;

[0012] S7: performing laser texturing on the surface of the mask SiO x layer;

[0013] S8: removing the residual mask SiO x layer and the melted layer and damage on the surface of the phosphorus-doped poly-silicon layer after laser texturing, and the PSG layer on the back surface of the silicon wafer;

[0014] S9: removing the N-poly and BSG layers on the back surface of the silicon wafer;

[0015] S10: depositing a passivation and anti-reflective film on the back surface;

[0016] S11: printing the back electrode and sintering.

[0017] Further, the depth of the recess structure formed by the laser texturing in S7 is greater than the thickness of the mask SiO x layer in S6, and less than the sum of the thickness of the mask SiO x layer in S6 and the thickness of the phosphorus-doped poly-silicon layer in S4.

[0018] Further, the resistivity of the N-type silicon wafer in S1 is 0.5-5 Ω / cm 2 , and the thickness is 100-200 μm.

[0019] Preferably, the polishing treatment is a double-side alkaline polishing treatment of the N-type silicon wafer using any one of KOH, NaOH or TMAH.

[0020] Further, the temperature of the boron diffusion deposition in S2 is 800-1000 °C, the time is 20-60 minutes, the sheet resistance of the boron-doped single-crystal silicon layer is 200-400 Ω / cm 2 , and the thickness of the boron-doped single-crystal silicon layer is 0.5-1.5 μm.

[0021] Preferably, the boron diffusion is a boron diffusion on the back surface of the N-type silicon wafer using BCl3 as the boron diffusion source to form a boron-doped single-crystal silicon layer, which forms a PN junction with the N-type silicon wafer.

[0022] Further, the thickness of the tunnel oxide layer in S4 is 1-2 nm, the thickness of the phosphorus-doped poly-silicon layer is 20-100 nm, and the phosphorus doping concentration ranges from (0.1-2.0)E21.

[0023] Preferably, the through-oxide layer and the poly-silicon layer are prepared on the front surface of the N-type silicon wafer by using LPCVD, PECVD or PVD; then the silicon wafer is loaded into a tube of a tube-type phosphorus diffusion furnace, and phosphorus diffusion and annealing are performed on the back surface of the silicon wafer by using POCI3 diffusion, so that the phosphorus-doped poly layer is formed on the back surface of the silicon wafer.

[0024] Further, in the S6, the deposition temperature is 500-600℃, the deposition time is 20-60min, the mask SiO x layer has a thickness of 100-300nm.

[0025] Preferably, the deposition process is any one of LPCVD, PECVD or PVD.

[0026] Further, in the S7, the single-pulse energy of the laser is 80-100uj, the pulse frequency is 1000-3000kHz, the scanning speed is 30000-50000mm / s, and the scanning times is 1.

[0027] Preferably, the laser texturing is performed on the surface of the mask SiO x layer by using a picosecond laser to prepare an array hole light-trapping structure, the hole distance is 0-60μm, and the reflectivity is 5-15%.

[0028] Further, the S8 is an isotropic etching process, and an etching solution with HF mass fraction of 10-60wt% and HNO3 mass fraction of 20-80wt% is used to remove the residual mask SiO x layer and the molten layer and damage on the surface of the phosphorus-doped poly-silicon layer on the back surface within 2-5min, and the PSG layer on the back surface is also removed.

[0029] Further, the passivation and anti-reflection film in the S10 includes but is not limited to AlO x , SiN x and SiO x film.

[0030] The application further provides a perovskite / silicon stacked solar cell, wherein the crystalline silicon bottom cell is prepared by using the preparation method.

[0031] Further, the crystalline silicon bottom cell comprises an N-type silicon wafer, the front surface of the N-type silicon wafer comprises a tunneling silicon oxide layer and a phosphorus-doped poly-silicon layer in sequence, and the back surface of the N-type silicon wafer comprises a boron-doped single-crystal silicon layer, a passivation and anti-reflection film layer and a back electrode in sequence; and the surface of the phosphorus-doped poly-silicon layer has a light-trapping structure.

[0032] Compared with the prior art, the application has the following beneficial effects:

[0033] (1) The poly-Si / SiO2 passivation contact structure is prepared on the polished surface, the front surface recombination is reduced, the passivation performance of the battery is effectively improved, the phosphorus-doped poly-silicon layer is thin, the parasitic absorption of long-wave band is greatly reduced, and the effective utilization efficiency of light is improved; and the light trapping structure is prepared on the basis of the passivation contact structure by laser, the recombination problem caused by preparing the passivation structure after the texturing is avoided, in addition, a certain thickness of mask SiO x layer is deposited on the surface of the poly-Si / SiO2 passivation contact structure, the damage of the passivation contact structure caused by laser texturing is greatly reduced; and the residual mask SiO x layer is removed after the texturing, the light trapping structure is formed on the surface of the passivation contact structure, and the light incidence rate is also increased.

[0034] (2) Compared with the chemical etching texturing method, the array hole texturing structure prepared by laser is used, the surface topography of the silicon wafer is very uniform, and it is more conducive to depositing the perovskite layer on the surface. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments or prior art of the present application, the drawings needed in the embodiment or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0036] Figure 1 A preparation process flow chart of a perovskite crystalline silicon stacked solar cell crystalline silicon bottom cell is provided for embodiments 1-3 of the present application DETAILED DESCRIPTION

[0037] The technical solutions of the present application will be described in detail below in combination with specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0038] Embodiment 1

[0039] The present embodiment provides a preparation method of a perovskite crystalline silicon stacked solar cell crystalline silicon bottom cell, as shown in the figure, the preparation method comprises the following steps: Figure 1

[0040] S1: select a silicon wafer with a resistivity of 0.5 Ω / cm 2 ​N-type single crystal silicon wafer with thickness of 100 μm, double-side alkaline polishing treatment is performed using KOH to remove damaged layer and impurities on the surface of the wafer, so that the surface of the wafer is smooth and clean, and a good foundation is provided for subsequent processes;

[0041] S2: BCl3 is used as boron diffusion source to perform diffusion deposition process for 20 minutes at 800℃, so that boron atoms diffuse into the wafer to form boron-doped single crystal silicon layer and PN junction with the N-type wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are accurately controlled to ensure that the sheet resistance of the boron-doped single crystal silicon layer reaches 400 Ω / cm 2 , and the thickness is 0.5 μm, so as to achieve good electrical performance;

[0042] S3: removing the boron-doped single crystal silicon layer and BSG layer around the wafer surface and side surface;

[0043] S4: preparing tunneling silicon oxide layer and phosphorus-doped poly silicon layer on the front surface of the wafer; first, using LPCVD (low pressure chemical vapor deposition) method, growing tunneling oxide layer and poly layer with thickness of 1.0 nm on the front surface of the wafer; then loading the wafer into the tube of the tube furnace, using POCl3 diffusion to diffuse phosphorus on the back surface of the wafer and annealing, so that the back surface forms phosphorus-doped poly silicon layer with thickness of 20 nm, and the phosphorus doping concentration of the phosphorus-doped poly layer is 0.1E21, so as to ensure that the front surface of the wafer forms good poly-Si / SiO2 passivation contact structure;

[0044] S5: removing PSG layer on the front surface of the wafer to avoid interference with subsequent processes and cell performance;

[0045] S6: using PECVD technology to deposit mask SiO x layer on the front surface of the wafer, the deposition temperature is set at 500℃, the deposition time is 20 min, and the thickness of the mask SiO x layer is 100 nm; by adjusting the deposition parameters, the quality and thickness of the mask SiO x layer are obtained;

[0046] Due to the difficulty in controlling laser texturing, if the poly-Si / SiO2 passivation contact structure is directly textured, it will inevitably cause laser burn-through of the poly-Si layer. Considering that the phosphorus-doped poly silicon layer is thin, a mask SiO x layer with passivation effect and easy to clean is deposited on the surface of the phosphorus-doped poly silicon layer to protect the phosphorus-doped poly silicon layer during the process of preparing array hole textured surface by laser.

[0047] S7: Array hole velvet is prepared by picosecond laser, hole distance is controlled at 0 μm, reflectivity reaches 5%, single pulse energy is 80 uJ, pulse frequency is 1000 kHz, scanning speed is 50000 mm / s, scanning times is 1, effective light trapping structure is formed, and light absorption efficiency is improved;

[0048] S8: By isotropic etching mode, HF mass fraction is 10wt%, HNO3 mass fraction is 20wt%, and the etching solution is used to remove the residual mask SiO x layer and the phosphorus-doped poly-silicon layer surface, and the backside PSG layer is removed, and the surface quality is improved;

[0049] The depth of the concave structure formed by the laser texturing is between the thickness of the surface-deposited mask SiO x and the thickness of the film layer and the sum of the thickness of the phosphorus-doped poly-silicon layer, that is, the thickness of the poly-silicon layer removed by the laser texturing is 110 nm, so that after the molten layer and the damage left by the laser are removed, the light trapping structure can appear on the phosphorus-doped poly-silicon layer;

[0050] S9: The backside N-poly and BSG layer of the silicon wafer are removed, and the battery structure is further optimized;

[0051] S10: AlO x passivation film and SiN x antireflection film are deposited on the back surface, the stability and optical performance of the battery are improved;

[0052] S11: The back surface electrode is printed and sintered, so that the electrode and the silicon wafer form a good ohmic contact, and the electrical performance of the battery is ensured.

[0053] Embodiment 2

[0054] The embodiment provides a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell, as shown in the figure, the preparation method comprises the following steps: Figure 1

[0055] S1: An N-type monocrystalline silicon wafer with a resistivity of 5 Ω / cm 2 and a thickness of 200 μm is selected, and NaOH is used for double-side alkali polishing treatment to remove the damage layer and impurities on the surface of the silicon wafer, so that the surface of the silicon wafer is smooth and clean, and a good foundation is provided for subsequent processes;

[0056] ​S2: using BCl3 as boron diffusion source, diffusion deposition process is carried out at 1000℃ for 60 minutes, boron atoms diffuse into silicon wafer, PN junction is formed by boron-doped monocrystalline silicon layer and N-type silicon wafer. In this process, the flow, pressure and other parameters of the boron diffusion source are accurately controlled to ensure that the sheet resistance of the boron-doped monocrystalline silicon layer reaches 200Ω / cm 2 , the thickness is 1.5μm, so as to realize good electrical performance;

[0057] S3: removing the boron-doped monocrystalline silicon layer and BSG layer around the front and side of the above-mentioned silicon wafer;

[0058] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front of the above-mentioned silicon wafer; first, using the method of LPCVD (low pressure chemical vapor deposition), a tunneling oxide layer and a poly layer with a thickness of 2.0nm are grown on the front of the silicon wafer; then, the silicon wafer is loaded into a tube-type phosphorus diffusion furnace tube, and POCl3 diffusion is used to diffuse and anneal the back of the silicon wafer to form a phosphorus-doped poly silicon layer with a thickness of 100nm on the back, and the phosphorus doping concentration in the phosphorus-doped poly layer is 2.0E21, so as to ensure that a good poly-Si / SiO2 passivation contact structure is formed on the front of the silicon wafer;

[0059] S5: removing the PSG layer on the front of the silicon wafer to avoid interference with subsequent processes and cell performance;

[0060] S6: using PECVD technology to deposit a mask SiO x layer on the front of the silicon wafer, the deposition temperature is set at 600℃, the deposition time is 60min, and the thickness of the mask SiO x layer is 300nm; by adjusting the deposition parameters, the quality and thickness of the mask SiO x layer are obtained;

[0061] S7: using picosecond laser to prepare an array hole textured surface, the hole distance is controlled at 60μm, the reflectivity reaches 15%, the single pulse energy is 100uJ, the pulse frequency is 3000kHz, the scanning speed is 30000mm / s, and the scanning times is 1, so as to form an effective light trapping structure and improve the light absorption efficiency;

[0062] S8: using isotropic etching method, using an etching solution with HF mass fraction of 60wt% and HNO3 mass fraction of 80wt%, the melted layer and damage on the surface of the laser residual mask SiO x layer and phosphorus-doped poly silicon layer are removed within 5min, and the PSG layer around the back is also removed, so as to improve the surface quality;

[0063] The depth of the concave structure formed by the laser texturing is between the thickness of the surface-deposited mask layer and the sum of the thickness of the mask layer and the thickness of the phosphorus-doped poly-silicon layer, that is, the thickness of the poly-silicon layer removed by the laser texturing is 350 nm, so as to ensure that the molten layer and the damage layer left by the laser can be removed, and the light-trapping structure can be formed on the phosphorus-doped poly-silicon layer after the damage.

[0064] S9: removing the N-poly and the BSG layer around the back of the silicon wafer by plating, and further optimizing the battery structure;

[0065] S10: depositing SiN on the back x passivation film and SiO x antireflection film, improving the stability and optical performance of the battery;

[0066] S11: printing the back electrode and sintering, so that the electrode forms a good ohmic contact with the silicon wafer, and the electrical performance of the battery is ensured.

[0067] Embodiment 3

[0068] The embodiment provides a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell, as shown in the figure, the preparation method comprises the following steps: Figure 1 The preparation method comprises the following steps:

[0069] S1: selecting an N-type monocrystalline silicon wafer with a resistivity of 2 Ω / cm 2 , and a thickness of 150 μm, and performing double-side alkali polishing treatment on the wafer by using TMAH, so as to remove the damage layer and impurities on the surface of the wafer, and make the surface of the wafer smooth and clean, thereby providing a good foundation for subsequent processes;

[0070] S2: diffusing boron atoms into the silicon wafer by using BCl3 as a boron diffusion source and performing a diffusion deposition process at 900 ℃ for 40 minutes, so as to form a boron-doped monocrystalline silicon layer and form a PN junction with the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are accurately controlled, so that the sheet resistance of the boron-doped monocrystalline silicon layer reaches 300 Ω / cm 2 , and the thickness is 1.0 μm, thereby realizing good electrical performance;

[0071] S3: removing the boron-doped monocrystalline silicon layer and the BSG layer around the front and side of the above-mentioned silicon wafer;

[0072] S4: A tunneling silicon oxide layer and a phosphorus-doped poly silicon layer are prepared on the front side of the silicon wafer. First, a tunneling oxide layer and a poly layer with a thickness of 1.5 nm are grown on the front side of the silicon wafer using PVD (physical vapor deposition). Then, the silicon wafer is placed into a tube-type phosphorus diffusion furnace, and phosphorus diffusion is performed on the back side of the silicon wafer using POCl3 diffusion and annealing, so that a phosphorus-doped poly silicon layer with a thickness of 60 nm is formed on the back side. The phosphorus doping concentration in the phosphorus-doped poly layer is 1.0E21, ensuring that a good poly-Si / SiO2 passivation contact structure is formed on the front side of the silicon wafer.

[0073] S5: Remove the PSG layer on the front side of the silicon wafer to avoid its interference with subsequent processes and cell performance;

[0074] S6: Deposit masked SiO2 on the front side of the silicon wafer using PECVD technology. x The deposition temperature was set at 550℃, and the deposition time was 40 min. The mask was SiO₂. x The layer thickness is 200 nm; by adjusting the deposition parameters, a suitable mask SiO2 layer is obtained. x Layer quality and thickness;

[0075] S7: Picosecond laser is used to prepare an array of aperture textured surfaces with aperture spacing controlled at 30μm, reflectivity reaching 10%, single pulse energy of 90uJ, pulse frequency of 2000kHz, scanning speed of 40000mm / s, and one scan, forming an effective light-trapping structure and improving light absorption efficiency.

[0076] S8: Using isotropic etching methods, and employing an etching solution with 35wt% HF and 50wt% HNO3, remove the residual mask SiO2 after laser etching within 3 minutes. x The molten layer and damage on the surface of the phosphorus-doped polysilicon layer are removed, while the PSG layer on the back side is removed to improve surface quality.

[0077] In this process, the depth of the recessed structure formed by laser texturing is intermediate to that of the mask SiO2 deposited on the surface. x The thickness of the layer and the sum of the thickness of the film layer and the thickness of the phosphorus-doped poly silicon layer, i.e. the thickness of the poly silicon layer removed by laser texturing is 230 nm, to ensure that after removing the molten layer and damage left by the laser, a light-trapping structure can appear on the phosphorus-doped poly silicon layer.

[0078] S9: The N-poly and BSG layers coated on the back are removed to further optimize the battery structure;

[0079] S10: SiO2 deposited on the back side x passivation film and SiN x Anti-reflective coatings improve the stability and optical performance of the battery;

[0080] S11: printing back electrode and sintering, forming good ohmic contact between electrode and silicon wafer, ensuring electrical performance of the battery.

[0081] Example 4

[0082] The embodiment provides a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell, and the preparation method comprises the following steps:

[0083] S1: selecting an N-type monocrystalline silicon wafer with a resistivity of 5 Ω / cm and a thickness of 200 μm, performing double-side alkali polishing treatment on the wafer by using NaOH, so as to remove a damage layer and impurities on the surface of the wafer and make the surface of the wafer smooth and clean, thereby providing a good foundation for subsequent processes; 2

[0084] S2: adopting BCl3 as a boron diffusion source to perform a diffusion deposition process for 60 minutes at 1000 DEG C, so that boron atoms diffuse into the silicon wafer to form a boron-doped monocrystalline silicon layer and a PN junction formed by the boron-doped monocrystalline silicon layer and the N-type silicon wafer; in the process, the flow and pressure of the boron diffusion source are accurately controlled, so that the sheet resistance of the boron-doped monocrystalline silicon layer reaches 200 Ω / cm 2 , and the thickness is 1.5 μm, thereby realizing good electrical performance;

[0085] S3: removing the boron-doped monocrystalline silicon layer and the BSG layer around the wafer on the front surface and the side surface of the wafer;

[0086] S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly silicon layer on the front surface of the wafer; first, a PECVD (plasma enhanced chemical vapor deposition) method is used to grow a tunneling oxide layer and a poly layer with a thickness of 2.0 nm on the front surface of the wafer; then, the wafer is loaded into a tube-type phosphorus diffusion furnace tube, and a POCl3 diffusion method is used to diffuse and anneal the back surface of the wafer, so that a phosphorus-doped poly silicon layer with a thickness of 100 nm is formed on the back surface, and the phosphorus doping concentration of the phosphorus-doped poly layer is 2.0E21, thereby ensuring that a poly-Si / SiO2 passivation contact structure is formed on the front surface of the wafer;

[0087] S5: removing the PSG layer on the front surface of the wafer, so as to avoid interference with subsequent processes and battery performance;

[0088] S6: depositing a mask SiO x layer on the front surface of the wafer by using a PECVD technology, setting the deposition temperature at 600 DEG C, setting the deposition time as 60 min, and setting the thickness of the mask SiO x layer as 300 nm; the deposition parameters are adjusted to obtain appropriate quality and thickness of the mask SiO x layer;

[0089] ​S7: Array hole velvet is prepared by picosecond laser, hole distance is controlled at 60 μm, reflectivity reaches 15%, single pulse energy is 100 uJ, pulse frequency is 3000 kHz, scanning speed is 30000 mm / s, scanning times is 1, effective light trapping structure is formed, and light absorption efficiency is improved;

[0090] S8: By isotropic etching mode, HF mass fraction 60wt% and HNO3 mass fraction 80wt% etching solution is used, and the mask SiO x layer left after laser is removed within 5 min, and the PSG layer is removed, so that the surface quality is improved;

[0091] Wherein, the poly-silicon layer thickness removed in the laser texturing process is 410 nm;

[0092] S9: The N-poly and BSG layers on the back surface of the silicon wafer are removed, and the battery structure is further optimized;

[0093] S10: SiN x passivation film and SiO x are deposited on the back surface, and the reflectivity of the back surface is reduced, so that the stability and optical performance of the battery are improved;

[0094] S11: The back surface electrode is printed and sintered, so that the electrode and the silicon wafer form a good ohmic contact, and the electrical performance of the battery is ensured.

[0095] Embodiment 5

[0096] The embodiment provides a preparation method of a perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell, and the preparation method comprises the following steps:

[0097] S1: An N-type monocrystalline silicon wafer with a resistivity of 0.5 Ω / cm 2 , and a thickness of 100 μm is selected, KOH is used for double-side alkali polishing treatment, so that a damage layer and impurities on the surface of the silicon wafer are removed, the surface of the silicon wafer is smooth and clean, and a good foundation is provided for subsequent processes;

[0098] S2: BCl3 is used as a boron diffusion source, a diffusion deposition process is performed at 800 DEG C for 20 minutes, boron atoms are diffused into the silicon wafer, a boron-doped monocrystalline silicon layer is formed, and a PN junction is formed by the boron-doped monocrystalline silicon layer and the N-type silicon wafer. In this process, the flow rate, pressure and other parameters of the boron diffusion source are accurately controlled, so that the sheet resistance of the boron-doped monocrystalline silicon layer reaches 400 Ω / cm 2 , and the thickness is 0.5 μm, so that good electrical performance is achieved;

[0099] S3: The boron-doped monocrystalline silicon layer and the BSG layer around the above-mentioned silicon wafer front surface and side surface are removed;

[0100] S4: Tunneling silicon oxide layer and phosphorus-doped poly-silicon layer are prepared on the front surface of the above silicon wafer; first, a tunneling oxide layer and a poly layer with a thickness of 1.0 nm are grown on the front surface of the silicon wafer by using the method of LPCVD (low pressure chemical vapor deposition); then the silicon wafer is loaded into a tube of a tube-type phosphorus diffusion furnace, and the back surface of the silicon wafer is subjected to phosphorus diffusion by using POCl3 diffusion and annealing, so that a phosphorus-doped poly-silicon layer with a thickness of 20 nm is formed on the back surface, and the phosphorus doping concentration in the phosphorus-doped poly layer is 0.5E21, so as to ensure that a good poly-Si / SiO2 passivation contact structure is formed on the front surface of the silicon wafer;

[0101] S5: The PSG layer on the front surface of the silicon wafer is removed to avoid interference with subsequent processes and cell performance;

[0102] S6: A mask SiO x layer is deposited on the front surface of the silicon wafer by using the LPCVD technology, the deposition temperature is set to 500°C, the deposition time is 20 min, and the thickness of the mask SiO x layer is 100 nm; by adjusting the deposition parameters, the quality and thickness of the mask SiO x layer are obtained;

[0103] S7: Array hole texturing is prepared by using picosecond laser, the hole distance is controlled to be 0 μm, the reflectivity reaches 5%, the single pulse energy is 80 uJ, the pulse frequency is 1000 kHz, the scanning speed is 50000 mm / s, the scanning times is 1, an effective light trapping structure is formed, and the light absorption efficiency is improved;

[0104] S8: By using the isotropic etching method, the etching solution with HF mass fraction of 10 wt% and HNO3 mass fraction of 20 wt% is used to remove the residual mask SiO x layer and the molten layer and damage on the surface of the phosphorus-doped poly-silicon layer after laser texturing within 2 min, and the PSG layer on the back surface is also removed, so as to improve the surface quality;

[0105] The thickness of the poly-silicon layer removed during the laser texturing process is 90 nm;

[0106] S9: The N-poly and BSG layers on the back surface of the silicon wafer are removed to further optimize the cell structure;

[0107] S10: AlO x passivation film and SiN x anti-reflection film are deposited on the back surface to improve the stability and optical performance of the cell;

[0108] S11: The back surface electrode is printed and sintered, so that a good ohmic contact is formed between the electrode and the silicon wafer, and the electrical performance of the cell is ensured.

[0109] Comparative Example 1

[0110] The difference between the present comparative example and example 1 is that the positive surface deposition mask SiO of S6 is not used x The laser texturing process of S7 is directly performed after the layer process, and the remaining preparation methods and parameters remain the same as those of example 1.

[0111] Comparative example 2

[0112] The difference between the present comparative example and example 1 is that the chemical etching texturing process of S7 is used instead of the laser texturing, and the remaining preparation methods and parameters remain the same as those of example 1.

[0113] Comparative example 3

[0114] The difference between the present comparative example and example 1 is that the laser texturing process of S7 is performed first, and then the process of forming the poly-Si / SiO2 passivation contact structure of S4 is performed, and the remaining preparation methods and parameters remain the same as those of example 1.

[0115] Performance test

[0116] The perovskite crystalline silicon laminated solar cell crystalline silicon bottom cell prepared by examples 1-5 and comparative examples 1-3 is subjected to electrical performance test.

[0117] The test method is to use an IV tester to measure the parameters of the solar cell sheet, and the results are shown in Table 1.

[0118] Table 1: Test results of example and comparative example cell

[0119]

[0120] Performance test data conclusion analysis:

[0121] From the above table, by preparing the poly-Si / SiO2 passivation contact structure first, and then depositing a certain thickness of mask SiO on the surface of the passivation contact structure x , and then performing the laser texturing process, the problem of optical parasitic absorption and current loss caused by the thick poly silicon layer in the prior art is effectively solved. In addition, the silicon bottom cell prepared based on the preparation method provided by the present application has excellent conversion efficiency.

[0122] Firstly, compared with example 4, the surface N-poly of examples 1-3 has good passivation effect, and the prepared cell has higher open voltage and conversion efficiency; compared with example 5, the surface texturing structure of example 1 has lower reflectivity, and the prepared cell has higher short-circuit current.

[0123] Secondly, by comparing example 1 and comparative examples 1-3, the positive surface deposition mask SiO of S6 is not used in comparative example 1 xThe laser texturing process can cause deep damage to the N-poly structure, reduce the passivation effect of the N-poly, and result in a low open-circuit voltage of the prepared battery; in the comparative example 2, the S7 uses a chemical etching texturing process instead of the laser texturing process, and since the chemical process has a fast reaction speed and is difficult to control, the passivation layer can be damaged, resulting in a very low open-circuit voltage; in the comparative example 3, the texturing is performed first and then the passivation contact structure is prepared, which causes too much damage to the surface of the silicon wafer, resulting in a low open-circuit voltage of the prepared battery.

[0124] The poly-Si / SiO2 passivation contact structure is prepared on the polished surface first, so as to minimize the recombination of the front surface, and the phosphorus-doped poly-silicon layer has a very thin thickness, which greatly reduces the parasitic absorption of long-wave bands; then the light-trapping structure is prepared by laser on the basis of the poly-Si / SiO2 passivation contact structure, which avoids the recombination problem caused by the texturing performed first and then the passivation structure prepared; meanwhile, the array hole texturing structure is prepared by laser, so that the surface morphology of the silicon wafer is very uniform, which is more conducive to the deposition of the perovskite layer on the surface in the later stage; in addition, considering the problem of the thin thickness of the phosphorus-doped poly-silicon layer, a film layer with passivation effect and easy to clean, i.e., a mask SiO x layer, is deposited on the surface of the phosphorus-doped poly-silicon layer, which protects the phosphorus-doped poly-silicon layer during the laser preparation of the array hole texturing structure, avoids the laser burning through the poly-silicon layer, reduces the reflectivity of sunlight, and the depth of the recess structure formed after the laser texturing needs to be between the thickness of the deposited mask SiO x layer and the sum of the thickness of the deposited mask SiO x layer and the thickness of the phosphorus-doped poly-silicon layer, so as to ensure that the light-trapping structure appears on the phosphorus-doped poly-silicon layer after removing the molten layer and damage left by the laser, and increase the light incidence.

[0125] The above further describes the present application by means of specific examples, but it should be understood that the specific description herein should not be understood as limiting the essence and scope of the present application, and various modifications made to the above examples by those skilled in the art after reading the present specification are within the scope of the present application.

Claims

1. A method for preparing a crystalline silicon bottom cell of a perovskite crystalline silicon tandem solar cell, characterized by, The method comprises the following steps: S1: polishing the N-type silicon wafer on both sides; S2: diffusing boron on the back side of the silicon wafer to form a boron-doped monocrystalline silicon layer; S3: removing the BSG layer on the front side of the silicon wafer; S4: preparing a tunneling silicon oxide layer and a phosphorus-doped poly-silicon layer on the front side of the silicon wafer; S5: removing the PSG layer on the front side of the silicon wafer; S6: depositing a mask SiO on the front side of the silicon wafer x layer; S7: laser texturing the surface of the mask SiO x layer; S8: Remove the residual mask SiO after laser x melting of the surface layer and phosphorous doped polysilicon layer and damage to the backside PSG layer; S9: removing the N-poly and BSG layers on the back side of the silicon wafer; S10: depositing a passivation and anti-reflection film on the back side of the silicon wafer; S11: printing the back electrode and sintering; In the S7, the depth of the concave structure formed by laser texturing is greater than the thickness of the SiO x masking layer in the S6 x The sum of the thickness of the SiO masking layer in the S6 and the thickness of the phosphorus-doped poly-silicon layer in the S4 is less than the depth of the light-trapping structure on the phosphorus-doped poly-silicon layer.

2. The production method according to claim 1, characterized by, The N-type silicon wafer in S1 has a resistivity of 0.5-5 Ω / cm² and a thickness of 100-200 μm.

3. The preparation method according to claim 1, characterized in that, The temperature of the boron diffusion deposition in S2 is 800-1000℃, the time is 20-60 minutes, the sheet resistance of the boron-doped monocrystalline silicon layer is 200-400Ω / cm 2 , and the thickness of the boron-doped monocrystalline silicon layer is 0.5-1.5μm.

4. The preparation method according to claim 1, characterized in that, The tunneling oxide layer in S4 has a thickness of 1-2 nm; the phosphorus-doped poly-silicon layer has a thickness of 20-100 nm and a phosphorus doping concentration of (0.1-2.0)E21.

5. The method of claim 1, wherein, The deposition temperature in the S6 is 500-600℃, the deposition time is 20-60 min, and the mask SiO x The thickness of the layer is 100-300 nm.

6. The method of claim 1, wherein, The laser in S7 has a single-pulse energy of 80-100 μj, a pulse frequency of 1000-3000 kHz, a scanning speed of 30000-50000 mm / s, and a scanning frequency of 1.

7. The preparation method according to claim 1, characterized in that, The S8 is to remove the residual mask SiO2 after laser by using isotropic etching method with etching solution of HF mass fraction 10-60wt% and HNO3 mass fraction 20-80wt% within 2-5min x The molten layer and damage of the surface of the phosphorus-doped poly-silicon layer and the backside sputtered PSG layer are removed simultaneously.

8. A crystalline silicon base cell characterized by, The crystalline silicon bottom cell is prepared by the method in any one of claims 1 to 7 and is applied to a perovskite crystalline silicon laminated solar cell.

9. The crystalline silicon bottom cell of claim 8, wherein, The crystalline silicon bottom cell comprises: The N-type silicon wafer has a front side comprising a tunneling silicon oxide layer and a phosphorus-doped poly-silicon layer in sequence and a back side comprising a boron-doped monocrystalline silicon layer, a passivation and anti-reflection film layer, and a back electrode in sequence; and the surface of the phosphorus-doped poly-silicon layer has light-trapping structures.

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