Display device

Abstract

The invention relates to a display device. The display device includes: a display panel including a circuit element layer and a light emitting element layer on the circuit element layer; and a first light conversion layer, a second light conversion layer, and a light transmission layer on the display panel and spaced apart from each other. The light emitting element layer includes: a pixel defining layer defining a light emitting opening overlapping the first light conversion layer, the second light conversion layer, and the light transmission layer; a plurality of light emitting elements disposed in the light emitting openings, respectively; and a blocking wall on the pixel defining layer, the color of the blocking wall being black. When viewed from above the plane, the barrier wall is located between light emitting elements adjacent to each other among the plurality of light emitting elements, and extends parallel to side portions of the adjacent light emitting elements facing each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0113138 filed in the Korean Intellectual Property Office on August 28, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0004] A multimedia display device (such as a television, a mobile phone, a tablet, a computer, a car navigation unit, a game console, etc.) may include a display panel for displaying an image. The display panel may include a plurality of pixels for displaying an image, and each of the pixels may include a light-emitting element for generating light and a driving element connected to the light-emitting element.

[0005] A display device including a light conversion layer and a light transmission layer to improve color purity is being developed. The light conversion layer and the light transmission layer are arranged on the light emitting element of the pixel. The light conversion layer converts the light generated by the light emitting element of the pixel into light with a different wavelength. The light transmission layer transmits the light generated by the light emitting element of the pixel. Each of the light conversion layer and the light transmission layer is arranged to overlap with the light emitting element of the corresponding pixel among the pixels. Each of the light conversion layers includes quantum dots and resin for converting the wavelength of light. The light transmission layer includes a scatterer and a resin. Summary of the invention

[0006] According to an aspect of an embodiment of the present disclosure, a display device having improved color purity is provided.

[0007] According to one or more embodiments, a display device includes: a display panel including a circuit element layer and a light-emitting element layer on the circuit element layer; and a first light conversion layer, a second light conversion layer, and a light transmission layer on the display panel and spaced apart from each other. The light-emitting element layer includes: a pixel defining layer defining a light-emitting opening overlapping the first light conversion layer, the second light conversion layer, and the light transmission layer; a plurality of light-emitting elements, respectively arranged in the light-emitting openings; and a barrier wall located on the pixel defining layer, the color of the barrier wall being black. When viewed from above a plane, the barrier wall is located between light-emitting elements adjacent to each other among the plurality of light-emitting elements, and extends parallel to the sides of the adjacent light-emitting elements facing each other.

[0008] According to one or more embodiments, a display device includes: a display panel; and a first light conversion layer, a second light conversion layer, and a light transmission layer, which are arranged on the display panel and spaced apart from each other. The display panel includes: a pixel defining layer, which defines a plurality of pixel openings; a first light emitting element, which is arranged in the pixel opening and overlaps with the first light conversion layer; a second light emitting element, which is arranged in the pixel opening and overlaps with the second light conversion layer; a third light emitting element, which is arranged in the pixel opening and spaced apart from the first light emitting element in a first direction and overlaps with the light transmission layer; and a blocking wall, which is located between the first light emitting element and the third light emitting element. When viewed from above a plane, the length of the blocking wall in a second direction intersecting the first direction is longer than the length of the first light emitting element in the second direction and the length of the third light emitting element in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, objects and features of the present disclosure will become more apparent by describing some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0010] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0011] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0012] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0013] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0014] Figure 5A is an enlarged plan view of a display area according to an embodiment of the present disclosure.

[0015] Figure 5B is an enlarged plan view of a display area according to another embodiment of the present disclosure.

[0016] Figure 6 It is along Figure 5A A cross-sectional view taken along line II'.

[0017] Fig. 7A is a cross-sectional view of a display device according to a comparative example.

[0018] Figure 7B is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0019] FIG. 8A to FIG. 8C It is a view used to explain the purity of color.

[0020] Fig. 9is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0021] Fig.10 is a cross-sectional view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] From the following description of the embodiments given in conjunction with the accompanying drawings, the above and other aspects, features and advantages of the present disclosure will become apparent. However, the present disclosure is not limited to the embodiments disclosed herein and can be implemented in various different forms. In this article, some embodiments are provided to provide a complete disclosure of the present disclosure and to provide a thorough understanding of the present disclosure to those skilled in the art to which the present disclosure belongs, and the scope of the present disclosure is set forth by the attached claims and their equivalents. The same reference numerals always represent the same elements.

[0023] When an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes each of the referenced items and all combinations of one or more of these items.

[0024] Spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used to easily describe the relationship of one element or component to another element or component as shown in the drawings. Spatially relative terms will be understood to include terms for different orientations of an element during use or operation in addition to the orientation shown in the drawings. Like reference numerals refer to like elements throughout.

[0025] Although the terms "first", "second", etc. are used herein to describe various elements, components and / or sections, these elements, components and / or sections are not limited by these terms. These terms are used to distinguish one element, component or section from another element, component or section. Therefore, within the spirit and scope of the present disclosure, the first element, first component or first section mentioned below may be referred to as the second element, second component or second section.

[0026] The embodiments described herein will be described with reference to plan views and cross-sectional views, which may be idealized schematic views of the present disclosure. Therefore, the form of the illustrative drawings may change according to manufacturing techniques and / or allowable errors. The embodiments of the present disclosure are not limited to the specific forms illustrated, but include formal changes produced according to the manufacturing process. The areas shown in the drawings have schematic characteristics, and the shapes of the areas shown in the drawings may illustrate specific forms of the areas of the device and are not intended to limit the scope of the present disclosure.

[0027] Herein, some embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings.

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure; and Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0029] refer to Figure 1 In an embodiment, the display device DD may have a rectangular shape having long sides extending in a first direction DR1 and short sides extending in a second direction DR2 crossing the first direction DR1. However, not limited thereto, the display device DD may have any of various shapes such as a circular shape, other polygonal shapes, etc.

[0030] Herein, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, the expression "when viewed from above a plane" used herein may mean that it is viewed in the third direction DR3.

[0031] The display device DD may display an image through a display surface DD-IS. The display surface DD-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An upper surface of an uppermost member of the display device DD relative to a third direction DR3 may be defined as the display surface DD-IS. In addition, a front surface (or upper surface) and a rear surface (or lower surface) of a layer or unit to be described below may be distinguished from each other based on the third direction DR3.

[0032] The display device DD (or display surface DD-IS) may include a display area DA and a non-display area NDA. The unit pixel PXU may be disposed in the display area DA and may not be disposed in the non-display area NDA. The non-display area NDA may be defined along the periphery of the display surface DD-IS. In an embodiment, the non-display area NDA may surround the display area DA. However, in an embodiment of the present disclosure, the non-display area NDA may be omitted or may be disposed only on one side of the display area DA. Figure 1 A flat type display device DD is shown. However, the display device DD may have a curved shape, or may be foldable, rollable, or slidable from a housing.

[0033] Figure 1 The unit pixel PXU shown may define pixel rows and pixel columns. Each of the unit pixels PXU may be a minimum repeating unit. The unit pixel PXU may include at least one pixel. The unit pixel PXU may include a plurality of pixels providing light of different colors.

[0034] refer to Figure 2 , the display device DD may include a display panel DP and a light control layer OP, the light control layer OP facing the display panel DP and spaced apart from the display panel DP. The display panel DP may be referred to as a lower display substrate, and the light control layer OP may be referred to as an upper display substrate. A cell gap may be formed between the display panel DP and the light control layer OP. The cell gap may be maintained by a sealing member SLM that couples the display panel DP and the light control layer OP. The sealing member SLM may include a binder resin and an inorganic filler mixed in the binder resin. The sealing member SLM may also include other additives. The additives may include an amine-based curing agent and a photoinitiator. The additives may further include a silane additive and an acrylic additive. In an embodiment, the sealing member SLM may include an inorganic material such as glass frit.

[0035] In each of the display panel DP and the light control layer OP, a display area DA and a non-display area NDA corresponding to the display area DA and the non-display area NDA of the display device DD may be defined. Here, the display area DA of the display device DD may represent the display area DA of each of the display panel DP and the light control layer OP, and the non-display area NDA of the display device DD may represent the non-display area NDA of each of the display panel DP and the light control layer OP.

[0036] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0037] refer to Figure 3 , showing an arrangement relationship between the signal lines GL1 to GLm and DL1 to DLn and the pixels PX11 to PXmn on a plane. The signal lines GL1 to GLm and DL1 to DLn may include a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn.

[0038] Each of the pixels PX11 to PXmn may be connected to a corresponding gate line among a plurality of gate lines GL1 to GLm and a corresponding data line among a plurality of data lines DL1 to DLn. Each of the pixels PX11 to PXmn may include a pixel driving circuit and a light emitting element. Depending on the configuration of the pixel driving circuit of the pixels PX11 to PXmn, the display panel DP may include more types of signal lines. For example, each of the gate lines GL1 to GLm may include a corresponding scan line SCLi (refer to Figure 4 ) and the corresponding sensing line SSLi (reference Figure 4 ).

[0039] The gate driving circuit GDC may be integrated into the display panel DP by an oxide semiconductor gate driving circuit (OSG) process or an amorphous silicon gate driving circuit (ASG) process. The gate driving circuit GDC connected to the gate lines GL1 to GLm may be disposed on one side of the non-display area NDA in the first direction DR1. The pad PD connected to the end of the plurality of data lines DL1 to DLn may be disposed on one side of the non-display area NDA in the second direction DR2.

[0040] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0041] refer to Figure 4 , a pixel PXij connected to the i-th scan line SCLi, the i-th sensing line SSLi, the j-th data line DLj and the j-th reference line RLj is shown as an example. The pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of transistors T1, T2 and T3 and a capacitor Cst. The plurality of transistors T1, T2 and T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Although the plurality of transistors T1, T2 and T3 are described as N-type transistors, at least one of the transistors T1, T2 and T3 may be implemented as a P-type transistor.

[0042] In the embodiment, a pixel circuit PC including a first transistor T1, a second transistor T2, a third transistor T3 and a capacitor Cst is shown as an example. However, the pixel circuit PC is not limited thereto. The first transistor T1 may be a driving transistor, the second transistor T2 may be a switching transistor, and the third transistor T3 may be a sensing transistor. The pixel circuit PC may further include another transistor, or may further include another capacitor.

[0043] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may emit light by receiving the first voltage ELVDD and the second voltage ELVSS.

[0044] The first transistor T1 may include a drain electrode D1 receiving the first voltage ELVDD, a source electrode S1 connected to the anode of the light emitting element OLED, and a gate electrode G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from the first voltage ELVDD to the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0045] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 receiving the i-th first scan signal SCi. The j-th data line DLj may receive the data voltage Vd. The second transistor T2 may provide the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0046] The third transistor T3 may include a source S3 connected to the jth reference line RLj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th second scan signal SSi. The jth reference line RLj may receive a reference voltage Vr. The third transistor T3 may initialize the capacitor Cst and the anode of the light emitting element OLED.

[0047] The capacitor Cst may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and the first voltage ELVDD. The capacitor Cst may be connected to the gate G1 of the first transistor T1 and the anode of the light emitting element OLED.

[0048] Figure 5A is an enlarged plan view of a display area according to an embodiment of the present disclosure. Figure 5B is an enlarged plan view of a display area according to another embodiment of the present disclosure.

[0049] Figure 5B The description will focus on Figure 5A The difference.

[0050] refer to Figure 5A and Figure 5B , the display area DA may include a plurality of unit pixels PXU and a peripheral area NPXA. The unit pixels PXU may be arranged in a first direction DR1 and a second direction DR2. Figure 5A 6 unit pixels PXU are shown as an example, but the number of the unit pixels PXU is not limited thereto. Here, one unit pixel PXU among the plurality of unit pixels PXU will be described.

[0051] The unit pixel PXU may include a first pixel, a second pixel, and a third pixel that emit light of different colors. The first pixel, the second pixel, and the third pixel may output red light, green light, and blue light, respectively. Figure 5A, a first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B are illustrated with respect to a first pixel, a second pixel, and a third pixel, respectively. The first pixel region PXA-R may be a region through which light generated by the first pixel is provided to the outside, the second pixel region PXA-G may be a region through which light generated by the second pixel is provided to the outside, and the third pixel region PXA-B may be a region through which light generated by the third pixel is provided to the outside.

[0052] Although not shown, the first pixel may include a first light emitting element OLED1 (refer to Figure 6 ) and the first light conversion layer WCP1 (reference Figure 6 ). The second pixel may include a second light emitting element OLED2 (refer to Figure 6 ) and the second light conversion layer WCP2 (reference Figure 6 ). The third pixel may include a third light emitting element OLED3 (refer to Figure 6 ) and light transmission layer LCP (reference Figure 6 ). The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may correspond to the pixel regions through which the emission from the Figure 6 The light-emitting element OLED described herein provides a region of light. Figure 6 A further detailed description thereof is provided.

[0053] When viewed from above a plane, the first pixel region PXA-R and the second pixel region PXA-G may be arranged in a first diagonal direction DDR1. The first pixel region PXA-R and the third pixel region PXA-B may be arranged in a first direction DR1. The second pixel region PXA-G and the third pixel region PXA-B may be arranged in a second diagonal direction DDR2. The first diagonal direction DDR1 may be defined as a direction intersecting the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 may be defined as a direction intersecting the first diagonal direction DDR1. However, the arrangement of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B is not limited thereto, and the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be arranged in various forms.

[0054] In an embodiment, when viewed from above a plane, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape. However, not limited thereto, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have different shapes.

[0055] For example, when viewed from above a plane, the area of ​​the second pixel region PXA-G may be greater than the areas of the first pixel region PXA-R and the third pixel region PXA-B. When viewed from above a plane, the area of ​​the first pixel region PXA-R may be greater than the area of ​​the third pixel region PXA-B. That is, the second pixel region PXA-G may have the largest area, and the third pixel region PXA-B may have the smallest area.

[0056] However, Figure 5A and Figure 5B The illustrated embodiment is illustrative, and depending on the design of the display device DD, the shapes, areas, and arrangements of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may vary according to light emitting efficiency.

[0057] The peripheral region NPXA may be disposed to surround the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. In addition, the peripheral region NPXA may be disposed between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The peripheral region NPXA may set a boundary between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B.

[0058] refer to Figure 5A The unit pixel PXU may further include a barrier wall GB. The barrier wall GB may be disposed between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B.

[0059] In an embodiment, the barrier wall GB may include a first barrier wall GB1, a second barrier wall GB2, and a third barrier wall GB3. When viewed from above in a plane, the first barrier wall GB1 may be disposed between the first pixel region PXA-R and the third pixel region PXA-B disposed in the same unit pixel PXU.

[0060] The first barrier wall GB1 may extend in the second direction DR2. The first barrier wall GB1 may extend parallel to the sides of the first pixel region PXA-R and the third pixel region PXA-B. In an embodiment, the length of the first barrier wall GB1 in the second direction DR2 may be longer than the length of the first pixel region PXA-R and the length of the third pixel region PXA-B in the second direction DR2.

[0061] The second barrier wall GB2 may be disposed between the first pixel region PXA-R and the third pixel region PXA-B disposed in different unit pixels PXU. The second barrier wall GB2 may be disposed to overlap a boundary between unit pixels PXU adjacent to each other in the first direction DR1. The second barrier wall GB2 may be disposed between the first pixel region PXA-R in the first unit pixel disposed among the plurality of unit pixels PXU and the third pixel region PXA-B in the second unit pixel adjacent to the first unit pixel in the first direction DR1.

[0062] The second barrier wall GB2 may extend in the second direction DR2. The second barrier wall GB2 may extend parallel to the sides of the first pixel region PXA-R and the third pixel region PXA-B. The length of the second barrier wall GB2 in the second direction DR2 may be longer than the length of the first pixel region PXA-R and the length of the third pixel region PXA-B in the second direction DR2.

[0063] The third barrier wall GB3 may be disposed between the first pixel region PXA-R and the second pixel region PXA-G. The third barrier wall GB3 may be disposed between the third pixel region PXA-B and the second pixel region PXA-G. The third barrier wall GB3 may extend in the first direction DR1. The third barrier wall GB3 may extend parallel to the side of the second pixel region PXA-G.

[0064] The length of the third barrier wall GB3 in the first direction DR1 may be longer than the length of the second pixel region PXA-G in the first direction DR1. The length of the third barrier wall GB3 in the first direction DR1 may be longer than the length from the first side of the first pixel region PXA-R to the first side of the third pixel region PXA-B. The first side of the first pixel region PXA-R may be defined as a side facing away from the first pixel region PXA-R and facing the opposite side of the third pixel region PXA-B in the first direction DR1. The first side of the third pixel region PXA-B may be defined as a side facing away from the third pixel region PXA-B and facing the opposite side of the first pixel region PXA-R in the first direction DR1.

[0065] refer to Figure 5B The barrier wall GBa may include a first barrier wall GB1 and a second barrier wall GB2. However, the third barrier wall GB3 (refer to Figure 5A ).

[0066] The first barrier wall GB1 may be disposed between the first pixel region PXA-R and the third pixel region PXA-B disposed adjacent to each other in the first direction DR1 in one unit pixel PXU.

[0067] The second barrier wall GB2 may be disposed between the first pixel region PXA-R and the third pixel region PXA-B disposed in different unit pixels PXU. The second barrier wall GB2 may be disposed to overlap a boundary between the unit pixels PXU adjacent to each other in the first direction DR1.

[0068] Figure 6 It is along Figure 5A A cross-sectional view taken along line II'.

[0069] For ease of description, Figure 5A The first barrier wall GB1, the second barrier wall GB2 and the third barrier wall GB3 will be defined as barrier walls GB.

[0070] refer to Figure 6 , the display device DD may include a display panel DP and a light-controlling layer OP. The light-controlling layer OP may be disposed on the display panel DP.

[0071] The display panel DP may include a lower substrate SUB1, a circuit layer DP-CL, a light emitting element layer DP-OL, and an encapsulation layer TFE. In the step of manufacturing the display panel DP, an insulating layer, a semiconductor layer, and a conductive layer may be formed on the lower substrate SUB1 by processes such as coating, deposition, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. The semiconductor pattern, the conductive pattern, the signal line, etc. included in the display panel DP may be formed by the processes described above.

[0072] The lower substrate SUB1 may provide a base surface on which the circuit layer DP-CL is to be formed. The lower substrate SUB1 may have a single-layer structure or a multi-layer structure. For example, the lower substrate SUB1 having a multi-layer structure may include a synthetic resin layer and at least one inorganic layer disposed between the synthetic resin layers, or may include a glass substrate and a synthetic resin layer disposed on the glass substrate. However, the embodiment of the lower substrate SUB1 is not limited thereto.

[0073] The (multiple) synthetic resin layers included in the lower substrate SUB1 may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyamide resin, perylene-based resin, and polyimide resin. However, the material of the (multiple) synthetic resin layer is not limited to the above examples.

[0074] Although not shown, the circuit layer DP-CL may include a driving element constituting an equivalent circuit of a pixel. For example, the circuit layer DP-CL may include at least one insulating layer, a transistor connected to the light-emitting elements OLED1, OLED2, and OLED3 described below, at least one capacitor, and a signal line. A plurality of transistors may be provided. A plurality of transistors and capacitors may be connected together. The transistor may include a semiconductor pattern, and the semiconductor pattern may be arranged on a plane according to the configuration of the equivalent circuit of the pixel, such as according to a predetermined rule. The semiconductor pattern may include polycrystalline silicon, amorphous silicon, crystalline oxide, or amorphous oxide.

[0075] The light emitting element layer DP-OL may be disposed on the circuit layer DP-CL. The light emitting element layer DP-OL may include a plurality of first electrodes EL1, an emission layer EML, a second electrode EL2, and a pixel defining layer PDL.

[0076] The first electrode EL1 may be disposed on the circuit layer DP-CL. The first electrode EL1 may be an anode or a cathode. In addition, the first electrode EL1 may be a pixel electrode. The first electrode EL1 may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode.

[0077] The pixel defining layer PDL may be disposed on the circuit layer DP-CL. The pixel defining layer PDL may cover a portion of the first electrode EL1. A light emitting opening OH may be defined by the pixel defining layer PDL. The light emitting opening OH of the pixel defining layer PDL may expose at least a portion of the first electrode EL1.

[0078] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined as a portion corresponding to the first electrode EL1 exposed by the light emitting opening OH of the pixel defining layer PDL. The first emission area EA1 may correspond to the first pixel area PXA-R. The second emission area EA2 may correspond to the second pixel area PXA-G. The third emission area EA3 may correspond to the third pixel area PXA-B. The area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined as a non-emission area.

[0079] The expression "corresponding to" used herein means that when viewed in the thickness direction (e.g., third direction DR3) of the display device DD, two components overlap each other and are not limited to the same area. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may overlap with the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively.

[0080] The barrier wall GB may be disposed on the upper surface of the pixel defining layer PDL. In an embodiment, the barrier wall GB may include a black colorant. For example, the black colorant may include carbon black, a metal such as chromium, or an oxide thereof. However, the embodiment of the barrier wall GB is not limited thereto.

[0081] In an implementation, the barrier wall GB may have a thickness of 1 μm to 3 μm.

[0082] In an embodiment, the barrier wall GB includes a black colorant, and the barrier wall GB may thus absorb a portion of the light output from the light emitting element OLED. Fig. 7A A further detailed description thereof is provided.

[0083] The emission layer EML may be disposed on the first electrode EL1. The emission layer EML may be disposed on the pixel defining layer PDL and the barrier wall GB. The emission layer EML may be commonly disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area. The emission layer EML may be disposed in the light emitting opening OH. The emission layer EML may cover the pixel defining layer PDL and the barrier wall GB.

[0084] The emission layer EML may generate source light. In an embodiment, the emission layer EML may emit blue light. In the display device DD according to the embodiment, blue light may be defined as source light. When the emission layer EML is divided into corresponding to the first emission area EA1, the second emission area EA2, and the third emission area EA3, the emission layer EML may all emit blue light, or the first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit light in different wavelength ranges.

[0085] The emission layer EML may have a single-layer structure formed of a single material, a single-layer structure formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials. The emission layer EML may include a fluorescent material or a phosphorescent material. In the light-emitting element OLED according to the embodiment, the emission layer EML may include an organic light-emitting material, a metal organic complex or a quantum dot as a light-emitting material.

[0086] The second electrode EL2 may be disposed on the emission layer EML. The second electrode EL2 may cover the emission layer EML. The second electrode EL2 may be a common electrode. The second electrode EL2 may be a cathode or an anode, but the embodiment of the second electrode EL2 is not limited thereto. For example, when the first electrode EL1 is an anode, the second electrode EL2 may be a cathode, and when the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode.

[0087] refer to Figure 5A and Figure 6 The first electrode EL1, the portion of the emission layer EML disposed in the light emitting opening OH, and the portion of the second electrode EL2 disposed in the light emitting opening OH may be defined as a light emitting element OLED. The light emitting element OLED may be disposed in the light emitting opening OH.

[0088] When viewed from above a plane, a barrier wall GB may be disposed between adjacent pixel regions PXA-R, PXA-G, and PXA-B. The light-emitting element OLED may overlap with the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. Among the light-emitting elements OLED, the light-emitting element OLED overlapping with the first pixel region PXA-R may be defined as a first light-emitting element OLED1. Among the light-emitting elements OLED, the light-emitting element OLED overlapping with the second pixel region PXA-G may be defined as a second light-emitting element OLED2. Among the light-emitting elements OLED, the light-emitting element OLED overlapping with the third pixel region PXA-B may be defined as a third light-emitting element OLED3.

[0089] The barrier wall GB may be disposed between sides of the adjacent light emitting elements OLED facing each other when viewed from above a plane, and may extend parallel to the sides of the light emitting elements OLED.

[0090] Although not shown, the light emitting element OLED may further include a light emitting functional layer, such as a hole control layer and an electron control layer, which are disposed between the first electrode EL1 and the second electrode EL2. The hole control layer may be disposed between the first electrode EL1 and the emission layer EML, and may include at least one of a hole transport layer and a hole injection layer. The electron control layer may be disposed between the emission layer EML and the second electrode EL2, and may include at least one of an electron transport layer and an electron injection layer. The light emitting functional layer may be provided as a common layer, and may overlap with the pixel regions PXA-R, PXA-G, and PXA-B and the peripheral region NPXA.

[0091] refer to Figure 6 , the encapsulation layer TFE may be disposed on the light emitting element layer DP-OL. For example, the encapsulation layer TFE may be a thin film encapsulation layer. The encapsulation layer TFE may seal the light emitting element layer DP-OL. In an embodiment, the encapsulation layer TFE may include a first encapsulation film EN1, a second encapsulation film EN2, and a third encapsulation film EN3. The first encapsulation film EN1 may be disposed on the second electrode EL2 and may cover the second electrode EL2. The second encapsulation film EN2 and the third encapsulation film EN3 may be sequentially disposed on the first encapsulation film EN1.

[0092] In an embodiment, the first encapsulation film EN1 and the third encapsulation film EN3 may include an inorganic film, and the inorganic film may protect the light emitting element layer DP-OL from moisture and / or oxygen. For example, the inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but is not limited thereto.

[0093] In an embodiment, the second encapsulation film EN2 may include an organic film, and the organic film may protect the light emitting element layer DP-OL from foreign substances such as dust particles. For example, the organic film may include acrylic resin, but is not limited thereto.

[0094] The light control layer OP may be disposed on the display panel DP. In an implementation, the light control layer OP may include a light adjustment layer CCL, a first capping layer CP1, a filling member FL, a second capping layer CP2, a low refractive index layer LR, a color filter layer CFL, and an upper substrate SUB2.

[0095] The light adjustment layer CCL may be disposed on the encapsulation layer TFE. The light adjustment layer CCL may include a bank layer BK, a light transmission layer LCP, and a light conversion layer WCP.

[0096] The bank layer BK may be disposed on the upper surface of the third encapsulation film EN3. Figure 6 , a plurality of bank layers BK are shown, but the bank layers BK may be substantially integrally formed. The bank layers BK may overlap the peripheral area NPXA. The bank layers BK may overlap the pixel defining layer PDL and the barrier wall GB.

[0097] In an embodiment, the bank layer BK may include a black pigment and a waterproof material. In an embodiment, the bank layer BK includes a black pigment, and the bank layer BK may be black. Therefore, in order to prevent or substantially prevent color mixing between lights emitted from the light emitting element OLED, the bank layer BK may block light.

[0098] The bank layer BK may define first, second, and third control openings OPP1, OPP2, and OPP3.

[0099] The light transmission layer LCP may be disposed on the third encapsulation film EN3. The light transmission layer LCP may be disposed in the first control opening OPP1. The light transmission layer LCP may be disposed in the third pixel region PXA-B. The light transmission layer LCP may overlap the third emission region EA3.

[0100] The light transmission layer LCP may include a first base resin BR1 and a scatterer SR dispersed in the first base resin BR1. The scatterer SR may scatter light incident from the third light emitting element OLED3 disposed in the third emission area EA3 in various directions. The scatterer SR may be particles having a relatively high density or specific gravity. For example, the scatterer SR may include titanium oxide (TiO x ) or silica-based nanoparticles. The scatterer SR may improve the luminous efficiency of light provided from the third light emitting element OLED3 and transmitted through the light transmitting layer LCP.

[0101] The light transmitting layer LCP may provide source light (or blue light) provided from the third light emitting element OLED3, and the source light may pass through the light transmitting layer LCP and may be output toward the front surface of the display device DD.

[0102] The light conversion layer WCP may be disposed in the second control opening OPP2 and the third control opening OPP3. The light conversion layer WCP may be disposed on the display panel DP. The light conversion layer WCP and the light transmission layer LCP may be disposed on the same layer.

[0103] The light conversion layer WCP may overlap the first pixel region PXA-R and the second pixel region PXA-G. The light conversion layer WCP may overlap the first light emitting element OLED1 and the second light emitting element OLED2.

[0104] The light conversion layer WCP may include a first light conversion layer WCP1 and a second light conversion layer WCP2. The first light conversion layer WCP1 may be disposed in the second control opening OPP2. The second light conversion layer WCP2 may be disposed in the third control opening OPP3. When viewed from a cross-sectional view, the light transmission layer LCP and the first light conversion layer WCP1 and the second light conversion layer WCP2 may be arranged from right to left in the order of the light transmission layer LCP, the second light conversion layer WCP2, and the first light conversion layer WCP1.

[0105] The first light conversion layer WCP1 may be disposed in the first pixel region PXA-R. The first light conversion layer WCP1 may overlap the first light emitting element OLED1. The second light conversion layer WCP2 may be disposed in the second pixel region PXA-G. The second light conversion layer WCP2 may overlap the second light emitting element OLED2.

[0106] When viewed from a cross-sectional view, the width of the second light conversion layer WCP2 may be greater than the widths of the first light conversion layer WCP1 and the light transmission layer LCP. When viewed from a cross-sectional view, the width of the first light conversion layer WCP1 may be greater than the width of the light transmission layer LCP. That is, when viewed from a cross-sectional view, the second light conversion layer WCP2 may have a maximum width, and the light transmission layer LCP may have a minimum width.

[0107] The first light conversion layer WCP1 may include a second base resin BR2 and first quantum dots QD1 dispersed in the second base resin BR2. The second light conversion layer WCP2 may include a third base resin BR3 and second quantum dots QD2 dispersed in the third base resin BR3.

[0108] The cores of the quantum dots QD1 and QD2 included in the first light conversion layer WCP1 and the second light conversion layer WCP2 may be selected from any one of group II-VI compounds, group III-VI compounds, group I-III-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0109] The II-VI compound may be selected from the group consisting of: a binary compound selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a ternary compound selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe , CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0110] The III-VI compounds may include compounds such as In 2 S 3 or In 2 Se 3 Binary compounds such as InGaS 3 or InGaSe 3 or any combination thereof.

[0111] The I-III-VI group compound can be selected from a ternary compound or a quaternary compound, wherein the ternary compound is selected from AgInS, AgInS 2 、CuInS、CuInS 2 、AgGaS 2 、CuGaS 2 、CuGaO 2 、AgGaO 2 、AgAlO 2and mixtures thereof, quaternary compounds such as AgInGaS 2 or CuInGaS 2 .

[0112] The III-V compound may be selected from the group consisting of: a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; and a quaternary compound selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. The III-V compound may further include a Group II metal. For example, InZnP may be selected as the III-II-V compound.

[0113] The IV-VI compound may be selected from the group consisting of: a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from SiC, SiGe and mixtures thereof.

[0114] Elements included in multinary compounds such as binary compounds, ternary compounds, and quaternary compounds may exist in particles at uniform or non-uniform concentrations. That is, the chemical formula may represent the type of elements included in the compound, and the ratios of the elements in the compounds may be different from each other. For example, AgInGaS 2 Can mean AgIn x Ga 1-x S 2 (x is a real number between 0 and 1).

[0115] The quantum dot may have a single structure or a core-shell dual structure in which the concentration of an element included in the corresponding quantum dot is uniform. For example, a material included in the core and a material included in the shell may be different from each other.

[0116] In an embodiment, quantum dots QD1 and QD2 may have a core-shell structure including nanocrystals. The shell of each quantum dot may be used as a protective layer for maintaining semiconductor properties by preventing or substantially preventing chemical modification of the core, and / or may be used as a charging layer for imparting electrophoretic properties to the quantum dots. The shell may have a single layer or multiple layers. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center. The shell of the quantum dot may be, for example, a metal oxide, a non-metal oxide, a semiconductor compound, or a combination thereof.

[0117] For example, metal oxides and non-metal oxides may include binary compounds such as SiO 2 , AL 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 or NiO, or may include ternary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 or CoMn 2 O 4 , but the materials are not limited thereto.

[0118] The semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb, but the material is not limited thereto.

[0119] Elements included in multi-component compounds such as binary compounds and ternary compounds may exist in particles at uniform or non-uniform concentrations. That is, the chemical formula may represent the types of elements included in the compound, and the element ratios in the compounds may be different from each other.

[0120] In an embodiment, quantum dots QD1 and QD2 may have a full width at half maximum (FWHM) of a light emission wavelength spectrum of about 45 nm or less, and about 40 nm or less in an embodiment, and about 30 nm or less in an embodiment, and color purity or color reproducibility may be improved within this range. In addition, light emitted by quantum dots QD1 and QD2 may be emitted in all directions, and thus a wide viewing angle may be improved.

[0121] The form of the quantum dots QD1 and QD2 is not particularly limited to the form commonly used in the related art. For example, nanoparticles, nanotubes, nanowires, nanofibers or nanosheets having a spherical, pyramidal, multi-armed or cubic shape may be used.

[0122] The quantum dots QD1 and QD2 can adjust the color of the emitted light by adjusting the particle size or the element ratio in the compound. Therefore, the quantum dots QD1 and QD2 can have various luminescent colors such as blue, red and green. Therefore, the first quantum dot QD1 can convert the source light provided by the first light-emitting element OLED1 into red light having a wavelength range different from the wavelength range of the source light. Therefore, the display device DD can output red light through the first pixel area PXA-R.

[0123] The second quantum dot QD2 may convert the source light provided by the second light emitting element OLED2 into green light having a wavelength range different from that of the source light. Therefore, the display device DD may output green light through the second pixel region PXA-G.

[0124] The first capping layer CP1 may be disposed on the light regulating layer CCL. The first capping layer CP1 may cover the light regulating layer CCL. The first capping layer CP1 may cover the bank layer BK, the light transmitting layer LCP, and the light converting layer WCP.

[0125] The first capping layer CP1 may include an inorganic material. The first capping layer CP1 may prevent or substantially prevent moisture or foreign matter from penetrating into the light adjustment layer CCL.

[0126] The filling member FL may be disposed on the first capping layer CP1. The filling member FL may be disposed between the second capping layer CP2 and the first capping layer CP1 to be described below. The separation space between the first capping layer CP1 and the second capping layer CP2 may be filled with the filling member FL. However, not limited thereto, the filling member FL may be omitted.

[0127] The color filter layer CFL, the low refractive index layer LR, and the second capping layer CP2 may be sequentially disposed on the rear surface of the upper substrate SUB2 in the third direction DR3. The rear surface of the upper substrate SUB2 may be defined as a surface facing the upper surface of the lower substrate SUB1.

[0128] The second capping layer CP2 may be disposed on the lower surface of the low refractive index layer LR facing the display panel DP. In an embodiment, the second capping layer CP2 may include an inorganic material. The second capping layer CP2 may prevent or substantially prevent moisture or gas from penetrating into the low refractive index layer LR.

[0129] The low refractive index layer LR may be disposed between the second capping layer CP2 and the color filter layer CFL. The low refractive index layer LR may have a refractive index lower than that of the first light conversion layer WCP1 and the second light conversion layer WCP2 and the light transmission layer LCP. For example, the low refractive index layer LR may have a refractive index of 1.1 to 1.5. In an embodiment, the low refractive index layer LR may have a refractive index of 1.1 to 1.35. However, the refractive index of the low refractive index layer LR is not limited to the above numerical examples. The low refractive index layer LR may include a low refractive index organic film having a relatively low refractive index. The low refractive index layer LR may also include hollow particles and / or voids dispersed in the organic film. The refractive index of the low refractive index layer LR may be adjusted by the percentage of hollow particles and / or voids.

[0130] The low refractive index layer LR disposed above the light adjustment layer CCL can input light that is not converted by the light conversion layers WCP1 and WCP2 and output from the upper surfaces of the light conversion layers WCP1 and WCP2 into the light conversion layers WCP1 and WCP2 by using the refractive index of the low refractive index layer LR. The light input into the light conversion layers WCP1 and WCP2 by the low refractive index layer LR can be converted by the quantum dots QD1 and QD2. That is, the low refractive index layer LR can improve the luminous efficiency of the display device DD by recycling light using the refractive index of the low refractive index layer LR.

[0131] The low refractive index layer LR may include a material having high transmittance. For example, the low refractive index layer LR may have a high transmittance of 90% or more. Since the low refractive index layer LR has high transmittance, the transmittance of light output to the front surface of the display device DD may not be reduced.

[0132] The color filter layer CFL may be disposed on a surface of the upper substrate SUB2 facing the display panel DP. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. When viewed from above a plane, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed to correspond to the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. For example, the first color filter CF1 may overlap the first emission area EA1, the second color filter CF2 may overlap the second emission area EA2, and the third color filter CF3 may overlap the third emission area EA3.

[0133] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a base resin and a pigment or dye dispersed in the base resin. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may transmit light having a specific wavelength range and may absorb most of light having a wavelength range different from the specific wavelength range.

[0134] For example, the first color filter CF1 may include a red color filter, the second color filter CF2 may include a green color filter, and the third color filter CF3 may include a blue color filter. The red color filter may transmit red light and may absorb most of green light and blue light. The green color filter may transmit green light and may absorb most of red light and blue light. The blue color filter may transmit blue light and may absorb most of red light and green light.

[0135] The first color filter CF1 may overlap with the first light conversion layer WCP1. The first color filter CF1 may transmit red light provided from the first light conversion layer WCP1. For example, the first light conversion layer WCP1 may convert blue light provided from the first light emitting element OLED1 into red light, and the first color filter CF1 may transmit red light provided from the first light conversion layer WCP1. The first color filter CF1 may absorb green light and blue light incident toward the first color filter CF1. The first color filter CF1 may absorb a light beam that is not converted by the first light conversion layer WCP1 among the light beams incident toward the first color filter CF1, thereby preventing or substantially preventing degradation of color purity in the first pixel region PXA-R.

[0136] The second color filter CF2 may overlap with the second light conversion layer WCP2. The second color filter CF2 may transmit the green light provided from the second light conversion layer WCP2. For example, the second light conversion layer WCP2 may convert the blue light provided from the second light emitting element OLED2 into green light, and the second color filter CF2 may transmit the green light provided from the second light conversion layer WCP2. The second color filter CF2 may absorb the red light and the blue light incident toward the second color filter CF2. The second color filter CF2 may absorb the light beam that is not converted by the second light conversion layer WCP2 among the light beam incident toward the second color filter CF2, thereby preventing or substantially preventing the degradation of the color purity in the second pixel region PXA-G.

[0137] The third color filter CF3 may overlap with the light transmission layer LCP. The third color filter CF3 may transmit blue light provided from the light transmission layer LCP. For example, the light transmission layer LCP may transmit blue light provided from the third light emitting element OLED3, and the third color filter CF3 may transmit blue light provided from the light transmission layer LCP. The third color filter CF3 may absorb red light and green light incident toward the third color filter CF3, thereby preventing or substantially preventing degradation of color purity in the third pixel region PXA-B.

[0138] External light, such as natural light, may be incident from the outside of the display device DD toward the display panel DP. The external light may include red light, green light, and blue light. If the display panel DP does not include the color filter layer CFL, the external light incident toward the display panel DP may be reflected by the conductive pattern (e.g., signal line and electrode) in the display panel DP and may be provided to the user, and the user may visually recognize the reflected light.

[0139] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent or substantially prevent reflection of external light. For example, the first color filter CF1 can be a red color filter. The first color filter CF1 can filter external light into red light by absorbing light corresponding to green light and blue light in the external light. Similarly, the second color filter CF2 can be a green color filter. The second color filter CF2 can filter external light into green light by absorbing light corresponding to red light and blue light in the external light. The third color filter CF3 can be a blue color filter. The third color filter CF3 can filter external light into blue light by absorbing light corresponding to red light and green light in the external light.

[0140] In an embodiment, at least two of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap each other in the peripheral area NPXA. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to overlap each other in the third direction DR3 in the peripheral area NPXA. For example, the first color filter CF1 may be arranged below the third color filter CF3, and the second color filter CF2 may be arranged below the first color filter CF1.

[0141] The first color filter CF1, the second color filter CF2, and the third color filter CF3 disposed to overlap each other may extend over the bank layer BK and may overlap each other. The first color filter CF1, the second color filter CF2, and the third color filter CF3 disposed to overlap each other may block light passing through the peripheral area NPXA to prevent or substantially prevent color mixing between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B.

[0142] The upper substrate SUB2 may be disposed on the color filter layer CFL. The upper substrate SUB2 may include a glass substrate, a polymer substrate, or an organic / inorganic composite substrate. The upper substrate SUB2 may include a front surface and a rear surface parallel to the first direction DR1 and the second direction DR2. The rear surface of the upper substrate SUB2 may face the upper surface of the lower substrate SUB1. The upper substrate SUB2 may provide a base surface on which a component of the light control layer OP is stacked.

[0143] Fig. 7A is a cross-sectional view of a display device according to a comparative example. Figure 7B is a cross-sectional view of a display device according to an embodiment of the present disclosure. FIG. 8A to FIG. 8C It is a view used to explain the purity of color.

[0144] Figure 7B The display device DD and Figure 6 The display device DD is the same as that of FIG. 1 , and therefore, further description thereof will be omitted.

[0145] Except for omitting the barrier GB, Fig. 7A The display device DD' and Figure 7B The display device DD is the same as that of FIG. 1 , and thus a detailed description thereof will be omitted.

[0146] Although reference Fig. 7A and Figure 7B The case where light is output from the second light emitting element OLED2 is described, but the description can be applied to the first light emitting element OLED1 and the third light emitting element OLED3 in the same manner.

[0147] refer to Fig. 7A , light may be output from the light emitting element OLED. An angle formed by the light with respect to a vertical line SLP parallel to the third direction DR3 may be defined as a light output angle.

[0148] For example, light output from the second light emitting element OLED2 may be incident toward the second light conversion layer WCP2. Green light converted from blue light by the second light conversion layer WCP2 may pass through the second color filter CF2 and may be provided to the outside.

[0149] However, when the light output angle gradually increases, light output from the second light emitting element OLED2 may be incident toward the first light conversion layer WCP1, and red light converted by the first light conversion layer WCP1 may be incident toward the second pixel region PXA-G' or the third pixel region PXA-B'.

[0150] In addition, light output from the second light emitting element OLED2 may be incident to the light transmitting layer LCP, and blue light transmitted through the light transmitting layer LCP may be incident to the first pixel region PXA-R′ or the second pixel region PXA-G′.

[0151] Therefore, light from the pixel areas PXA-R', PXA-G', and PXA-B' may be mixed and provided to the outside, and thus color purity may be reduced.

[0152] However, reference Figure 7B , the display device DD according to an embodiment of the present disclosure includes a barrier wall GB. The barrier wall GB may include a black material. In an embodiment, the barrier wall GB includes a black material so that the barrier wall GB may absorb light. In an embodiment, for example, the barrier wall GB may have a light absorption rate of 0.01 / μm.

[0153] Light with a large light output angle may be absorbed by the blocking wall GB. Therefore, light with a large light output angle may not be incident to the first light conversion layer WCP1 or the light transmission layer LCP. Therefore, light with different colors may be provided to the outside without being mixed, so that color purity may be improved.

[0154] refer to FIG. 8A to FIG. 8C , Fig. 8A is a view showing the wavelength of red light provided to the outside by the unit pixel PXU. Figure 8B is a view showing the wavelength of green light provided to the outside by the unit pixel PXU. Figure 8C is a view showing the wavelength of blue light provided to the outside by the unit pixel PXU.

[0155] exist FIG. 8A to FIG. 8C In each of the graphs shown, the horizontal axis may represent wavelength, and the vertical axis may represent intensity.

[0156] The intensity of red light may be higher in the wavelength range of 580nm to 780nm than in other wavelength ranges. The intensity of green light may be higher in the wavelength range of 480nm to 580nm than in other wavelength ranges. The intensity of blue light may be higher in the wavelength range of 380nm to 540nm than in other wavelength ranges.

[0157] refer to Figure 5A , Fig. 7A , Figure 7B and Fig. 8A , Graph R1-1 is a graph depicting the wavelength of red light provided by the unit pixel PXU when there is no barrier wall GB. Graph R1-2 is a graph depicting the wavelength of red light provided by the unit pixel PXU when there is a barrier wall GB.

[0158] In the example showing the result of graph R1 - 1 , it can be seen that in addition to red light being output from the first pixel region PXA-R′, green light is output from the second pixel region PXA-G′, and blue light is output from the third pixel region PXA-B′.

[0159] In the embodiment according to the present disclosure showing the results of graph R1-2, it can be seen that since the light beam with a large light output angle among the light beams output from the first light emitting element OLED1 is absorbed by the blocking wall GB, the intensity of blue light and green light output from the unit pixel PXU is reduced.

[0160] refer to Fig. 7A , Figure 7B and Figure 8B , the graph G2-1 is a graph depicting the wavelength of green light provided by the unit pixel PXU when there is no barrier wall GB. The graph G2-2 is a graph depicting the wavelength of green light provided by the unit pixel PXU when there is a barrier wall GB.

[0161] In the example showing the result of graph G2-1, it can be seen that in addition to green light output from the second pixel region PXA-G', red light is output from the first pixel region PXA-R' and blue light is output from the third pixel region PXA-B'.

[0162] In the embodiment according to the present disclosure showing the results of graph G2-2, it can be seen that since the light beam with a large light output angle among the light beams output from the second light emitting element OLED2 is absorbed by the blocking wall GB, the intensity of the red light and blue light output from the unit pixel PXU is reduced.

[0163] refer to Fig. 7A , Figure 7B and Figure 8C , Graph B3-1 is a graph depicting the wavelength of blue light provided by the unit pixel PXU when there is no barrier wall GB. Graph B3-2 is a graph depicting the wavelength of blue light provided by the unit pixel PXU when there is a barrier wall GB.

[0164] In the example showing the result of graph B3-1, it can be seen that in addition to blue light output from the third pixel region PXA-B', red light is output from the first pixel region PXA-R' and green light is output from the second pixel region PXA-G'.

[0165] In the embodiment according to the present disclosure showing the results of graph B3-2, it can be seen that since the light beam with a large light output angle among the light beams output from the third light emitting element OLED3 is absorbed by the blocking wall GB, the intensity of the red light and green light output from the unit pixel PXU is reduced.

[0166] refer to FIG. 8A to FIG. 8C , through the graphs R1-1 to B3-2, it can be seen that the color purity of light provided to the outside through the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B increases.

[0167] Fig. 9 is a cross-sectional view of a display device DDa according to an embodiment of the present disclosure.

[0168] Fig. 9 The lower substrate SUB1, the circuit layer DP-CL, the light emitting element OLED, the pixel defining layer PDL and the light control layer OP can be connected with Figure 6 The lower substrate SUB1, the circuit layer DP-CL, the light emitting element OLED, the pixel defining layer PDL, and the light controlling layer OP are the same, and therefore, a description thereof will be omitted or will be briefly provided.

[0169] refer to Fig. 9 , the first electrode EL1 may be disposed on the circuit layer DP-CL. The first electrode EL1 may be an anode or a cathode. In addition, the first electrode EL1 may be a pixel electrode. The first electrode EL1 may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode.

[0170] The pixel defining layer PDL may be disposed on the circuit layer DP-CL. The pixel defining layer PDL may cover a portion of the first electrode EL1. A light emitting opening OH may be defined by the pixel defining layer PDL. The light emitting opening OH of the pixel defining layer PDL may expose at least a portion of the first electrode EL1.

[0171] The emission layer EML may be disposed on the first electrode EL1. The emission layer EML may be disposed on the pixel defining layer PDL. The emission layer EML may be commonly disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area. The emission layer EML may be disposed in the light emitting opening OH. The emission layer EML may cover the pixel defining layer PDL.

[0172] The second electrode EL2 may be disposed on the emission layer EML. The second electrode EL2 may cover the emission layer EML. The second electrode EL2 may be a common electrode. The second electrode EL2 may be a cathode or an anode, but the embodiment of the second electrode EL2 is not limited thereto. For example, when the first electrode EL1 is an anode, the second electrode EL2 may be a cathode, and when the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode.

[0173] The encapsulation layer TFE may be disposed on the second electrode EL2. In an implementation, the encapsulation layer TFE may include a first encapsulation film EN1, a second encapsulation film EN2, and a third encapsulation film EN3. The first encapsulation film EN1 may cover the second electrode EL2.

[0174] The barrier wall GBb may be disposed on the first encapsulation film EN1. The barrier wall GBb may be disposed on an upper surface of the first encapsulation film EN1 overlapping the pixel defining layer PDL. In an embodiment, the barrier wall GBb may include a black material. In an embodiment, the barrier wall GBb includes a black material, and thus the barrier wall GBb may absorb a portion of the light output from the light emitting element OLED. Therefore, the barrier wall GBb may prevent or substantially prevent color mixing of light. Therefore, the color purity of the display device DDa may be improved.

[0175] The second encapsulation film EN2 may be disposed on the first encapsulation film EN1. The second encapsulation film EN2 may cover the barrier wall GBb. The third encapsulation film EN3 may be disposed on the second encapsulation film EN2.

[0176] Fig.10 is a cross-sectional view of a display device DDb according to an embodiment of the present disclosure.

[0177] Fig.10 The lower substrate SUB1, the circuit layer DP-CL, the light emitting element OLED, the encapsulation layer TFE and the light control layer OP can be connected with Figure 6 The lower substrate SUB1, the circuit layer DP-CL, the light emitting element OLED, the encapsulation layer TFE, and the light control layer OP are the same, and therefore, a description thereof will be omitted or will be briefly provided.

[0178] refer to Fig.10 , the barrier wall GBc may be disposed on the pixel defining layer PDL. The barrier wall GBc may extend from the upper surface of the pixel defining layer PDL. Basically, the barrier wall GBc may be formed integrally with the pixel defining layer PDL.

[0179] In an embodiment, when viewed from a cross-sectional view, the width of the pixel defining layer PDL may decrease away from the upper surface of the circuit layer DP-CL, and the width of the barrier wall GBc may be constant. When viewed from a cross-sectional view, the width of the upper surface of the pixel defining layer PDL may be greater than the width of the barrier wall GBc.

[0180] Since the barrier wall GBc is disposed on the pixel defining layer PDL, the barrier wall GBc can absorb a light beam having a large light output angle among the light beams output from the light emitting element OLED, thereby improving the color purity of light provided to the outside from the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B.

[0181] According to an embodiment of the present disclosure, a barrier wall may be disposed between adjacent light emitting elements. The barrier wall may absorb some of the light beams output from the light emitting elements and may prevent mixing with the colors of the light beams output from other light emitting elements. Thus, the color purity of the display device may be improved.

[0182] While the present disclosure has been described with reference to certain embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A display device, comprising: A display panel comprising a circuit element layer and a light emitting element layer on the circuit element layer; as well as A first light conversion layer, a second light conversion layer and a light transmission layer are on the display panel and are spaced apart from each other, Wherein, the light emitting element layer comprises: a pixel defining layer, defining a light emitting opening overlapping the first light conversion layer, the second light conversion layer and the light transmission layer; a plurality of light emitting elements, respectively arranged in the light emitting openings; and a barrier wall, on the pixel defining layer, the barrier wall being black in color, and Wherein, when viewed from above a plane, the barrier wall is located between mutually adjacent light emitting elements among the plurality of light emitting elements, and extends parallel to mutually facing sides of the adjacent light emitting elements.

2. The display device according to claim 1, wherein: The plurality of light emitting elements include a first light emitting element, a second light emitting element, and a third light emitting element having different sizes, and Wherein, when viewed from above the plane, the first light emitting element and the third light emitting element are arranged in a first direction.

3. The display device according to claim 2, wherein: When viewed from above the plane, the blocking wall is located between the first light-emitting element and the third light-emitting element, and extends parallel to one side of the first light-emitting element and one side of the third light-emitting element in a second direction intersecting the first direction, and the one side of the first light-emitting element and the one side of the third light-emitting element face each other.

4. The display device according to claim 3, wherein: When viewed from above the plane, the second light-emitting element and the first light-emitting element are spaced apart from each other in a first diagonal direction, and the second light-emitting element and the third light-emitting element are spaced apart from each other in a second diagonal direction, the first diagonal direction intersects the first direction and the second direction, and the second diagonal direction intersects the first diagonal direction.

5. The display device according to claim 4, wherein: When viewed from above the plane, the barrier wall is also located between the first light emitting element and the second light emitting element and between the second light emitting element and the third light emitting element, and extends in the first direction.

6. The display device according to claim 1, wherein: Each of the plurality of light emitting elements comprises: an anode on the circuit element layer; an emitting layer on the anode; and A cathode is on the emission layer.

7. The display device according to claim 6, wherein: The barrier wall is located on an upper surface of the pixel defining layer, and the emission layer covers the pixel defining layer and the barrier wall.

8. The display device according to claim 6, wherein: The barrier wall and the pixel defining layer are integrally formed.

9. The display device according to claim 1, further comprising: The thin film encapsulation layer includes a first inorganic layer on the light emitting element layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

10. The display device according to claim 9, wherein: The barrier wall is located on an upper surface of the first inorganic layer and overlaps the pixel defining layer.

11. The display device according to claim 10, wherein: The organic layer covers the barrier wall.

12. The display device according to claim 1, wherein: The barrier wall has a thickness of 1 μm to 3 μm.

13. The display device according to claim 1, further comprising: a first color filter, on the first light conversion layer; a second color filter, on the second light conversion layer; as well as A third color filter is on the light transmission layer.

14. A display device comprising: Display panel; as well as A first light conversion layer, a second light conversion layer and a light transmission layer are on the display panel and are spaced apart from each other, Wherein, the display panel comprises: A pixel defining layer, defining a plurality of pixel openings; a first light emitting element disposed in the pixel opening and overlapping the first light conversion layer; a second light emitting element disposed in the pixel opening and overlapping the second light conversion layer; a third light emitting element disposed in the pixel opening and spaced apart from the first light emitting element in a first direction, the third light emitting element overlapping the light transmission layer; and a barrier wall between the first light emitting element and the third light emitting element, and When viewed from above a plane, the length of the barrier wall in a second direction intersecting the first direction is longer than the length of the first light emitting element in the second direction and the length of the third light emitting element in the second direction.

15. The display device according to claim 14, wherein: The barrier wall is also located between the first light emitting element and the second light emitting element and between the second light emitting element and the third light emitting element, and a length of the barrier wall in the first direction is longer than a length of the second light emitting element in the first direction.

16. The display device according to claim 14, wherein: Each of the first light emitting element, the second light emitting element, and the third light emitting element comprises: an anode, at least a portion of which is exposed from the pixel defining layer to the outside through the pixel opening; an emitting layer on the anode; and A cathode is on the emission layer.

17. The display device according to claim 16, wherein: The barrier wall is located on the upper surface of the pixel defining layer, and Wherein, the emission layer covers the pixel defining layer and the blocking wall.

18. The display device according to claim 17, wherein: The pixel defining layer and the barrier wall are integrally formed.

19. The display device according to claim 14, further comprising: The thin film encapsulation layer includes a first inorganic layer on the first light emitting element, the second light emitting element and the third light emitting element, an organic layer on the first inorganic layer and a second inorganic layer on the organic layer.

20. The display device according to claim 19, wherein: The barrier wall is located on an upper surface of the first inorganic layer, and the organic layer covers the barrier wall.

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