Display device

Abstract

A display device is provided. The display device includes a substrate, a circuit layer, and an element layer. The circuit layer includes a light emitting pixel driver, a data line, a first auxiliary line extending in a first direction, a second auxiliary line extending in a second direction, a mesh auxiliary line extending in the second direction and adjacent to a boundary between the first light emitting pixel driver and the second light emitting pixel driver, a first connection auxiliary electrode in the first light emitting pixel driver and connected to one of the second auxiliary lines, a second connection auxiliary electrode overlapping the first connection auxiliary electrode and electrically connected to the first connection auxiliary electrode, a third connection auxiliary electrode connected to one of the first auxiliary lines, and a fourth connection auxiliary electrode overlapping the third connection auxiliary electrode and electrically connected to the third connection auxiliary electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0113674 filed in the Korean Intellectual Property Office on August 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to display devices. Background Art

[0004] As information-oriented society progresses, there are increasing demands for display devices that display images in various ways. For example, display devices are employed in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of light-emitting display devices may include: an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element (such as an inorganic semiconductor), and a micro light-emitting display device including a micro light-emitting element.

[0006] An organic light-emitting display device uses a plurality of light-emitting elements, each of which includes a light-emitting layer made of an organic light-emitting material, to display an image. As described above, an organic light-emitting display device uses a self-luminous element to realize image display, and therefore can have relatively excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area as a periphery of the display area. An emission area emitting light having corresponding brightness and color may be arranged in the display area.

[0008] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0009] The display device may include light emitting elements respectively positioned in the emission regions, and light emitting pixel drivers respectively electrically connected to the light emitting elements.

[0010] The light emitting pixel driver may supply a driving current corresponding to a data signal of the emission area to the light emitting element.

[0011] However, in order to supply the driving current relatively more uniformly and stably, the light-emitting pixel driver may include not only a driving transistor for generating the driving current but also a transistor for initializing the potential of a node connected to the driving transistor or the light-emitting element. As a result, the display device may include wiring for transmitting a constant voltage for initializing the potential of the node, thereby increasing the width of each of the light-emitting pixel drivers, which limits the improvement of resolution.

[0012] In view of the foregoing, aspects of the present disclosure provide a display device capable of improving resolution while maintaining the number of wirings connected to a light emitting pixel driver.

[0013] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area in which an emission area is arranged and a non-display area around the display area, a circuit layer on the substrate, and an element layer on the circuit layer and including light-emitting elements respectively in the emission area. According to some embodiments, the circuit layer includes light-emitting pixel drivers respectively electrically connected to the light-emitting elements and arranged side by side in a first direction and a second direction, data lines extending in the second direction and transmitting data signals to the light-emitting pixel drivers, first auxiliary lines extending in the first direction, second auxiliary lines extending in the second direction and respectively paired with the data lines, grid auxiliary lines extending in the second direction and adjacent to a boundary between a first light-emitting pixel driver and a second light-emitting pixel driver adjacent in the first direction among the light-emitting pixel drivers, a first connection auxiliary electrode in the first light-emitting pixel driver and connected to a second auxiliary line overlapping the first light-emitting pixel driver, a second connection auxiliary electrode overlapping the first connection auxiliary electrode and electrically connected to the first connection auxiliary electrode through a first connection auxiliary contact hole, a third connection auxiliary electrode connected to a first auxiliary line overlapping the first light-emitting pixel driver and the second light-emitting pixel driver, and a fourth connection auxiliary electrode overlapping the third connection auxiliary electrode and electrically connected to the third connection auxiliary electrode through a second connection auxiliary contact hole.

[0014] According to some embodiments, the circuit layer also includes a fifth connection auxiliary electrode and a sixth connection auxiliary electrode, the fifth connection auxiliary electrode being adjacent to an intersection area between the grid auxiliary line and one of the first auxiliary lines and being connected to the grid auxiliary line, the sixth connection auxiliary electrode overlapping the fifth connection auxiliary electrode, the sixth connection auxiliary electrode being electrically connected to the fifth connection auxiliary electrode through a third connection auxiliary contact hole and being spaced apart from the second connection auxiliary electrode and the fourth connection auxiliary electrode.

[0015] According to some embodiments, the circuit layer further includes a first anode initialization voltage line, a second anode initialization voltage line, a seventh connection auxiliary electrode, an eighth connection auxiliary electrode, a ninth connection auxiliary electrode, and a tenth connection auxiliary electrode, the first anode initialization voltage line extending in the first direction, the first anode initialization voltage line being adjacent to one side of a first auxiliary line in the second direction and transmitting the first anode initialization voltage, the second anode initialization voltage line extending in the first direction, the second anode initialization voltage line being adjacent to one side of the first anode initialization voltage line in the second direction and transmitting the second anode initialization voltage, the seventh connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the first light-emitting pixel driver in the second direction and being spaced apart from the first anode initialization voltage line and the second anode initialization voltage line, the eighth connection auxiliary electrode overlapping the seventh connection auxiliary electrode and being electrically connected to the seventh connection auxiliary electrode through a fourth connection auxiliary contact hole, the ninth connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the second direction and being spaced apart from the first anode initialization voltage line and the second anode initialization voltage line in the second light-emitting pixel driver, and the tenth connection auxiliary electrode overlapping the ninth connection auxiliary electrode and being electrically connected to the ninth connection auxiliary electrode through a fifth connection auxiliary contact hole. According to some embodiments, the eighth connection auxiliary electrode is adjacent to one side of the grid auxiliary line in the first direction. According to some embodiments, the tenth connection auxiliary electrode is adjacent to the other side of the grid auxiliary line in the first direction.

[0016] According to some embodiments, the circuit layer further includes a gate initialization voltage line, an eleventh connection auxiliary electrode, and a twelfth connection auxiliary electrode, the gate initialization voltage line extending in the first direction, the gate initialization voltage line being adjacent to the other side of one of the first auxiliary lines in the second direction and transmitting the gate initialization voltage, the eleventh connection auxiliary electrode being between the gate initialization voltage line and the one of the first auxiliary lines, and the twelfth connection auxiliary electrode overlapping the eleventh connection auxiliary electrode and being electrically connected to the eleventh connection auxiliary electrode through a sixth connection auxiliary contact hole. According to some embodiments, the sixth connection auxiliary electrode and the twelfth connection auxiliary electrode overlap the grid auxiliary lines and are spaced apart from each other.

[0017] According to some embodiments, the bypass area on one side of the display area includes: a bypass middle area at the center, a first bypass side area parallel to the bypass middle area in a first direction and in contact with the non-display area, and a second bypass side area between the bypass middle area and the first bypass side area. According to some embodiments, the data line includes a first data line in the first bypass side area, and a second data line in the second bypass side area. According to some embodiments, the first auxiliary line includes a first bypass auxiliary line electrically connected to the first data line. According to some embodiments, the second auxiliary line includes a second bypass auxiliary line paired with the second data line and electrically connected to the first bypass auxiliary line.

[0018] According to some embodiments, the first light-emitting pixel driver and the second light-emitting pixel driver are in the second bypass side region. According to some embodiments, the first light-emitting pixel driver is electrically connected to the second data line and overlaps with the intersection region between the first bypass auxiliary line and the second bypass auxiliary line. According to some embodiments, the circuit layer also includes a first connection auxiliary line connecting the second connection auxiliary electrode to the fourth connection auxiliary electrode. According to some embodiments, the second bypass auxiliary line is electrically connected to the first bypass auxiliary line through the first connection auxiliary electrode, the first connection auxiliary contact hole, the second connection auxiliary electrode, the first connection auxiliary line, the fourth connection auxiliary electrode, the second connection auxiliary contact hole and the third connection auxiliary electrode.

[0019] According to some embodiments, the circuit layer further includes a second connection auxiliary line and a third connection auxiliary line, the second connection auxiliary line connects the first anode initialization voltage line to the seventh connection auxiliary electrode, and the third connection auxiliary line connects the sixth connection auxiliary electrode to the eighth connection auxiliary electrode. According to some embodiments, the grid auxiliary line is electrically connected to the first anode initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the third connection auxiliary line, the eighth connection auxiliary electrode, the fourth connection auxiliary contact hole, the seventh connection auxiliary electrode, and the second connection auxiliary line.

[0020] According to some embodiments, the circuit layer further includes a fourth connection auxiliary line and a fifth connection auxiliary line, the fourth connection auxiliary line connects the second anode initialization voltage line to the ninth connection auxiliary electrode, and the fifth connection auxiliary line connects the sixth connection auxiliary electrode to the tenth connection auxiliary electrode. According to some embodiments, the grid auxiliary line is electrically connected to the second anode initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the fifth connection auxiliary line, the tenth connection auxiliary electrode, the fifth connection auxiliary contact hole, the ninth connection auxiliary electrode, and the fourth connection auxiliary line.

[0021] According to some embodiments, the circuit layer further includes a sixth connection auxiliary line and a seventh connection auxiliary line, the sixth connection auxiliary line connecting the gate initialization voltage line to the eleventh connection auxiliary electrode, and the seventh connection auxiliary line connecting the sixth connection auxiliary electrode to the twelfth connection auxiliary electrode. According to some embodiments, the grid auxiliary line is electrically connected to the gate initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the seventh connection auxiliary line, the twelfth connection auxiliary electrode, the sixth connection auxiliary contact hole, the eleventh connection auxiliary electrode, and the sixth connection auxiliary line.

[0022] According to some embodiments, the data line also includes a third data line in the bypass middle area. According to some embodiments, the first auxiliary line also includes a second power auxiliary transverse line having a second power applied thereto between the first power and the second power for driving the light-emitting element. According to some embodiments, the second auxiliary line also includes a second power auxiliary longitudinal line having a second power applied thereto. According to some embodiments, the first light-emitting pixel driver and the second light-emitting pixel driver are in the bypass middle area and overlap with a second power auxiliary transverse line among a plurality of second power auxiliary transverse lines. According to some embodiments, the first light-emitting pixel driver is electrically connected to the third data line. According to some embodiments, the circuit layer also includes an eighth connection auxiliary line connecting the fourth connection auxiliary electrode to the sixth connection auxiliary electrode. According to some embodiments, the grid auxiliary line is electrically connected to a second power auxiliary transverse line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the eighth connection auxiliary line, the fourth connection auxiliary electrode, the second connection auxiliary contact hole and the third connection auxiliary electrode.

[0023] According to some embodiments, the display device further includes a display driving circuit configured to transmit a data signal of a light-emitting pixel driver to a data line. According to some embodiments, the circuit layer further includes a data supply line in a non-display area and electrically connected between the data line and the display driving circuit. According to some embodiments, among the data supply lines, a first data supply line transmitting a data signal of a first data line is electrically connected to the first data line through a first bypass auxiliary line and a second bypass auxiliary line. According to some embodiments, among the data supply lines, a second data supply line transmitting a data signal of a second data line is directly electrically connected to the second data line. According to some embodiments, among the data supply lines, a third data supply line transmitting a data signal of a third data line is directly electrically connected to the third data line.

[0024] According to some embodiments, the third connection auxiliary electrode is in the second light emitting pixel driver.

[0025] According to some embodiments, the third connection auxiliary electrode is adjacent to a boundary between a first light emitting pixel driver and a second light emitting pixel driver adjacent to each other in the first direction.

[0026] According to some embodiments, the circuit layer also includes a thirteenth connection auxiliary electrode and a fourteenth connection auxiliary electrode, the thirteenth connection auxiliary electrode is in the second light-emitting pixel driver and is connected to another second auxiliary line overlapping with the second light-emitting pixel driver, and the fourteenth connection auxiliary electrode overlaps with the thirteenth connection auxiliary electrode and is electrically connected to the thirteenth connection auxiliary electrode through the seventh connection auxiliary contact hole.

[0027] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area in which an emission area is arranged and a non-display area around the display area, a circuit layer on the substrate, and an element layer on the circuit layer and including light-emitting elements respectively in the emission area. According to some embodiments, the circuit layer comprises a light-emitting pixel driver, a data line, a first auxiliary line, a second auxiliary line, a grid auxiliary line, a first anode initialization voltage line, a second anode initialization voltage line, a gate initialization voltage line and a first power line, the light-emitting pixel drivers are respectively electrically connected to the light-emitting elements and arranged side by side in the first direction and the second direction, the data line extends in the second direction and transmits a data signal to the light-emitting pixel driver, the first auxiliary line extends in the first direction, the second auxiliary line extends in the second direction and is paired with the data line respectively, the grid auxiliary line extends in the second direction and between the second auxiliary lines, the first anode initialization voltage line extends in the first direction and transmits a first anode initialization voltage, the second anode initialization voltage line extends in the first direction and transmits a second anode initialization voltage, the gate initialization voltage line extends in the first direction and transmits a gate initialization voltage; and the first power line transmits the first power between the first power and the second power used to drive the light-emitting element. According to some embodiments, the first auxiliary line includes a first bypass auxiliary line and a second power auxiliary transverse line, the first bypass auxiliary line is electrically connected to a first data line among the data lines that is adjacent to the non-display area in the first direction, and the second power auxiliary transverse line transmits a second power. According to some embodiments, the second auxiliary line includes a second bypass auxiliary line and a second power auxiliary longitudinal line, the second bypass auxiliary line is paired with a second data line among the data lines that is spaced farther from the non-display area than the first data line in the first direction and is electrically connected to the first bypass auxiliary line, and the second power auxiliary longitudinal line transmits the second power. According to some embodiments, the light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver, the first light-emitting pixel driver includes a crossing area between the first bypass auxiliary line and the second bypass auxiliary line, and the second light-emitting pixel driver is adjacent to the first light-emitting pixel driver in the first direction. According to some embodiments, the second bypass auxiliary line is electrically connected to the first bypass auxiliary line through the first connection auxiliary electrode, the second connection auxiliary electrode, the third connection auxiliary electrode, the fourth connection auxiliary electrode and the first connection auxiliary line, the first connection auxiliary electrode is connected to the second bypass auxiliary line, the second connection auxiliary electrode overlaps with the first connection auxiliary electrode and is electrically connected to the first connection auxiliary electrode through the first connection auxiliary contact hole, the third connection auxiliary electrode is connected to the first bypass auxiliary line, the fourth connection auxiliary electrode overlaps with the third connection auxiliary electrode and is electrically connected to the third connection auxiliary electrode through the second connection auxiliary contact hole, and the first connection auxiliary line connects the second connection auxiliary electrode to the fourth connection auxiliary electrode.

[0028] According to some embodiments, the grid auxiliary line includes a first grid auxiliary line electrically connected to the first anode initialization voltage line, a second grid auxiliary line electrically connected to the second anode initialization voltage line, a third grid auxiliary line electrically connected to the gate initialization voltage line, and a fourth grid auxiliary line electrically connected to at least one of the plurality of second power auxiliary lateral lines.

[0029] According to some embodiments, the first grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. According to some embodiments, the first grid auxiliary line is electrically connected to the first anode initialization voltage line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the seventh connection auxiliary electrode, the eighth connection auxiliary electrode, the second connection auxiliary line and the third connection auxiliary line, the fifth connection auxiliary electrode is connected to the first grid auxiliary line, the sixth connection auxiliary electrode overlaps with the fifth connection auxiliary electrode and is electrically connected to the fifth connection auxiliary electrode through the third connection auxiliary contact hole, the seventh connection auxiliary electrode is between the first anode initialization voltage line and the second anode initialization voltage line, the eighth connection auxiliary electrode overlaps with the seventh connection auxiliary electrode and is electrically connected to the seventh connection auxiliary electrode through the fourth connection auxiliary contact hole, the second connection auxiliary line connects the first anode initialization voltage line to the seventh connection auxiliary electrode, and the third connection auxiliary line connects the sixth connection auxiliary electrode to the eighth connection auxiliary electrode.

[0030] According to some embodiments, the second grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. According to some embodiments, the second grid auxiliary line is electrically connected to the second anode initialization voltage line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the ninth connection auxiliary electrode, the tenth connection auxiliary electrode, the fourth connection auxiliary line and the fifth connection auxiliary line, the fifth connection auxiliary electrode is connected to the first grid auxiliary line, the sixth connection auxiliary electrode overlaps with the fifth connection auxiliary electrode and is electrically connected to the fifth connection auxiliary electrode through the third connection auxiliary contact hole, the ninth connection auxiliary electrode is between the first anode initialization voltage line and the second anode initialization voltage line, the tenth connection auxiliary electrode overlaps with the ninth connection auxiliary electrode and is electrically connected to the ninth connection auxiliary electrode through the fifth connection auxiliary contact hole, the fourth connection auxiliary line connects the second anode initialization voltage line to the ninth connection auxiliary electrode, and the fifth connection auxiliary line connects the sixth connection auxiliary electrode to the tenth connection auxiliary electrode.

[0031] According to some embodiments, the third grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. According to some embodiments, the third grid auxiliary line is electrically connected to the gate initialization voltage line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the eleventh connection auxiliary electrode, the twelfth connection auxiliary electrode, the sixth connection auxiliary line and the seventh connection auxiliary line, the fifth connection auxiliary electrode is connected to the third grid auxiliary line, the sixth connection auxiliary electrode overlaps with the fifth connection auxiliary electrode and is electrically connected to the fifth connection auxiliary electrode through the third connection auxiliary contact hole, the eleventh connection auxiliary electrode is between the gate initialization voltage line and the sixth connection auxiliary electrode, the twelfth connection auxiliary electrode overlaps with the eleventh connection auxiliary electrode and is electrically connected to the eleventh connection auxiliary electrode through the sixth connection auxiliary contact hole, the sixth connection auxiliary line connects the gate initialization voltage line to the eleventh connection auxiliary electrode, and the seventh connection auxiliary line connects the sixth connection auxiliary electrode to the twelfth connection auxiliary electrode.

[0032] According to some embodiments, the luminescent pixel driver further includes a third luminescent pixel driver and a fourth luminescent pixel driver, the third luminescent pixel driver including a second luminescent power auxiliary lateral line in a plurality of second power auxiliary lateral lines and a second luminescent power auxiliary longitudinal line in a plurality of second power auxiliary longitudinal lines in a cross region, and the fourth luminescent pixel driver is adjacent to the third luminescent pixel driver in the first direction and includes a cross region between a second luminescent power auxiliary lateral line and another second luminescent power auxiliary longitudinal line in a plurality of second power auxiliary longitudinal lines. According to some embodiments, the third connection auxiliary electrode is connected to a second power auxiliary lateral line. According to some embodiments, the fourth grid auxiliary line is adjacent to a boundary between the third luminescent pixel driver and the fourth luminescent pixel driver. The fourth grid auxiliary line is electrically connected to a second power auxiliary lateral line through a fifth connection auxiliary electrode, a sixth connection auxiliary electrode, a third connection auxiliary electrode, a fourth connection auxiliary electrode, and an eighth connection auxiliary line, the fifth connection auxiliary electrode is connected to the fourth grid auxiliary line, the sixth connection auxiliary electrode overlaps the fifth connection auxiliary electrode and is electrically connected to the fifth connection auxiliary electrode through the third connection auxiliary contact hole, and the eighth connection auxiliary line connects the fourth connection auxiliary electrode to the sixth connection auxiliary electrode.

[0033] According to some embodiments, a display device includes a substrate, a circuit layer on the substrate, and an element layer on the circuit layer. According to some embodiments, the substrate includes a display area in which an emission area is arranged, and a non-display area around the display area. According to some embodiments, the element layer includes light-emitting elements respectively in the emission area. According to some embodiments, the circuit layer includes a light-emitting pixel driver, a data line, a first auxiliary line, a second auxiliary line, a grid auxiliary line, a first connection auxiliary electrode, a second connection auxiliary electrode, a third connection auxiliary electrode and a fourth connection auxiliary electrode, the light-emitting pixel drivers are respectively electrically connected to the light-emitting elements and are arranged side by side in the first direction and the second direction, the data line extends in the second direction and transmits the data signal to the light-emitting pixel driver, the first auxiliary line extends in the first direction, the second auxiliary line extends in the second direction and is paired with the data line, the grid auxiliary line extends in the second direction and is adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver adjacent to each other in the first direction among the light-emitting pixel drivers, the first connection auxiliary electrode is in the first light-emitting pixel driver and is connected to a second auxiliary line overlapping with the first light-emitting pixel driver, the second connection auxiliary electrode is electrically connected to the first connection auxiliary electrode through a first connection auxiliary contact hole, the third connection auxiliary electrode is in the second light-emitting pixel driver and is connected to a first auxiliary line overlapping with the first light-emitting pixel driver and the second light-emitting pixel driver, and the fourth connection auxiliary electrode is electrically connected to the third connection auxiliary electrode through the second connection auxiliary contact hole.

[0034] Thus, according to some embodiments, the third connection auxiliary electrode connected to a first auxiliary line overlapping the first light-emitting pixel driver and the second light-emitting pixel driver is only in the second light-emitting pixel driver among the first light-emitting pixel driver and the second light-emitting pixel driver. Accordingly, the width of each of the light-emitting pixel drivers can be relatively reduced, which can lead to an improvement in resolution.

[0035] According to some embodiments, the first auxiliary line may include a first bypass auxiliary line electrically connected to a first data line in a first bypass side region contacting the non-display region in the first direction. According to some embodiments, the second auxiliary line may include a second bypass auxiliary line paired with a second data line in a second bypass side region between the bypass middle region and the first bypass side region in the first direction and electrically connected to the first bypass auxiliary line.

[0036] According to some embodiments, the first light-emitting pixel driver may be electrically connected to the second data line and may overlap with the intersection area between the first bypass auxiliary line and the second bypass auxiliary line. In this case, the second connection auxiliary electrode may be connected to the fourth connection auxiliary electrode through the first connection auxiliary line. Here, the second connection auxiliary electrode may be connected to the second bypass auxiliary line through the first connection auxiliary electrode and the first connection auxiliary contact hole, and the fourth connection auxiliary electrode may be connected to the first bypass auxiliary line through the third connection auxiliary electrode and the second connection auxiliary contact hole, so that the second bypass auxiliary line can be electrically connected to the first bypass auxiliary line through the first connection auxiliary line.

[0037] That is, even if the third connection auxiliary electrode connected to the first bypass auxiliary line is not in the first light-emitting pixel driver, the electrical connection between the first bypass auxiliary line and the second bypass auxiliary line can be achieved through the first connection auxiliary line.

[0038] According to some embodiments, the circuit layer may further include a fifth connection auxiliary electrode connected to the mesh auxiliary line, and a sixth connection auxiliary electrode electrically connected to the fifth connection auxiliary electrode through the third connection auxiliary contact hole.

[0039] According to some embodiments, the circuit layer may further include a seventh connection auxiliary electrode, an eighth connection auxiliary electrode, a ninth connection auxiliary electrode and a tenth connection auxiliary electrode, the seventh connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the first light-emitting pixel driver, the eighth connection auxiliary electrode being electrically connected to the seventh connection auxiliary electrode through a fourth connection auxiliary contact hole, the ninth connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the second light-emitting pixel driver, and the tenth connection auxiliary electrode being electrically connected to the ninth connection auxiliary electrode through a fifth connection auxiliary contact hole.

[0040] According to some embodiments, when the grid auxiliary line between the first light-emitting pixel driver and the second light-emitting pixel driver transmits the first anode initialization voltage, the grid auxiliary line can be electrically connected to the first anode initialization voltage line through a second connection auxiliary line connecting the first anode initialization voltage line to the seventh connection auxiliary electrode and a third connection auxiliary line connecting the sixth connection auxiliary electrode to the eighth connection auxiliary electrode.

[0041] According to some embodiments, when the grid auxiliary line between the first light-emitting pixel driver and the second light-emitting pixel driver transmits the second anode initialization voltage, the grid auxiliary line can be electrically connected to the second anode initialization voltage line by connecting the second anode initialization voltage line to the fourth connection auxiliary line of the ninth connection auxiliary electrode and the fifth connection auxiliary line connecting the sixth connection auxiliary electrode to the tenth connection auxiliary electrode.

[0042] According to some embodiments, the circuit layer may further include an eleventh connection auxiliary electrode and a twelfth connection auxiliary electrode, the eleventh connection auxiliary electrode being between the gate initialization voltage line and one of the first auxiliary lines, and the twelfth connection auxiliary electrode being electrically connected to the eleventh connection auxiliary electrode through a sixth connection auxiliary contact hole.

[0043] According to some embodiments, when the grid auxiliary line between the first light-emitting pixel driver and the second light-emitting pixel driver transmits a gate initialization voltage, the grid auxiliary line can be electrically connected to the gate initialization voltage line by connecting the gate initialization voltage line to the sixth connection auxiliary line of the eleventh connection auxiliary electrode and the seventh connection auxiliary line connecting the sixth connection auxiliary electrode to the twelfth connection auxiliary electrode.

[0044] In this way, even if the sixth connection auxiliary electrode electrically connected to the grid auxiliary line through the fifth connection auxiliary electrode and the third connection auxiliary contact hole is not in each of the first light-emitting pixel driver and the second light-emitting pixel driver, electrical connection between the grid auxiliary line and any one of the first anode initialization voltage line, the second anode initialization voltage line and the gate initialization voltage line can be achieved.

[0045] As a result, the width of each of the light-emitting pixel drivers can be further reduced, which can improve the resolution.

[0046] According to some embodiments, the circuit layer may also include a thirteenth connection auxiliary electrode in the second light-emitting pixel driver and connected to another second auxiliary line overlapping the second light-emitting pixel driver, and a fourteenth connection auxiliary electrode electrically connected to the thirteenth connection auxiliary electrode through a seventh connection auxiliary contact hole.

[0047] In this way, the first connection auxiliary electrode and the thirteenth connection auxiliary electrode can be in the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, so that the first light-emitting pixel driver and the second light-emitting pixel driver can be symmetrical with respect to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

[0048] As a result, a change in optical characteristics caused by the first light-emitting pixel driver and a change in optical characteristics caused by the second light-emitting pixel driver may become similar to each other, and thus the display quality may be relatively improved.

[0049] However, features according to the embodiments of the present disclosure are not limited to those described above, and various other features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing in more detail various aspects according to some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0051] Figure 1 is a perspective view showing an electronic device according to some embodiments;

[0052] Figure 2 According to some embodiments Figure 1 An exploded perspective view of the electronic device shown in ;

[0053] Figure 3 is a diagram showing some embodiments of the present invention. Figure 2 A plan view of a display device;

[0054] Figure 4 According to some embodiments, Figure 3 A cross-sectional view taken along line A-A';

[0055] Figure 5 is a diagram showing some embodiments of the present invention. Figure 3 a layout diagram of part B;

[0056] Figure 6 is a diagram showing some embodiments of the present invention. Figure 5 A diagram of the scanning function of the light sensing area shown in FIG.

[0057] Figure 7 is a diagram showing some embodiments of the present invention. Figure 4 The block diagram of the circuit layer;

[0058] Figure 8 According to some embodiments Figure 7 An equivalent circuit diagram of a light emitting pixel driver and a light sensing pixel driver shown in;

[0059] Fig. 9 is a diagram showing some embodiments of the present invention. Figure 8 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light emitting element;

[0060] Fig.10 is a diagram showing some embodiments of the present invention. Figure 2 A plan view of a substrate;

[0061] Fig.11 It is shown Fig.10 a layout diagram of part C;

[0062] Fig.12 is along Fig.11 A cross-sectional view taken along the line D-D';

[0063] Fig.13 is a diagram showing some embodiments of the present invention. Fig.11 a plan view of section E;

[0064] Fig.14 is along Fig.13 A cross-sectional view taken along line II';

[0065] Fig.15 is along Fig.13 A cross-sectional view taken along the line J-J';

[0066] Fig.16 is a diagram showing some embodiments of the present invention. Fig.11 a plan view of section F;

[0067] Fig.17 is a diagram showing some embodiments of the present invention. Fig.11 A plan view of a portion G;

[0068] Fig.18 is along Fig.17 A cross-sectional view taken along line K-K';

[0069] Fig.19 is a diagram showing some embodiments of the present invention. Fig.11 A plan view of a portion H;

[0070] Fig. 20 is along Fig.19 A cross-sectional view taken along the line L-L';

[0071] Fig.21 is a diagram showing some embodiments of the present invention. Fig.11 a plan view of section E;

[0072] Fig. 22 is a diagram showing some embodiments of the present invention. Fig.11 a plan view of section F;

[0073] Fig.23 is a diagram showing some embodiments of the present invention. Fig.11 A plan view of a portion G;

[0074] Fig.24 is a diagram showing some embodiments of the present invention. Fig.11 a plan view of part H of ; and

[0075] Fig.25 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section E'. DETAILED DESCRIPTION

[0076] Hereinafter, various aspects of some embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. However, these embodiments can be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same parts. In the accompanying drawings, for clarity, the thickness of the layers and regions may be magnified.

[0077] In order to describe aspects of some embodiments of the present disclosure, some of parts that are not associated with the description may not be provided.

[0078] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0079] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-sectional view obtained by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapped" means that the first object can be positioned above or below the second object, or to the side of the second object, and / or vice versa. Additionally, the term "overlap" may include layers, stacks, facing or facing, extending above, covering or partially covering, or any other suitable terms that a person of ordinary skill in the art will appreciate and understand. The expression "non-overlapping" may include meanings such as "separated from" or "beside" or "offset from", as well as any other suitable equivalents that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0080] For ease of description, spatially relative terms "below", "beneath", "lower", "above", "upper" or the like may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It should be understood that in addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is turned over, a device located "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, spatially relative terms may be interpreted differently depending on the orientation.

[0081] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element through one or more intervening elements therebetween. It should also be understood that when the terms “comprise,” “comprising,” “has,” “have,” “having,” “include,” and / or “including,” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0082] It should be understood that although "first", "second", "third" or similar terms may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate its description and explanation. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be named in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0083] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0084] For the purpose of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". For the purpose of its meaning and interpretation, in the specification and claims, the phrase "at least one of..." is intended to include "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean A, B, or A and B.

[0085] Unless otherwise defined or implied, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined in this specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0086] Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings.

[0087] Figure 1 is a perspective view showing an electronic device according to some embodiments. Figure 2 According to some embodiments Figure 1 An exploded perspective view of the electronic device shown in FIG.

[0088] Reference Figure 1 The electronic device 10 according to some embodiments is a device having a function of displaying an image in a display area. The electronic device 10 may provide portability. For example, the electronic device 10 may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0089] However, the electronic device 10 according to some embodiments is not limited to a portable electronic device, and may be a large device such as a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IoT) device.

[0090] The electronic device 10 according to some embodiments may include a display device 100 (see FIG. Figure 2 )'s shell has a cover window 11 and a lower cover 12.

[0091] Reference Figure 2 The electronic device 10 may further include a display device 100 , a bracket 13 , and a main circuit board 14 accommodated between the cover window 11 and the lower cover 12 .

[0092] The display device 100 may include a main area MA including a display area DA in which an image is displayed and a non-display area NDA around the display area DA, and a sub area SBA protruding from one side of the main area MA.

[0093] The display device 100 may also include a display driving circuit 200 positioned in the sub-area SBA, a display circuit board 300 bonded to one side of the sub-area SBA, a touch driving circuit 400 and a scan driving circuit 500 mounted on the display circuit board 300, and a cable 600 extending from one side of the display circuit board 300.

[0094] In the present specification, the first direction DR1 may be a direction parallel to the short side of the electronic device 10 in a plan view, that is, a transverse direction of the electronic device 10. The second direction DR2 may be a direction parallel to the long side of the electronic device 10 in a plan view, that is, a longitudinal direction of the electronic device 10. The third direction DR3 may be a thickness direction of the electronic device 10.

[0095] The electronic device 10 may have a shape close to a rectangular shape in a plan view. For example, the electronic device 10 may have a rectangular shape with short sides in the first direction DR1 and long sides in the second direction DR2 in a plan view. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be right angles or rounded with a curvature (e.g., a set or predetermined curvature). The planar shape of the electronic device 10 is not limited to a rectangular shape, and may be formed in another polygonal shape different from the rectangular shape, a circular shape, or an elliptical shape.

[0096] The cover window 11 may be positioned on the display device 100 to cover the top surface of the display device 100. The cover window 11 may serve to protect the top surface of the display device 100.

[0097] The cover window 11 may include a transparent light-transmitting portion and an opaque light-blocking portion.

[0098] The light-transmitting portion may overlap the display area DA of the display device 100 in the third direction DR3 , and the light-blocking portion may overlap the non-display area NDA of the display device 100 in the third direction DR3 .

[0099] The cover window 11 may include a top surface portion forming a top surface of the electronic device 10, a left surface portion forming a left side surface of the electronic device 10, and a right surface portion forming a right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and the right surface portion thereof may extend from the right side of the top surface portion.

[0100] Each of the top, left, and right surface portions of the cover window 11 may include a light-transmitting portion and a light-blocking portion.

[0101] The light-transmitting portion of the cover window 11 may be positioned on most of each of the top, left, and right surface portions of the cover window 11 .

[0102] The light blocking portion of the cover window 11 can be positioned at the upper and lower edges of the top surface portion of the cover window 11, the upper, left and lower edges of the left surface portion of the cover window 11, and the upper, right and lower edges of the right surface portion of the cover window 11.

[0103] The display device 100 may be positioned under the cover window 11 .

[0104] That is, the cover window 11 may be positioned on the display device 100 .

[0105] The display device 100 may include a main area MA serving as a display surface and a sub area SBA protruding from one side of the main area MA.

[0106] The main area MA may include a display area DA configured to display an image and a non-display area NDA which is a peripheral area of ​​the display area DA.

[0107] The display area DA may be positioned in most of the main area MA. The display area DA may be positioned at the center of the main area MA.

[0108] The non-display area NDA may be located outside the display area DA (eg, outside the periphery or footprint thereof). The non-display area NDA may be an edge area of ​​the main area MA.

[0109] The sub area SBA may protrude in the second direction DR2 from one side of the main area MA.

[0110] The length of the sub-area SBA in the first direction DR1 may be less than or equal to the length of the main area MA in the first direction DR1. The length of the sub-area SBA in the second direction DR2 may be less than the length of the main area MA in the second direction DR2, but is not limited thereto.

[0111] Since a portion of the sub-area SBA is deformed to be curved, another portion of the sub-area SBA may overlap the main area MA in the third direction DR3.

[0112] The display driving circuit 200 may be disposed in the sub-area SBA.

[0113] The display device 100 may include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from the left side of the top surface portion, and the right surface portion of the display device 100 may extend from the right side of the top surface portion.

[0114] Each of the top, left, and right surface portions of the display device 100 may include a display area DA and a non-display area NDA.

[0115] The display area DA may be positioned on most of each of the top, left, and right surface portions of the display device 100 .

[0116] The non-display area NDA may be positioned at the upper and lower edges of the top surface portion of the display device 100 , the upper, left and lower edges of the left surface portion of the display device 100 , and the upper, right and lower edges of the right surface portion of the display device 100 .

[0117] The display driving circuit 200 may be mounted on the sub-area SBA of the display device 100 , and the display circuit board 300 may be attached thereto.

[0118] One end of the display circuit board 300 may be attached to a pad positioned on a lower edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0119] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0120] The display driving circuit 200 may drive the light emitting pixel driver EPD (see FIG. 1 ) of the display area DA based on the control signal and the power voltage supplied from the display circuit board 300. Figure 7 ) data signal Vdata (see Figure 8 ) is transmitted to the data line DL (see Figure 7 ).

[0121] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted on the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, this is only an example, and the embodiments according to the present disclosure are not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0122] According to some embodiments, the touch driving circuit 400 and the scan driving circuit 500 may also be mounted in the sub-area SBA of the display device 100 .

[0123] Alternatively, if Figure 2 As shown in , the touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0124] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 (see FIG. Figure 4 ).

[0125] The scanning driving circuit 500 can detect the light of the display area DA through the light sensing pixel driver DPD (see Figure 7 ) and the readout line ROL (see Figure 7 ) is electrically connected to the light sensing element PD (see Figure 8 ).

[0126] The bracket 13 may be positioned below the display device 100 .

[0127] The bracket 13 may include plastic, metal, or both. The bracket 13 may include a first camera hole CMH1 for inserting the camera device 16 therein, a battery hole BH for positioning the battery 18 therein, and a cable hole CAH for passing the cable 600 connected to the display circuit board 300 therethrough.

[0128] The main circuit board 14 and the battery 18 may be positioned below the bracket 13. The main circuit board 14 may be a rigid printed circuit board or a flexible printed circuit board.

[0129] The main circuit board 14 may include a main processor 15, a camera device 16, and a main connector 17. The main processor 15 may be formed as an integrated circuit.

[0130] The camera device 16 may be positioned on both the top and bottom surfaces of the main circuit board 14 , the main processor 15 may be positioned on the top surface of the main circuit board 14 , and the main connector 17 may be positioned on the bottom surface of the main circuit board 14 .

[0131] The main processor 15 can control all functions of the electronic device 10 .

[0132] For example, the main processor 15 may output digital video data to the display driving circuit 200 through the display circuit board 300 so that the display device 100 displays an image. In addition, the main processor 15 may receive touch data including the touch coordinates of the user from the touch driving circuit 400, determine whether the user touches or approaches, and then perform an operation corresponding to the user's touch input or approach input. For example, the main processor 15 may perform an operation indicated by an icon touched by the user or execute an application indicated by it.

[0133] In addition, the main processor 15 may receive scan data from the scan driving circuit 500 and perform an operation or execute an application based on whether the scan data is valid.

[0134] The main processor 15 may be an application processor formed by an integrated circuit, a central processing unit, or a system chip.

[0135] The camera device 16 may process image frames of still images or videos obtained by an image sensor in a camera mode and output them to the main processor 15 .

[0136] The cable 600 passing through the cable hole CAH of the bracket 13 may be connected to the main connector 17. Thus, the main circuit board 14 may be electrically connected to the display circuit board 300.

[0137] The battery 18 may be arranged so as not to overlap with the main circuit board 14 in the third direction DR3. The battery 18 may overlap with the battery hole BH of the bracket 13 in the third direction DR3.

[0138] In addition, the main circuit board 14 may also be equipped with a mobile communication module capable of transmitting and receiving radio signals with at least one of a base station, an external terminal and a server in a mobile communication network. The radio signal may include various types of data according to the transmission and reception of a voice signal, a video call signal or a text / multimedia message.

[0139] The lower cover 12 may be positioned below the main circuit board 14 and the battery 18. The lower cover 12 may be fixed by being fastened to the bracket 13. The lower cover 12 may form an upper side surface, a lower side surface, and a bottom surface of the electronic device 10. The lower cover 12 may include plastic, metal, or both plastic and metal.

[0140] The lower cover 12 may include a second camera hole CMH2 through which the bottom surface of the camera device 16 is exposed. The position of the camera device 16 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera device 16 are not limited to relative to Figure 2 The illustrated embodiment.

[0141] Next, the display device 100 according to some embodiments will be described.

[0142] Figure 3 is a diagram showing some embodiments of the present invention. Figure 2 A plan view of a display device. Figure 4 According to some embodiments, Figure 3 A cross-sectional view taken along line AA'. Figure 5 is a diagram showing some embodiments of the present invention. Figure 3 Layout diagram of part B.

[0143] Figure 3 and Figure 4 The display device 100 is shown with a portion of the sub-area SBA in a bent state.

[0144] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micro or nano light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0145] The display device 100 may be formed to be flat, but is not limited thereto according to an embodiment of the present disclosure. For example, the display device 100 may include a bent portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, curved, folded, or curled.

[0146] Reference Figure 3 , at least one surface of the display device 100 includes a main area MA from which light for displaying an image is emitted.

[0147] The display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1 in a plan view. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a curvature (e.g., a set or predetermined curvature) or may be a right angle. The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in another polygonal shape different from the rectangular shape, a circular shape, or an elliptical shape.

[0148] The display area DA may occupy most of the main area MA. The display area DA may be positioned at the center of the main area MA.

[0149] Reference Figure 4 , the display device 100 further includes a sub-area SBA protruding from one side of the main area MA.

[0150] The sub-area SBA may be an area protruding to one side in the second direction DR2 from the non-display area NDA of the main area MA.

[0151] Since a portion of the sub-area SBA is deformed to be curved, another portion of the sub-area SBA may be positioned on the rear surface of the display device 100 .

[0152] The display device 100 according to some embodiments includes a substrate 110 , a circuit layer 120 positioned on the substrate 110 , and an element layer 130 positioned on the circuit layer 120 .

[0153] According to some embodiments, the display device 100 may further include an encapsulation layer 140 positioned on the element layer 130, and a touch sensor layer 150 positioned on the encapsulation layer 140. In addition, the display device 100 may further include a polarization layer 160 positioned on the touch sensor layer 150 to reduce reflection of external light.

[0154] The substrate 110 may include a main area MA corresponding to a display surface, and a sub area SBA protruding in the second direction DR2 from one side of the main area MA.

[0155] The main area MA of the substrate 110 may include a display area DA as a central majority, and a non-display area NDA as a periphery of the display area DA.

[0156] The sub area SBA may protrude in the second direction DR2 from one side of the main area MA.

[0157] Reference Figure 5 , the display area DA includes the emission areas EA, the non-emission areas NEA as separation areas between the emission areas EA, and the light sensing areas ODA positioned in portions of the non-emission areas NEA.

[0158] Each of the emission areas EA may be a unit that emits light in a wavelength band corresponding to one of two or more different colors with brightness corresponding to an image signal.

[0159] Each of the emission areas EA may have a rhombus planar shape or a rectangular planar shape. However, this is only an example, and according to some embodiments, the planar shape of the emission area EA is not limited to Figure 5 That is, the emission area EA may have a polygonal shape (such as a diamond shape or a hexagonal shape), a circular shape, or an elliptical shape other than a rectangular shape in a plan view.

[0160] The emission area EA may include a first emission area EA1 that emits light of a first color having a wavelength band (e.g., a set or predetermined wavelength band), a second emission area EA2 that emits light of a second color having a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color having a wavelength band lower than the wavelength band of the second color.

[0161] For example, the first color may be red having a wavelength band in the range of 600 nanometers (nm) (or approximately 600 nm) to 750 nm (or approximately 750 nm), the second color may be green having a wavelength band in the range of 480 nm (or approximately 480 nm) to 560 nm (or approximately 560 nm), and the third color may be blue having a wavelength band in the range of 370 nm (or approximately 370 nm) to 460 nm (or approximately 460 nm). However, this is only an example, and the wavelength bands of the first color, the second color, and the third color according to some embodiments are not limited thereto.

[0162] Since the emission area EA includes a first emission area EA1, a second emission area EA2 and a third emission area EA3, each of the unit pixels UPX can be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2 and one or more third emission areas EA3 adjacent to each other in the emission area EA.

[0163] Each of the unit pixels UPX may be a unit for displaying various colors including white. That is, various colors of light displayed by the unit pixel UPX may be realized as a mixture of light emitted from two or more emission areas EA included in each unit pixel UPX.

[0164] In the case where the first color of the first emission area EA1, the second color of the second emission area EA2, and the third color of the third emission area EA3 are red, green, and blue, respectively, the third emission area EA3 may have a width greater than that of the first emission area EA1, and the second emission area EA2 may have a width less than that of the first emission area EA1. However, this is only an example, and the width of each of the emission areas EA is not limited to Figure 5 Width shown in .

[0165] Furthermore, the first emission region EA1 and the third emission region EA3 may be alternately arranged in the second direction DR2. In addition, the second emission region EA2 may be arranged side by side in the second direction DR2 and may be positioned between the first emission region EA1 and the third emission region EA3 in the first direction DR1.

[0166] In this case, each of the unit pixels UPX may include one first emission area EA1 and one third emission area EA3 adjacent to each other in the second direction DR2, and two second emission areas EA2 adjacent thereto in the first direction DR1. However, this is only an example, and the arrangement pattern of the emission areas EA and components of the unit pixels UPX according to some embodiments is not limited to Figure 5 Those shown in .

[0167] According to some embodiments, the display area DA includes a light sensing area ODA positioned in a portion of the non-emission area NEA.

[0168] For example, the light-sensing area ODA may be positioned between the second emission areas EA2 having a relatively small width in the second direction DR2. One or more emission areas EA may be positioned between the light-sensing areas ODA in each of the first direction DR1 and the second direction DR2.

[0169] like Figure 4 According to some embodiments, the element layer 130 includes light emitting elements LE respectively positioned in the emission areas EA (see Figure 8 ), and light sensing elements PD respectively arranged in the light sensing area ODA (see Figure 8 ).

[0170] According to some embodiments, the circuit layer 120 may include light emitting pixel drivers EPD (see FIG. 1 ) electrically connected to the light emitting elements LE of the element layer 130, respectively. Figure 7 ), respectively electrically connected to the light sensing element PD of the element layer 130 of the light sensing pixel driver DPD (see Figure 7 ), the data line DL electrically connected to the light-emitting pixel driver EPD (see Figure 7 ), and a readout line ROL electrically connected to the light sensing pixel driver DPD (see Figure 7 ).

[0171] The encapsulation layer 140 may cover the element layer 130 and may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0172] The touch sensor layer 150 may be positioned on the encapsulation layer 140 and may correspond to the main area MA. The touch sensor layer 150 may include a touch electrode for sensing a touch of a person or an object.

[0173] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 and interfaces thereof, and this is to prevent degradation of visibility of an image due to external light reflection.

[0174] Meanwhile, as a portion of the sub-area SBA is deformed into a curved shape, the display driving circuit 200 mounted in the sub-area SBA and the display circuit board 300 connected to one side of the sub-area SBA may be positioned under the substrate 110 .

[0175] The display driving circuit 200 may be electrically connected to the data line DL of the circuit layer 120. The display driving circuit 200 may transmit the data signal Vdata of the light emitting pixel driver EPD to the data line DL based on the control signal and the power voltage supplied from the display circuit board 300.

[0176] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted on the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, this is only an example, and the embodiment is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0177] One end of the display circuit board 300 may be attached to a pad positioned on one edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0178] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0179] The display circuit board 300 may be connected to the signal pad SPD (see Fig.10 ).

[0180] The touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0181] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 of the display device 100 .

[0182] The touch drive circuit 400 may apply a touch drive signal to a drive line of the touch sensor layer 150 and receive a touch sensing signal from a sensing line. In addition, the touch drive circuit 400 may detect the amount of charge change of the capacitor based on the touch sensing signal to determine whether the user touches or approaches. The user's touch means that an object such as a pen or a user's finger directly contacts the top surface of the cover window 11 positioned on the touch sensor layer 150. The user's approach means that an object such as a pen or a user's finger hovers above the top surface of the cover window 11. The touch drive circuit 400 may output touch data including the user's touch coordinates to the main processor 15.

[0183] The scan driving circuit 500 may be electrically connected to the readout line ROL of the circuit layer 120 .

[0184] The scanning driving circuit 500 can collect light sensing signals of the light sensing elements PD positioned in the light sensing area ODA of the main area MA through the light sensing pixel driver DPD and the readout line ROL. In addition, based on the collected light sensing signals, the scanning driving circuit 500 can output scanning data about the shape of the object in contact with the screen to the main processor 15 by detecting the difference in the amount of light reflected by the object in contact with the screen.

[0185] Figure 6 is a diagram showing some embodiments of the present invention. Figure 5 The scanning function of the light sensing area is shown in the diagram.

[0186] Reference Figure 6 , the display device 100 according to some embodiments may include a light sensing element PD positioned in the light sensing area ODA, and thus may provide a scanning function to detect a shape of an object in contact with the screen.

[0187] The fingerprint of the user's finger FG in contact with the cover window 11 includes ridges RID and valleys VAL between the ridges RID. The ridges RID in the fingerprint are in contact with the cover window 11. However, the valleys VAL in the fingerprint are spaced apart from the cover window 11. That is, the top surface of the cover window 11 facing the valleys VAL is in contact with the air.

[0188] The light emitted from the emission area EA may be reflected by the user's finger FG in contact with the cover window 11 and detected by the light sensing element PD of the light sensing area ODA. However, since the refractive index of the finger FG is different from that of air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0189] Accordingly, based on the difference in the amount of light incident on the light sensing element PD, the ridges RID and the valleys VAL in the fingerprint of the finger FG can be derived, so that the fingerprint pattern of the finger FG can be detected.

[0190] Figure 7 is a diagram showing some embodiments of the present invention. Figure 4 Block diagram of the circuit layer.

[0191] Reference Figure 7 According to some embodiments, the circuit layer 120 of the display device 100 may include light-emitting pixel drivers EPD corresponding to the emission areas EA of the display area DA, light-sensing pixel drivers DPD corresponding to the light-sensing areas ODA of the display area DA, data lines DL electrically connected to the light-emitting pixel drivers EPD, and readout lines ROL electrically connected to the light-sensing pixel drivers DPD.

[0192] The display device 100 according to some embodiments may include a data signal Vdata (see Figure 8 ) is transmitted to the display driving circuit 200 of the data line DL, and the scanning driving circuit 500 collects the light sensing signal of the light sensing pixel driver DPD through the readout line ROL.

[0193] The display device 100 according to some embodiments may further include a gate driving circuit 101 that supplies one or more gate signals to the light emitting pixel driver EPD and the light sensing pixel driver DPD, an emission control signal EC (see Figure 8 ) is supplied to the emission control circuit 102 of the light-emitting pixel driver EPD, a power supply unit 700 that supplies various powers and voltages to the light-emitting pixel driver EPD and the light-sensing pixel driver DPD, and a timing controller 800 that controls the driving timing.

[0194] The timing controller 800 receives an image signal supplied from the outside of the display device 100. The timing controller 800 may output the image data DATA and the data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101, and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate the scan control signal SCS and the emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through the scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through the emission control driving line.

[0195] The display driving circuit 200 may convert the image data DATA into analog data voltages and output them to the data lines DL.

[0196] The gate driving circuit 101 may generate a gate signal in response to the scan control signal SCS and sequentially output the gate signal to the gate lines GL. The gate lines GL may include a gate line for transmitting a scan write signal GW (see Figure 8 ) of the scan write line GWL (see Figure 8 ), used to transmit the scan initialization signal GI (see Figure 8 ) of the scan initialization line GIL (see Figure 8 ), used to transmit the gate control signal GC (see Figure 8 ) of the gate control line GCL (see Figure 8 ), used to transmit the bias control signal GB (see Figure 8 ) of the bias control line GBL (see Figure 8 ), and for transmitting a reset control signal GR (see Figure 8 ) of the reset control line GRL (see Figure 8 ).

[0197] The emission control circuit 102 may generate an emission control signal EC (see Figure 8 ) are sequentially output to the emission control line ECL. The emission control signal EC of the emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. Meanwhile, the emission control circuit 102 may not be provided separately from the gate driving circuit 101, but may be incorporated into the gate driving circuit 101.

[0198] The power supply unit 700 may supply various types of power required to drive the light emitting pixel driver EPD and the light sensing pixel driver DPD.

[0199] For example, the power supply unit 700 may supply a first power ELVDD (see Figure 8 ) and the second power ELVSS (see Figure 8 ), and a gate initialization voltage VGINT for initializing the light-emitting pixel driver EPD (see Figure 8 ) and the anode initialization voltage VAINT (see Figure 8 ).

[0200] In addition, the power supply unit 700 may also supply a reset voltage VRST (see Figure 8 ).

[0201] The scan driving circuit 500 may be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD.

[0202] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD, and the scan driving circuit 500 may detect the shape of the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0203] The scan driving circuit 500 may generate scan data according to the magnitude of the photocurrent detected by the photo sensing element PD and transmit it to the main processor 15, and the main processor 15 may compare the scan data with the reference data and execute an application based on whether the scan data matches the user's fingerprint.

[0204] Figure 8 According to some embodiments Figure 7 The equivalent circuit diagram of the light-emitting pixel driver and the light-sensing pixel driver is shown in FIG.

[0205] Reference Figure 8 , one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0206] That is, the anode electrode 131 (see Fig. 9 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (see Fig. 9 ) may be applied with the second power ELVSS having a voltage level lower than that of the first power ELVDD.

[0207] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0208] The circuit layer 120 may further include a first power line VDL for transmitting a first power ELVDD, a gate initialization voltage line VGIL for transmitting a gate initialization voltage VGINT, an anode initialization voltage line VAIL for transmitting an anode initialization voltage VAINT, and a bias power line VBL for transmitting a bias power VBS.

[0209] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0210] A light-emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light-emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1, and at least one capacitor (e.g., a first capacitor PC1) (hereinafter, for the convenience of explanation, the transistor Tn and the nth transistor Tn indicate the same features and are not particularly distinguished in the description).

[0211] The first transistor T1 and the light emitting element LE are connected in series between the first power ELVDD and the second power ELVSS.

[0212] That is, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0213] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0214] The gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0215] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained by the first power ELVDD of the first power line VDL.

[0216] In addition, when the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2 , a voltage difference corresponding to the data signal Vdata and the first power ELVDD may be generated between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 .

[0217] In this case, when a voltage difference between a gate electrode of the first transistor T1 and a first electrode of the first transistor T1 (ie, a gate-source voltage difference) becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0218] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0219] Accordingly, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0220] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0221] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of the gate control line GCL.

[0222] The fourth transistor T4 may be electrically connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0223] The third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0224] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0225] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0226] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0227] The seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the anode initialization voltage line VAIL, and may be turned on by a bias control signal GB of a bias control line GBL.

[0228] The eighth transistor T8 may be connected between the first electrode of the first transistor T1 and the bias power line VBL.

[0229] The eighth transistor T8 may be turned on by a bias control signal GB of a bias control line GBL.

[0230] Among the first to eighth transistors T1 to T8 , the transistors T1 , T2 , and T5 to T8 excluding the third and fourth transistors T3 and T4 may be provided as P-type MOSFETs.

[0231] In addition, one of the light sensing elements PD of the element layer 130 may be electrically connected between the element output node NOP of one of the light sensing pixel drivers DPD of the circuit layer 120 and the second power ELVSS.

[0232] The circuit layer 120 may also include a reset control line GRL for transmitting a reset control signal GR for starting the reset of the light sensing pixel driver DPD, a reset voltage line VRL for transmitting a reset voltage VRST for resetting the light sensing pixel driver DPD, and a readout line ROL that electrically connects the light sensing pixel driver DPD to the scan driving circuit 500.

[0233] Each of the light-sensing pixel drivers DPD may include at least one transistor T9 , T10 , T11 .

[0234] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a light sensing signal.

[0235] The light sensing element PD may be a photodiode including a sensing anode electrode, a sensing cathode electrode, and a photoelectric conversion layer positioned between the sensing anode electrode and the sensing cathode electrode.

[0236] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a pn-type or pin-type inorganic material. Alternatively, the light sensing element PD may also be an organic photodiode including an electron donating material that generates donor ions and an electron accepting material that generates acceptor ions.

[0237] When light is incident on the light sensing element PD, the photoelectric conversion layer may react to the incident light to generate photocharges, and the photocharges generated in the photoelectric conversion layer may move, thereby generating a photocurrent between the sensing anode electrode and the sensing cathode electrode.

[0238] As an example, the photoelectric charge generated in the photoelectric conversion layer by the light incident on the light sensing element PD may be accumulated in the sensing anode electrode. In addition, the potential of the element output node NOP electrically connected to the sensing anode electrode may be increased by the photoelectric charge accumulated in the sensing anode electrode. When the light sensing element PD and the readout line ROL are connected to the element output node NOP by the conduction of the ninth transistor T9 and the eleventh transistor T11, the sensing voltage may be accumulated at the node N3 between the readout line ROL and the eleventh transistor T11 in proportion to the voltage of the element output node NOP at the charge accumulation.

[0239] The ninth transistor T9 may include a gate electrode electrically connected to the element output node NOP, and may be electrically connected between the anode initialization voltage line VAIL and the eleventh transistor T11 .

[0240] The ninth transistor T9 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge input to the element output node NOP of the gate electrode thereof.

[0241] That is, when the potential of the element output node NOP is increased by the photocharge accumulated in the light sensing element PD and the voltage difference between the anode initialization voltage VAINT and the potential of the element output node NOP becomes equal to or greater than the threshold voltage of the ninth transistor T9, the ninth transistor T9 may be turned on. In this case, a light sensing signal corresponding to the voltage difference between the anode initialization voltage VAINT and the potential of the element output node NOP may be generated by the turned-on ninth transistor T9.

[0242] At the same time, despite Figure 8 The first electrode of the ninth transistor T9 is shown to be connected to the anode initialization voltage line VAIL, but the embodiment is not limited to Figure 8 That is, the first electrode of the ninth transistor T9 may be connected to one of the first power line VDL and the gate initialization voltage line VGIL, instead of being connected to the anode initialization voltage line VAIL.

[0243] The tenth transistor T10 may be electrically connected between the element output node NOP and the reset voltage line VRL, and may be turned on by the reset control signal GR of the reset control line GRL. Accordingly, when the tenth transistor T10 is turned on by the reset control signal GR, the potential of the element output node NOP may be reset to the reset voltage VRST of the reset voltage line VRL.

[0244] The eleventh transistor T11 may be electrically connected between the second electrode of the ninth transistor T9 and the readout line ROL, and may be turned on by the scan write signal GW of the scan write line GWL. Accordingly, the source-drain current of the ninth transistor T9 (i.e., the light sensing signal) may be transmitted to the readout line ROL through the eleventh transistor T11 turned on by the scan write signal GW.

[0245] The ninth transistor T9 and the eleventh transistor T11 may be provided as P-type MOSFETs, and the tenth transistor T10 may be provided as an N-type MOSFET.

[0246] Fig. 9 is a diagram showing some embodiments of the present invention. Figure 8 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light-emitting element.

[0247] Reference Fig. 9 According to some embodiments, the circuit layer 120 of the display device 100 may include a buffer layer 121 covering the first light blocking layer LB1 on the substrate 110, first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6 positioned on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6, first gate conductive layers G1, G2 and G6 positioned on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layers G1, G2 and G6, a second gate conductive layer CPE and LB2 positioned on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer CPE and LB2, and a first interlayer insulating layer 125 positioned on the first interlayer insulating layer 126. 4, a second semiconductor layer CH4, S4 and D4 on the third gate insulating layer 125 covering the second semiconductor layers CH4, S4 and D4, a third gate conductive layer G4 positioned on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer G4, a first source / drain conductive layer ANCE1, DCE1, GCNE and VGIL positioned on the second interlayer insulating layer 126, a first planarizing layer 127 covering the first source / drain conductive layer ANCE1, DCE1, GCNE and VGIL, a second source / drain conductive layer ANCE2 and DCE2 positioned on the first planarizing layer 127, a second planarizing layer 128 covering the second source / drain conductive layer ANCE2 and DCE2, and a third source / drain conductive layer ANCE3 and DL positioned on the second planarizing layer 128.

[0248] The first transistor T1 may include a channel portion CH1 formed of a first semiconductor layer on the buffer layer 121 , a source portion S1 and a drain portion D1 , and a gate electrode G1 positioned on the first gate insulating layer 122 and overlapping the channel portion CH1 .

[0249] A channel portion CH1 of the first transistor T1 may overlap the first light blocking layer LB1 on the substrate 110 .

[0250] The second transistor T2 may include a channel portion CH2 formed of the first semiconductor layer on the buffer layer 121 , a source portion S2 and a drain portion D2 , and a gate electrode G2 positioned on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0251] The sixth transistor T6 may include a channel portion CH6 formed of the first semiconductor layer on the buffer layer 121 , a source portion S6 and a drain portion D6 , and a gate electrode G6 positioned on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0252] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through the first data link electrode DCE1 and the second data link electrode DCE2.

[0253] The first data link electrode DCE1 may be positioned on the second interlayer insulating layer 126 and may be electrically connected to the source portion S2 of the second transistor T2 through a first data contact hole DCH1 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0254] The second data link electrode DCE2 may be positioned on the first planarization layer 127 and may be electrically connected to the first data link electrode DCE1 through a second data contact hole DCH2 penetrating the first planarization layer 127 .

[0255] The data line DL may be positioned on the second planarization layer 128 and may be electrically connected to the second data link electrode DCE2 through a third data contact hole DCH3 penetrating the second planarization layer 128 .

[0256] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1 .

[0257] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6 .

[0258] The drain portion D6 of the sixth transistor T6 may be electrically connected to the anode electrode 131 through the first, second, and third anode connection electrodes ANCE1, ANCE2, and ANCE3.

[0259] The first anode connection electrode ANCE1 may be positioned on the second interlayer insulating layer 126 and may be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode contact hole ANCH1 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0260] The second anode connection electrode ANCE2 may be positioned on the first planarization layer 127 and may be electrically connected to the first anode connection electrode ANCE1 through a second anode contact hole ANCH2 penetrating the first planarization layer 127 .

[0261] The third anode connection electrode ANCE3 may be positioned on the second planarization layer 128 and may be electrically connected to the second anode connection electrode ANCE2 through a third anode contact hole ANCH3 penetrating the second planarization layer 128 .

[0262] The anode electrode 131 may be positioned on the third planarization layer 129 and may be electrically connected to the third anode connection electrode ANCE3 through a fourth anode contact hole ANCH4 penetrating the third planarization layer 129. The pixel defining layer 132 may be positioned on the third planarization layer 129 and cover an edge of the anode electrode 131. The light emitting layer 133 may be positioned on the anode electrode 131 in an opening provided in the pixel defining layer 132. The cathode electrode 134 may be provided to cover the pixel defining layer 132 and the light emitting layer 133.

[0263] The first capacitor PC1 may be provided by an overlap region between the capacitor electrode CPE positioned on the second gate insulating layer 123 and the gate electrode G1 of the first transistor T1 .

[0264] The fourth transistor T4 may include a channel portion CH4 formed of the second semiconductor layer on the first interlayer insulating layer 124 , a source portion S4 and a drain portion D4 , and a gate electrode G4 positioned on the third gate insulating layer 125 and overlapping the channel portion CH4 .

[0265] A channel portion CH4 of the fourth transistor T4 may overlap the second light blocking layer LB2 on the second gate insulating layer 123 .

[0266] The source portion S4 of the fourth transistor T4 may be electrically connected to a gate initialization voltage line VGIL on the second interlayer insulating layer 126 through a hole VICH penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0267] The drain portion D4 of the fourth transistor T4 may be electrically connected to the gate electrode G1 of the first transistor T1 through the gate connection electrode GCNE on the second interlayer insulating layer 126 .

[0268] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 through the first gate contact hole GCH1 penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0269] The gate connection electrode GCNE may be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate contact hole GCH2 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , and the second gate insulating layer 123 .

[0270] At the same time, since the third transistor T3, the tenth transistor T10 are similar in structure to the fourth transistor T4, and the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are similar in structure to the second transistor T2 and the sixth transistor T6, some redundant descriptions of the same or similar elements will be omitted below.

[0271] In addition, according to some embodiments, the circuit layer 120 of the display device 100 may also include wiring electrically connected between some of the data lines DL and the display driving circuit 200 and positioned in the display area DA, and wiring electrically connected between some of the read-out lines ROL and the scan driving circuit 500 and positioned in the display area DA, so as to reduce the width of the non-display area NDA.

[0272] Fig.10 is a diagram showing some embodiments of the present invention. Figure 2 A plan view of the substrate.

[0273] Reference Fig.10 , the substrate 110 of the display device 100 according to some embodiments may include a main area MA corresponding to a display surface, and a sub area SBA protruding from one side of the main area MA.

[0274] The main area MA may include a display area DA positioned in the center of the substrate 110 , and a non-display area NDA positioned at an edge of the display device 100 to surround the display area DA (eg, outside a periphery or footprint thereof).

[0275] The display area DA may include a bypass area DEA positioned on one side adjacent to the sub-area SBA, and a general area GA positioned in a remaining area except the bypass area DEA.

[0276] The bypass area DEA may include a bypass middle area MDDA positioned at the center in the first direction DR1, a first bypass side area SDA1 parallel to the bypass middle area MDDA in the first direction DR1 and in contact with the non-display area NDA, a second bypass side area SDA2 positioned between the bypass middle area MDDA and the first bypass side area SDA1, and a third bypass side area SDA3 positioned between the first bypass side area SDA1 and the second bypass side area SDA2.

[0277] The first bypass side area SDA1 may be located closer to a bending corner of the substrate 110 than the bypass middle area MDDA, the second bypass side area SDA2, and the third bypass side area SDA3.

[0278] The first, third, and second bypass side areas SDA1, SDA3, and SDA2 may be positioned between each of both sides of the bypass middle area MDDA in the first direction DR1 and the non-display area NDA.

[0279] The general area GA may include a general middle area GMA of a bypass middle area MDDA connected to the bypass area DEA in the second direction DR2, a first general side area GSA1 connected to the first bypass side area SDA1 in the second direction DR2, a second general side area GSA2 connected to the second bypass side area SDA2 in the second direction DR2, and a third general side area GSA3 connected to the third bypass side area SDA3 in the second direction DR2.

[0280] The non-display area NDA may include a gate driving circuit area GDRA in which the gate driving circuit 101 and the emission control circuit 102 are located.

[0281] The gate driving circuit area GDRA may be positioned in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0282] The sub-region SBA may include the bending area BA deformed into a bent shape, a first sub-region SB1 positioned between one side of the bending area BA and the main area MA, and a second sub-region SB2 connected to the other side of the bending area BA.

[0283] When the bending area BA is deformed into a bent shape, the second sub-area SB2 is positioned under the substrate 110 and overlaps the main area MA.

[0284] The display driving circuit 200 may be positioned in the second sub-region SB2 .

[0285] The signal pad SPD bonded to the display circuit board 300 may be positioned at one edge of the second sub-region SB2 .

[0286] Fig.11 It is shown Fig.10 Layout diagram of part C. Fig.12 is along Fig.11 A cross-sectional view taken along line D-D'.

[0287] See also Fig.11 According to some embodiments, the circuit layer 120 of the display device 100 may include light emitting elements LE electrically connected to the element layer 130 and arranged side by side in the first direction DR1 and the second direction DR2, data lines DL extending in the second direction DR2 and transmitting data signals Vdata to the light emitting pixel drivers EPD, first auxiliary lines ASL1 extending in the first direction DR1, second auxiliary lines ASL2 extending in the second direction DR2 and paired with the data lines DL, and mesh auxiliary lines MAL extending in the second direction DR2.

[0288] According to some embodiments, the circuit layer 120 may further include light sensing pixel drivers DPD electrically connected to the light sensing elements PD of the element layer 130 , respectively, and readout lines ROL extending in the second direction DR2 and electrically connected to the light sensing pixel drivers DPD to transmit light sensing signals.

[0289] According to some embodiments, the data lines DL may include a first data line DL1 positioned in the first bypass side area SDA1, and a second data line DL2 positioned in the second bypass side area SDA2.

[0290] The first auxiliary line ASL1 may include a first bypass auxiliary line TASL1 electrically connected to the first data line DL1 of the first bypass side area SDA1.

[0291] The second auxiliary line ASL2 may include a second bypass auxiliary line TASL2 paired with the second data line DL2 of the second bypass side area SDA2 and electrically connected to the first bypass auxiliary line TASL1.

[0292] According to some embodiments, the circuit layer 120 may further include a data supply line DSPL positioned in the non-display area NDA and electrically connected to the display driving circuit 200 and the data line DL.

[0293] The data supply lines DSPL may include a first data supply line DSPL1 transmitting a data signal of the first data line DL1 and a second data supply line DSPL2 transmitting a data signal of the second data line DL2 .

[0294] According to some embodiments, the data supply line DSPL may extend to the second bypass side area SDA2 and the bypass middle area MDDA.

[0295] Accordingly, the first data supply line DSPL1 may extend to the second bypass auxiliary line TASL2 of the second bypass side area SDA2 and may be electrically connected to the first data line DL1 through the second bypass auxiliary line TASL2 and the first bypass auxiliary line TASL1.

[0296] On the other hand, the second data supply line DSPL2 may extend to the second bypass side area SDA2 and may be directly electrically connected to the second data line DL2.

[0297] The data lines DL may further include a third data line DL3 positioned in the bypass middle area MDDA, and the data supply line DSPL may further include a third data supply line DSPL3 transmitting a data signal of the third data line DL3.

[0298] The third data supply line DSPL3 may extend to the bypass middle area MDDA and may be directly electrically connected to the third data line DL3 .

[0299] In this way, since the first data supply line DSPL1 does not extend to the first data line DL1 of the first bypass side area SDA1 but extends to the second bypass auxiliary line TASL2 of the second bypass side area SDA2, the extension length of the first data supply line DSPL1 can be shortened. As a result, the width of the area required for the arrangement of the data supply line DSPL can be reduced, so that the width of the non-display area NDA can be reduced.

[0300] In addition, since the data supply line DSPL is not positioned in a portion of the non-display area NDA positioned between the bent corner of the substrate 110 and the first bypass side area SDA1 , the width of the non-display area NDA can be further reduced.

[0301] The first bypass auxiliary line TASL1 extends from the second bypass auxiliary line TASL2 to the first data line DL1.

[0302] The second bypass auxiliary line TASL2 extends from the first data supply line DSPL1 of the non-display area NDA to the first bypass auxiliary line TASL1.

[0303] In this way, as the first and second bypass auxiliary lines TASL1 and TASL2 are restrictively arranged in the bypass area DEA, the ends of the first and second bypass auxiliary lines TASL1 and TASL2 are regularly arranged. Accordingly, the visibility of the first and second bypass auxiliary lines TASL1 and TASL2 may be increased.

[0304] To prevent this, the first auxiliary line ASL1 may include not only the first bypass auxiliary line TASL1 but also the second power auxiliary horizontal line VSAHL. Also, the second auxiliary line ASL2 may include not only the second bypass auxiliary line TASL2 but also the second power auxiliary vertical line VSAVL.

[0305] Two of the second power auxiliary transverse lines VSAHL may extend from both ends of the first bypass auxiliary line TASL1 to the non-display area NDA.

[0306] One of the second power auxiliary longitudinal lines VSAVL may extend from one end of the second bypass auxiliary line TASL2 to the non-display area NDA in a direction away from the sub-area SBA.

[0307] Accordingly, a portion of each second data line DL2 is paired with the second bypass auxiliary line TASL2, and another portion of the second data line DL2 may be paired with one second power auxiliary longitudinal line VSAVL extending from one end of the second bypass auxiliary line TASL2.

[0308] Since the second bypass auxiliary line TASL2 is positioned only in the second bypass side area SDA2 , the first data line DL1 of the first bypass side area SDA1 may be paired with the second power auxiliary longitudinal line VSAVL as a whole.

[0309] The third data line DL3 of the bypass middle area MDDA may be generally paired with the second power auxiliary longitudinal line VSAVL.

[0310] The circuit layer 120 may further include a first power supply line VDSPL and a second power supply line VSSPL that transmit a first power ELVDD and a second power ELVSS for driving the light emitting element LE, respectively.

[0311] The first power supply line VDSPL and the second power supply line VSSPL may be positioned in the non-display area NDA and may extend to the sub-area SBA.

[0312] The first power supply line VDSPL may be electrically connected to a first power pad for transmitting the first power ELVDD among the signal pads SPD positioned in the second sub-region SB2 .

[0313] The second power supply line VSSPL may be electrically connected to a second power pad for transmitting the second power ELVSS among the signal pads SPD positioned in the second sub-region SB2 .

[0314] The second power auxiliary lateral line VSAHL may be electrically connected to the second power supply line VSSPL and may transmit the second power ELVSS.

[0315] The second power auxiliary longitudinal line VSAVL may be electrically connected to the second power auxiliary transverse line VSAHL and the second power supply line VSSPL to transfer the second power ELVSS.

[0316] According to some embodiments, the circuit layer 120 may include an anode initialization voltage line VAIL transmitting an anode initialization voltage VAINT, and a gate initialization voltage line VGIL transmitting a gate initialization voltage VGINT.

[0317] At the same time, Figure 5 As shown in FIG. 1 , the emission area EA may include a first emission area EA1 , a second emission area EA2 , and a third emission area EA3 .

[0318] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be arranged side by side in the first direction DR1.

[0319] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in the second direction DR2.

[0320] The second emission region EA2 may be arranged side by side in the second direction DR2 and may be adjacent to the first emission region EA1 and the third emission region EA3 in a fourth direction DR4 or a fifth direction DR5 inclined with respect to the first direction DR1 and the second direction DR2.

[0321] Since the second emission area EA2 has a width smaller than those of the first emission area EA1 and the third emission area EA3, when the light-emitting elements of the second emission area EA2 are initialized to the same voltage level as those of the first emission area EA1 and the third emission area EA3, it may be difficult to display the brightness corresponding to the data signal Vdata.

[0322] Therefore, according to some embodiments, the anode initialization voltage line VAIL may include a first anode initialization voltage line VAIL1 (see Fig.13 ), and a second anode initialization voltage line VAIL2 (see Fig.13 ).

[0323] In one example, the first anode initialization voltage may be used to initialize the light emitting elements in the first emission area EA1 and the third emission area EA3, and the second anode initialization voltage may be used to initialize the light emitting elements in the second emission area EA2.

[0324] That is, the circuit layer 120 according to some embodiments may include a first anode initialization voltage line VAIL1 transmitting a first anode initialization voltage, a second anode initialization voltage line VAIL2 transmitting a second anode initialization voltage, and a gate initialization voltage line VGIL transmitting a gate initialization voltage VGINT.

[0325] According to some embodiments, each of the light emitting pixel drivers EPD may overlap one data line DL, one second auxiliary line ASL2, and one first auxiliary line ASL1.

[0326] According to some embodiments, at least one readout line ROL may be positioned between two data lines DL overlapping any two light emitting pixel drivers EPD adjacent to each other in the first direction DR1 .

[0327] According to some embodiments, one of the mesh auxiliary lines MAL may be positioned between two second auxiliary lines ASL2 overlapping other two light emitting pixel drivers EPD adjacent in the first direction DR1 .

[0328] The mesh auxiliary line MAL extends in the second direction DR2 and is electrically connected to the constant voltage line extending in the first direction DR1 to provide a mesh-shaped wiring structure. The constant voltage line may include a gate initialization voltage line VGIL transmitting a gate initialization voltage VGINT, an anode initialization voltage line VAIL transmitting an anode initialization voltage VAINT, a second power auxiliary lateral line VSAHL transmitting a second power ELVSS, and the like.

[0329] That is, the grid auxiliary line MAL may include a first grid auxiliary line MAL1 electrically connected to the first anode initialization voltage line VAIL1, a second grid auxiliary line MAL2 electrically connected to the second anode initialization voltage line VAIL2, a third grid auxiliary line MAL3 electrically connected to the gate initialization voltage line VGIL, and a fourth grid auxiliary line MAL4 electrically connected to at least one of the second power auxiliary lateral lines VSAHL.

[0330] Reference Fig.12 The data line DL, the second auxiliary line ASL2, the mesh auxiliary line MAL, and the readout line ROL may be positioned on at least one insulating layer (eg, the first planarization layer 127 and the second planarization layer 128) covering the first auxiliary line ASL1.

[0331] For example, the first auxiliary line ASL1 may be positioned in the first source / drain conductive layer on the second interlayer insulating layer 126 and covered with the first planarization layer 127 .

[0332] The data line DL, the second auxiliary line ASL2 , the mesh auxiliary line MAL, and the readout line ROL may be positioned in the third source / drain conductive layer on the second planarization layer 128 .

[0333] In this case, the first data line DL1 may be electrically connected to the first bypass auxiliary line TASL1 through a contact hole penetrating the second planarization layer 128 and the first planarization layer 127 .

[0334] The second bypass auxiliary line TASL2 may also be electrically connected to the first bypass auxiliary line TASL1 through a contact hole penetrating the second planarization layer 128 and the first planarization layer 127 .

[0335] Fig.13 is a diagram showing some embodiments of the present invention. Fig.11 Floor plan of Section E. Fig.14 is along Fig.13 A cross-sectional view taken along line II'. Fig.15 is along Fig.13 A cross-sectional view taken along line J-J'. Fig.16 is a diagram showing some embodiments of the present invention. Fig.11 Floor plan of Section F. Fig.17 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section G. Fig.18 is along Fig.17 A cross-sectional view taken along line K-K'.

[0336] exist Fig.13 , Fig.16 and Fig.17 In each of the embodiments, any two light-emitting pixel drivers EPD located in the second bypass side area SDA2 and adjacent to each other in the first direction DR1 are shown as a first light-emitting pixel driver EPD1 and a second light-emitting pixel driver EPD2. In this case, the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may be electrically connected to the second data line DL2, respectively.

[0337] Reference Fig.13 , Fig.16 and Fig.17 According to some embodiments, the circuit layer 120 of the display device 100 may further include a second auxiliary line ASL2 (ie, Fig.13 , Fig.16 and Fig.17A first connection auxiliary electrode CASE1 (a second bypass auxiliary line TASL2 in the embodiment of the present invention) and a second connection auxiliary electrode CASE2 overlapping with the first connection auxiliary electrode CASE1 and electrically connected to the first connection auxiliary electrode CASE1 through a first connection auxiliary contact hole CACT1 are connected to a first auxiliary line ASL1 (i.e., Fig.13 , Fig.16 and Fig.17 A third connection auxiliary electrode CASE3 of the first bypass auxiliary line TASL1 in the embodiment of the present invention, and a fourth connection auxiliary electrode CASE4 overlapping the third connection auxiliary electrode CASE3 and electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary contact hole CACT2.

[0338] According to some embodiments, the third connection auxiliary electrode CASE3 and the fourth connection auxiliary electrode CASE4 overlapped therewith may be positioned in the second light emitting pixel driver EPD2.

[0339] According to some embodiments, the circuit layer 120 may further include a circuit layer 120 positioned to align with the grid auxiliary line MAL (ie, Fig.13 MAL1 in Fig.16 MAL2 in Fig.17 MAL3 and Fig.19 A fifth connection auxiliary electrode CASE5 adjacent to the crossing area between the first auxiliary lines ASL4 and connected to the mesh auxiliary line MAL, and a sixth connection auxiliary electrode CASE6 overlapping with the fifth connection auxiliary electrode CASE5 and electrically connected to the fifth connection auxiliary electrode CASE5 through a third connection auxiliary contact hole CACT3.

[0340] According to some embodiments, one first anode initialization voltage line VAIL1 overlapping the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may be positioned adjacent to one side (e.g., lower side) of one first auxiliary line ASL1 in the second direction DR2. In addition, one second anode initialization voltage line VAIL2 overlapping the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may be positioned adjacent to one side of the first anode initialization voltage line VAIL1 in the second direction DR2.

[0341] According to some embodiments, the circuit layer 120 may further include a seventh connection auxiliary electrode CASE7 positioned between the first anode initialization voltage line VAIL1 and the second anode initialization voltage line VAIL2 in the second direction DR2 in the first light-emitting pixel driver EPD1 and spaced apart from the first anode initialization voltage line VAIL1 and the second anode initialization voltage line VAIL2, an eighth connection auxiliary electrode CASE8 overlapping with the seventh connection auxiliary electrode CASE7 and electrically connected to the seventh connection auxiliary electrode CASE7 through a fourth connection auxiliary contact hole CACT4, a ninth connection auxiliary electrode CASE9 positioned between the first anode initialization voltage line VAIL1 and the second anode initialization voltage line VAIL2 in the second light-emitting pixel driver EPD2 and spaced apart from the first anode initialization voltage line VAIL1 and the second anode initialization voltage line VAIL2, and a tenth connection auxiliary electrode CASE10 overlapping with the ninth connection auxiliary electrode CASE9 and electrically connected to the ninth connection auxiliary electrode CASE9 through a fifth connection auxiliary contact hole CACT5.

[0342] According to some embodiments, one gate initialization voltage line VGIL overlapping the first and second light emitting pixel drivers EPD1 and EPD2 may be positioned adjacent to the other side (eg, upper side) of one first auxiliary line ASL1 in the second direction DR2 .

[0343] According to some embodiments, the circuit layer 120 may further include an eleventh connection auxiliary electrode CASE11 positioned between the gate initialization voltage line VGIL and one first auxiliary line ASL1, and a twelfth connection auxiliary electrode CASE12 overlapping the eleventh connection auxiliary electrode CASE11 and electrically connected to the eleventh connection auxiliary electrode CASE11 through a sixth connection auxiliary contact hole CACT6.

[0344] According to some embodiments, the circuit layer 120 may include a first power line VDL transmitting the first power ELVDD. The first power line VDL may be positioned at the same layer as the second connection auxiliary electrode CASE2, the fourth connection auxiliary electrode CASE4, the sixth connection auxiliary electrode CASE6, the eighth connection auxiliary electrode CASE8, the tenth connection auxiliary electrode CASE10, and the twelfth connection auxiliary electrode CASE12.

[0345] In an example, the first power line VDL, the second connection auxiliary electrode CASE2, the fourth connection auxiliary electrode CASE4, the sixth connection auxiliary electrode CASE6, the eighth connection auxiliary electrode CASE8, the tenth connection auxiliary electrode CASE10 and the twelfth connection auxiliary electrode CASE12 may be in the second source / drain conductive layer positioned on the first planarization layer 127.

[0346] Accordingly, the first power line VDL may be spaced apart from the second connection auxiliary electrode CASE2, the fourth connection auxiliary electrode CASE4, the sixth connection auxiliary electrode CASE6, the eighth connection auxiliary electrode CASE8, the tenth connection auxiliary electrode CASE10, and the twelfth connection auxiliary electrode CASE12. That is, the first power line VDL may be arranged to surround the area in which the second connection auxiliary electrode CASE2, the fourth connection auxiliary electrode CASE4, the sixth connection auxiliary electrode CASE6, the eighth connection auxiliary electrode CASE8, the tenth connection auxiliary electrode CASE10, and the twelfth connection auxiliary electrode CASE12 are located.

[0347] Reference Fig.13 and Fig.14 , the first light emitting pixel driver EPD1 may overlap a crossing region between the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2.

[0348] In this case, the circuit layer 120 may further include a first connection auxiliary line CNAL1 connecting the second connection auxiliary electrode CASE2 to the fourth connection auxiliary electrode CASE4.

[0349] The second connection auxiliary electrode CASE2 may be electrically connected to the second bypass auxiliary line TASL2 through the first connection auxiliary contact hole CACT1 and the first connection auxiliary electrode CASE1.

[0350] The fourth connection auxiliary electrode CASE4 may be electrically connected to the first bypass auxiliary line TASL1 through the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3 .

[0351] Accordingly, when the first connection auxiliary line CNAL1 is provided to connect the second connection auxiliary electrode CASE2 to the fourth connection auxiliary electrode CASE4, the second bypass auxiliary line TASL2 can be electrically connected to the first bypass auxiliary line TASL1 through the first connection auxiliary electrode CASE1, the first connection auxiliary contact hole CACT1, the second connection auxiliary electrode CASE2, the first connection auxiliary line CNAL1, the fourth connection auxiliary electrode CASE4, the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3.

[0352] The first connection auxiliary line CNAL1 may be positioned adjacent to the gate initialization voltage line VGIL. In this case, the first connection auxiliary line CNAL1 may be connected to the twelfth connection auxiliary electrode CASE12 positioned between the gate initialization voltage line VGIL and the first bypass auxiliary line TASL1. In this way, the length of the first connection auxiliary line CNAL1 may be reduced while reducing the possibility of disconnection of the first connection auxiliary line CNAL1, which may be beneficial to reducing the width of the light-emitting pixel driver EPD.

[0353] That is to say, even if the third connection auxiliary electrode CASE3 connected to a first bypass auxiliary line TASL1 overlapping with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 is not provided in the first light-emitting pixel driver EPD1, the electrical connection between a second bypass auxiliary line TASL2 overlapping with the first light-emitting pixel driver EPD1 and a first bypass auxiliary line TASL1 can be achieved through the first connection auxiliary line CNAL1.

[0354] As described above, according to some embodiments, among the first and second light emitting pixel drivers EPD1 and EPD2, the first connection auxiliary electrode CASE1 may be located only in the first light emitting pixel driver EPD1, and the third connection auxiliary electrode CASE3 may be located only in the second light emitting pixel driver EPD2.

[0355] That is, the first and second light emitting pixel drivers EPD1 and EPD2 may include only different ones of the first and third connection auxiliary electrodes CASE1 and CASE3 so that the width of the light emitting pixel driver EPD may be reduced, resulting in an improvement in resolution.

[0356] Meanwhile, although not separately shown in the drawings, for electrical connection between another second bypass auxiliary line TASL2 overlapping the second light-emitting pixel driver EPD2 and one first bypass auxiliary line TASL1, positions of the first connection auxiliary electrode CASE1 and the third connection auxiliary electrode CASE3 may be reversed in the first direction DR1. That is, the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 may be positioned in the second light-emitting pixel driver EPD2, and the third connection auxiliary electrode CASE3 and the fourth connection auxiliary electrode CASE4 may be positioned in the first light-emitting pixel driver EPD1.

[0357] Reference Fig.13 and Fig.15Among the mesh auxiliary lines MAL, the first mesh auxiliary line MAL1 electrically connected to the first anode initialization voltage line VAIL1 may be positioned adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. In this case, the circuit layer 120 may further include a second connection auxiliary line CNAL2 connecting the first anode initialization voltage line VAIL1 to the seventh connection auxiliary electrode CASE7, and a third connection auxiliary line CNAL3 connecting the sixth connection auxiliary electrode CASE6 to the eighth connection auxiliary electrode CASE8.

[0358] The seventh connection auxiliary electrode CASE7 may be electrically connected to the eighth connection auxiliary electrode CASE8 through the fourth connection auxiliary contact hole CACT4.

[0359] The sixth connection auxiliary electrode CASE6 may be electrically connected to the first mesh auxiliary line MAL1 through the third connection auxiliary contact hole CACT3 and the fifth connection auxiliary electrode CASE5 .

[0360] Accordingly, when a second connection auxiliary line CNAL2 connecting the seventh connection auxiliary electrode CASE7 to the first anode initialization voltage line VAIL1 and a third connection auxiliary line CNAL3 connecting the sixth connection auxiliary electrode CASE6 to the eighth connection auxiliary electrode CASE8 are provided, the first grid auxiliary line MAL1 can be electrically connected to the first anode initialization voltage line VAIL1 through the fifth connection auxiliary electrode CASE5, the third connection auxiliary contact hole CACT3, the sixth connection auxiliary electrode CASE6, the third connection auxiliary line CNAL3, the eighth connection auxiliary electrode CASE8, the fourth connection auxiliary contact hole CACT4, the seventh connection auxiliary electrode CASE7 and the second connection auxiliary line CNAL2.

[0361] Reference Fig.16 Among the mesh auxiliary lines MAL, the second mesh auxiliary line MAL2 electrically connected to the second anode initialization voltage line VAIL2 may be positioned adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. In this case, the circuit layer 120 may further include a fourth connection auxiliary line CNAL4 connecting the second anode initialization voltage line VAIL2 to the ninth connection auxiliary electrode CASE9, and a fifth connection auxiliary line CNAL5 connecting the sixth connection auxiliary electrode CASE6 to the tenth connection auxiliary electrode CASE10.

[0362] The ninth connection auxiliary electrode CASE9 may be electrically connected to the tenth connection auxiliary electrode CASE10 through the fifth connection auxiliary contact hole CACT5 .

[0363] The sixth connection auxiliary electrode CASE6 may be electrically connected to the second mesh auxiliary line MAL2 through the third connection auxiliary contact hole CACT3 and the fifth connection auxiliary electrode CASE5 .

[0364] Accordingly, when a fourth connection auxiliary line CNAL4 connecting the ninth connection auxiliary electrode CASE9 to the second anode initialization voltage line VAIL2 and a fifth connection auxiliary line CNAL5 connecting the sixth connection auxiliary electrode CASE6 to the tenth connection auxiliary electrode CASE10 are provided, the second grid auxiliary line MAL2 can be electrically connected to the second anode initialization voltage line VAIL2 through the fifth connection auxiliary electrode CASE5, the third connection auxiliary contact hole CACT3, the sixth connection auxiliary electrode CASE6, the fifth connection auxiliary line CNAL5, the tenth connection auxiliary electrode CASE10, the fifth connection auxiliary contact hole CACT5, the ninth connection auxiliary electrode CASE9 and the fourth connection auxiliary line CNAL4.

[0365] Reference Fig.17 and Fig.18 Among the grid auxiliary lines MAL, a third grid auxiliary line MAL3 electrically connected to the gate initialization voltage line VGIL may be positioned adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. In this case, the circuit layer 120 may further include a sixth connection auxiliary line CNAL6 connecting the gate initialization voltage line VGIL to the eleventh connection auxiliary electrode CASE11, and a seventh connection auxiliary line CNAL7 connecting the sixth connection auxiliary electrode CASE6 to the twelfth connection auxiliary electrode CASE12.

[0366] The eleventh connection auxiliary electrode CASE11 may be electrically connected to the twelfth connection auxiliary electrode CASE12 through the sixth connection auxiliary contact hole CACT6 .

[0367] The sixth connection auxiliary electrode CASE6 may be electrically connected to the third mesh auxiliary line MAL3 through the third connection auxiliary contact hole CACT3 and the fifth connection auxiliary electrode CASE5 .

[0368] Accordingly, when a sixth connection auxiliary line CNAL6 connecting the eleventh connection auxiliary electrode CASE11 to the gate initialization voltage line VGIL and a seventh connection auxiliary line CNAL7 connecting the sixth connection auxiliary electrode CASE6 to the twelfth connection auxiliary electrode CASE12 are provided, the third grid auxiliary line MAL3 can be electrically connected to the gate initialization voltage line VGIL through the fifth connection auxiliary electrode CASE5, the third connection auxiliary contact hole CACT3, the sixth connection auxiliary electrode CASE6, the seventh connection auxiliary line CNAL7, the twelfth connection auxiliary electrode CASE12, the sixth connection auxiliary contact hole CACT6, the eleventh connection auxiliary electrode CASE11 and the sixth connection auxiliary line CNAL6.

[0369] When the sixth connection auxiliary line CNAL6 is provided to connect the gate initialization voltage line VGIL to the eleventh connection auxiliary electrode CASE11, the first connection auxiliary line CNAL1 may be positioned adjacent to the first anode initialization voltage line VAIL1 so as to avoid the sixth connection auxiliary line CNAL6. In this case, the first connection auxiliary line CNAL1 may be connected to at least one of the eighth connection auxiliary electrode CASE8 and the tenth connection auxiliary electrode CASE10.

[0370] Fig.19 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section H. Fig. 20 is along Fig.19 A cross-sectional view taken along line L-L'.

[0371] exist Fig.19 , the other two light-emitting pixel drivers EPD located in the bypass middle area MDDA and adjacent to each other in the first direction DR1 are shown as a third light-emitting pixel driver EPD3 and a fourth light-emitting pixel driver EPD4. In this case, the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4 may be electrically connected to the third data line DL3, respectively. Meanwhile, in the following, Fig.19 The third light emitting pixel driver EPD3 and the fourth light emitting pixel driver EPD4 may also be referred to as the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 adjacent to each other in the first direction DR1.

[0372] Reference Fig.19 According to some embodiments, the third light emitting pixel driver EPD3 and the fourth light emitting pixel driver EPD4 are Fig.13 , Fig.16 and Fig.17The first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 shown in FIG. 1 are substantially the same, except that they overlap with the second power assist transverse line VSAHL instead of the first bypass assist line TASL1 and overlap with the second power assist longitudinal line VSAVL instead of the second bypass assist line TASL2. Therefore, some redundant descriptions of the same or similar elements may be omitted below.

[0373] That is, the first connection auxiliary electrode CASE1 positioned in the third light emitting pixel driver EPD3 is connected to the second power auxiliary longitudinal line VSAVL, and the third connection auxiliary electrode CASE3 positioned in the fourth light emitting pixel driver EPD4 is connected to the second power auxiliary transverse line VSAHL.

[0374] The fifth connection auxiliary electrode CASE5, the seventh connection auxiliary electrode CASE7, the ninth connection auxiliary electrode CASE9 and the eleventh connection auxiliary electrode CASE11 in the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4 are the same as those in the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and therefore some redundant descriptions of the same or similar elements can be omitted.

[0375] Reference Fig.19 and Fig. 20 Among the mesh auxiliary lines MAL, a fourth mesh auxiliary line MAL4 electrically connected to the second power auxiliary transverse line VSAHL may be positioned adjacent to a boundary between the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4. In this case, the circuit layer 120 may further include an eighth connection auxiliary line CNAL8 connecting the fourth connection auxiliary electrode CASE4 to the sixth connection auxiliary electrode CASE6.

[0376] The fourth connection auxiliary electrode CASE4 may be electrically connected to the second power auxiliary lateral line VSAHL through the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3 .

[0377] The sixth connection auxiliary electrode CASE6 may be electrically connected to the fourth mesh auxiliary line MAL4 through the third connection auxiliary contact hole CACT3 and the fifth connection auxiliary electrode CASE5 .

[0378] Accordingly, when the eighth connection auxiliary line CNAL8 is provided to connect the fourth connection auxiliary electrode CASE4 to the sixth connection auxiliary electrode CASE6, the fourth grid auxiliary line MAL4 can be electrically connected to the second power auxiliary lateral line VSAHL through the fifth connection auxiliary electrode CASE5, the third connection auxiliary contact hole CACT3, the sixth connection auxiliary electrode CASE6, the eighth connection auxiliary line CNAL8, the fourth connection auxiliary electrode CASE4, the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3.

[0379] As described above, according to some embodiments, the mesh auxiliary line MAL positioned adjacent to a boundary between two light emitting pixel drivers EPD1 and EPD2 or EPD3 and EPD4 adjacent in the first direction DR1 may be connected to one fifth connection auxiliary electrode CASE5 .

[0380] In addition, the sixth connection auxiliary electrode CASE6 electrically connected to the fifth connection auxiliary electrode CASE5 can be selectively connected to one of the third connection auxiliary line CNAL3, the fifth connection auxiliary line CNAL5, the seventh connection auxiliary line CNAL7 and the eighth connection auxiliary line CNAL8, so that each of the grid auxiliary lines MAL can be electrically connected to one of the first anode initialization voltage line VAIL1, the second anode initialization voltage line VAIL2, the gate initialization voltage line VGIL and the second power auxiliary lateral line VSAHL.

[0381] That is, electrical connection between the mesh auxiliary line MAL and each of the first anode initialization voltage line VAIL1 , the second anode initialization voltage line VAIL2 , the gate initialization voltage line VGIL and the second power auxiliary lateral line VSAHL can be more simply achieved through only one third connection auxiliary contact hole CACT3 .

[0382] Accordingly, the width of the light-emitting pixel driver EPD can be further reduced, which can be beneficial to improving the resolution.

[0383] At the same time, according to some embodiments, the first connection auxiliary electrode CASE1 connected to the second auxiliary line ASL2 is positioned in one of two light-emitting pixel drivers EPD adjacent in the first direction DR1, and the third connection auxiliary electrode CASE3 connected to the first auxiliary line ASL1 is positioned in the other of the two light-emitting pixel drivers EPD adjacent in the first direction DR1. Accordingly, since the two light-emitting pixel drivers EPD adjacent in the first direction DR1 are asymmetric to each other in the first direction DR1, different image qualities may be displayed in the field of view in the first direction DR1.

[0384] Fig.21 is a diagram showing some embodiments of the present invention. Fig.11 Floor plan of Section E. Fig. 22 is a diagram showing some embodiments of the present invention. Fig.11 Floor plan of Section F. Fig.23 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section G. Fig.24 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section H. Fig.25 is a diagram showing some embodiments of the present invention. Fig.11 Plan view of section E'.

[0385] Reference Fig.21 , Fig. 22 and Fig.23 According to some embodiments, the circuit layer 120 of the display device 100 is related to Fig.13 , Fig.16 and Fig.17 , except that the third connection auxiliary electrode CASE3 is positioned adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and the circuit layer 120 further includes a thirteenth connection auxiliary electrode CASE13 and a fourteenth connection auxiliary electrode CASE14 positioned in the second light-emitting pixel driver EPD2. Therefore, some redundant descriptions of the same or similar elements may be omitted below.

[0386] Reference Fig.24 According to some embodiments, the circuit layer 120 of the display device 100 is related to Fig.19 The circuit layer 120 of the illustrated embodiment is substantially the same, except that the third connection auxiliary electrode CASE3 is positioned adjacent to the boundary between the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4, and the circuit layer 120 further includes a thirteenth connection auxiliary electrode CASE13 and a fourteenth connection auxiliary electrode CASE14 positioned in the fourth light-emitting pixel driver EPD4. Therefore, some redundant descriptions of the same or similar elements may be omitted below.

[0387] According to some embodiments, the third connection auxiliary electrode CASE3 connected to one first auxiliary line ASL1 overlapping the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may be positioned adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. That is, the third connection auxiliary electrode CASE3 may overlap the mesh auxiliary line MAL.

[0388] In one example, the third connection auxiliary electrode CASE3 and the fourth connection auxiliary electrode CASE4 overlapped therewith may be positioned between the sixth connection auxiliary electrode CASE6 and the twelfth connection auxiliary electrode CASE12 in the second direction DR2.

[0389] The thirteenth connection auxiliary electrode CASE13 may be positioned in the second light emitting pixel driver EPD2, and may be connected to another second auxiliary line ASL2 (ie, Fig.21 The second bypass auxiliary line TASL2 in the circuit).

[0390] The fourteenth connection auxiliary electrode CASE14 may overlap the thirteenth connection auxiliary electrode CASE13 and may be electrically connected to the thirteenth connection auxiliary electrode CASE13 through the seventh connection auxiliary contact hole CACT7.

[0391] exist Fig.25 In the figure, the other two light-emitting pixel drivers EPD located in the second bypass side area SDA2 and adjacent to each other in the first direction DR1 are shown as a fifth light-emitting pixel driver EPD5 and a sixth light-emitting pixel driver EPD6. Fig.25 The fifth light emitting pixel driver EPD5 and the sixth light emitting pixel driver EPD6 may also be referred to as the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 adjacent to each other in the first direction DR1.

[0392] Reference Fig.25 ,and Fig.21 , Fig. 22 and Fig.23 The first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 shown in FIG. Fig.24 Similar to the third and fourth light-emitting pixel drivers EPD3 and EPD4 shown in FIG, the fifth and sixth light-emitting pixel drivers EPD5 and EPD6 according to some embodiments include first to fourteenth connection auxiliary electrodes CASE1 to CASE14. Therefore, some redundant descriptions of the same or similar elements may be omitted.

[0393] like Fig.25As shown in, the fifth light-emitting pixel driver EPD5 may include an intersection area between a first bypass auxiliary line TASL1 overlapping with the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6 and a second power auxiliary longitudinal line VSAVL overlapping with the fifth light-emitting pixel driver EPD5. In addition, the sixth light-emitting pixel driver EPD6 may include an intersection area between a first bypass auxiliary line TASL1 overlapping with the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6 and a second bypass auxiliary line TASL2 overlapping with the sixth light-emitting pixel driver EPD6.

[0394] In this case, the circuit layer 120 may further include a first connection auxiliary symmetry line CNAL1 ′ connecting the fourteenth connection auxiliary electrode CASE14 to the fourth connection auxiliary electrode CASE4 .

[0395] The fourteenth connection auxiliary electrode CASE14 may be electrically connected to the second bypass auxiliary line TASL2 through the seventh connection auxiliary contact hole CACT7 and the thirteenth connection auxiliary electrode CASE13 .

[0396] The fourth connection auxiliary electrode CASE4 may be electrically connected to the first bypass auxiliary line TASL1 through the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3 .

[0397] Accordingly, when the first connection auxiliary symmetry line CNAL1' is provided to connect the fourteenth connection auxiliary electrode CASE14 to the fourth connection auxiliary electrode CASE4, the second bypass auxiliary line TASL2 of the sixth light-emitting pixel driver EPD6 can be electrically connected to the first bypass auxiliary line TASL1 through the thirteenth connection auxiliary electrode CASE13, the seventh connection auxiliary contact hole CACT7, the fourteenth connection auxiliary electrode CASE14, the first connection auxiliary symmetry line CNAL1', the fourth connection auxiliary electrode CASE4, the second connection auxiliary contact hole CACT2 and the third connection auxiliary electrode CASE3.

[0398] As described above, according to some embodiments, the first connection auxiliary electrode CASE1 and the thirteenth connection auxiliary electrode CASE13 may be symmetrical to each other with respect to the boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0399] Accordingly, since two adjacent light-emitting pixel drivers EPD in the first direction DR1 may be symmetrical to each other in the first direction DR1, changes in optical characteristics caused by the two adjacent light-emitting pixel drivers EPD in the first direction DR1 may be similarly derived. As a result, differences in image quality according to the field of view in the first direction DR1 may be reduced, resulting in improved image quality.

[0400] However, the effects of the present disclosure are not limited to the effects described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: a substrate, the substrate comprising a display area and a non-display area around the display area, wherein an emission area is arranged in the display area; a circuit layer, the circuit layer being on the substrate; as well as an element layer on the circuit layer and including light emitting elements respectively in the emission regions, Wherein, the circuit layer includes: Light-emitting pixel drivers, the light-emitting pixel drivers are electrically connected to the light-emitting elements, respectively, and are arranged side by side in a first direction and a second direction; a data line extending in the second direction and configured to transmit a data signal to the light-emitting pixel driver; a first auxiliary line, the first auxiliary line extending in the first direction; second auxiliary lines, the second auxiliary lines extending in the second direction and respectively paired with the data lines; a grid auxiliary line extending in the second direction and adjacent to a boundary between a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the first direction among the light-emitting pixel drivers; a first connection auxiliary electrode, the first connection auxiliary electrode being in the first light-emitting pixel driver and connected to a second auxiliary line overlapping the first light-emitting pixel driver; a second connection auxiliary electrode, the second connection auxiliary electrode overlapping the first connection auxiliary electrode and electrically connected to the first connection auxiliary electrode through a first connection auxiliary contact hole; a third connection auxiliary electrode connected to one first auxiliary line overlapping the first light-emitting pixel driver and the second light-emitting pixel driver; and a fourth connection auxiliary electrode overlapping the third connection auxiliary electrode and electrically connected to the third connection auxiliary electrode through a second connection auxiliary contact hole.

2. The display device according to claim 1, wherein: The circuit layer also includes: a fifth connection auxiliary electrode adjacent to a crossing region between the grid auxiliary line and the one first auxiliary line and connected to the grid auxiliary line; and a sixth connection auxiliary electrode, which overlaps the fifth connection auxiliary electrode, is electrically connected to the fifth connection auxiliary electrode through a third connection auxiliary contact hole, and is spaced apart from the second connection auxiliary electrode and the fourth connection auxiliary electrode.

3. The display device according to claim 2, wherein: The circuit layer also includes: a first anode initialization voltage line extending in the first direction, adjacent to one side of the one first auxiliary line in the second direction and configured to transmit a first anode initialization voltage; a second anode initialization voltage line extending in the first direction, adjacent to one side of the first anode initialization voltage line in the second direction and configured to transmit a second anode initialization voltage; a seventh connection auxiliary electrode, the seventh connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the first light-emitting pixel driver in the second direction and being spaced apart from the first anode initialization voltage line and the second anode initialization voltage line; an eighth connection auxiliary electrode, the eighth connection auxiliary electrode overlapping the seventh connection auxiliary electrode and being electrically connected to the seventh connection auxiliary electrode through a fourth connection auxiliary contact hole; a ninth connection auxiliary electrode, the ninth connection auxiliary electrode being between the first anode initialization voltage line and the second anode initialization voltage line in the second direction in the second light emitting pixel driver and being spaced apart from the first anode initialization voltage line and the second anode initialization voltage line; and a tenth connection auxiliary electrode, the tenth connection auxiliary electrode overlapping the ninth connection auxiliary electrode and being electrically connected to the ninth connection auxiliary electrode through a fifth connection auxiliary contact hole, The eighth connection auxiliary electrode is adjacent to one side of the grid auxiliary line in the first direction, and The tenth connection auxiliary electrode is adjacent to the other side of the grid auxiliary line in the first direction.

4. The display device according to claim 3, wherein: The circuit layer also includes: a gate initialization voltage line extending in the first direction, adjacent to the other side of the one first auxiliary line in the second direction and configured to transmit a gate initialization voltage; an eleventh connecting auxiliary electrode, the eleventh connecting auxiliary electrode being between the gate initializing voltage line and the one first auxiliary line; and a twelfth connection auxiliary electrode, the twelfth connection auxiliary electrode overlapping the eleventh connection auxiliary electrode and being electrically connected to the eleventh connection auxiliary electrode through a sixth connection auxiliary contact hole, Wherein, the sixth connection auxiliary electrode and the twelfth connection auxiliary electrode overlap with the grid auxiliary line and are spaced apart from each other.

5. The display device according to claim 4, wherein: The bypass area on one side of the display area includes a bypass middle area at the center, a first bypass side area parallel to the bypass middle area in the first direction and in contact with the non-display area, and a second bypass side area between the bypass middle area and the first bypass side area, The data lines include a first data line in the first bypass side region and a second data line in the second bypass side region, The first auxiliary line includes a first bypass auxiliary line electrically connected to the first data line, and The second auxiliary line includes a second bypass auxiliary line paired with the second data line and electrically connected to the first bypass auxiliary line.

6. The display device according to claim 5, wherein: The first light-emitting pixel driver and the second light-emitting pixel driver are in the second bypass side region, The first light-emitting pixel driver is electrically connected to the second data line and overlaps a crossing area between the first bypass auxiliary line and the second bypass auxiliary line, The circuit layer further includes a first connection auxiliary line connecting the second connection auxiliary electrode to the fourth connection auxiliary electrode, The second bypass auxiliary line is electrically connected to the first bypass auxiliary line through the first connection auxiliary electrode, the first connection auxiliary contact hole, the second connection auxiliary electrode, the first connection auxiliary line, the fourth connection auxiliary electrode, the second connection auxiliary contact hole and the third connection auxiliary electrode.

7. The display device according to claim 6, wherein: The circuit layer also includes: a second connection auxiliary line connecting the first anode initialization voltage line to the seventh connection auxiliary electrode; and a third connection auxiliary line, the third connection auxiliary line connecting the sixth connection auxiliary electrode to the eighth connection auxiliary electrode, Among them, the grid auxiliary line is electrically connected to the first anode initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the third connection auxiliary line, the eighth connection auxiliary electrode, the fourth connection auxiliary contact hole, the seventh connection auxiliary electrode and the second connection auxiliary line.

8. The display device according to claim 6, wherein: The circuit layer also includes: a fourth connection auxiliary line connecting the second anode initialization voltage line to the ninth connection auxiliary electrode; and a fifth connection auxiliary line, the fifth connection auxiliary line connecting the sixth connection auxiliary electrode to the tenth connection auxiliary electrode, Among them, the grid auxiliary line is electrically connected to the second anode initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the fifth connection auxiliary line, the tenth connection auxiliary electrode, the fifth connection auxiliary contact hole, the ninth connection auxiliary electrode and the fourth connection auxiliary line.

9. The display device according to claim 6, wherein: The circuit layer also includes: a sixth connection auxiliary line, the sixth connection auxiliary line connecting the gate initialization voltage line to the eleventh connection auxiliary electrode; and a seventh connection auxiliary line, the seventh connection auxiliary line connecting the sixth connection auxiliary electrode to the twelfth connection auxiliary electrode, Among them, the grid auxiliary line is electrically connected to the gate initialization voltage line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the seventh connection auxiliary line, the twelfth connection auxiliary electrode, the sixth connection auxiliary contact hole, the eleventh connection auxiliary electrode and the sixth connection auxiliary line.

10. The display device according to claim 5, wherein: The data lines further include a third data line in the bypass middle region, The first auxiliary line further includes a second power auxiliary transverse line between the first power and the second power for driving the light emitting element, and the second power is applied to the second power auxiliary transverse line. The second auxiliary line further includes a second power-assisted longitudinal line, and the second power is applied to the second power-assisted longitudinal line. The first light emitting pixel driver and the second light emitting pixel driver are in the bypass middle area and overlap with one of the second power assisting transverse lines in the plurality of second power assisting transverse lines, The first light-emitting pixel driver is electrically connected to the third data line, The circuit layer further includes an eighth connection auxiliary line connecting the fourth connection auxiliary electrode to the sixth connection auxiliary electrode, The grid auxiliary line is electrically connected to the one second power auxiliary lateral line through the fifth connection auxiliary electrode, the third connection auxiliary contact hole, the sixth connection auxiliary electrode, the eighth connection auxiliary line, the fourth connection auxiliary electrode, the second connection auxiliary contact hole and the third connection auxiliary electrode.

11. The display device according to claim 10, further comprising: a display driving circuit configured to transmit a data signal of the light-emitting pixel driver to the data line; The circuit layer further includes a data supply line in the non-display area and electrically connected between the data line and the display driving circuit. Among the data supply lines, a first data supply line for transmitting the data signal of the first data line is electrically connected to the first data line through the first bypass auxiliary line and the second bypass auxiliary line, Among the data supply lines, a second data supply line configured to transmit the data signal of the second data line is directly electrically connected to the second data line, and Among the data supply lines, a third data supply line configured to transmit the data signal of the third data line is directly electrically connected to the third data line.

12. The display device according to claim 4, wherein: The third connection auxiliary electrode is in the second light-emitting pixel driver.

13. The display device according to claim 4, wherein: The third connection auxiliary electrode is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver that are adjacent to each other in the first direction.

14. The display device according to claim 13, wherein: The circuit layer also includes: a thirteenth connection auxiliary electrode, the thirteenth connection auxiliary electrode being in the second light emitting pixel driver and connected to another second auxiliary line overlapping the second light emitting pixel driver; and a fourteenth connection auxiliary electrode, the fourteenth connection auxiliary electrode overlaps the thirteenth connection auxiliary electrode and is electrically connected to the thirteenth connection auxiliary electrode through a seventh connection auxiliary contact hole.

15. A display device, comprising: a substrate, the substrate comprising a display area and a non-display area around the display area, wherein an emission area is arranged in the display area; a circuit layer, the circuit layer being on the substrate; as well as an element layer on the circuit layer and including light emitting elements respectively in the emission regions, Wherein, the circuit layer includes: Light-emitting pixel drivers, the light-emitting pixel drivers are electrically connected to the light-emitting elements, respectively, and are arranged side by side in a first direction and a second direction; a data line extending in the second direction and configured to transmit a data signal to the light-emitting pixel driver; a first auxiliary line extending in the first direction; and a second auxiliary line extending in the second direction and paired with the data line, respectively; grid auxiliary lines extending in the second direction and between the second auxiliary lines; a first anode initialization voltage line extending in the first direction and configured to transmit a first anode initialization voltage; a second anode initialization voltage line extending in the first direction and configured to transmit a second anode initialization voltage; a gate initialization voltage line extending in the first direction and configured to transmit a gate initialization voltage; and a first power line configured to transmit the first power between a first power for driving the light emitting element and a second power, Wherein, the first auxiliary line includes: a first bypass auxiliary line electrically connected to a first data line adjacent to the non-display area in the first direction among the data lines; and a second power-assisting transverse line, the second power-assisting transverse line being configured to transmit the second power, Wherein, the second auxiliary line includes: a second bypass auxiliary line paired with a second data line among the data lines that is spaced farther from the non-display area than the first data line in the first direction and electrically connected to the first bypass auxiliary line; and a second power-assisting longitudinal line, said second power-assisting longitudinal line being configured to transmit said second power, Wherein, the light-emitting pixel driver comprises: a first light-emitting pixel driver, the first light-emitting pixel driver comprising a crossing area between the first bypass auxiliary line and the second bypass auxiliary line; and a second light-emitting pixel driver, the second light-emitting pixel driver being adjacent to the first light-emitting pixel driver in the first direction; wherein the second bypass auxiliary line is electrically connected to the first bypass auxiliary line through the first connection auxiliary electrode, the second connection auxiliary electrode, the third connection auxiliary electrode, the fourth connection auxiliary electrode and the first connection auxiliary line, The first connection auxiliary electrode is connected to the second bypass auxiliary line; the second connection auxiliary electrode overlaps with the first connection auxiliary electrode and is electrically connected to the first connection auxiliary electrode through a first connection auxiliary contact hole; The third connection auxiliary electrode is connected to the first bypass auxiliary line; the fourth connection assisting electrode overlaps the third connection assisting electrode and is electrically connected to the third connection assisting electrode through a second connection assisting contact hole; and The first connection auxiliary line connects the second connection auxiliary electrode to the fourth connection auxiliary electrode.

16. The display device according to claim 15, wherein: The grid auxiliary lines include: a first grid auxiliary line, the first grid auxiliary line being electrically connected to the first anode initialization voltage line; a second grid auxiliary line, the second grid auxiliary line being electrically connected to the second anode initialization voltage line; a third grid auxiliary line, the third grid auxiliary line being electrically connected to the gate initialization voltage line; and A fourth grid auxiliary line, the fourth grid auxiliary line is electrically connected to at least one of the plurality of second power auxiliary transverse lines.

17. The display device according to claim 16, wherein: The first grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and The first grid auxiliary line is electrically connected to the first anode initialization voltage line through a fifth connection auxiliary electrode, a sixth connection auxiliary electrode, a seventh connection auxiliary electrode, an eighth connection auxiliary electrode, a second connection auxiliary line and a third connection auxiliary line, The fifth connection auxiliary electrode is connected to the first grid auxiliary line; the sixth connection assisting electrode overlaps the fifth connection assisting electrode and is electrically connected to the fifth connection assisting electrode through a third connection assisting contact hole; The seventh connection auxiliary electrode is between the first anode initialization voltage line and the second anode initialization voltage line; the eighth connection auxiliary electrode overlaps the seventh connection auxiliary electrode and is electrically connected to the seventh connection auxiliary electrode through a fourth connection auxiliary contact hole; The second connection auxiliary line connects the first anode initialization voltage line to the seventh connection auxiliary electrode; as well as The third connection auxiliary line connects the sixth connection auxiliary electrode to the eighth connection auxiliary electrode.

18. The display device according to claim 16, wherein: The second grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and The second grid auxiliary line is electrically connected to the second anode initialization voltage line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the ninth connection auxiliary electrode, the tenth connection auxiliary electrode, the fourth connection auxiliary line and the fifth connection auxiliary line, The fifth connection auxiliary electrode is connected to the first grid auxiliary line; the sixth connection assisting electrode overlaps the fifth connection assisting electrode and is electrically connected to the fifth connection assisting electrode through a third connection assisting contact hole; The ninth connection auxiliary electrode is between the first anode initialization voltage line and the second anode initialization voltage line; the tenth connection auxiliary electrode overlaps the ninth connection auxiliary electrode and is electrically connected to the ninth connection auxiliary electrode through a fifth connection auxiliary contact hole; The fourth connection auxiliary line connects the second anode initialization voltage line to the ninth connection auxiliary electrode; as well as The fifth connection auxiliary line connects the sixth connection auxiliary electrode to the tenth connection auxiliary electrode.

19. The display device according to claim 16, wherein: The third grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and The third grid auxiliary line is electrically connected to the gate initialization voltage line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the eleventh connection auxiliary electrode, the twelfth connection auxiliary electrode, the sixth connection auxiliary line and the seventh connection auxiliary line, The fifth connection auxiliary electrode is connected to the third grid auxiliary line; the sixth connection assisting electrode overlaps the fifth connection assisting electrode and is electrically connected to the fifth connection assisting electrode through a third connection assisting contact hole; The eleventh connection auxiliary electrode is between the gate initialization voltage line and the sixth connection auxiliary electrode; The twelfth connection auxiliary electrode overlaps with the eleventh connection auxiliary electrode and is electrically connected to the eleventh connection auxiliary electrode through a sixth connection auxiliary contact hole; The sixth connection auxiliary line connects the gate initialization voltage line to the eleventh connection auxiliary electrode; as well as The seventh connection auxiliary line connects the sixth connection auxiliary electrode to the twelfth connection auxiliary electrode.

20. The display device according to claim 16, wherein: The light-emitting pixel driver further includes: a third light-emitting pixel driver including a crossover region between one of the second power-assisting transverse lines and one of the second power-assisting longitudinal lines; and a fourth light-emitting pixel driver, the fourth light-emitting pixel driver being adjacent to the third light-emitting pixel driver in the first direction and comprising a crossing area between the one second power-assisting transverse line and another second power-assisting longitudinal line of the plurality of second power-assisting longitudinal lines, wherein the third connection auxiliary electrode is connected to the one second power auxiliary transverse line, The fourth grid auxiliary line is adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver, wherein the fourth grid auxiliary line is electrically connected to the one second power auxiliary transverse line through the fifth connection auxiliary electrode, the sixth connection auxiliary electrode, the third connection auxiliary electrode, the fourth connection auxiliary electrode and the eighth connection auxiliary line, The fifth connection auxiliary electrode is connected to the fourth grid auxiliary line; the sixth connection assisting electrode overlaps the fifth connection assisting electrode and is electrically connected to the fifth connection assisting electrode through a third connection assisting contact hole; and The eighth connection auxiliary line connects the fourth connection auxiliary electrode to the sixth connection auxiliary electrode.

Images