Display device and wearable device

Abstract

A display device and a wearable device are provided. The display device includes a substrate including a non-display area and a display area; a sub-pixel in the display area; and a metal line passing through the non-display area and the display area in the first direction. Each of the metal lines extends in a first direction to not overlap the emission regions of the sub-pixel, and includes a metal pattern protruding between the emission regions in a direction crossing the first direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0115475 filed in the Korean Intellectual Property Office on August 31, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Aspects of embodiments of the present disclosure generally relate to a display device and a wearable device. Background Art

[0003] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, various display devices such as liquid crystal display devices, organic light emitting display devices, and inorganic light emitting display devices are increasingly used.

[0004] A display device displays an image using pixels. In order to realize augmented reality (AR), virtual reality (VR) and / or mixed reality (MR), a larger number of pixels may need to be provided on a small display surface in a display device.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0006] As the distance between pixels becomes narrower, leakage current may result through a common layer of adjacent pixels.

[0007] One or more embodiments of the present disclosure relate to a display device and a wearable device that can prevent or reduce leakage current through a common layer between adjacent pixels.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a non-display area and a display area; a sub-pixel in the display area; and a metal line passing through the non-display area and the display area in a first direction. Each of the metal lines extends in the first direction so as not to overlap with an emission area of ​​the sub-pixel, and includes a metal pattern protruding in a direction intersecting the first direction between the emission areas.

[0009] In an embodiment, each of the metal patterns may have a ring shape.

[0010] In an embodiment, each of the metal lines may be located on a pixel defining layer, and the pixel defining layer may define an emission region of a sub-pixel in a display region.

[0011] In an embodiment, the display device may further include: a first metal pad in the non-display area; and a second metal pad in the non-display area, the second metal pad being located in a first direction from the first metal pad. The metal wire may connect the first metal pad and the second metal pad to each other.

[0012] In an embodiment, the shapes of the metal lines may be identical to each other.

[0013] In an embodiment, the sub-pixel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel positioned along a first direction. The metal line may include a first metal line, the first metal line including: a first metal pattern protruding in a second direction intersecting the first direction between a first emission region of the first sub-pixel and a second emission region of the second sub-pixel; and a second metal pattern protruding in the second direction between the second emission region and a third emission region of the third sub-pixel.

[0014] In an embodiment, a length of each of the first and second metal patterns in the second direction may be longer than a length of each of the first, second, and third emission regions in the second direction.

[0015] In an embodiment, the first metal line may further include: a first line portion, which is located in the opposite direction of the second direction from the first emission area, and the first line portion is connected to the first metal pattern; a second line portion, which is located in the opposite direction of the second direction from the second emission area, and the second line portion connects the first metal pattern and the second metal pattern to each other; and a third line portion, which is located in the opposite direction of the second direction from the third emission area, and the third line portion is connected to the second metal pattern.

[0016] In an embodiment, the sub-pixel may further include a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel positioned along the first direction. The metal line may further include a second metal line, the second metal line passing between the first emission region and the fourth emission region of the fourth sub-pixel, between the second emission region and the fifth emission region of the fifth sub-pixel, and between the third emission region and the sixth emission region of the sixth sub-pixel, and the first metal line and the second metal line may be spaced apart from each other.

[0017] In an embodiment, the metal line may further include a dummy metal line, and the dummy metal line is located in the second direction from the outermost sub-pixel in the second direction among the sub-pixels.

[0018] In an embodiment, the metal lines may include: a first group of metal lines including metal patterns protruding in a second direction intersecting the first direction; and a second group of metal lines including metal patterns protruding in a direction opposite to the second direction. The first group of metal lines and the second group of metal lines may be alternately positioned along the second direction.

[0019] In an embodiment, the first group of metal lines and the second group of metal lines may have shapes symmetrical to each other with respect to the first direction.

[0020] In an embodiment, the subpixel may include a first subpixel and a second subpixel positioned along a first direction. The metal line may include a first metal line, the first metal line sequentially including along the first direction: a first metal pattern protruding in a second direction intersecting the first direction; a second metal pattern protruding in a direction opposite to the second direction; a third metal pattern protruding in the second direction; a fourth metal pattern protruding in a direction opposite to the second direction; and a fifth metal pattern protruding in the second direction. The first emission region of the first subpixel may be located in the second direction from the second metal pattern, and the second emission region of the second subpixel may be located in the second direction from the fourth metal pattern.

[0021] In an embodiment, the first metal line may further include: a first line portion connecting the first metal pattern and the second metal pattern to each other; a second line portion connecting the second metal pattern and the third metal pattern to each other; a third line portion connecting the third metal pattern and the fourth metal pattern to each other; and a fourth line portion connecting the fourth metal pattern and the fifth metal pattern to each other. The first line portion and the third line portion may be parallel to each other; the second line portion and the fourth line portion may be parallel to each other; and the first line portion and the second line portion may not be parallel to each other.

[0022] In an embodiment, the sub-pixel may further include a third sub-pixel. The metal line may further include a second metal line, the second metal line sequentially including along the first direction: a sixth metal pattern protruding in the opposite direction of the second direction; a seventh metal pattern protruding in the second direction; an eighth metal pattern protruding in the opposite direction of the second direction; a ninth metal pattern protruding in the second direction; and a tenth metal pattern protruding in the opposite direction of the second direction. The first emission region may be located in the opposite direction of the second direction from the seventh metal pattern, the second emission region may be located in the opposite direction of the second direction from the ninth metal pattern, and the third emission region of the third sub-pixel may be located in the second direction from the eighth metal pattern.

[0023] In an embodiment, the third metal pattern and the eighth metal pattern may face each other between the first emission region and the second emission region.

[0024] In an embodiment, the metal line may further include a third metal line, the third metal line sequentially including along the first direction: an eleventh metal pattern protruding in a direction opposite to the second direction; a twelfth metal pattern protruding in the second direction; and a thirteenth metal pattern protruding in a direction opposite to the second direction. The third emission region may be located in a direction opposite to the second direction from the twelfth metal pattern, the eleventh metal pattern and the seventh metal pattern may face each other in the second direction, and the thirteenth metal pattern and the ninth metal pattern may face each other in the second direction.

[0025] In an embodiment, the metal line may include: a first metal line, sequentially including along the first direction: a first metal pattern, protruding in a second direction intersecting the first direction; a second metal pattern, protruding in the second direction; and a third metal pattern, protruding in the second direction; and a second metal line, sequentially including along the first direction: a fourth metal pattern, protruding in the opposite direction of the second direction; a fifth metal pattern, protruding in the opposite direction of the second direction; and a sixth metal pattern, protruding in the opposite direction of the second direction. The first metal line may also include: a first line portion, connecting the first metal pattern and the second metal pattern to each other; and a second line portion, connecting the second metal pattern and the third metal pattern to each other. The second metal line may also include: a third line portion, connecting the fourth metal pattern and the fifth metal pattern to each other; and a fourth line portion, connecting the fifth metal pattern and the sixth metal pattern to each other. The positions of the first line portion and the second line portion may be the same as each other relative to the second direction, and the positions of the third line portion and the fourth line portion may be different from each other relative to the second direction.

[0026] In an embodiment, the subpixel may include: a first subpixel including a first emission region; a second subpixel located in the first direction from the first subpixel and including a second emission region; and a third subpixel located in the second direction from the first subpixel and including a third emission region. The length of the second emission region in the second direction may be longer than the length of each of the first emission region and the third emission region in the second direction, the first emission region may be located between the first line portion and the third line portion, the second emission region may be located between the second line portion and the fourth line portion, and the third emission region may be located in the second direction from the third line portion.

[0027] In an embodiment, the second metal pattern and the fifth metal pattern may face each other between the first emission region and the second emission region.

[0028] According to one or more embodiments of the present disclosure, a wearable device includes a first display panel and a second display panel. Each of the first display panel and the second display panel includes: a substrate including a non-display area and a display area; a sub-pixel in the display area; and a metal line passing through the non-display area and the display area in a first direction. Each of the metal lines extends in the first direction so as not to overlap with the emission area of ​​the sub-pixel, and includes a metal pattern protruding between the emission areas in a direction intersecting the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0030] Figure 1 is a block diagram of a display device according to one or more embodiments.

[0031] Figure 2 is a diagram showing a method according to one or more embodiments Figure 1 Block diagram of one of the sub-pixels shown in .

[0032] Figure 3 is a diagram showing a method according to one or more embodiments Figure 1 A plan view of the display panel shown in FIG.

[0033] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of a display panel is shown in FIG.

[0034] Figure 5 is a diagram showing a method according to one or more embodiments Figure 4 A plan view of the pixel shown in FIG.

[0035] Figure 6 It is along Figure 5 A cross-sectional view taken along line II' shown in FIG.

[0036] Figure 7 is a diagram showing a method of performing a Figure 6 A cross-sectional view of a light emitting structure included in one of the first to third light emitting elements shown in FIG.

[0037] Figure 8 is a diagram showing a method of performing a Figure 6 A cross-sectional view of a light emitting structure included in one of the first to third light emitting elements shown in FIG.

[0038] Fig. 9 According to one or more embodiments, Figure 5 A cross-sectional view taken along line II' shown in FIG.

[0039] Fig.10 is a diagram showing a method for applying a Figure 5 View of metal lines of different configurations of the pixel shown in .

[0040] Fig.11 is a view illustrating a metal line applied to another pixel according to one or more embodiments.

[0041] Fig.12 is a view illustrating a metal line applied to another pixel according to one or more embodiments.

[0042] Fig.13 is a view showing a connection portion of a metal pad and a metal wire.

[0043] Fig.14 is a diagram illustrating a display system according to one or more embodiments.

[0044] Fig.15 It is shown Fig.14 A perspective view of an application example of the display system shown in FIG.

[0045] Fig.16 is shown as being worn by the user Fig.15 A view of a head mounted display device shown in FIG. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, throughout the accompanying drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0047] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0048] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "under ... ", "under ... ", "above ... ", "on ", etc. may be used here to describe the relationship between an element or feature and other elements or features as shown in the accompanying drawings. It will be understood that, in addition to the orientation shown in the accompanying drawings, spatial relative terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the element described as "under" or "under" or "below" other elements or features will be subsequently oriented to "above" the other elements or features. Therefore, the example terms "under ... " and "under ... " can cover both the upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly.

[0049] In the drawings, the DR1 direction, the DR2 direction, and the DR3 direction are not limited to the x direction, the y direction, and the z direction of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 direction, the DR2 direction, and the DR3 direction may be perpendicular to each other or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0050] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be named as the second element, component, region, layer or part.

[0051] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, the element or layer may be directly on, directly connected to, or directly bound to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements therebetween. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0052] The terms used here are for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "one (kind / person)" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include" and its variations, "contain" and its variations, "have" and its variations when used in this specification, illustrate the existence of the features, integral bodies, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. For example, the statement "A and / or B" means A, B or A and B. The statement such as "at least one (kind / person) in ... " modifies the entire column of elements when it is after a column of elements, and does not modify the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0053] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0055] Figure 1 is a block diagram of a display device according to one or more embodiments.

[0056] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0057] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm (where m is a positive integer greater than or equal to 1). The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn (where n is a positive integer greater than or equal to 1).

[0058] Each of the sub-pixels SP may include at least one light emitting element to generate light. Therefore, each of the sub-pixels SP may generate light of a desired color (e.g., a specific or predetermined color) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG. , three sub-pixels can constitute one pixel PXL.

[0059] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to the gate control signal GCS. In one or more embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing of applying a data signal, and the like.

[0060] In one or more embodiments, first to m-th emission control lines EL1 to ELm connected to the subpixels SP in the row direction may also be provided. The gate driver 120 may include an emission control driver for controlling the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0061] The gate driver 120 may be disposed on one side of the display panel 110. However, the present disclosure is not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically divided, and these drivers may be disposed on one side of the display panel 110 and on the other side of the display panel 110 that is opposite to the one side. Thus, in some embodiments, the gate driver 120 may be disposed on the periphery of the display panel 110 in various suitable forms.

[0062] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 may receive the image data DATA and the data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In one or more embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0063] The data driver 130 may apply a data signal having a grayscale voltage (e.g., grayscale or grayscale voltage) corresponding to the image data DATA to the first to n-th data lines DL1 to DLn by using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. Therefore, an image may be displayed on the display panel 110.

[0064] In one or more embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0065] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may generate a plurality of voltages, and may provide the generated voltages to various components of the display device 100. For example, the voltage generator 140 may receive an input voltage from outside the display device 100, adjust the received voltage, and adjust the adjusted voltage, thereby generating a plurality of voltages.

[0066] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than the voltage level of the first power voltage VDD. However, the present disclosure is not limited thereto, and in some embodiments, the first power voltage VDD and / or the second power voltage VSS may be provided by an external device of the display device 100.

[0067] In addition, the voltage generator 140 may generate various suitable voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, in a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a predetermined reference voltage) may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate the reference voltage.

[0068] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling its display from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the received control signal CTRL.

[0069] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, thereby outputting the image data DATA. In one or more embodiments, the controller 150 may align the input image data IMG in units of rows to be suitable for the sub-pixels SP, thereby outputting the image data DATA.

[0070] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be functionally divided components in the driver integrated circuit DIC (e.g., in one driver integrated circuit DIC). However, the present disclosure is not limited thereto, and in some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component distinguished from the driver integrated circuit DIC.

[0071] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature of its periphery and generate temperature data TEP indicating the sensed temperature. In one or more embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0072] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In one or more embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control various components (such as the data driver 130 and / or the voltage generator 140) to adjust the data signal and / or the first power voltage VDD and the second power voltage VSS according to the temperature data TEP.

[0073] Figure 2 is a diagram showing a method according to one or more embodiments Figure 1 A block diagram of one of the sub-pixels shown in FIG. Figure 2 For convenience, the arrangement in Figure 1 The sub-pixel SPij at (e.g., in the middle or above) the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP shown in . Figure 1 Each of the sub-pixels SP shown in FIG. Figure 2 The structure of the sub-pixel SPij shown in FIG. 1 is the same or substantially the same as the structure of the sub-pixel SPij shown in FIG. 1 , and therefore, a redundant description may not be repeated.

[0074] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0075] The light emitting element LD may be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN may be used to transmit Figure 1 The second power voltage node VSSN may be used to transmit Figure 1 A node of the second power voltage VSS shown in .

[0076] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN.

[0077] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi, the m-th gate line GLm, and the m-th gate line GL1 are shown in FIG. Figure 1 The i-th emission control line ELi among the first to m-th emission control lines EL1 to ELm shown in FIG. Figure 1The j-th data line DLj among the first to n-th data lines DL1 to DLn shown in FIG. The sub-pixel circuit SPC may control the light emitting element LD according to the signal received through the above-mentioned signal line.

[0078] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In one or more embodiments, Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding two or more sub-gate lines.

[0079] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In one or more embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding two or more sub-emission control lines.

[0080] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may control a current flowing from the first power voltage node VDDN through the light emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0081] Figure 3 is a diagram showing a method according to one or more embodiments Figure 1 A plan view of the display panel shown in FIG.

[0082] Reference Figure 3 , can be used with Figure 1 The display panel DP corresponding to the display panel 110 shown in FIG. 1 may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed at the periphery of the display area DA. For example, in some embodiments, the non-display area NDA may be adjacent to the display area DA or surround the periphery of the display area DA.

[0083] The display panel DP may include a substrate SUB, sub-pixels SP, a first metal pad (also called “bonding pad” or “pad”) JPD1, a second metal pad JPD2, metal lines JHL1 to JHLo (where o is a positive integer greater than or equal to 1), and a pad PD.

[0084] When the display panel DP is used as a display screen for a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be positioned very close to the user's eyes (e.g., a predetermined distance from the user's eyes). As such, a sub-pixel SP having a relatively high degree of integration may be required. In order to increase the degree of integration of the sub-pixel SP, the substrate SUB may be set to a silicon substrate. The sub-pixel SP and / or the display panel DP may be formed on a silicon substrate SUB. A display device 100 (e.g., see FIG. 1 ) including a display panel DP formed on a substrate SUB being a silicon substrate Figure 1 ) can be designated as an OLED-on-silicon (OLEDoS) display device.

[0085] The sub-pixels SP may be disposed in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting or crossing the first direction DR1. However, the present disclosure is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, a plurality of sub-pixels SP may be arranged in an RGBG form (e.g., form, is an officially registered trademark of Samsung Display Co., Ltd.) The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0086] Two or more sub-pixels SP among the sub-pixels SP may constitute one pixel PXL.

[0087] The substrate SUB may include a display area DA and a non-display area NDA. Components for controlling the sub-pixel SP may be disposed in the non-display area NDA on the substrate SUB. For example, a line (such as a Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn) shown in FIG. 1 may be spatially efficiently disposed in the non-display area NDA.

[0088] The first metal pad JPD1 may be disposed in the non-display area NDA. The first metal pad JPD1 may have a rectangular or substantially rectangular shape including a long side extending in the second direction DR2 and a short side extending in the first direction DR1. The length of the long side may be the same as or similar to the length of the display area DA in the second direction DR2. The first metal pad JPD1 may include at least one metal material. For example, the first metal pad JPD1 may include a suitable material having a high resistivity and a high melting point (such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN)). The first metal pad JPD1 may be located in the opposite direction of the first direction DR1 from the display area DA.

[0089] The second metal pad JPD2 may be located in the non-display area NDA and may be located in the first direction DR1 from the first metal pad JPD1. The second metal pad JPD2 may have a rectangular or substantially rectangular shape including a long side extending in the second direction DR2 and a short side extending in the first direction DR1. The length of the long side may be the same as or similar to the length of the display area DA in the second direction DR2. The second metal pad JPD2 may include at least one metal material. For example, the second metal pad JPD2 may include a suitable material having a high resistivity and a high melting point (such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN)). The second metal pad JPD2 may be located in the first direction DR1 from the display area DA.

[0090] The metal lines JHL1 to JHLo may connect the first metal pad JPD1 and the second metal pad JPD2 to each other. Here, o may be an integer greater than 1. Each of the metal lines JHL1 to JHLo may extend in the first direction DR1 and may not overlap with the sub-pixel SP. As used herein, the phrase "not overlapping with the sub-pixel SP" means not overlapping with the emission area of ​​the sub-pixel SP. The metal lines JHL1 to JHLo may be arranged parallel to each other in the second direction DR2. One end of the metal lines JHL1 to JHLo may be connected to the first metal pad JPD1, and the other end (e.g., the opposite end) of the metal lines JHL1 to JHLo may be connected to the second metal pad JPD2. For example, the metal lines JHL1 to JHLo may include a suitable material having a high resistivity and a high melting point (such as molybdenum (Mo), titanium (Ti), or titanium nitride (TiN)).

[0091] The first metal pad JPD1, the second metal pad JPD2, and the metal lines JHL1 to JHLo may be integrally formed of the same material through the same or substantially the same process as one another.

[0092] When a power voltage is applied to the first metal pad JPD1, heat may be generated in the metal lines JHL1 to JHLo due to Joule heating. The power voltage may be a single pulse or may include a plurality of pulses. Due to the generated heat, an organic material adjacent to the metal lines JHL1 to JHLo may sublime.

[0093] The first cutting line SCL1 may extend in the second direction DR2 between the first metal pad JPD1 and the display area DA. The first cutting line SCL1 may pass through the metal lines JHL1 to JHLo. The second cutting line SCL2 may extend in the second direction DR2 between the second metal pad JPD2 and the display area DA. The second cutting line SCL2 may pass through the metal lines JHL1 to JHLo.

[0094] After the Joule heating process, when the display panel DP is cut along the cutting lines SCL1 and SCL2, the first metal pad JPD1 and the second metal pad JPD2 do not exist in the final product. In another embodiment, if the display panel DP is not cut along the cutting lines SCL1 and SCL2, the first metal pad JPD1 and the second metal pad JPD2 may exist in the final product.

[0095] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in the figure may be integrated in the non-display area NDA of the display panel DP. In one or more embodiments, Figure 1 The gate driver 120 shown in FIG. 1 is installed at (e.g., in or above) the display panel DP and may be disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0096] The pad PD may be disposed on the substrate SUB in the non-display area NDA. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0097] The pad PD can make the display panel DP and the display device 100 (for example, see Figure 1 ) other components. In one or more embodiments, the PD pad can be connected from Figure 1The driver integrated circuit DIC shown in FIG. 1 provides voltages and signals for the operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, when the gate driver 120 is installed at (e.g., in or above) the display panel DP, the gate control signal GCS may be sent from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0098] In one or more embodiments, the circuit board may be electrically connected to the pad PD by (e.g., using) a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film including a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0099] In an embodiment, the display area DA may have various suitable shapes. The display area DA may have a closed loop shape including linear edges and / or curved edges. For example, the display area DA may have a polygonal shape, a circular shape, a semicircular shape, or an elliptical shape.

[0100] In one or more embodiments, the display panel DP may have a flat or substantially flat display surface. In other embodiments, the display panel DP may at least partially have a rounded display surface. In one or more embodiments, the display panel DP may be bendable, foldable or rollable. The display panel DP and / or the substrate SUB may include one or more suitable materials having flexibility.

[0101] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of a display panel is shown in FIG. Figure 4 In order to facilitate the description, the display panel DP is schematically shown. Figure 3 Portions of the display panel DP corresponding to two pixels PXL1 and PXL2 among the pixels PXL shown in FIG. Portions of the display panel DP corresponding to other pixels PXL may also be configured in the same or similar manner, and thus, a redundant description thereof may not be repeated.

[0102] Reference Figure 3 and Figure 4, the first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The second pixel PXL2 may include fourth to sixth sub-pixels having the same or substantially the same shape as the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0103] exist Figure 4 , when viewed in a third direction DR3 intersecting or crossing the first direction DR1 and the second direction DR2 (e.g., in a plan view), the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are shown to have a quadrilateral shape and have the same size as each other. However, the present disclosure is not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be variously modified to have various suitable shapes.

[0104] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0105] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided by a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0106] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, etc. The conductive pattern may include copper, but the present disclosure is not limited thereto.

[0107] The circuit element may include a sub-pixel circuit SPC (eg, see FIG. 1 ) of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Figure 2). The sub-pixel circuit SPC may include a plurality of transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In one or more embodiments, when the substrate SUB is set to a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included as a conductive pattern of the pixel circuit layer PCL (for example, included in the pixel circuit layer PCL). In one or more embodiments, when the substrate SUB is set to a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 perpendicular to a plane defined by the first direction DR1 and the second direction DR2. For example, the capacitor may include electrodes spaced apart from each other in the third direction DR3, with an insulating layer interposed therebetween.

[0108] The lines of the pixel circuit layer PCL may include signal lines (eg, gate lines, emission control lines, data lines, etc.) connected to each of the sub-pixels. The lines may also include lines connected to Figure 2 The line may also include a line connected to the first power voltage node VDDN shown in FIG. Figure 2 The line of the second power voltage node VSSN is shown in .

[0109] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0110] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact the circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the present disclosure is not limited thereto.

[0111] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the anode electrodes AE. One opening OP of the pixel defining layer PDL may be understood as an emission region of a corresponding sub-pixel among the first to third sub-pixels SP1 to SP3.

[0112] In one or more embodiments, the pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0113] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer for generating light, an electron transport layer for transporting electrons, a hole transport layer for transporting holes, and the like.

[0114] In one or more embodiments, the light emitting structure EMS fills the opening OP of the pixel defining layer PDL and may be entirely disposed on top of the pixel defining layer PDL. In other words, the light emitting structure EMS may extend through the first sub-pixel SP1 to the third sub-pixel SP3. At least some of the layers in the light emitting structure EMS may be cut or bent at the boundaries between the sub-pixels SP. However, the present disclosure is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the sub-pixels SP may be separated from each other (e.g., spaced apart), and each of these portions may be disposed in a corresponding opening OP of the pixel defining layer PDL.

[0115] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend through the plurality of sub-pixels SP. In this way, the cathode electrode CE may be disposed as a common electrode of the plurality of sub-pixels SP.

[0116] The cathode electrode CE may be a thin metal layer having a thickness to the extent that the light emitted from the light emitting structure EMS can be transmitted through it. The cathode electrode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of a transparent conductive material. In one or more embodiments, the cathode electrode CE may include at least one of various suitable transparent conductive materials (including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide). In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a suitable mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0117] Any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping therewith, and the portion of the cathode electrode CE overlapping therewith constitutes one light emitting element LD (for example, see Figure 2 ). Each of the light emitting elements LD of the sub-pixels SP may include an anode electrode AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light emitting layer of the light emitting structure EMS to form excitons, and light may be generated when the excitons change from an excited state to a ground state. The brightness of the light may be determined according to the amount of current flowing through the light emitting layer. The wavelength band of the generated light may be determined according to the configuration of the light emitting layer.

[0118] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may prevent or substantially prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In one or more embodiments, the encapsulation layer TFE may include a structure of alternately stacking at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin or benzocyclobutene (BCB) resin. However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0119] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x The thin film including aluminum oxide may be located on the top surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the bottom surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0120] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) process. However, the present disclosure is not limited thereto. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0121] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0122] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may filter the light emitted from the light emitting structure EMS, thereby selectively outputting light of a desired wavelength band or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the sub-pixels, respectively. Each of the color filters CF may allow light having a wavelength band corresponding to the corresponding sub-pixel to pass through it. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through it, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through it, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through it. Depending on the light emitted from the light emitting structure EMS in each sub-pixel SP (e.g., the color of the light), at least some of the color filters CF may be omitted.

[0123] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the sub-pixels, respectively. Each of the lenses LS may output light emitted from the light emitting structure EMS along an intended path, thereby improving light emission efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In one or more embodiments, the lens LS may include an organic material. In one or more embodiments, the lens LS may include an acryl-based material. However, the material of the lens LS is not limited thereto.

[0124] In one or more embodiments, compared to the opening OP of the pixel defining layer PDL, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be displaced in a direction parallel or substantially parallel to the plane defined by the first direction DR1 and the second direction DR2. In more detail, in the central area of ​​the display area DA, when viewed in the third direction DR3 (e.g., in a plan view), the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may be completely overlapped with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3 (e.g., in a plan view), the center of the color filter CF and the center of the lens LS may be displaced on the plane from the center of the corresponding opening OP of the pixel defining layer PDL. For example, in an area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light emitting structure EMS may be effectively output in the normal direction of the display surface. In an area of ​​the display area DA adjacent to the non-display area NDA, the light emitted from the light emitting structure EMS may be effectively output in a direction inclined at an angle (e.g., a predetermined angle) relative to the normal direction.

[0125] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the layers below it from moisture or foreign matter such as dust. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the present disclosure is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0126] The cover window CW may be disposed on the outer coating layer OC. The cover window CW may protect the layers below it. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the present disclosure is not limited thereto. For example, the cover window CW may be encapsulation glass to protect components disposed on its bottom. In other embodiments, the cover window CW may be omitted as needed or desired.

[0127] Figure 5 is a diagram showing a method according to one or more embodiments Figure 4 A plan view of a pixel shown in FIG. Figure 5 , for convenience of explanation, the first pixel PXL1a and the second pixel PXL2a are shown. The other pixels PXL may be configured in the same or similar manner as the first pixel PXL1a and the second pixel PXL2a.

[0128] The first pixel PXL1a may include a first subpixel SP1a, a second subpixel SP2a, and a third subpixel SP3a arranged along the first direction DR1. The first subpixel SP1a may include a first emission area EMA1a and a non-emission area NEAa at the periphery of the first emission area EMA1a. The second subpixel SP2a may include a second emission area EMA2a and a non-emission area NEAa at the periphery of the second emission area EMA2a. The third subpixel SP3a may include a third emission area EMA3a and a non-emission area NEAa at the periphery of the third emission area EMA3a.

[0129] The first emission area EMA1a may be a light emitting structure EMS (eg, see Figure 4 ) The second emission area EMA2a may be an area where light is emitted from the light emitting structure EMS in the second sub-pixel SP2a. The third emission area EMA3a may be an area where light is emitted from the light emitting structure EMS in the third sub-pixel SP3a. Figure 4 As described, each emission area may be understood as a corresponding opening OP of the pixel defining layer PDL corresponding to one of the first sub-pixel SP1a, the second sub-pixel SP2a, and the third sub-pixel SP3a. The shapes and areas of the first emission area EMA1a, the second emission area EMA2a, and the third emission area EMA3a may be the same or substantially the same as each other. For example, each of the first emission area EMA1a, the second emission area EMA2a, and the third emission area EMA3a may be arranged in a rectangular shape or a square shape.

[0130] The second pixel PXL2a may include a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel arranged along the first direction DR1. The second pixel PXL2a may be located in the second direction DR2 from the first pixel PXL1a. The fourth sub-pixel may include a fourth emission area EMA4a, the fifth sub-pixel may include a fifth emission area EMA5a, and the sixth sub-pixel may include a sixth emission area EMA6a. The configuration of the second pixel PXL2a is the same or substantially the same as that of the first pixel PXL1a, and therefore, a redundant description thereof may not be repeated.

[0131] The plurality of metal lines JHL1a, JHL2a, and JHDLa may each extend in the first direction DR1 and may not overlap the emission regions of the subpixels SP. The metal lines JHL1a, JHL2a, and JHDLa may include metal patterns protruding between the emission regions in a direction intersecting or crossing the first direction DR1.

[0132] The first metal line JHL1a may include line portions LP1a, LP2a, and LP3a and metal patterns UR1a and UR2a. The first metal pattern UR1a may protrude in a second direction DR2 that intersects or crosses the first direction DR1 between the first emission area EMA1a and the second emission area EMA2a. The second metal pattern UR2a may protrude in the second direction DR2 between the second emission area EMA2a and the third emission area EMA3a.

[0133] Each of the metal patterns UR1a and UR2a may have a ring shape. The metal patterns UR1a and UR2a may be configured as Korean characters. , or may be configured as a "U" shape in the English alphabet. The metal patterns UR1a and UR2a may sublimate the organic material of the area OPAa between the first metal line JHL1a and the second metal line JHL2a and not overlapped with the first metal line JHL1a and the second metal line JHL2a, thereby preventing or reducing leakage current through the common layer of organic materials between adjacent sub-pixels SP. For example, the first metal pattern UR1a may prevent or reduce leakage current between the first sub-pixel SP1a and the second sub-pixel SP2a, and the second metal pattern UR2a may prevent or reduce leakage current between the second sub-pixel SP2a and the third sub-pixel SP3a.

[0134] The length of each of the first and second metal patterns UR1a and UR2a in the second direction DR2 may be longer than the length of each of the first, second, and third emission areas EMA1a, EMA2a, and EMA3a in the second direction DR2.

[0135] The first line portion LP1a may be located in the opposite direction of the second direction DR2 from the first emission area EMA1a, and may be connected to one end of the first metal pattern UR1a. The length of the first line portion LP1a in the first direction DR1 may be longer than the length of the first emission area EMA1a in the first direction DR1. The second line portion LP2a may be located in the opposite direction of the second direction DR2 from the second sub-pixel SP2a, and may connect the first metal pattern UR1a and the second metal pattern UR2a to each other. The length of the second line portion LP2a in the first direction DR1 may be longer than the length of the second emission area EMA2a in the first direction DR1. The third line portion LP3a may be located in the opposite direction of the second direction DR2 from the third emission area EMA3a, and may be connected to the other end (e.g., the opposite end) of the second metal pattern UR2a. The length of the third line portion LP3a in the first direction DR1 may be longer than the length of the third emission area EMA3a in the first direction DR1.

[0136] The second metal wire JHL2a may pass between the first and fourth emission areas EMA1a, EMA4a, EMA2a, EMA5a, and EMA3a and EMA6a. The first and second metal wires JHL1a and JHL2a may be spaced apart from each other in the second direction DR2.

[0137] The dummy metal line JHDLa may be located in the second direction DR2 of the sub-pixel SP located at the outermost portion in the second direction DR2 among the sub-pixels SP. Figure 5 , the fourth to sixth subpixels of the second pixel PXL2a are shown as subpixels SP located at the outermost portion in the second direction DR2. The upper area UPAa located in the second direction DR2 from the second pixel PXL2a may correspond to the non-display area NDA, and may not include any subpixel SP (or any emission area thereof). The dummy metal line JHDLa may be located in the second direction DR2 from the fourth to the sixth subpixel, so that leakage current from the fourth to the sixth subpixel in the second direction DR2 may be prevented or reduced. Both ends (e.g., opposite ends) of the dummy metal line JHDLa may be connected to the first metal pad JPD1 and the second metal pad JPD2, respectively, and may be supplied with a power voltage like the other metal lines JHL1a and JHL2a.

[0138] The shapes of the first metal wire JHL1a, the second metal wire JHL2a, and the dummy metal wire JHDLa may be the same or substantially the same as each other. Therefore, the resistance values ​​of the first metal wire JHL1a, the second metal wire JHL2a, and the dummy metal wire JHDLa may be the same or substantially the same as each other, and Joule heating may be uniformly or substantially uniformly generated.

[0139] Figure 6 It is along Figure 5 A cross-sectional view taken along line II' shown in FIG.

[0140] Reference Figure 6 , the pixel circuit layer PCL may be disposed on the substrate SUB.

[0141] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0142] The substrate SUB and the pixel circuit layer PCL disposed on the substrate SUB may include circuit elements of each of the first to third sub-pixels SP1a to SP3a. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1a, a transistor T_SP2 of the second sub-pixel SP2a, and a transistor T_SP3 of the third sub-pixel SP3a. The transistor T_SP1 of the first sub-pixel SP1a may be a sub-pixel circuit SPC (for example, see Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2a may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2a. The transistor T_SP3 of the third sub-pixel SP3a may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3a. Figure 6 , for ease of explanation, one of the transistors for each of the sub-pixels is shown, and other circuit elements are not shown.

[0143] The transistor T_SP1 of the first subpixel SP1 a may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0144] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed in the well WL to be spaced apart from each other. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0145] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL and / or the channel region by a suitable insulating material (such as a gate insulating layer GI). The gate electrode GE may include a conductive material.

[0146] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA by penetrating one or more drain connection portions DRC in the insulating layer. The second conductive pattern CP2 may be electrically connected to the source region SRA by penetrating one or more source connection portions SRC in the insulating layer.

[0147] Because the gate electrode GE and the first and second conductive patterns CP1 and CP2 may be connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1a may be set to (eg, may correspond to) any one of the transistors of the first subpixel SP1a.

[0148] Each of the transistor T_SP2 of the second subpixel SP2 a and the transistor T_SP3 of the third subpixel SP3 a may be configured in the same or substantially the same manner as the transistor T_SP1 of the first subpixel SP1 a .

[0149] As such, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 a to SP3 a .

[0150] The via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have a completely flat surface. The via layer VIAL may be configured to flatten or substantially flatten the step difference of the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the present disclosure is not limited thereto.

[0151] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0152] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 are respectively disposed in the first to third subpixels SP1a to SP3a. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole penetrating the via layer VIAL.

[0153] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors that reflect light emitted from the light emitting structure EMS toward a display surface (e.g., a cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and a suitable alloy of two or more materials selected therefrom. However, the present disclosure is not limited thereto.

[0154] In one or more embodiments, the connecting electrode may be disposed on the bottom of each of the first to third reflective electrodes RE1 to RE3. The connecting electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the present disclosure is not limited thereto. In one or more embodiments, the corresponding reflective electrode may be located between multiple layers of the connecting electrode.

[0155] The buffer pattern BFP may be disposed on the bottom of at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the present disclosure is not limited thereto. When the buffer pattern BFP is disposed, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0156] The first to third reflective electrodes RE1 to RE3 may be used as full reflective mirrors, and the cathode electrode CE may be used as a half reflective mirror. Light emitted from the light emitting layer of the light emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE may be understood as the resonance distance of the light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0157] By the buffer pattern BFP, the first subpixel SP1a can have a resonance distance shorter than the resonance distance of another subpixel. The resonance distance adjusted as described above can allow light of a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first subpixel SP1a can effectively and efficiently emit light of the corresponding wavelength range.

[0158] exist Figure 6 , the buffer pattern BFP is shown as being provided to the first sub-pixel SP1a, but not to the second sub-pixel SP2a and the third sub-pixel SP3a. However, the present disclosure is not limited thereto. In some embodiments, the buffer pattern may also be provided in at least one of the second sub-pixel SP2a and the third sub-pixel SP3a to adjust the resonance distance of at least one of the second sub-pixel SP2a and the third sub-pixel SP3a. For example, the first sub-pixel SP1a to the third sub-pixel SP3a may correspond to red, green, and blue, respectively, and therefore, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0159] In order to flatten or substantially flatten the step difference between the first to third reflective electrodes RE1 to RE3, a flattening layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The flattening layer PLNL entirely covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, and may have a flat or substantially flat surface (e.g., an upper surface). In one or more embodiments, the flattening layer PLNL may be omitted as needed or desired.

[0160] On the planarization layer PLNL, first to third anode electrodes AE1 to AE3 respectively overlapping the first to third reflective electrodes RE1 to RE3 may be disposed. When viewed in the third direction DR3 (eg, in a plan view), the first to third anode electrodes AE1 to AE3 may have the same Figure 5The shapes of the first emission area EMA1a to the third emission area EMA3a shown in FIG. 1 are the same or similar shapes. The first anode electrode AE1 to the third anode electrode AE3 may be connected to the first reflective electrode RE1 to the third reflective electrode RE3, respectively. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via hole VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via hole VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via hole VIA3 penetrating the planarization layer PLNL.

[0161] In one or more embodiments, the first to third anode electrodes AE1 to AE3 may include at least one of various suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and / or indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0162] In one or more embodiments, an insulating layer for adjusting the height of one or more anode electrodes among the first anode electrode AE1 to the third anode electrode AE3 may also be provided. The insulating layer may be provided between at least one of the first anode electrode AE1 to the third anode electrode AE3 and the corresponding reflective electrode. The planarization layer PLNL and / or the buffer pattern BFP may be omitted as needed or desired. For example, the first sub-pixel SP1a to the third sub-pixel SP3a may correspond to red, green, and blue, respectively, and therefore, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. The pixel defining layer PDL may be provided on a portion of the first anode electrode AE1 to the third anode electrode AE3 and a portion of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first anode electrode AE1 to the third anode electrode AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first sub-pixel SP1a to the third sub-pixel SP3a. Thus, the pixel definition layer PDL can define Figure 5 The first emission area EMA1a to the third emission area EMA3a shown in FIG. Figure 5 In the non-emitting area NEA shown in .

[0163] In one or more embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide and / or silicon oxynitride. However, the present disclosure is not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the opening OP.

[0164] In the boundary area BDA between sub-pixels adjacent to each other, a first metal line JHL1 a may be disposed. Each of the metal lines including the first metal line JHL1 a may be located on the pixel defining layer PDL.

[0165] In the display area DA, each of the metal wires including the first metal wire JHL1a may be in contact with the cathode electrode CE of the light emitting element of the sub-pixel SP. For example, the metal wire may radiate heat caused by Joule heating after stacking the light emitting structure EMS, thereby sublimating a portion of the light emitting structure EMS located near it. Therefore, leakage current through the cut portion of the light emitting structure EMS may be prevented or substantially prevented by the metal wire. The metal wire may be exposed to the outside of the light emitting structure EMS and may be in contact with the cathode electrode CE subsequently deposited thereon.

[0166] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. In one or more embodiments, the light emitting structure EMS may be formed by a suitable process such as vacuum deposition or inkjet printing. The light emitting structure EMS fills the opening OP of the pixel defining layer PDL and may be disposed entirely in the entire first to third sub-pixels SP1a to SP3a. As described above, the light emitting structure EMS may be at least partially cut by the first metal line JHL1a in the boundary area BDA. Therefore, during operation of the display panel DP, the current leaking from each of the first to third sub-pixels SP1a to SP3a to the sub-pixels adjacent thereto through the layers included in the light emitting structure EMS may be reduced. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0167] The cathode electrode CE may be disposed over the light emitting structure EMS. The cathode electrode CE may be commonly disposed in the first to third subpixels SP1a to SP3a. The cathode electrode CE may function as a half mirror to allow light emitted from the light emitting structure EMS to partially transmit therethrough and partially reflect therefrom.

[0168] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE overlapping the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 may constitute a third light emitting element LD3.

[0169] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may prevent or substantially prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0170] The optical functional layer OFL may be disposed on the encapsulation layer TFE. In one or more embodiments, the optical functional layer OFL may be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optical functional layer OFL may be manufactured separately to be attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the underlying layers (including the encapsulation layer TFE).

[0171] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1a to SP3a, respectively. The first to third color filters CF1 to CF3 may allow light having wavelength ranges different from each other to pass through them. For example, the first to third color filters CF1 to CF3 may allow red, green, and blue light to pass through them, respectively.

[0172] In one or more embodiments, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be disposed between the first to third color filters CF1 to CF3.

[0173] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third subpixels SP1a to SP3a, respectively. The first to third lenses LS1 to LS3 may output light emitted from the first to third light emitting elements LD1 to LD3 along intended paths, respectively, thereby improving light emission efficiency.

[0174] Figure 7 is a diagram showing a method of performing a Figure 6A cross-sectional view of a light emitting structure included in one of the first to third light emitting elements shown in FIG.

[0175] Reference Figure 7 , the light emitting structure EMS may have a series structure in which a first light emitting unit (eg, a first light emitting substructure) EU1 and a second light emitting unit (eg, a second light emitting substructure) EU2 are stacked. Figure 6 In each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 , the light emitting structure EMS may have the same or substantially the same configuration.

[0176] Each of the first light emitting unit EU1 and the second light emitting unit EU2 may include a light emitting layer for generating light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit (e.g., a first electron transport structure) ETU1, and a first hole transport unit (e.g., a first hole transport structure) HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit (e.g., a second electron transport structure) ETU2, and a second hole transport unit (e.g., a second hole transport structure) HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0177] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer, an electron blocking layer, etc. as needed or necessary. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0178] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer. Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may further include an electron buffer layer, a hole blocking layer, etc. as needed or necessary. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0179] A connection layer provided in the form of a charge generation layer CGL may be provided between the first light emitting unit EU1 and the second light emitting unit EU2 to electrically connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. In one or more embodiments, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any suitable combination thereof. However, the present disclosure is not limited thereto.

[0180] In one or more embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors from each other. The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2, respectively, may be mixed together to be regarded as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In one or more embodiments, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer generating red light and a second sub-light-emitting layer generating green light are stacked. The red light and the green light may be mixed together to provide yellow light. An intermediate layer that performs a function of transporting holes and / or a function of blocking electron transport may be further provided between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0181] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color as each other.

[0182] In one or more embodiments, the light emitting structure EMS may be formed by a suitable process such as vacuum deposition or inkjet printing, but the present disclosure is not limited thereto.

[0183] Figure 8 is a diagram showing a method of performing a Figure 6 A cross-sectional view of a light emitting structure included in one of the first to third light emitting elements shown in FIG.

[0184] Reference Figure 8 , the light emitting structure EMS' may be a series structure in which the first light emitting unit (eg, the first light emitting substructure) EU1' to the third light emitting unit (eg, the third light emitting substructure) EU3' are stacked. Figure 6 In each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 , the light emitting structure EMS′ may have the same or substantially the same configuration.

[0185] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer for generating light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit (e.g., a first electron transport structure) ETU1', and a first hole transport unit (e.g., a first hole transport structure) HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit (e.g., a second electron transport structure) ETU2', and a second hole transport unit (e.g., a second hole transport structure) HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit (e.g., a third electron transport structure) ETU3', and a third hole transport unit (e.g., a third hole transport structure) HTU3'. The third light emitting layer EML3 ′ may be disposed between the third electron transport unit ETU3 ′ and the third hole transport unit HTU3 ′.

[0186] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer. Each of the first to third hole transport units HTU1' to HTU3' may further include a hole buffer layer, an electron blocking layer, etc. as needed or necessary. The first to third hole transport units HTU1' to HTU3' may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0187] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer. Each of the first to third electron transport units ETU1' to ETU3' may further include an electron buffer layer, a hole blocking layer, etc. as needed or necessary. The first to third electron transport units ETU1' to ETU3' may have the same or substantially the same configuration as each other, or may have different configurations from each other.

[0188] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0189] In one or more embodiments, the first to third light-emitting layers EML1' to EML3' may generate light of different colors from each other. Light emitted from the first to third light-emitting layers EML1' to EML3', respectively, may be mixed together to be regarded as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0190] In other embodiments, at least two light emitting layers among the first to third light emitting layers EML1 ′ to EML3 ′ may generate light of the same color as each other.

[0191] However, the present disclosure is not limited thereto, and is consistent with the above reference Figure 7 and Figure 8 The described luminous structures EMS and EMS' are different. Figure 6 The light-emitting structure EMS shown in the figure may include a light-emitting unit (e.g., a light-emitting substructure) in each of the first light-emitting element LD1 to the third light-emitting element LD3. The light-emitting units included in each of the first light-emitting element LD1 to the third light-emitting element LD3 may be configured to emit light of different colors from each other. For example, the light-emitting unit of the first light-emitting element LD1 may emit red light, the light-emitting unit of the second light-emitting element LD2 may emit green light, and the light-emitting unit of the third light-emitting element LD3 may emit blue light. In addition, the light-emitting units of the first subpixel SP1a to the third subpixel SP3a may be separated from each other (e.g., spaced apart), and each of the light-emitting units may be disposed in a corresponding opening of the pixel defining layer PDL. In addition, in some embodiments, at least some of the color filters CF1 to CF3 may be omitted as needed or desired.

[0192] Fig. 9 According to one or more embodiments, Figure 5 A cross-sectional view taken along line II' shown in FIG.

[0193] Fig. 9 The light emitting structure EMS shown in FIG. Figure 6 The described luminous structures EMS may differ in that: Fig. 9 A portion of the light emitting structure EMS in the display area DA may remain on the first metal line JHL1a. In other words, in the display area DA, each of the metal lines including the first metal line JHL1a may not contact the cathode electrode CE of the light emitting element of the sub-pixel.

[0194] For example, after stacking the first light emitting unit EU1 and the charge generation layer CGL on the first metal wire JHL1a, heat caused by Joule heating may be radiated into the first metal wire JHL1a, and thus, portions of the first light emitting unit EU1 and the charge generation layer CGL located near the first metal wire JHL1a may sublime. Subsequently, stacking the second light emitting unit EU2 (for example, see Figure 7 ) steps.

[0195] In another example, after stacking the first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2', and the second charge generation layer CGL2' on the first metal wire JHL1a, heat caused by Joule heating may be radiated into the first metal wire JHL1a, and thus, portions of the first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2', and the second charge generation layer CGL2' located near the first metal wire JHL1a may sublime. Subsequently, stacking the third light emitting unit EU3' (e.g., see Figure 8 ) steps.

[0196] Since the charge generation layer CGL, the first charge generation layer CGL1 ′, or the second charge generation layer CGL2 ′ sublimates, leakage current may be prevented or substantially prevented even when a portion of the light emitting structure EMS or EMS′ remains.

[0197] Fig.10 is a diagram showing a method for applying a Figure 5 View of metal lines of different configurations of the pixel shown in .

[0198] exist Fig.10 In the embodiment, the structures of the first pixel PXL1b, the first sub-pixel SP1b, the second sub-pixel SP2b and the third sub-pixel SP3b may be the same as those described above. Figure 5 The structures described are the same or substantially the same, and therefore, redundant descriptions thereof may not be repeated. Fig.10 In the embodiment, the second pixel PXL2b and the fourth sub-pixel, the fifth sub-pixel and the sixth sub-pixel may be constructed in the same manner as described above. Figure 5 The described configurations are the same or substantially the same, and thus, a redundant description thereof may not be repeated.

[0199] Reference Fig.10, each of the plurality of metal lines JHL1b, JHL2b, JHL3b, and JHL4b may extend in the first direction DR1 and may not overlap with the emission areas EMA1b, EMA2b, EMA3b, EMA4b, EMA5b, and EMA6b of the sub-pixel. The plurality of metal lines JHL1b, JHL2b, JHL3b, and JHL4b may include metal patterns (e.g., UR1b and UR2b) that protrude between the emission areas EMA1b, EMA2b, EMA3b, EMA4b, EMA5b, and EMA6b in a direction that intersects or crosses the first direction DR1. A portion that does not correspond to the emission area in the display area DA may be a non-emission area NEAb.

[0200] However, Fig.10 The construction of the metal wires JHL1b, JHL2b, JHL3b and JHL4b shown in FIG. Figure 5 The metal lines JHL1a, JHL2a, and JHDL1a are described to be differently configured. Fig.10 The metal wires shown in the figure may include a first group of metal wires JHL1b and JHL3b and a second group of metal wires JHL2b and JHL4b. The first group of metal wires JHL1b and JHL3b and the second group of metal wires JHL2b and JHL4b may be alternately arranged along the second direction DR2. In an embodiment, the first group of metal wires JHL1b and JHL3b and the second group of metal wires JHL2b and JHL4b may have shapes that are symmetrical or substantially symmetrical to each other with respect to the first direction DR1.

[0201] The first group of metal lines JHL1b and JHL3b may include a metal pattern protruding in the second direction DR2. For example, along the first direction DR1, the first metal line JHL1b may sequentially include a first line portion LP1b, a first metal pattern UR1b, a second line portion LP2b, a second metal pattern UR2b, and a third line portion LP3b. The first metal pattern UR1b and the second metal pattern UR2b of the first metal line JHL1b may protrude in the second direction DR2 relative to (e.g., from) the line portions LP1b, LP2b, and LP3b.

[0202] The second group of metal lines JHL2b and JHL4b may include a metal pattern protruding in the opposite direction of the second direction DR2. For example, along the first direction DR1, the second metal line JHL2b may sequentially include a fourth line portion LP4b, a third metal pattern UR3b, a fifth line portion LP5b, a fourth metal pattern UR4b, and a sixth line portion LP6b. The third metal pattern UR3b and the fourth metal pattern UR4b of the second metal line JHL2b may protrude in the opposite direction of the second direction DR2 relative to (e.g., from) the line portions LP4b, LP5b, and LP6b.

[0203] The first metal pattern UR1b and the third metal pattern UR3b may face each other between the first emission area EMA1b and the second emission area EMA2b. The heat generated between the first metal pattern UR1b and the third metal pattern UR3b may remove the organic common layer between the first emission area EMA1b and the second emission area EMA2b. In more detail, a partial area not covered by the metal lines JHL1b and JHL2b may exist between the first emission area EMA1b and the second emission area EMA2b. However, unlike the line portions LP1b, LP2b, and LP3b constructed with a single line, the metal patterns UR1b and UR3b constructed with two lines may radiate a larger amount of heat, and therefore, the organic common layer between the first emission area EMA1b and the second emission area EMA2b may be effectively removed. Therefore, the leakage current between the first emission area EMA1b and the second emission area EMA2b may be prevented or reduced.

[0204] The second metal pattern UR2b and the fourth metal pattern UR4b may face each other between the second emission area EMA2b and the third emission area EMA3b. The heat generated in the second metal pattern UR2b and the fourth metal pattern UR4b may remove the organic common layer between the second emission area EMA2b and the third emission area EMA3b. In more detail, a partial area not covered by the metal lines JHL1b and JHL2b may exist between the second emission area EMA2b and the third emission area EMA3b. However, unlike the line portions LP1b, LP2b, and LP3b constructed with a single line, the metal patterns UR2b and UR4b constructed with two lines may radiate a larger amount of heat, and therefore, the organic common layer between the second emission area EMA2b and the third emission area EMA3b may be effectively removed. Therefore, the leakage current between the second emission area EMA2b and the third emission area EMA3b may be prevented or reduced.

[0205] exist Fig.10Since the fourth metal line JHL4b located in the display area DA can prevent or substantially prevent leakage current of the second pixel PXL2b in the second direction DR2, the upper area UPAb in the non-display area NDA from the second pixel PXL2b positioned in the second direction DR2 may not include any dummy metal line.

[0206] The lengths of the metal wires JHL1b, JHL2b, JHL3b, and JHL4b may be the same or substantially the same as each other. Therefore, the resistance values ​​of the metal wires JHL1b, JHL2b, JHL3b, and JHL4b may be the same or substantially the same as each other, and heat may be uniformly generated during Joule heating.

[0207] Fig.11 is a view illustrating a metal line applied to another pixel according to one or more embodiments.

[0208] Reference Fig.11 , for convenience of explanation, an example of four pixels PXL1c, PXL2c, PXL3c, and PXL4c and a plurality of metal lines JHL1c, JHL2c, JHL3c, JHL4c, and JHDLc corresponding thereto is shown.

[0209] The first pixel PXL1c may include a first subpixel, a second subpixel located in a first direction DR1 from the first subpixel, and a third subpixel located in a second direction DR2 from the first subpixel. The first subpixel may include a first emission area EMA1c, the second subpixel may include a second emission area EMA2c, and the third subpixel may include a third emission area EMA3c. A portion not corresponding to the emission area in the display area DA may be a non-emission area NEAc.

[0210] Similarly, the second pixel PXL2c may include a fourth sub-pixel having a fourth emission area EMA4c, a fifth sub-pixel having a fifth emission area EMA5c, and a sixth sub-pixel having a sixth emission area EMA6c. The third pixel PXL3c may include a seventh sub-pixel having a seventh emission area EMA7c, an eighth sub-pixel having an eighth emission area EMA8c, and a ninth sub-pixel having a ninth emission area EMA9c. The fourth pixel PXL4c may include a tenth sub-pixel having a tenth emission area EMA10c, an eleventh sub-pixel having an eleventh emission area EMA11c, and a twelfth sub-pixel having a twelfth emission area EMA12c.

[0211] Hereinafter, for convenience, the first pixel PXL1c will be mainly described in more detail. The second pixel PXL2c, the third pixel PXL3c and the fourth pixel PXL4c and Fig.11Other pixels not shown in the figure may have the same or substantially the same configuration as that of the first pixel PXL1 c described in more detail below, and thus, a redundant description thereof may not be repeated.

[0212] The length of the second emission area EMA2c in the second direction DR2 may be longer than the length of each of the first emission area EMA1c and the third emission area EMA3c in the second direction DR2. For example, the area of ​​the second emission area EMA2c may be greater than the area of ​​each of the first emission area EMA1c and the third emission area EMA3c. In some embodiments, the area of ​​the first emission area EMA1c may also be greater than the area of ​​the third emission area EMA3c. In another embodiment, the area of ​​the first emission area EMA1c may be equal to or substantially equal to the area of ​​the third emission area EMA3c.

[0213] Along the first direction DR1, the first metal line JHL1c may sequentially include a first metal pattern UR1c protruding in the second direction DR2, a second metal pattern UR2c protruding in the second direction DR2, and a third metal pattern UR3c protruding in the second direction DR2. Lengths of the first metal pattern UR1c, the second metal pattern UR2c, and the third metal pattern UR3c in the second direction DR2 may be the same or substantially the same as each other.

[0214] The first metal line JHL1c may further include a first line portion LP1c connecting the first metal pattern UR1c and the second metal pattern UR2c to each other and a second line portion LP2c connecting the second metal pattern UR2c and the third metal pattern UR3c to each other. Positions of the first line portion LP1c and the second line portion LP2c may be identical or substantially identical to each other with respect to the second direction DR2. Lengths of the first line portion LP1c and the second line portion LP2c in the first direction DR1 may be identical or substantially identical to each other.

[0215] Along the first direction DR1, the second metal line JHL2c may sequentially include a fourth metal pattern UR4c protruding in the opposite direction of the second direction DR2, a fifth metal pattern UR5c protruding in the opposite direction of the second direction DR2, and a sixth metal pattern UR6c protruding in the opposite direction of the second direction DR2. The shapes of the fourth metal pattern UR4c and the sixth metal pattern UR6c may be identical or substantially identical to each other. The shape of the fifth metal pattern UR5c may be symmetrical or substantially symmetrical to the shape of the fourth metal pattern UR4c in the second direction DR2.

[0216] The second metal line JHL2c may further include a third line portion LP3c connecting the fourth metal pattern UR4c and the fifth metal pattern UR5c to each other, and a fourth line portion LP4c connecting the fifth metal pattern UR5c and the sixth metal pattern UR6c to each other. Positions of the third line portion LP3c and the fourth line portion LP4c may be different from each other with respect to the second direction DR2. Lengths of the third line portion LP3c and the fourth line portion LP4c in the first direction DR1 may be the same or substantially the same as each other.

[0217] The first emission area EMA1c may be located between the first line portion LP1c and the third line portion LP3c. The second emission area EMA2c may be located between the second line portion LP2c and the fourth line portion LP4c. The distance between the first line portion LP1c and the third line portion LP3c may be smaller than (e.g., narrower than) the distance between the second line portion LP2c and the fourth line portion LP4c.

[0218] The third emission area EMA3c may be located in the second direction DR2 from the third line portion LP3c. The third metal line JHL3c having the same or substantially the same shape as the first metal line JHL1c may be located in the second direction DR2 from the third emission area EMA3c. Leakage current from the third emission area EMA3c in the second direction DR2 may be blocked by the third metal line JHL3c.

[0219] The second metal pattern UR2c and the fifth metal pattern UR5c may face each other between the first emission area EMA1c and the second emission area EMA2c. In addition, the first metal pattern UR1c and the fourth metal pattern UR4c may approach each other in the opposite direction of the first direction DR1 from the first emission area EMA1c to face each other in the second direction DR2. In addition, the third metal pattern UR3c and the sixth metal pattern UR6c may face each other between the second emission area EMA2c and the seventh emission area EMA7c. The positions of the metal patterns UR1c, UR2c, UR3c, UR4c, UR5c and UR6c may be arranged so that the length of the first metal wire JHL1c and the length of the second metal wire JHL2c are the same or substantially the same as each other. Therefore, the resistance values ​​of the metal wires JHL1c and JHL2c may be the same or substantially the same as each other, and heat may be uniformly generated during Joule heating.

[0220] The dummy metal line JHDLc may be located in the second direction DR2 from the outermost pixel among the pixels located in the second direction DR2. Fig.11, the second pixel PXL2c and the fourth pixel PXL4c are shown as pixels located at the outermost part in the second direction DR2. The upper area UPAc located in the second direction DR2 from the second pixel PXL2c and the fourth pixel PXL4c may correspond to the non-display area NDA, and may not include any sub-pixel (or its emission area). The dummy metal line JHDLc is located in the second direction DR2 from the second pixel PXL2c and the fourth pixel PXL4c, so that leakage current from the emission areas EMA5c, EMA6c, EMA11c and EMA12c in the second direction DR2 can be prevented or substantially prevented. Both ends (e.g., opposite ends) of the dummy metal line JHDLc can be connected to the first metal pad JPD1 and the second metal pad JPD2, respectively, and can be supplied with a power voltage similar to the power voltage of the other metal lines JHL1c, JHL2c, JHL3c and JHL4c. The dummy metal line JHDLc may have the same or substantially the same shape as the first metal line JHL1c and / or the third metal line JHL3c.

[0221] Fig.12 is a view illustrating a metal line applied to another pixel according to one or more embodiments.

[0222] The first pixel PXL1d may include a first sub-pixel and a second sub-pixel arranged along the first direction DR1. In addition, the first pixel PXL1d may include a third sub-pixel located between the first sub-pixel and the second sub-pixel in the second direction DR2. The first sub-pixel may include a first emission area EMA1d, the second sub-pixel may include a second emission area EMA2d, and the third sub-pixel may include a third emission area EMA3d. The first emission area EMA1d, the second emission area EMA2d, and the third emission area EMA3d may have a hexagonal shape. In another embodiment, the first emission area EMA1d, the second emission area EMA2d, and the third emission area EMA3d may have a circular shape. The shapes of the first emission area EMA1d, the second emission area EMA2d, and the third emission area EMA3d are not limited thereto, and may be modified differently as needed or desired (such as according to a desired product).

[0223] The second pixel PXL2d may include a fourth sub-pixel and a fifth sub-pixel arranged along the first direction DR1. In addition, the second pixel PXL2d may include a sixth sub-pixel located between the fourth sub-pixel and the fifth sub-pixel in the opposite direction of the second direction DR2. The fourth sub-pixel may include a fourth emission area EMA4d, the fifth sub-pixel may include a fifth emission area EMA5d, and the sixth sub-pixel may include a sixth emission area EMA6d. The fourth emission area EMA4d, the fifth emission area EMA5d, and the sixth emission area EMA6d may have a hexagonal shape. In another embodiment, the fourth emission area EMA4d, the fifth emission area EMA5d, and the sixth emission area EMA6d may have a circular shape. The shapes of the fourth emission area EMA4d, the fifth emission area EMA5d, and the sixth emission area EMA6d are not particularly limited and may be modified differently as needed or desired (such as according to a desired product).

[0224] Hereinafter, for convenience, the first pixel PXL1d will be mainly described in more detail. The second pixel PXL2d and Fig.12 Other pixels not shown in the figure may have the same or substantially the same configuration as that of the first pixel PXL1d, and thus, a redundant description thereof may not be repeated.

[0225] Each of the plurality of metal lines JHL1d, JHL2d, and JHL3d may extend in the first direction DR1 and may not overlap the emission region of the subpixel. The plurality of metal lines JHL1d, JHL2d, and JHL3d may include a metal pattern protruding between the emission regions in a direction intersecting or crossing the first direction DR1.

[0226] The metal lines JHL1d, JHL2d, and JHL3d may include a first group of metal lines JHL1d and JHL3d and a second group of metal lines JHL2d, ..., etc. The first group of metal lines JHL1d and JHL3d and the second group of metal lines JHL2d, ... may be alternately arranged along the second direction DR2. In an embodiment, the first group of metal lines JHL1d and JHL3d and the second group of metal lines JHL2d, ... may have shapes that are symmetrical or substantially symmetrical to each other with respect to the first direction DR1.

[0227] Along the first direction DR1, the first metal line JHL1d may sequentially include a first metal pattern UR1d protruding in the second direction DR2, a second metal pattern UR2d protruding in the opposite direction of the second direction DR2, a third metal pattern UR3d protruding in the second direction DR2, a fourth metal pattern UR4d protruding in the opposite direction of the second direction DR2, and a fifth metal pattern UR5d protruding in the second direction DR2. The first emission area EMA1d may be located in the second direction DR2 from the second metal pattern UR2d. The second emission area EMA2d may be located in the second direction DR2 from the fourth metal pattern UR4d.

[0228] The first metal line JHL1d may include a first line portion LP1d connecting the first metal pattern UR1d and the second metal pattern UR2d to each other, a second line portion LP2d connecting the second metal pattern UR2d and the third metal pattern UR3d to each other, a third line portion LP3d connecting the third metal pattern UR3d and the fourth metal pattern UR4d to each other, and a fourth line portion LP4d connecting the fourth metal pattern UR4d and the fifth metal pattern UR5d to each other.

[0229] The first line portion LP1d and the third line portion LP3d may be parallel to each other or substantially parallel to each other. For example, the first line portion LP1d and the third line portion LP3d may extend in a direction between the opposite direction of the second direction DR2 and the first direction DR1. The second line portion LP2d and the fourth line portion LP4d may be parallel to each other or substantially parallel to each other. For example, the second line portion LP2d and the fourth line portion LP4d may extend in a direction between the second direction DR2 and the first direction DR1. Therefore, the first line portion LP1d and the second line portion LP2d may not be parallel to each other.

[0230] Along the first direction DR1, the second metal line JHL2d may sequentially include a sixth metal pattern UR6d protruding in the opposite direction of the second direction DR2, a seventh metal pattern UR7d protruding in the second direction DR2, an eighth metal pattern UR8d protruding in the opposite direction of the second direction DR2, a ninth metal pattern UR9d protruding in the second direction DR2, and a tenth metal pattern UR10d protruding in the opposite direction of the second direction DR2. The first emission area EMA1d may be located in the opposite direction of the second direction DR2 from the seventh metal pattern UR7d. The second emission area EMA2d may be located in the opposite direction of the second direction DR2 from the ninth metal pattern UR9d. The third emission area EMA3d may be located in the second direction DR2 from the eighth metal pattern UR8d. The third metal pattern UR3d and the eighth metal pattern UR8d may face each other between the first emission area EMA1d and the second emission area EMA2d. The second metal line JHL2d may also include a fifth line portion LP5d, a sixth line portion LP6d, a seventh line portion LP7d, and an eighth line portion LP8d.

[0231] Along the first direction DR1, the third metal line JHL3d may sequentially include an eleventh metal pattern UR11d protruding in the opposite direction of the second direction DR2, a twelfth metal pattern UR12d protruding in the second direction DR2, and a thirteenth metal pattern UR13d protruding in the opposite direction of the second direction DR2. The third emission area EMA3d may be located in the opposite direction of the second direction DR2 from the twelfth metal pattern UR12d. The eleventh metal pattern UR11d and the seventh metal pattern UR7d may face each other in the second direction DR2. The thirteenth metal pattern UR13d and the ninth metal pattern UR9d may face each other in the second direction DR2. The third metal line JHL3d may further include a ninth line portion LP9d and a tenth line portion LP10d.

[0232] Fig.12 It is shown that the upper area UPAd in the non-display area NDA in the second direction DR2 may not include any dummy metal line because the third metal line JHL3d in the display area DA may prevent or substantially prevent leakage current from the emission areas EMA3d, EMA4d, and EMA5d in the second direction DR2.

[0233] The lengths of the metal wires JHL1d, JHL2d, and JHL3d may be the same or substantially the same as each other. Therefore, the resistance values ​​of the metal wires JHL1d, JHL2d, and JHL3d may be the same or substantially the same as each other, and heat may be uniformly generated during Joule heating.

[0234] Fig.13is a view showing a connection portion of a metal pad and a metal wire.

[0235] Reference Fig.13 , portions of the first metal pad JPD1 and the metal lines JHL1 to JHL5 at the boundary of the non-display area NDA and the display area DA are enlarged and illustrated.

[0236] According to one or more embodiments, the first metal pad JPD1 and the metal lines JHL1 to JHL5 may be connected to each other through the connection parts BFN1 to BFN5. The connection parts BFN1 to BFN5 and the metal lines JHL1 to JHL5 may be connected to each other to correspond one to one to each other.

[0237] The width of each of the connection portions BFN1 to BFN5 in the second direction DR2 may be greater than (e.g., wider than) the width of each of the metal lines JHL1 to JHL5 in the second direction DR2. In addition, the connection area POI1 where the first metal pad JPD1 is connected to each of the connection portions BFN1 to BFN5 may have a curved shape. In addition, the connection area POI2 where each of the connection portions BFN1 to BFN5 is connected to the corresponding metal line of the metal lines JHL1 to JHL5 may have a curved shape. Because each of the connection areas POI1 and POI2 may have a curved shape, a current deflection phenomenon may be prevented or substantially prevented. If the current deflection phenomenon occurs, sparks may occur, and the light emitting structure EMS may be sublimated due to unintentional heat generation in an area close to the display area DA.

[0238] Although Fig.13 Only the first metal pad JPD1 is shown, but the second metal pad JPD2 may have the same or substantially the same connection structure and relationship as those of the first metal pad JPD1 described above, and thus a redundant description thereof will not be repeated.

[0239] Fig.14 is a diagram illustrating a display system according to one or more embodiments.

[0240] Reference Fig.14 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0241] The processor 1100 may perform various tasks and various calculations. In one or more embodiments, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the components of the display system 1000.

[0242] Fig.14 The display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0243] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The configuration of the display device 100 described above is the same or substantially the same. The first image data IMG1 and the first control signal CTRL1 may be provided as shown in FIG. Figure 1 The image data IMG and the control signal CTRL shown in FIG.

[0244] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The configuration of the display device 100 described above is the same or substantially the same. The second image data IMG2 and the second control signal CTRL2 may be provided as shown in FIG. Figure 1 The image data IMG and the control signal CTRL shown in FIG.

[0245] The display system 1000 may include a computing system for providing an image display function (such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC)). In addition, the display system 1000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0246] Fig.15 It is shown Fig.14 A perspective view of an application example of the display system shown in FIG.

[0247] Reference Fig.15 , Fig.14The display system 1000 shown in FIG. 1 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0248] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing 2200. The head-mounted band 2100 may be connected to the display device housing 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band, and may be used to fix the head-mounted display device 2000 to the user's head. The horizontal band may surround the side of the user's head, and the vertical band may surround the upper part of the user's head. However, the present disclosure is not limited thereto. For example, the head-mounted band 2100 may be implemented in the form of a frame, a helmet, etc.

[0249] The display device receiving housing 2200 can receive Fig.14 The first display device 1210 and the second display device 1220 are shown in FIG. The display device receiving housing 2200 can also receive Fig.14 Processor 1100 shown in .

[0250] Fig.16 is shown as being worn by the user Fig.15 A view of a head mounted display device shown in FIG.

[0251] Reference Fig.16 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 may be provided in the head mounted display device 2000. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0252] In the display device accommodating housing 2200, a right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user. In the display device accommodating housing 2200, a left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user.

[0253] The image output from the first display panel DP1 may be viewed by the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract the light emitted from the first display panel DP1 to face the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0254] The image output from the second display panel DP2 may be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract the light emitted from the second display panel DP2 to face the user's left eye. The left eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0255] In one or more embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. Each display panel DP1 and DP2 may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may be viewed by the user while passing through the corresponding sub-regions, respectively.

[0256] In a display device and a wearable device according to one or more embodiments of the present disclosure, leakage current through a common layer between adjacent pixels may be prevented or substantially prevented.

[0257] The foregoing is an explanation of some embodiments of the present disclosure and will not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically noted, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the foregoing is an explanation of various example embodiments and will not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, including a non-display area and a display area; a sub-pixel, in the display area; as well as a metal line passing through the non-display area and the display area in a first direction, Each of the metal lines extends in the first direction so as not to overlap with the emission regions of the sub-pixels, and includes a metal pattern protruding in a direction crossing the first direction between the emission regions.

2. The display device according to claim 1, wherein: Each of the metal patterns has a ring shape.

3. The display device according to claim 2, wherein: Each of the metal lines is located on a pixel defining layer, and the pixel defining layer defines the emission region of the sub-pixel in the display region.

4. The display device according to claim 1, further comprising: a first metal pad, in the non-display area; as well as a second metal pad, in the non-display area, the second metal pad being located in the first direction from the first metal pad, The metal wire connects the first metal pad and the second metal pad to each other.

5. The display device according to claim 1, wherein: The metal wires have the same shapes as each other.

6. The display device according to claim 1, wherein: The sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel positioned along the first direction, and Wherein, the metal wire comprises a first metal wire, and the first metal wire comprises: a first metal pattern protruding in a second direction intersecting the first direction between a first emission region of the first sub-pixel and a second emission region of the second sub-pixel; and A second metal pattern protrudes in the second direction between the second emission region and a third emission region of the third sub-pixel.

7. The display device according to claim 6, wherein: A length of each of the first metal pattern and the second metal pattern in the second direction is longer than a length of each of the first emission region, the second emission region, and the third emission region in the second direction.

8. The display device according to claim 7, wherein: The first metal line further includes: a first line portion located in a direction opposite to the second direction from the first emission region, the first line portion being connected to the first metal pattern; a second line portion located in the opposite direction of the second direction from the second emission region, the second line portion connecting the first metal pattern and the second metal pattern to each other; and A third line portion is located in the opposite direction of the second direction from the third emission region, the third line portion being connected to the second metal pattern.

9. The display device according to claim 8, wherein: The sub-pixels further include a fourth sub-pixel, a fifth sub-pixel and a sixth sub-pixel located along the first direction, The metal line further includes a second metal line, the second metal line passes between the first emission area and the fourth emission area of ​​the fourth sub-pixel, between the second emission area and the fifth emission area of ​​the fifth sub-pixel, and between the third emission area and the sixth emission area of ​​the sixth sub-pixel, and The first metal line and the second metal line are spaced apart from each other.

10. The display device according to claim 6, wherein: The metal lines further include dummy metal lines located in the second direction from the outermost sub-pixels in the second direction among the sub-pixels.

11. The display device according to claim 1, wherein: The metal wire comprises: a first group of metal lines including metal patterns protruding in a second direction intersecting the first direction; and a second set of metal lines including metal patterns protruding in a direction opposite to the second direction, and The first group of metal wires and the second group of metal wires are alternately positioned along the second direction.

12. The display device according to claim 11, wherein: The first group of metal lines and the second group of metal lines have shapes symmetrical to each other with respect to the first direction.

13. The display device according to claim 1, wherein: The sub-pixels include a first sub-pixel and a second sub-pixel located along the first direction, The metal line includes a first metal line, and the first metal line sequentially includes along the first direction: a first metal pattern protruding in a second direction intersecting the first direction; a second metal pattern protruding in a direction opposite to the second direction; a third metal pattern protruding in the second direction; a fourth metal pattern protruding in the direction opposite to the second direction; and a fifth metal pattern protruding in the second direction. Wherein, the first emission region of the first sub-pixel is located in the second direction from the second metal pattern, and The second emission region of the second sub-pixel is located in the second direction from the fourth metal pattern.

14. The display device according to claim 13, wherein: The first metal line further includes: a first line portion connecting the first metal pattern and the second metal pattern to each other; a second line portion connecting the second metal pattern and the third metal pattern to each other; a third line portion connecting the third metal pattern and the fourth metal pattern to each other; and a fourth line portion connecting the fourth metal pattern and the fifth metal pattern to each other, and in: The first line portion and the third line portion are parallel to each other; The second line portion and the fourth line portion are parallel to each other; and The first line portion and the second line portion are not parallel to each other.

15. The display device according to claim 14, wherein: The sub-pixel further includes a third sub-pixel, Wherein, the metal line further includes a second metal line, and the second metal line sequentially includes along the first direction: a sixth metal pattern protruding in the opposite direction to the second direction; a seventh metal pattern protruding in the second direction; an eighth metal pattern protruding in the opposite direction to the second direction; a ninth metal pattern protruding in the second direction; and a tenth metal pattern protruding in the opposite direction to the second direction, wherein the first emission region is located in the opposite direction of the second direction from the seventh metal pattern, wherein the second emission region is located in the opposite direction of the second direction from the ninth metal pattern, and The third emission region of the third sub-pixel is located in the second direction from the eighth metal pattern.

16. The display device according to claim 15, wherein: The third metal pattern and the eighth metal pattern face each other between the first emission region and the second emission region.

17. The display device according to claim 16, wherein: The metal line further includes a third metal line, and the third metal line sequentially includes along the first direction: an eleventh metal pattern protruding in the opposite direction to the second direction; a twelfth metal pattern protruding in the second direction; and a thirteenth metal pattern protruding in the opposite direction to the second direction, The third emission region is located in the opposite direction of the second direction from the twelfth metal pattern. wherein the eleventh metal pattern and the seventh metal pattern face each other in the second direction, and Wherein, the thirteenth metal pattern and the ninth metal pattern face each other in the second direction.

18. The display device according to claim 1, wherein: The metal wire comprises: A first metal line sequentially including, along the first direction: a first metal pattern protruding in a second direction crossing the first direction; a second metal pattern protruding in the second direction; and a third metal pattern protruding in the second direction; and The second metal line sequentially includes, along the first direction: a fourth metal pattern protruding in a direction opposite to the second direction; a fifth metal pattern protruding in the direction opposite to the second direction; and a sixth metal pattern protruding in the direction opposite to the second direction, The first metal line further includes: a first line portion connecting the first metal pattern and the second metal pattern to each other; and a second line portion connecting the second metal pattern and the third metal pattern to each other. The second metal line further includes: a third line portion connecting the fourth metal pattern and the fifth metal pattern to each other; and a fourth line portion connecting the fifth metal pattern and the sixth metal pattern to each other. wherein the positions of the first line portion and the second line portion are identical to each other with respect to the second direction, and wherein positions of the third line portion and the fourth line portion are different from each other with respect to the second direction.

19. The display device according to claim 18, wherein: The sub-pixel comprises: A first subpixel including a first emission region; a second sub-pixel located in the first direction from the first sub-pixel and including a second emission area; and a third sub-pixel, located in the second direction from the first sub-pixel and comprising a third emission area, wherein the length of the second emission region in the second direction is longer than the length of each of the first emission region and the third emission region in the second direction, wherein the first emission region is located between the first line portion and the third line portion, wherein the second emission region is located between the second line portion and the fourth line portion, and The third emission region is located in the second direction from the third line portion.

20. The display device according to claim 19, wherein: The second metal pattern and the fifth metal pattern face each other between the first emission region and the second emission region.

21. A wearable device, comprising: a first display panel; as well as The second display panel, Each of the first display panel and the second display panel comprises: a substrate including a non-display area and a display area; a sub-pixel in the display area; and a metal line passing through the non-display area and the display area in a first direction, and Each of the metal lines extends in the first direction so as not to overlap with the emission regions of the sub-pixels, and includes a metal pattern protruding in a direction crossing the first direction between the emission regions.

Images