Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device may include a pixel defining layer defining sub-pixels, a pixel electrode of each sub-pixel disposed in an opening of the pixel defining layer, a trench formed by etching a portion of the pixel defining layer and surrounding at least a portion of each of the sub-pixels, heating wirings disposed on the pixel defining layer and spaced apart from each other via a trench located between the heating wirings, a first organic material covering a first pixel electrode of the first sub-pixel and a portion of the pixel defining layer surrounding the first pixel electrode, a second organic material covering a second pixel electrode of the second sub-pixel and a portion of the pixel defining layer surrounding the second pixel electrode; and a third organic material covering a third pixel electrode of the third sub-pixel and a portion of the pixel defining layer surrounding the third pixel electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0114400 filed in the Korean Intellectual Property Office on August 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] Wearable devices in the form of glasses or helmets that form a focal point at a short distance from the user's eyes are being developed. For example, the wearable device may be a head-mounted display (HMD) device or augmented reality (AR) glasses. Such wearable devices provide AR images or virtual reality (VR) images to the user.

[0005] Wearable devices such as HMD devices or AR glasses need to have a display specification of at least 2000 pixels per inch (PPI) so that users can use it for a long time without dizziness. Silicon-based organic light-emitting diode (OLEDoS) technology is being proposed as a small-scale high-resolution organic light-emitting display device. OLEDoS is a technology for placing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0006] As the distance between pixels in a display panel to which OLEDoS technology is applied is reduced, unexpected leakage current may be generated between adjacent pixels. The leakage current may be generated by some conductive layers in the intermediate layer arranged between the pixel electrode (e.g., anode) and the common electrode (e.g., cathode). It is known that the leakage current is the cause of color crosstalk between adjacent pixels. Summary of the invention

[0007] The embodiment provides a display device and a method of manufacturing the display device in which leakage current is prevented by depositing and patterning an organic material for each sub-pixel using a heating wiring and encapsulation performance of the organic material can be improved using a groove.

[0008] According to an embodiment, a method for manufacturing a display device may include: forming a semiconductor backplane including a substrate and a light-emitting element backplane; and forming a light-emitting element layer and an encapsulation layer on the light-emitting element backplane. Forming the light-emitting element layer and the encapsulation layer includes: depositing a pixel electrode for each of a plurality of sub-pixels; depositing a pixel defining layer on the pixel electrode to define the sub-pixels; etching a portion of the pixel defining layer between adjacent sub-pixels to form a groove surrounding at least a portion of each of the sub-pixels; forming a heating wiring on the pixel defining layer so that the heating wirings can be spaced apart from each other with the grooves interposed therebetween; depositing a first organic material for a first sub-pixel on the entire surface of the substrate; removing the portion of the first organic material deposited around the heating wiring and the groove by heating the heating wiring; depositing a first common electrode on the entire surface of the substrate; depositing a first encapsulation layer on the entire surface of the substrate; removing the first organic material, the first common electrode, and the first encapsulation layer deposited in the second and third sub-pixels by using a first light patterning process, and retaining the first organic material, the first common electrode, and the first encapsulation layer deposited in the portion of the groove surrounding the first sub-pixel; depositing a second organic material for a second sub-pixel ... portion of the groove surrounding the first sub-pixel by heating the heating wiring; removing the first organic material, the first common electrode, and the first encaps The thermal wiring heats and removes the second organic material deposited around the heating wiring and the groove; deposits the second common electrode on the entire surface of the substrate; deposits the second encapsulation layer on the entire surface of the substrate; removes the second organic material, the second common electrode and the second encapsulation layer deposited in the first sub-pixel and the third sub-pixel by using a second photo-patterning process, and retains the second organic material, the second common electrode and the second encapsulation layer deposited in the portion of the groove surrounding the second sub-pixel; deposits the third organic material of the third sub-pixel on the entire surface of the substrate; removes the third organic material deposited around the heating wiring and the groove by heating the heating wiring; deposits the third common electrode on the entire surface of the substrate; deposits the third encapsulation layer on the entire surface of the substrate; and removes the third organic material, the third common electrode and the third encapsulation layer deposited in the first sub-pixel and the second sub-pixel by using a third photo-patterning process, and retains the third organic material, the third common electrode and the third encapsulation layer deposited in the portion of the groove surrounding the third sub-pixel.

[0009] A non-groove region in which the groove is not formed may be disposed outside each of the sub-pixels, and the first common electrode, the second common electrode, and the third common electrode may be electrically connected through the non-groove region.

[0010] The groove located between the first sub-pixel and the second sub-pixel can be divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area.

[0011] The groove located between the second sub-pixel and the third sub-pixel can be divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0012] The groove located between the first subpixel and the third subpixel can be divided into a first area adjacent to the first subpixel and a third area adjacent to the third subpixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0013] The first encapsulation layer, the second encapsulation layer, and the third encapsulation layer may have the same stack structure.

[0014] The first organic material includes a first light emitting layer emitting light of a first color having a red wavelength band, the second organic material includes a second light emitting layer emitting light of a second color having a green wavelength band, and the third organic material includes a third light emitting layer emitting light of a third color having a blue wavelength band.

[0015] According to an embodiment, a display device may include a pixel defining layer defining a plurality of sub-pixels, a pixel electrode of each sub-pixel arranged in an opening of the pixel defining layer, a groove formed by etching a portion of the pixel defining layer and surrounding at least a portion of each of the sub-pixels, heating wirings arranged on the pixel defining layer and spaced apart from each other via the grooves arranged between heating wirings, a first organic material covering a first pixel electrode of a first sub-pixel and a portion of the pixel defining layer surrounding the first pixel electrode, a first common electrode covering the first organic material and the first heating wiring around the first sub-pixel, a first encapsulation layer covering the first common electrode and a portion of the groove located around the first sub-pixel, a second organic material covering a second pixel electrode of a second sub-pixel and a portion of the pixel defining layer surrounding the second pixel electrode, a second common electrode covering the second organic material and the second heating wiring around the second sub-pixel, a second encapsulation layer covering the second common electrode and a portion of the groove located around the second sub-pixel, a third organic material covering a third pixel electrode of a third sub-pixel and a portion of the pixel defining layer surrounding the third pixel electrode, a third common electrode covering the third organic material and the third heating wiring around the third sub-pixel, and a third encapsulation layer covering the third common electrode and a portion of the groove located around the third sub-pixel.

[0016] A non-groove region in which the groove is not formed may be disposed outside each of the sub-pixels, and the first common electrode, the second common electrode, and the third common electrode may be electrically connected through the non-groove region.

[0017] The groove located between the first sub-pixel and the second sub-pixel can be divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area.

[0018] The groove located between the second sub-pixel and the third sub-pixel can be divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0019] The groove located between the first subpixel and the third subpixel can be divided into a first area adjacent to the first subpixel and a third area adjacent to the third subpixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0020] The first encapsulation layer, the second encapsulation layer, and the third encapsulation layer may have the same stack structure.

[0021] The first organic material includes a first light emitting layer emitting light of a first color having a red wavelength band, the second organic material includes a second light emitting layer emitting light of a second color having a green wavelength band, and the third organic material includes a third light emitting layer emitting light of a third color having a blue wavelength band.

[0022] The display device may further include a display panel in which the light emitting element layer is arranged on a semiconductor backplane.

[0023] According to an embodiment, a display device may include a pixel defining layer defining a plurality of sub-pixels, a pixel electrode of each sub-pixel arranged in an opening of the pixel defining layer, a groove formed by etching a portion of the pixel defining layer and surrounding at least a portion of each of the sub-pixels, a heating wiring arranged on a bottom surface of the groove, an auxiliary common electrode arranged on the pixel defining layer and spaced apart from each other via the groove arranged between the auxiliary common electrodes, a first organic material covering a first pixel electrode of a first sub-pixel and a portion of the pixel defining layer surrounding the first pixel electrode, a first common electrode covering the first organic material and a first auxiliary common electrode adjacent to the first pixel electrode, and a first common electrode covering the first common electrode and the groove. A first encapsulation layer located around a first subpixel, a second organic material covering a second pixel electrode of a second subpixel and a portion of a pixel defining layer surrounding the second pixel electrode, a second common electrode covering the second organic material and a second auxiliary common electrode adjacent to the second pixel electrode, a second encapsulation layer covering the second common electrode and a portion of the groove located around the second subpixel, a third organic material covering a third pixel electrode of a third subpixel and a portion of the pixel defining layer surrounding the third pixel electrode, a third common electrode covering the third organic material and a third auxiliary common electrode adjacent to the third pixel electrode, and a third encapsulation layer covering the third common electrode and a portion of the groove located around the third subpixel.

[0024] A groove-free region in which the groove is not formed may be disposed outside each of the sub-pixels, and the first, second, and third auxiliary common electrodes may be electrically connected through the groove-free region.

[0025] The groove located between the first sub-pixel and the second sub-pixel can be divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area.

[0026] The groove located between the second sub-pixel and the third sub-pixel can be divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, the second common electrode and the second encapsulation layer covering the second common electrode can be arranged in the second area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0027] The groove located between the first subpixel and the third subpixel can be divided into a first area adjacent to the first subpixel and a third area adjacent to the third subpixel, the first common electrode and the first encapsulation layer covering the first common electrode can be arranged in the first area, and the third common electrode and the third encapsulation layer covering the third common electrode can be arranged in the third area.

[0028] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become clear and more readily understood through the following description of embodiments made in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic perspective view of a head mounted display device according to an embodiment;

[0031] Figure 2 yes Figure 1 An exploded schematic perspective view of an example of a head mounted display device;

[0032] Figure 3 is a schematic perspective view of a head mounted display device according to an embodiment;

[0033] Figure 4 is an exploded schematic perspective view of a display device according to an embodiment;

[0034] Figure 5 is a schematic cross-sectional view of an example of a portion of a display panel according to an embodiment;

[0035] Figure 6 is a schematic cross-sectional view showing a (1-1) operation of forming a heating wiring according to an embodiment on a pixel defining layer;

[0036] Figure 7 is a schematic cross-sectional view showing a (1-2) operation of depositing a first organic material;

[0037] Figure 8 is a schematic cross-sectional view showing a (1-3) operation of removing a portion of a first organic material by using a heating wiring;

[0038] Fig. 9 is a schematic cross-sectional view showing the (1-4) operation of depositing a first common electrode;

[0039] Fig.10 is a schematic cross-sectional view showing operation (1-5) of depositing a first encapsulation layer;

[0040] Fig.11 is a schematic cross-sectional view showing a (1-6) operation of partially photo-patterning a first encapsulation layer, a first common electrode, and a first organic material;

[0041] Fig.12is a schematic cross-sectional view showing operation (1-7) of depositing and patterning a second organic material and a third organic material in a manner similar to operations (1-2) to (1-6);

[0042] Fig.13 is a schematic cross-sectional view showing the (2-1) operation of forming a heating wiring according to the embodiment on the bottom surface of a groove;

[0043] Fig.14 is a schematic cross-sectional view showing operation (2-2) of depositing a first organic material;

[0044] Fig.15 is a schematic cross-sectional view showing a (2-3) operation of removing a portion of the first organic material by using a heating wiring;

[0045] Fig.16 is a schematic cross-sectional view showing operation (2-4) of depositing a first common electrode;

[0046] Fig.17 is a schematic cross-sectional view showing operation (2-5) of depositing a first encapsulation layer;

[0047] Fig.18 is a schematic cross-sectional view showing a (2-6) operation of partially photo-patterning a first encapsulation layer, a first common electrode, and a first organic material;

[0048] Fig.19 is a schematic cross-sectional view showing operation (2-7) of depositing and patterning a second organic material and a third organic material in a manner similar to operations (2-2) to (2-6);

[0049] Fig. 20 is a layout diagram showing a portion of a display panel for explaining an auxiliary common electrode according to an embodiment;

[0050] Fig.21 is a schematic cross-sectional view showing a (3-1) operation of forming a heating wiring according to an embodiment on a bottom surface of a groove and a pixel defining layer;

[0051] Fig. 22 is a schematic cross-sectional view showing the (3-2) operation of depositing a first organic material;

[0052] Fig.23 is a schematic cross-sectional view showing operation (3-3) of removing a portion of the first organic material by using a heating wiring;

[0053] Fig.24 is a schematic cross-sectional view showing the (3-4) operation of depositing a first common electrode;

[0054] Fig.25 is a schematic cross-sectional view showing operation (3-5) of depositing a first encapsulation layer;

[0055] Fig.26 is a schematic cross-sectional view illustrating a (3-6) operation of partially photo-patterning a first encapsulation layer, a first common electrode, and a first organic material; and

[0056] Fig. 27 : is a schematic cross-sectional view showing operation (3-7) of depositing and patterning the second organic material and the third organic material in a manner similar to operations (3-2) to (3-6). DETAILED DESCRIPTION

[0057] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0058] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0059] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material performance, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When an embodiment can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. Moreover, similar reference numerals represent similar elements.

[0060] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis, and the Z-axis), and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0062] Spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is able to encompass both the above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0063] The terms used herein are for the purpose of describing a particular embodiment and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "the" as used herein are also intended to include plural forms. In addition, the terms "include", "include", "include" and / or "include" when used in this specification specify the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and thus, are used to consider the inherent deviations in measured values, calculated values ​​and / or provided values ​​recognized by those of ordinary skill in the art.

[0064] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the zones, but rather will include deviations in shape resulting from, for example, manufacturing. In this manner, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and thus are not necessarily intended to be limiting.

[0065] As is customary in the art, some embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented using electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally, they can be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0066] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0067] Figure 1 is a schematic perspective view of the head mounted display device 1 according to the embodiment. Figure 2 yes Figure 1 1 is an exploded schematic perspective view of an example of a head mounted display device 1.

[0068] Reference Figure 1 and Figure 2 The head mounted display device 1 may include a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head strap 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0069] The first display device 10_1 may provide an image to the left eye of the user, and the second display device 10_2 may provide an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 may be connected to the reference Figures 4 to 27 The display devices 10 to be described are substantially the same. Therefore, for convenience of description, the description of the first display device 10_1 and the second display device 10_2 will be referred to as Figures 4 to 27 The description given is used instead.

[0070] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0071] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 may support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0072] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source received from the outside into digital video data, and transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0073] The control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and may transmit digital video data corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. In another example, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0074] The display device housing 110 may accommodate the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 may cover the opening surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 on which the user's left eye may be arranged and a second eyepiece 132 on which the user's right eye may be arranged. Figure 1 and Figure 2 The first eyepiece 131 and the second eyepiece 132 are separately arranged, but the embodiment is not limited thereto. The first eyepiece 131 and the second eyepiece 132 may also be combined with each other.

[0075] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0076] The headband 140 can fix the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 can be respectively held on the user's left eye and right eye. In the case where the display device housing 110 is implemented to be lightweight and small, the head mounted display device 1 may include a Figure 3 , rather than the headband 140 .

[0077] For example, the head mounted display device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0078] Figure 3 is a schematic perspective view of a head mounted display device 1_1 according to an embodiment.

[0079] Reference Figure 3 The head mounted display device 1_1 may be a display device in which the display device housing 110_1 is implemented as a lightweight and small glasses form. The head mounted display device 1_1 may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 110_1.

[0080] Figure 3 The display device 10_3 shown in FIG. Figures 4 to 27 The display device 10 to be described is substantially the same. Therefore, for ease of description, the description of the display device 10_3 will be referred to as Figures 4 to 27 The description given is used instead.

[0081] The display device housing 110_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. An image displayed on the display device 10_3 may be magnified by the optical member 320, its optical path may be converted by the optical path conversion member 330, and may be provided to the right eye of the user through the right eye lens 312. Accordingly, the user may view an augmented reality image generated by combining a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 312 through the right eye.

[0082] Although in Figure 3 The display device housing 110_1 is arranged at the right end of the support frame 350, but the embodiment is not limited thereto. For example, the display device housing 110_1 may also be arranged at the left end of the support frame 350. For example, the image of the display device 10_3 may be provided to the left eye of the user. In another example, the display device housing 110_1 may be arranged at both the left and right ends of the support frame 350. For example, the user may view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0083] Figure 4 is an exploded schematic perspective view of the display device 10 according to the embodiment.

[0084] Reference Figure 4, the display device 10 may be a device for displaying a moving image or a still image. The display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. In another example, the display device 10 may be applied to a smart watch, a watch phone, and a head-mounted display for realizing virtual reality and augmented reality.

[0085] The display device 10 may include a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0086] The display panel 410 may have a planar shape similar to a quadrilateral. For example, the display panel 410 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 410, each corner portion where a short side extending in the first direction DR1 intersects with a long side extending in the second direction DR2 may be rounded with a selectable curvature or may be a right angle. The planar shape of the display panel 410 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the embodiment is not limited thereto.

[0087] The display panel 410 may include a display area where an image is displayed and a non-display area where an image is not displayed.

[0088] The display area may include pixels, and each of the pixels may include sub-pixels SP1 to SP3 (see Figure 5 ). The sub-pixels SP1 to SP3 may include pixel transistors. The pixel transistors may be formed by a semiconductor process and may be arranged on a substrate (or semiconductor substrate) SSUB (see Figure 5 ). For example, the pixel transistor may be formed as a complementary metal oxide semiconductor (CMOS) transistor.

[0089] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be arranged on a surface (e.g., a back surface (or rear surface)) of the display panel 410. The heat dissipation layer 420 may dissipate heat generated in the display panel 410. The heat dissipation layer 420 may include graphite having high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0090] The circuit board 430 may be electrically connected to the pads PD in the pad area PDA of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board made of a flexible material, or may be a flexible film. Figure 4 The circuit board 430 is unfolded, but the circuit board 430 may also be bent. For example, an end of the circuit board 430 may be arranged on the back surface (or rear surface) of the display panel 410. The end of the circuit board 430 may be opposite to the other end of the pad PD in the pad area PDA of the circuit board 430 connected to the display panel 410 by using a conductive adhesive member.

[0091] The driving circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0092] The power supply circuit 450 may generate a panel driving voltage according to a power supply voltage received from the outside. For example, the power supply circuit 450 may generate a first driving voltage (e.g., a low power voltage), a second driving voltage (e.g., a high power voltage), and a third driving voltage (e.g., a reference voltage) and supply them to the display panel 410.

[0093] Each of the driving circuit 440 and the power supply circuit 450 may be formed as an integrated circuit and attached to a surface of the circuit board 430 .

[0094] Figure 5 is a schematic cross-sectional view of an example of a portion of a display panel 410 according to an embodiment. For example, Figure 5 A partial cross-sectional structure of a display region including sub-pixels SP1 to SP3 is shown.

[0095] Reference Figure 5 , the display panel 410 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer.

[0096] The semiconductor backplane SBP may include a substrate (eg, semiconductor substrate) SSUB including the pixel transistor PTR, a semiconductor insulating layer covering the pixel transistor PTR, and a contact terminal CTE electrically connected to the pixel transistor PTR.

[0097] The substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The substrate SSUB may be a substrate doped with a first type of impurity. The well area WA may be arranged below the upper surface of the substrate SSUB. The well area WA may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, in the case where the first type of impurity is a p-type impurity (or a p-type dopant), the second type of impurity may be an n-type impurity (or an n-type dopant). In the case where the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0098] Each of the well areas WA may include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0099] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of each pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be arranged on one side of the gate electrode GE, and the drain region DA may be arranged on the other side of the gate electrode GE.

[0100] Each of the well regions WA may further include a first lightly doped impurity region disposed between the channel region CH and the source region SA and a second lightly doped impurity region disposed between the channel region CH and the drain region DA. The first lightly doped impurity region may be a region having an impurity concentration lower than that of the source region SA. The second lightly doped impurity region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first lightly doped impurity region and the second lightly doped impurity region. Accordingly, the length of the channel region CH of each pixel transistor PTR may be increased, thereby preventing a punch-through phenomenon and a hot carrier phenomenon caused by a short channel.

[0101] The first semiconductor insulating layer SINS1 may be disposed on the substrate SSUB. The first semiconductor insulating layer SINS1 may be silicon carbon nitride (SiC x N y ) or silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto.

[0102] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto.

[0103] The contact terminal CTE may be arranged on the second semiconductor insulating layer SINS2. Each of the contact terminals CTE may be connected to any one of the source area SA and the drain area DA of the pixel transistor PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact terminal CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy containing any one of the same materials.

[0104] The third semiconductor insulating layer SINS3 may be disposed on a side surface of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto.

[0105] The substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide (PI). For example, a thin film transistor may be arranged on a glass substrate or a polymer resin substrate. A glass substrate may be a rigid substrate that does not bend, and a polymer resin substrate may be a flexible substrate that can be bent or folded.

[0106] The light emitting element back plate EBP may include first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, via layers VA1 to VA10, and step layers STPL. For example, the light emitting element back plate EBP may further include interlayer insulating layers INS1 to INS10 disposed between the semiconductor back plate SBP, the first to eighth metal layers ML1 to ML8, and the light emitting element layer EML.

[0107] The first metal layer ML1 to the eighth metal layer ML8 play the function of realizing the circuit of each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 by connecting the contact terminal CTE exposed in the semiconductor backplane SBP. For example, the first transistor to the sixth transistor can be formed only in the semiconductor backplane SBP, and the connection of the first transistor to the sixth transistor and the first capacitor and the second capacitor can be realized through the first metal layer ML1 to the eighth metal layer ML8. For example, the connection between the drain region corresponding to the drain electrode of the fourth transistor and the source region corresponding to the source electrode of the fifth transistor and the pixel electrode AND of the light emitting element LE can also be realized through the first metal layer ML1 to the eighth metal layer ML8.

[0108] The first interlayer insulating layer INS1 may be disposed on the semiconductor backplane SBP. The first via layers VA1 may penetrate the first interlayer insulating layer INS1 and may be respectively connected to the contact terminals CTE exposed in the semiconductor backplane SBP. The first metal layer ML1 may be disposed on the first interlayer insulating layer INS1 and may be respectively connected to the first via layers VA1.

[0109] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. The second via layers VA2 may penetrate the second interlayer insulating layer INS2 and may be respectively connected to the exposed first metal layers ML1. The second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and may be respectively connected to the second via layers VA2.

[0110] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. The third via layers VA3 may penetrate the third interlayer insulating layer INS3 and may be respectively connected to the exposed second metal layers ML2. The third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may be respectively connected to the third via layers VA3.

[0111] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. The fourth via layers VA4 may penetrate the fourth interlayer insulating layer INS4 and may be respectively connected to the exposed third metal layers ML3. The fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be respectively connected to the fourth via layers VA4.

[0112] The fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. The fifth via layers VA5 may penetrate the fifth interlayer insulating layer INS5 and may be respectively connected to the exposed fourth metal layers ML4. The fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be respectively connected to the fifth via layers VA5.

[0113] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. The sixth via layer VA6 may penetrate the sixth interlayer insulating layer INS6 and may be respectively connected to the exposed fifth metal layers ML5. The sixth metal layer ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be respectively connected to the sixth via layer VA6.

[0114] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. The seventh via layers VA7 may penetrate the seventh interlayer insulating layer INS7 and may be respectively connected to the exposed sixth metal layers ML6. The seventh metal layers ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be respectively connected to the seventh via layers VA7.

[0115] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. The eighth via layer VA8 may penetrate the eighth interlayer insulating layer INS8 and may be respectively connected to the exposed seventh metal layer ML7. The eighth metal layer ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be respectively connected to the eighth via layer VA8.

[0116] The first metal layer ML1 to the eighth metal layer ML8 and the first via layer VA1 to the eighth via layer VA8 may be made of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first via layer VA1 to the eighth via layer VA8 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or may be made of an alloy containing any of the above-mentioned same materials. The first via layer VA1 to the eighth via layer VA8 may be made of substantially the same material. Each of the first interlayer insulating layer INS1 to the eighth interlayer insulating layer INS8 may be silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto.

[0117] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first via layer VA1, the thickness of the second via layer VA2, the thickness of the third via layer VA3, the thickness of the fourth via layer VA4, the thickness of the fifth via layer VA5, and the thickness of the sixth via layer VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be about The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be about 100 Å. And the thickness of the first via layer VA1, the thickness of the second via layer VA2, the thickness of the third via layer VA3, the thickness of the fourth via layer VA4, the thickness of the fifth via layer VA5, and the thickness of the sixth via layer VA6 may each be about 1000 Å.

[0118] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the seventh via layer VA7 and the thickness of the eighth via layer VA8. The thickness of the seventh via layer VA7 and the thickness of the eighth via layer VA8 may each be greater than the thickness of the first via layer VA1, the thickness of the second via layer VA2, the thickness of the third via layer VA3, the thickness of the fourth via layer VA4, the thickness of the fifth via layer VA5, and the thickness of the sixth via layer VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other. For example, the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be about The thickness of the seventh via layer VA7 and the thickness of the eighth via layer VA8 may each be about 100 Å.

[0119] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto.

[0120] The ninth via layer VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8, respectively. The ninth via layer VA9 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy including any of the same materials. The thickness of the ninth via layer VA9 may be about 1000 Å.

[0121] The first reflective electrodes RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via layers VA9, respectively. The first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy including any of the same materials.

[0122] The second reflective electrodes RL2 may be disposed on the first reflective electrodes RL1, respectively. The second reflective electrodes RL2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy containing any of the same materials. For example, the second reflective electrode RL2 may be titanium nitride (TiN).

[0123] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be determined in consideration of the wavelength of the light of the first color and the distance from the first light-emitting element layer EML1 to the fourth reflective electrode RL4 to perform reflection of the light of the first color emitted from the first light-emitting element layer EML1 of the first sub-pixel SP1. The step layer STPL may be silicon carbon nitride (SiC x N y ) or silicon oxide (SiO x )-based inorganic layer, but the embodiment is not limited thereto. The thickness of the step layer STPL may be about

[0124] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy containing any of the same materials.

[0125] In another example, at least one of the first to third reflective electrodes RL1 to RL3 may be omitted.

[0126] The fourth reflective electrode RL4 may be arranged on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may be a layer that reflects light from the first light emitting element layer EML1, the second light emitting element layer EML2, and the third light emitting element layer EML3, respectively arranged in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The fourth reflective electrode RL4 may include a metal with high reflectivity to perform reflection of light. The fourth reflective electrode RL4 may be made of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy which is an alloy of silver (Ag), palladium (Pd), and copper (Cu), or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO), but the embodiment is not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be about 1000 Å.

[0127] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating layer INS10 may be silicon oxide (SiO x)-based inorganic layer, but the embodiment is not limited thereto.

[0128] The tenth via layer VA10 may penetrate the tenth interlayer insulating layer INS10 and may be connected to the exposed fourth reflective electrodes RL4, respectively. The tenth via layer VA10 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy containing any of the same materials. Due to the step layer STPL, the thickness of the tenth via layer VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via layer VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via layer VA10 in the first sub-pixel SP1 may be about 100 Å. And the thickness of the tenth via layer VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 100 Å.

[0129]

[0130] The light emitting element layer EML (e.g., EML1, EML2, and EML3) may be arranged on the light emitting element backplane EBP. The light emitting element layer EML may include light emitting elements LE each including a pixel electrode AND, an intermediate layer IL, and a common electrode CAT, and a pixel defining layer PDL. The pixel electrode AND may also be referred to as an "anode" or a "first electrode". The common electrode CAT may also be referred to as a "cathode" or a "second electrode".

[0131] The pixel electrodes AND (eg, AND1, AND2, and AND3 (see Figure 6 )) may be arranged on the tenth interlayer insulating layer INS10 and may be connected to the tenth via layer VA10. The pixel electrode AND (e.g., AND1, AND2, and AND3) of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via layer VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first via layer VA1 to the ninth via layer VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The pixel electrode AND of each of the light emitting elements LE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be made of an alloy containing any of the same materials mentioned above. For example, the pixel electrode AND of each of the light emitting elements LE may be titanium nitride (TiN).

[0132] The pixel defining layer PDL may be disposed on a portion of the pixel electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover an edge portion of the pixel electrode AND of each of the light emitting elements LE. The pixel defining layer PDL defines first to third emission areas EA1 to EA3.

[0133] The first emission area EA1 may be defined as an area where the pixel electrode AND, the intermediate layer IL, and the common electrode CAT in the first sub-pixel SP1 are sequentially stacked to emit light. The second emission area EA2 may be defined as an area where the pixel electrode AND, the intermediate layer IL, and the common electrode CAT in the second sub-pixel SP2 are sequentially stacked to emit light. The third emission area EA3 may be defined as an area where the pixel electrode AND, the intermediate layer IL, and the common electrode CAT in the third sub-pixel SP3 are sequentially stacked to emit light.

[0134] The pixel defining layer PDL may include first to third pixel defining layers PDL1 to PDL3. The first pixel defining layer PDL1 may be arranged on the edge portion of the pixel electrode AND of each of the light emitting elements LE, the second pixel defining layer PDL2 may be arranged on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be arranged on the second pixel defining layer PDL2. Each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be silicon oxide (SiO x ) base inorganic layer, but the embodiment is not limited thereto. The thickness of the first pixel defining layer PDL1, the thickness of the second pixel defining layer PDL2, and the thickness of the third pixel defining layer PDL3 may each be about

[0135] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0136] The intermediate layer IL may have a series structure including intermediate layers IL1 to IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0137] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0138] According to an embodiment, the intermediate layer IL may have an organic light emitting layer emitting light of different colors in each sub-pixel. For example, the intermediate layer IL may include a first organic material 711 (see Figure 7 ), the second organic material 712 arranged in the second sub-pixel SP2 (see Fig.12 ) and the third organic material 713 arranged in the third sub-pixel SP3 (see Fig.12 ).

[0139] The first organic material 711 may include a first light emitting layer that emits light of a first color in a red wavelength band.

[0140] The second organic material 712 may include a second light emitting layer that emits light of a second color in a green wavelength band.

[0141] The third organic material 713 may include a third light emitting layer that emits light of a third color in a blue wavelength band.

[0142] The intermediate layer IL may cover the pixel electrode AND in each opening of the pixel defining layer PDL and cover the pixel defining layer PDL between adjacent sub-pixels (or neighboring sub-pixels) SP1 to SP3, but may be disposed between the heating wiring (eg, Figure 7 Accordingly, the display device 10 can prevent color interference caused by leakage current.

[0143] The color interference phenomenon indicates, for example, a phenomenon in which the first sub-pixel SP1 adjacent to the third sub-pixel SP3 is unexpectedly turned on in a case where the third sub-pixel SP3 emits blue light. The color interference phenomenon may occur due to leakage current, and may occur under the condition that the third sub-pixel SP3 and the first sub-pixel SP1 having a large pixel driving voltage difference are adjacent to each other. For example, the leakage current indicates a phenomenon in which a portion of the driving current is transmitted to the first sub-pixel SP1 through at least some conductive layers of the intermediate layer IL in a case where the driving current is supplied to the light emitting element LE of the third sub-pixel SP3 to turn on the third sub-pixel SP3. In the case where the leakage current occurs, the first sub-pixel SP1 may be unexpectedly turned on while the third sub-pixel SP3 is turned on.

[0144] The common electrode CAT may be disposed on the intermediate layer IL and may be made of a transparent conductive material (TCO) capable of transmitting light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmitting conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag.

[0145] The encapsulation layer TFE may be arranged on the light emitting element layer EML. The encapsulation layer TFE may include one or more inorganic layers to prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0146] The first encapsulation inorganic layer TFE1 may be disposed on the common electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. Each of the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be a layer in which silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The encapsulating organic layer TFE2 may be a monomer. In another example, the encapsulating organic layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0147] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL together. The adhesive layer ADL may be a double-sided adhesive member. For example, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0148] The optical layer OPL may include a lens LNS and a filling layer FIL.

[0149] Each of the lenses LNS may be a structure for increasing the ratio of light directed toward the front surface of the display device 10. Each of the lenses LNS may have an upwardly convex cross-sectional shape.

[0150] The filling layer FIL may be arranged on the lens LNS. The filling layer FIL may have a selectable refractive index so that light can propagate in the third direction DR3 at the interface between the lens LNS and the filling layer FIL. For example, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0151] The cover layer CVL may be arranged on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer substrate such as a resin. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. For example, the filling layer FIL may function to bond the cover layer CVL. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In the case where the cover layer CVL is a polymer substrate such as a resin, the cover layer CVL may be arranged (for example, directly arranged) on the filling layer FIL.

[0152] The polarizer may be arranged on the surface of the cover layer CVL. The polarizer may be a structure for preventing visibility reduction due to reflection of external light. The polarizer may include a linear polarizer and a phase delay film. For example, the phase delay film may be a quarter wave plate (λ / 4 plate), but the embodiment is not limited thereto.

[0153] In the following, reference will be made to Figure 6 to Figure 27 The display device 10 according to the embodiment and the method of manufacturing the display device 10 are described in detail. In the display device 10 and the method of manufacturing the display device 10 according to the embodiment, leakage current can be prevented by depositing and patterning an organic material for each sub-pixel using a heating wiring 610, and the encapsulation performance of the organic material can be improved using the groove 620.

[0154] Figures 6 to 12 is a schematic cross-sectional view illustrating a method of manufacturing a display panel 410 according to an embodiment. Figures 6 to 12 The display panel 410 of the display device 10 is shown, but a portion of the semiconductor backplane SBP disposed on the substrate SSUB and a light emitting element backplane EBP disposed on the semiconductor backplane SBP are omitted. For convenience of description, the description of the elements not shown will be referred to in detail. Figure 5 The description given is used instead.

[0155] Now refer to Figures 6 to 12 A method of manufacturing the display panel 410 is described in which an organic material is deposited and patterned for each sub-pixel by using the heating wiring 610 .

[0156] Figure 6is a schematic cross-sectional view illustrating a (1-1)th operation of forming the heating wiring 610 (eg, 611 , 612 , and 613 ) according to the embodiment on the pixel defining layer PDL.

[0157] Reference Figure 6 In the (1-1) operation, a substrate SSUB of the display panel 410 may be prepared. The substrate SSUB may be a semiconductor substrate.

[0158] For example, reference layers may be sequentially formed on the substrate SSUB. Figure 5 Described are a portion of the semiconductor back plate SBP arranged on the substrate SSUB and the light emitting element back plate EBP.

[0159] For example, a pixel electrode AND (eg, AND1 , AND2 , and AND3 ) of each of the sub-pixels SP1 to SP3 may be deposited.

[0160] For example, a pixel defining layer PDL may be deposited on the pixel electrode AND to define the sub-pixels SP1 to SP3. The pixel defining layer PDL may be patterned to expose a portion of the pixel electrode AND of each of the sub-pixels SP1 to SP3. For example, during the process, the pixel electrode AND of each of the sub-pixels SP1 to SP3 may be exposed through an opening of the pixel defining layer PDL.

[0161] For example, a portion of the pixel defining layer PDL located between adjacent sub-pixels (or neighboring sub-pixels) SP1 to SP3 may be etched to form a groove 620 surrounding at least a portion of each of the sub-pixels SP1 to SP3. For example, the groove 620 may not completely surround each of the sub-pixels SP1 to SP3 and may not be formed in some areas. The area in which the groove 620 is not formed may be referred to as a "groove-free area 2010 (see Fig. 20 The groove-free region 2010 may be a region for preventing the common electrodes CAT from being disconnected from each other.

[0162] For example, a heating wiring 610 may be formed on the pixel defining layer PDL. The heating wiring 610 may surround at least a portion of each of the sub-pixels SP1 to SP3. The heating wiring 610 may be spaced apart from each other via a groove 620 between the heating wirings 610. For example, a pair of heating wirings 610 may be arranged between adjacent sub-pixels (or adjacent sub-pixels) SP1 to SP3, and may be spaced apart from each other via a groove 620 between the pair of heating wirings 610. The heating wiring 610 may receive a Joule heating voltage from the outside, and may be heated to a specified temperature (e.g., about 400° C.) or higher based on the received Joule heating voltage. As will be described later, the heating wiring 610 functions to remove organic materials deposited around the heating wiring 610.

[0163] Figure 7is a schematic cross-sectional view showing the (1-2) operation of depositing the first organic material 711. Figure 7 , in the (1-2)th operation, a first organic material 711 of the first sub-pixel SP1 may be deposited on the entire surface of the substrate SSUB. The first organic material 711 may include a first light emitting layer that emits light of a first color in a red wavelength band. The first organic material 711 may be commonly deposited not only in the first sub-pixel SP1 for displaying the first color, but also in the second sub-pixel SP2 for displaying the second color and the third sub-pixel SP3 for displaying the third color.

[0164] Figure 8 610 is a schematic cross-sectional view showing the (1-3) operation of removing a portion of the first organic material 711 by using the heating wiring 610. Figure 8 In the (1-3) operation, a Joule heating voltage may be applied to the heating wiring 610, and the first organic material 711 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the first organic material 711 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0165] Fig. 9 is a schematic cross-sectional view showing the (1-4) operation of depositing the first common electrode CAT1. Fig. 9 In the (1-4) operation, the first common electrode CAT1 may be deposited on the entire surface of the substrate SSUB. The first common electrode CAT1 may be deposited on the first organic material 711, the pixel defining layer PDL disposed around the heating wiring 610 and the heating wiring 610, and in the groove 620.

[0166] Fig.10 is a schematic cross-sectional view showing the (1-5) operation of depositing the first encapsulation layer TFE1. Fig.10 In the operation (1-5), a first encapsulation layer TFE1 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the first encapsulation layer TFE1 may include a multilayer in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0167] Fig.11 is a schematic cross-sectional view showing a (1-6)th operation of partially photo-patterning the first encapsulation layer TFE1, the first common electrode CAT1, and the first organic material 711. Fig.11In the (1-6) operation, a first photo-patterning process may be performed. For example, the first photo-patterning process may be used to remove the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in a portion of the groove 620 surrounding the first sub-pixel SP1 may be left (or retained).

[0168] Fig.12 is a schematic cross-sectional view showing the (1-7) operation of depositing and patterning the second organic material 712 and the third organic material 713 in a manner similar to the (1-2) to (1-6) operations. Fig.12 , the (1-7) operation may include depositing and patterning the second organic material 712 and depositing and patterning the third organic material 713 .

[0169] For example, the second organic material 712 of the second sub-pixel SP2 may be deposited on the entire surface of the substrate SSUB. The second organic material 712 may include a second light emitting layer that emits light of a second color in a green wavelength band. The second organic material 712 may be commonly deposited not only in the second sub-pixel SP2 for displaying the second color, but also in the first sub-pixel SP1 for displaying the first color and the third sub-pixel SP3 for displaying the third color.

[0170] For example, a Joule heating voltage may be applied to the heating wiring 610, and the second organic material 712 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the second organic material 712 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0171] For example, the second common electrode CAT2 may be deposited on the entire surface of the substrate SSUB. The second common electrode CAT2 may be deposited on the second organic material 712, the pixel defining layer PDL disposed around the heating wiring 610 and the heating wiring 610, and in the groove 620.

[0172] For example, the second encapsulation layer TFE2 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the second encapsulation layer TFE2 may include a plurality of layers in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0173] For example, a second photo-patterning process may be performed. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in the first sub-pixel SP1 and the third sub-pixel SP3 may be removed using the second photo-patterning process. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in a portion of the groove 620 surrounding the second sub-pixel SP2 may be left (or retained).

[0174] For example, the third organic material 713 of the third sub-pixel SP3 may be deposited on the entire surface of the substrate SSUB. The third organic material 713 may include a third light emitting layer emitting light of a third color in a blue wavelength band. The third organic material 713 may be commonly deposited not only in the third sub-pixel SP3 for displaying the third color, but also in the first sub-pixel SP1 for displaying the first color and the second sub-pixel SP2 for displaying the second color.

[0175] For example, a Joule heating voltage may be applied to the heating wiring 610, and the third organic material 713 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the third organic material 713 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0176] For example, the third common electrode CAT3 may be deposited on the entire surface of the substrate SSUB. The third common electrode CAT3 may be deposited on the third organic material 713, the pixel defining layer PDL disposed around the heating wiring 610 and the heating wiring 610, and in the groove 620.

[0177] For example, the third encapsulation layer TFE3 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the third encapsulation layer TFE3 may include a plurality of layers in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked. According to an embodiment, the stacking structure of the first encapsulation layer TFE1, the stacking structure of the second encapsulation layer TFE2, and the stacking structure of the third encapsulation layer TFE3 may all be the same.

[0178] For example, a third photo-patterning process may be performed. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in the first sub-pixel SP1 and the second sub-pixel SP2 may be removed using the third photo-patterning process. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in a portion of the groove 620 surrounding the third sub-pixel SP3 may be left (or retained).

[0179] According to an embodiment, the groove 620 between the first sub-pixel SP1 and the second sub-pixel SP2 may be divided into a first area 620_1 adjacent to the first sub-pixel SP1 and a second area 620_2 adjacent to the second sub-pixel SP2. The first common electrode CAT1 and the first encapsulation layer TFE1 covering the first common electrode CAT1 may be arranged in the first area 620_1. The second common electrode CAT2 and the second encapsulation layer TFE2 covering the second common electrode CAT2 may be arranged in the second area 620_2.

[0180] According to an embodiment, the groove 620 between the second subpixel SP2 and the third subpixel SP3 may be divided into a second region 620_2 adjacent to the second subpixel SP2 and a third region 620_3 adjacent to the third subpixel SP3. The second common electrode CAT2 and the second encapsulation layer TFE2 covering the second common electrode CAT2 may be arranged in the second region 620_2, and the third common electrode CAT3 and the third encapsulation layer TFE3 covering the third common electrode CAT3 may be arranged in the third region 620_3.

[0181] According to an embodiment, the groove 620 between the first subpixel SP1 and the third subpixel SP3 may be divided into a first region 620_1 adjacent to the first subpixel SP1 and a third region 620_3 adjacent to the third subpixel SP3. The first common electrode CAT1 and the first encapsulation layer TFE1 covering the first common electrode CAT1 may be arranged in the first region 620_1. The third common electrode CAT3 and the third encapsulation layer TFE3 covering the third common electrode CAT3 may be arranged in the third region 620_3.

[0182] In the display device 10 according to the embodiment, each of the first encapsulation layer TFE1, the second encapsulation layer TFE2, and the third encapsulation layer TFE3 may contact (e.g., directly contact) the surface of the pixel defining layer PDL in the groove 620, thereby improving encapsulation performance. For example, in the display panel 410, the encapsulation layer TFE may contact (e.g., directly contact) the surface of the pixel defining layer PDL in the groove 620, thereby reducing lateral damage (e.g., degradation) to the first organic material 711, the second organic material 712, and the third organic material 713.

[0183] According to an embodiment, the trench-free region 2010 (eg, in the Fig. 20 The first common electrode CAT1, the second common electrode CAT2, and the third common electrode CAT3 may be electrically connected through the groove-free region 2010. Accordingly, the common electrodes CAT respectively provided in the sub-pixels SP1 to SP3 may be electrically connected to each other without being disconnected.

[0184] Figures 13 to 19 4 is a schematic cross-sectional view illustrating a method of manufacturing a display panel 410 using a heating wiring 610 arranged on a bottom surface of a groove 620 . Figures 13 to 19 The display panel 410 of the display device 10 is shown, but a portion of the semiconductor backplane SBP disposed on the substrate SSUB and a light emitting element backplane EBP disposed on the semiconductor backplane SBP are omitted. For convenience of description, the description of the elements not shown will be referred to in detail. Figure 5 The description given is used instead.

[0185] Figures 13 to 19 Examples and Figures 6 to 12 The embodiment of FIG. 6 is different in that the heating wiring 610 is arranged on the bottom surface of the groove 620 .

[0186] Now refer to Figures 13 to 19 A method of manufacturing the display panel 410 is described in which an organic material is deposited and patterned for each sub-pixel by using the heating wiring 610 arranged on the bottom surface of the groove 620 .

[0187] Fig.13 is a schematic cross-sectional view illustrating a (2-1)th operation of forming the heating wiring 610 according to the embodiment on the bottom surface of the groove 620 .

[0188] Reference Fig.13 In the (2-1) operation, a substrate SSUB of the display panel 410 may be prepared. The substrate SSUB may be a semiconductor substrate.

[0189] For example, reference layers may be sequentially formed on the substrate SSUB. Figure 5 Described are a portion of the semiconductor back plate SBP arranged on the substrate SSUB and the light emitting element back plate EBP.

[0190] For example, a pixel electrode AND (eg, AND1 , AND2 , and AND3 ) of each of the sub-pixels SP1 to SP3 may be deposited.

[0191] For example, a pixel defining layer PDL may be deposited on the pixel electrode AND to define the sub-pixels SP1 to SP3. The pixel defining layer PDL may be patterned to expose a portion of the pixel electrode AND of each of the sub-pixels SP1 to SP3. For example, during the process, the pixel electrode AND of each of the sub-pixels SP1 to SP3 may be exposed through an opening of the pixel defining layer PDL.

[0192] For example, a portion of the pixel defining layer PDL located between adjacent sub-pixels (or neighboring sub-pixels) SP1 to SP3 may be etched to form a groove 620 surrounding at least a portion of each of the sub-pixels SP1 to SP3. For example, the groove 620 may not completely surround each of the sub-pixels SP1 to SP3 and may not be formed in some areas. The area in which the groove 620 is not formed may be referred to as a "groove-free area 2010 (see Fig. 20 The groove-free region 2010 may be a region for preventing the common electrodes CAT from being disconnected from each other.

[0193] For example, a heating wiring 610 may be formed on the bottom surface of the groove 620. The heating wiring 610 may surround at least a portion of each of the sub-pixels SP1 to SP3. For example, the auxiliary common electrodes 1310 may be formed separately from each other via the groove 620 between the auxiliary common electrodes 1310. For example, a pair of auxiliary common electrodes 1310 may be arranged between adjacent sub-pixels (or adjacent sub-pixels) SP1 to SP3, and may be spaced apart from each other via the groove 620 between the pair of auxiliary common electrodes 1310. The heating wiring 610 may receive a Joule heating voltage from the outside, and may be heated to a specified temperature (e.g., about 400° C.) or higher based on the received Joule heating voltage. As will be described later, the heating wiring 610 may function to remove organic materials deposited around it.

[0194] Fig.14 is a schematic cross-sectional view showing the (2-2) operation of depositing the first organic material 711. Fig.14 , in the (2-2)th operation, a first organic material 711 of the first sub-pixel SP1 may be deposited on the entire surface of the substrate SSUB. The first organic material 711 may include a first light emitting layer that emits light of a first color in a red wavelength band. The first organic material 711 may be commonly deposited not only in the first sub-pixel SP1 for displaying the first color, but also in the second sub-pixel SP2 for displaying the second color and the third sub-pixel SP3 for displaying the third color.

[0195] Fig.15 6 is a schematic cross-sectional view showing the (2-3) operation of removing a portion of the first organic material 711 by using the heating wiring 610. Fig.15 In the (2-3) operation, a Joule heating voltage may be applied to the heating wiring 610, and the first organic material 711 disposed around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the first organic material 711 disposed around the auxiliary common electrode 1310, on the auxiliary common electrode 1310, and in the groove 620 may be removed.

[0196] Fig.16is a schematic cross-sectional view showing the (2-4) operation of depositing the first common electrode CAT1. Fig.16 In the (2-4) operation, the first common electrode CAT1 may be deposited on the entire surface of the substrate SSUB. The first common electrode CAT1 may be deposited on the first organic material 711, the pixel defining layer PDL disposed around the auxiliary common electrode 1310 and the auxiliary common electrode 1310, and in the groove 620.

[0197] Fig.17 is a schematic cross-sectional view showing the (2-5) operation of depositing the first encapsulation layer TFE1. Fig.17 In the operation (2-5), a first encapsulation layer TFE1 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the first encapsulation layer TFE1 may include a multilayer in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0198] Fig.18 is a schematic cross-sectional view showing a (2-6) operation of partially photo-patterning the first encapsulation layer TFE1, the first common electrode CAT1, and the first organic material 711. Fig.18 In the (2-6) operation, a first photo-patterning process may be performed. For example, the first photo-patterning process may be used to remove the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in a portion of the groove 620 surrounding the first sub-pixel SP1 may be left (or retained).

[0199] Fig.19 is a schematic cross-sectional view showing the operation (2-7) of depositing and patterning the second organic material 712 and the third organic material 713 in a manner similar to the operations (2-2) to (2-6). Fig.19 , the (2-7) operation may include depositing and patterning the second organic material 712 and depositing and patterning the third organic material 713 .

[0200] For example, the second organic material 712 of the second sub-pixel SP2 may be deposited on the entire surface of the substrate SSUB. The second organic material 712 may include a second light emitting layer that emits light of a second color in a green wavelength band. The second organic material 712 may be commonly deposited not only in the second sub-pixel SP2 for displaying the second color, but also in the first sub-pixel SP1 for displaying the first color and the third sub-pixel SP3 for displaying the third color.

[0201] For example, a Joule heating voltage may be applied to the heating wiring 610, and the second organic material 712 disposed around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the second organic material 712 disposed around the auxiliary common electrode 1310, on the auxiliary common electrode 1310, and in the groove 620 may be removed.

[0202] For example, the second common electrode CAT2 may be deposited on the entire surface of the substrate SSUB. The second common electrode CAT2 may be deposited on the second organic material 712, the pixel defining layer PDL disposed around the auxiliary common electrode 1310 and the auxiliary common electrode 1310, and in the groove 620.

[0203] For example, the second encapsulation layer TFE2 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the second encapsulation layer TFE2 may include a plurality of layers in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0204] For example, a second photo-patterning process may be performed. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in the first sub-pixel SP1 and the third sub-pixel SP3 may be removed using the second photo-patterning process. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in a portion of the groove 620 surrounding the second sub-pixel SP2 may be left (or retained).

[0205] For example, the third organic material 713 of the third sub-pixel SP3 may be deposited on the entire surface of the substrate SSUB. The third organic material 713 may include a third light emitting layer emitting light of a third color in a blue wavelength band. The third organic material 713 may be commonly deposited not only in the third sub-pixel SP3 for displaying the third color, but also in the first sub-pixel SP1 for displaying the first color and the second sub-pixel SP2 for displaying the second color.

[0206] For example, a Joule heating voltage may be applied to the heating wiring 610, and the third organic material 713 disposed around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the third organic material 713 disposed around the auxiliary common electrode 1310, on the auxiliary common electrode 1310, and in the groove 620 may be removed.

[0207] For example, the third common electrode CAT3 may be deposited on the entire surface of the substrate SSUB. The third common electrode CAT3 may be deposited on the third organic material 713, the pixel defining layer PDL disposed around the auxiliary common electrode 1310 and the auxiliary common electrode 1310, and in the groove 620.

[0208] For example, the third encapsulation layer TFE3 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the third encapsulation layer TFE3 may include a multilayer in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0209] For example, a third photo-patterning process may be performed. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in the first sub-pixel SP1 and the second sub-pixel SP2 may be removed using the third photo-patterning process. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in a portion of the groove 620 surrounding the third sub-pixel SP3 may be left (or retained).

[0210] Fig. 20 1 is a layout diagram showing a portion of a display panel 410 for explaining an auxiliary common electrode 1310 according to an embodiment. For example, Fig. 20 Shows Figures 13 to 19 The heating wiring 610 and the auxiliary common electrode 1310 are shown in FIG.

[0211] Reference Fig. 20 , a groove-free region 2010 in which the groove 620 is not formed may be arranged outside each of the sub-pixels SP1 to SP3. The first auxiliary common electrode 1311, the second auxiliary common electrode 1312, and the third auxiliary common electrode 1313 may be electrically connected through the groove-free region 2010. Accordingly, the common electrodes CAT respectively provided in the sub-pixels SP1 to SP3 may be electrically connected to each other without being disconnected.

[0212] Figure 21 to Figure 27 4 is a schematic cross-sectional view illustrating a method of manufacturing the display panel 410 using the heating wiring 610 extending from the bottom surface of the groove 620 onto the pixel defining layer PDL. Figure 21 to Figure 27 The display panel 410 of the display device 10 is shown, but a portion of the semiconductor backplane SBP disposed on the substrate SSUB and a light emitting element backplane EBP disposed on the semiconductor backplane SBP are omitted. For convenience of description, the description of the elements not shown will be referred to in detail. Figure 5 The description given is used instead.

[0213] Figure 21 to Figure 27 Examples and Figures 13 to 19 The embodiment of FIG. 6 is different in that the heating wiring 610 extends from the bottom surface of the groove 620 onto the pixel defining layer PDL.

[0214] Now refer to Figure 21 to Figure 27A method of manufacturing the display panel 410 is described in which an organic material is deposited and patterned for each sub-pixel by using a heating wiring 610 extending from a bottom surface of a groove 620 onto a pixel defining layer PDL.

[0215] Fig.21 is a schematic cross-sectional view illustrating a (3-1)th operation of forming the heating wiring 610 according to the embodiment on the bottom surface of the groove 620 and the pixel defining layer PDL.

[0216] Reference Fig.21 In the (3-1) operation, a substrate SSUB of the display panel 410 may be prepared. The substrate SSUB may be a semiconductor substrate.

[0217] For example, reference layers may be sequentially formed on the substrate SSUB. Figure 5 Described are a portion of the semiconductor back plate SBP arranged on the substrate SSUB and the light emitting element back plate EBP.

[0218] For example, a pixel electrode AND (eg, AND1 , AND2 , and AND3 ) of each of the sub-pixels SP1 to SP3 may be deposited.

[0219] For example, a pixel defining layer PDL may be deposited on the pixel electrode AND to define the sub-pixels SP1 to SP3. The pixel defining layer PDL may be patterned to expose a portion of the pixel electrode AND of each of the sub-pixels SP1 to SP3. For example, during the process, the pixel electrode AND of each of the sub-pixels SP1 to SP3 may be exposed through an opening of the pixel defining layer PDL.

[0220] For example, a portion of the pixel defining layer PDL located between adjacent sub-pixels (or neighboring sub-pixels) SP1 to SP3 may be etched to form a groove 620 surrounding at least a portion of each of the sub-pixels SP1 to SP3. For example, the groove 620 may not completely surround each of the sub-pixels SP1 to SP3 and may not be formed in some areas. The area in which the groove 620 is not formed may be referred to as a "groove-free area 2010". The groove-free area 2010 may be an area for preventing the common electrodes CAT from being disconnected from each other.

[0221] For example, a heating wiring 610 may be formed on the bottom surface of the groove 620. For example, the heating wiring 610 may extend from the bottom surface of the groove 620 to the pixel defining layer PDL. The heating wiring 610 may surround at least a portion of each of the sub-pixels SP1 to SP3. For example, the auxiliary common electrodes 1310 may be formed separately from each other across the groove 620 between the auxiliary common electrodes 1310. For example, a pair of auxiliary common electrodes 1310 may be arranged between adjacent sub-pixels (or adjacent sub-pixels) SP1 to SP3, and may be spaced apart from each other across the groove 620 between the pair of auxiliary common electrodes 1310. The heating wiring 610 may receive a Joule heating voltage from the outside, and may be heated to a specified temperature (e.g., about 400° C.) or higher based on the received Joule heating voltage. As will be described later, the heating wiring 610 may function to remove organic materials deposited around it.

[0222] Fig. 22 is a schematic cross-sectional view showing the (3-2) operation of depositing the first organic material 711. Fig. 22 , in the (3-2)th operation, a first organic material 711 of the first sub-pixel SP1 may be deposited on the entire surface of the substrate SSUB. The first organic material 711 may include a first light emitting layer that emits light of a first color in a red wavelength band. The first organic material 711 may be commonly deposited not only in the first sub-pixel SP1 for displaying the first color, but also in the second sub-pixel SP2 for displaying the second color and the third sub-pixel SP3 for displaying the third color.

[0223] Fig.23 6 is a schematic cross-sectional view showing the (3-3) operation of removing a portion of the first organic material 711 by using the heating wiring 610. Fig.23 In the (3-3)th operation, a Joule heating voltage may be applied to the heating wiring 610, and the first organic material 711 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the first organic material 711 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0224] Fig.24 is a schematic cross-sectional view showing the (3-4) operation of depositing the first common electrode CAT1. Fig.24 In the (3-4) operation, the first common electrode CAT1 may be deposited on the entire surface of the substrate SSUB. The first common electrode CAT1 may be deposited on the first organic material 711, the pixel defining layer PDL and the auxiliary common electrode 1310 disposed around the heating wiring 610, and in the groove 620.

[0225] Fig.25is a schematic cross-sectional view showing the (3-5) operation of depositing the first encapsulation layer TFE1. Fig.25 In the operation (3-5), a first encapsulation layer TFE1 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the first encapsulation layer TFE1 may include a multilayer in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0226] Fig.26 is a schematic cross-sectional view showing a (3-6) operation of partially photo-patterning the first encapsulation layer TFE1, the first common electrode CAT1, and the first organic material 711. Fig.26 In the (3-6) operation, a first photo-patterning process may be performed. For example, the first photo-patterning process may be used to remove the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first organic material 711, the first common electrode CAT1, and the first encapsulation layer TFE1 deposited in a portion of the groove 620 surrounding the first sub-pixel SP1 may be left (or retained).

[0227] Fig. 27 is a schematic cross-sectional view showing the operation (3-7) of depositing and patterning the second organic material 712 and the third organic material 713 in a manner similar to the operations (3-2) to (3-6). Fig. 27 , the (3-7) operation may include depositing and patterning the second organic material 712 and depositing and patterning the third organic material 713 .

[0228] For example, the second organic material 712 of the second sub-pixel SP2 may be deposited on the entire surface of the substrate SSUB. The second organic material 712 may include a second light emitting layer that emits light of a second color in a green wavelength band. The second organic material 712 may be commonly deposited not only in the second sub-pixel SP2 for displaying the second color, but also in the first sub-pixel SP1 for displaying the first color and the third sub-pixel SP3 for displaying the third color.

[0229] For example, a Joule heating voltage may be applied to the heating wiring 610, and the second organic material 712 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the second organic material 712 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0230] For example, the second common electrode CAT2 may be deposited on the entire surface of the substrate SSUB. The second common electrode CAT2 may be deposited on the second organic material 712, the pixel defining layer PDL and the auxiliary common electrode 1310 disposed around the heating wiring 610, and in the groove 620.

[0231] For example, the second encapsulation layer TFE2 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the second encapsulation layer TFE2 may include a plurality of layers in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0232] For example, a second photo-patterning process may be performed. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in the first sub-pixel SP1 and the third sub-pixel SP3 may be removed using the second photo-patterning process. For example, the second organic material 712, the second common electrode CAT2, and the second encapsulation layer TFE2 deposited in a portion of the groove 620 surrounding the second sub-pixel SP2 may be left (or retained).

[0233] For example, the third organic material 713 of the third sub-pixel SP3 may be deposited on the entire surface of the substrate SSUB. The third organic material 713 may include a third light emitting layer emitting light of a third color in a blue wavelength band. The third organic material 713 may be commonly deposited not only in the third sub-pixel SP3 for displaying the third color, but also in the first sub-pixel SP1 for displaying the first color and the second sub-pixel SP2 for displaying the second color.

[0234] For example, a Joule heating voltage may be applied to the heating wiring 610, and the third organic material 713 arranged around the heating wiring 610 may be removed using the heated heating wiring 610. For example, the third organic material 713 arranged around the heating wiring 610, on the heating wiring 610, and in the groove 620 may be removed.

[0235] For example, the third common electrode CAT3 may be deposited on the entire surface of the substrate SSUB. The third common electrode CAT3 may be deposited on the third organic material 713, the pixel defining layer PDL and the auxiliary common electrode 1310 disposed around the heating wiring 610, and in the groove 620.

[0236] For example, the third encapsulation layer TFE3 may be deposited on the entire surface of the substrate SSUB. Figure 5 Like the encapsulation layer TFE described above, the third encapsulation layer TFE3 may include a multilayer in which at least one encapsulation inorganic layer and at least one encapsulation organic layer are stacked.

[0237] For example, a third photo-patterning process may be performed. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in the first sub-pixel SP1 and the second sub-pixel SP2 may be removed using the third photo-patterning process. For example, the third organic material 713, the third common electrode CAT3, and the third encapsulation layer TFE3 deposited in a portion of the groove 620 surrounding the third sub-pixel SP3 may be left (or retained).

[0238] exist Figure 21 to Figure 27 In the embodiment of FIG. 1 , the auxiliary common electrode 1310 may also be omitted. For example, the heating wiring 610 extending onto the pixel defining layer PDL may electrically connect the first common electrode CAT1 , the second common electrode CAT2 , and the third common electrode CAT3 through the groove-free region 2010 .

[0239] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A method for manufacturing a display device, the method comprising: forming a semiconductor backplane including a substrate and a light emitting element backplane; as well as forming a light emitting element layer and a packaging layer on the light emitting element backplane, Wherein, forming the light emitting element layer and the encapsulation layer comprises: depositing a pixel electrode for each of the plurality of sub-pixels; Depositing a pixel defining layer on the pixel electrode to define the sub-pixel; Etching a portion of the pixel defining layer between adjacent sub-pixels to form a groove surrounding at least a portion of each of the sub-pixels; forming a plurality of heating wirings on the pixel defining layer so that the plurality of heating wirings are spaced apart from each other with the grooves interposed between the heating wirings; depositing a first organic material of a first sub-pixel among the plurality of sub-pixels on the entire surface of the substrate; removing a portion of the first organic material deposited around the heating wiring and the groove by heating the heating wiring; depositing a first common electrode on the entire surface of the substrate; depositing a first encapsulation layer on the entire surface of the substrate; removing the first organic material, the first common electrode, and the first encapsulation layer deposited in a second sub-pixel and a third sub-pixel among the plurality of sub-pixels by using a first photo-patterning process, and retaining the first organic material, the first common electrode, and the first encapsulation layer deposited in a portion of the groove surrounding the first sub-pixel; depositing a second organic material for the second sub-pixel on the entire surface of the substrate; removing a portion of the second organic material deposited around the heating wiring and the groove by heating the heating wiring; depositing a second common electrode on the entire surface of the substrate; depositing a second encapsulation layer on the entire surface of the substrate; removing the second organic material, the second common electrode, and the second encapsulation layer deposited in the first sub-pixel and the third sub-pixel by using a second photo-patterning process, and retaining the second organic material, the second common electrode, and the second encapsulation layer deposited in a portion of the groove surrounding the second sub-pixel; depositing a third organic material of the third sub-pixel on the entire surface of the substrate; removing a portion of the third organic material deposited around the heating wiring and the groove by heating the heating wiring; depositing a third common electrode on the entire surface of the substrate; depositing a third encapsulation layer on the entire surface of the substrate; and The third organic material, the third common electrode and the third encapsulation layer deposited in the first sub-pixel and the second sub-pixel are removed by using a third photo-patterning process, and the third organic material, the third common electrode and the third encapsulation layer deposited in a portion of the groove surrounding the third sub-pixel are retained.

2. The method of claim 1, wherein: A groove-free region in which the groove is not formed is arranged outside each of the sub-pixels, and The first common electrode, the second common electrode, and the third common electrode are electrically connected through the groove-free region.

3. The method of claim 1, wherein: The groove between the first sub-pixel and the second sub-pixel is divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region.

4. The method of claim 1, wherein: The groove between the second sub-pixel and the third sub-pixel is divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

5. The method of claim 1, wherein: The groove between the first sub-pixel and the third sub-pixel is divided into a first region adjacent to the first sub-pixel and a third region adjacent to the third sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

6. The method of claim 1, wherein: The first encapsulation layer, the second encapsulation layer and the third encapsulation layer have the same stacking structure.

7. The method of claim 1, wherein: The first organic material includes a first light emitting layer that emits light of a first color having a red wavelength band, The second organic material includes a second light emitting layer that emits light of a second color having a green wavelength band, and The third organic material includes a third light emitting layer that emits light of a third color having a blue wavelength band.

8. A display device, comprising: A pixel defining layer, wherein the pixel defining layer defines a plurality of sub-pixels; a pixel electrode of each of the sub-pixels, the pixel electrode being arranged in an opening of the pixel defining layer; a groove formed by etching a portion of the pixel defining layer and surrounding at least a portion of each of the sub-pixels; a plurality of heating wirings arranged on the pixel defining layer and spaced apart from each other via the grooves arranged between the heating wirings; a first organic material, the first organic material covering a first pixel electrode of a first sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the first pixel electrode; a first common electrode, the first common electrode covering the first organic material and a first heating wiring located around the first sub-pixel among the plurality of heating wirings; a first encapsulation layer, the first encapsulation layer covering the first common electrode and a portion of the groove located around the first sub-pixel; a second organic material, wherein the second organic material covers a second pixel electrode of a second sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the second pixel electrode; a second common electrode, the second common electrode covering the second organic material and a second heating wiring located around the second sub-pixel among the plurality of heating wirings; a second encapsulation layer, the second encapsulation layer covering the second common electrode and a portion of the groove located around the second sub-pixel; a third organic material, wherein the third organic material covers a third pixel electrode of a third sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the third pixel electrode; a third common electrode, the third common electrode covering the third organic material and a third heating wiring located around the third sub-pixel among the plurality of heating wirings; as well as A third encapsulation layer covers the third common electrode and a portion of the groove located around the third sub-pixel.

9. The display device according to claim 8, wherein: A groove-free region in which the groove is not formed is arranged outside each of the sub-pixels, and The first common electrode, the second common electrode, and the third common electrode are electrically connected through the groove-free region.

10. The display device according to claim 8, wherein: The groove between the first sub-pixel and the second sub-pixel is divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region.

11. The display device according to claim 8, wherein: The groove between the second sub-pixel and the third sub-pixel is divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

12. The display device according to claim 8, wherein: The groove between the first sub-pixel and the third sub-pixel is divided into a first region adjacent to the first sub-pixel and a third region adjacent to the third sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

13. The display device according to claim 8, wherein: The first encapsulation layer, the second encapsulation layer and the third encapsulation layer have the same stacking structure.

14. The display device according to claim 8, wherein: The first organic material includes a first light emitting layer that emits light of a first color having a red wavelength band, The second organic material includes a second light emitting layer that emits light of a second color having a green wavelength band, and The third organic material includes a third light emitting layer that emits light of a third color having a blue wavelength band.

15. The display device according to claim 8, further comprising: A display panel in which a light emitting element layer is arranged on a semiconductor backplane.

16. A display device, comprising: A pixel defining layer, wherein the pixel defining layer defines a plurality of sub-pixels; a pixel electrode of each of the sub-pixels, the pixel electrode being arranged in an opening of the pixel defining layer; a groove formed by etching a portion of the pixel defining layer and surrounding at least a portion of each of the sub-pixels; a heating wiring arranged on a bottom surface of the groove; a plurality of auxiliary common electrodes, the plurality of auxiliary common electrodes being arranged on the pixel defining layer and spaced apart from each other via the grooves arranged between the auxiliary common electrodes; a first organic material, the first organic material covering a first pixel electrode of a first sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the first pixel electrode; a first common electrode, the first common electrode covering the first organic material and a first auxiliary common electrode adjacent to the first pixel electrode among the plurality of auxiliary common electrodes; a first encapsulation layer, the first encapsulation layer covering the first common electrode and a portion of the groove located around the first sub-pixel; a second organic material, wherein the second organic material covers a second pixel electrode of a second sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the second pixel electrode; a second common electrode, the second common electrode covering the second organic material and a second auxiliary common electrode adjacent to the second pixel electrode among the plurality of auxiliary common electrodes; a second encapsulation layer, the second encapsulation layer covering the second common electrode and a portion of the groove located around the second sub-pixel; a third organic material, wherein the third organic material covers a third pixel electrode of a third sub-pixel among the plurality of sub-pixels and a portion of the pixel defining layer surrounding the third pixel electrode; a third common electrode, the third common electrode covering the third organic material and a third auxiliary common electrode adjacent to the third pixel electrode among the plurality of auxiliary common electrodes; as well as A third encapsulation layer covers the third common electrode and a portion of the groove located around the third sub-pixel.

17. The display device according to claim 16, wherein: A groove-free region in which the groove is not formed is arranged outside each of the sub-pixels, and The first auxiliary common electrode, the second auxiliary common electrode, and the third auxiliary common electrode are electrically connected through the groove-free region.

18. The display device according to claim 16, wherein: The groove between the first sub-pixel and the second sub-pixel is divided into a first area adjacent to the first sub-pixel and a second area adjacent to the second sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region.

19. The display device according to claim 16, wherein: The groove between the second sub-pixel and the third sub-pixel is divided into a second area adjacent to the second sub-pixel and a third area adjacent to the third sub-pixel, The second common electrode and the second encapsulation layer covering the second common electrode are arranged in the second region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

20. The display device according to claim 16, wherein: The groove between the first sub-pixel and the third sub-pixel is divided into a first region adjacent to the first sub-pixel and a third region adjacent to the third sub-pixel, The first common electrode and the first encapsulation layer covering the first common electrode are arranged in the first region, and The third common electrode and the third encapsulation layer covering the third common electrode are arranged in the third region.

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