Display device and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes: a substrate; an active pattern disposed on the substrate; an insulating layer disposed on the active pattern and defining an opening exposing a portion of the active pattern; a first conductive layer including a first conductive pattern disposed on the insulating layer and in contact with a side surface of the insulating layer defining the opening, and a second conductive pattern disposed in the opening, on the active pattern and disconnected from the first conductive pattern; an organic layer pattern disposed in the opening, in contact with the first conductive pattern and the second conductive pattern, and exposing a portion of the second conductive pattern; and a second conductive layer covering a side surface of the first conductive pattern and the organic layer pattern and in contact with the second conductive pattern.

Description

Technical Field

[0001] The present disclosure generally relates to a display device and more particularly to a display device and a method for manufacturing the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. For example, the use of display devices such as liquid crystal display ("LCD") devices, organic light emitting display ("OLED") devices, plasma display panel ("PDP") devices, or quantum dot display devices is increasing.

[0003] The display device may include a thin film transistor ("TFT"), a capacitor, etc. as a driving circuit. The thin film transistor may include an active pattern, a gate electrode electrically insulated from the active pattern, and a source electrode and a drain electrode electrically connected to the active pattern through an opening. Recently, the integration of thin film transistors has become increasingly higher to improve the resolution of the display device. Summary of the invention

[0004] The embodiment provides a display device having improved contact between active patterns and electrodes.

[0005] The embodiment provides a method of manufacturing the display device.

[0006] A display device according to an embodiment of the present disclosure includes: a substrate; an active pattern disposed on the substrate; an insulating layer disposed on the active pattern and defining an opening that exposes a portion of the active pattern; a first conductive layer, including a first conductive pattern and a second conductive pattern, the first conductive pattern being disposed on the insulating layer and contacting a side surface of the insulating layer that defines the opening, the second conductive pattern being disposed in the opening, on the active pattern and disconnected from the first conductive pattern; an organic layer pattern being disposed in the opening, contacting the first conductive pattern and the second conductive pattern, and exposing a portion of the second conductive pattern; and a second conductive layer covering the side surface of the first conductive pattern and the organic layer pattern and contacting the second conductive pattern.

[0007] In an embodiment, an edge of an upper surface of the first conductive pattern may protrude more than an edge of a lower surface of the first conductive pattern in a direction toward a center of the opening.The first conductive pattern and the second conductive pattern may define an undercut structure in the opening.

[0008] In embodiments, the organic layer pattern may be disposed to fill a space defined by the undercut structure.

[0009] In an embodiment, the organic layer pattern may connect the first conductive pattern and the second conductive pattern that are disconnected from each other.

[0010] In an embodiment, the second conductive layer may extend continuously in the opening.

[0011] In an embodiment, the second conductive layer may cover an upper surface of the portion of the second conductive pattern exposed from the organic layer pattern.

[0012] In embodiments, the organic layer pattern may include a positive photosensitive organic material.

[0013] In embodiments, the organic layer pattern may include a non-photosensitive organic material.

[0014] In an embodiment, the active pattern may include a first active pattern disposed on the substrate and a second active pattern disposed on the first active pattern. The opening may include a first opening exposing a portion of the first active pattern and a second opening exposing a portion of the second active pattern. The organic layer pattern may be disposed in the first opening.

[0015] In embodiments, an organic layer pattern may be further disposed in the second opening.

[0016] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: forming an active pattern on a substrate, and forming an insulating layer on the active pattern; forming an opening in the insulating layer to expose a portion of the active pattern; forming a first conductive layer, the first conductive layer including a first conductive pattern and a second conductive pattern, the first conductive pattern being arranged on the insulating layer and contacting a side surface of the insulating layer defining the opening, the second conductive pattern being arranged in the opening, on the active pattern and disconnected from the first conductive pattern; forming a preliminary organic layer on the first conductive layer; forming an organic layer pattern by patterning the preliminary organic layer, the organic layer pattern contacting the first conductive pattern and the second conductive pattern in the opening and exposing a portion of the second conductive pattern; and forming a second conductive layer, the second conductive layer covering the side surface of the first conductive pattern and the organic layer pattern and contacting the second conductive pattern.

[0017] In an embodiment, an edge of an upper surface of the first conductive pattern may protrude more than an edge of a lower surface of the first conductive pattern in a direction toward a center of the opening.The first conductive pattern and the second conductive pattern may define an undercut structure in the opening.

[0018] In embodiments, the organic layer pattern may be formed to fill a space defined by the undercut structure.

[0019] In embodiments, the organic layer pattern may be formed by exposing the preliminary organic layer to light using the first conductive pattern as a mask.

[0020] In embodiments, the organic layer pattern may be formed by etching the preliminary organic layer using the first conductive pattern as a mask.

[0021] In an embodiment, each of the first conductive layer and the second conductive layer may be formed by a sputtering process.

[0022] In an embodiment, the second conductive layer may be formed to continuously extend in the opening.

[0023] In an embodiment, the second conductive layer may be formed to cover an upper surface of the portion of the second conductive pattern exposed from the organic layer pattern.

[0024] In an embodiment, the forming of the active pattern on the substrate may include: forming a first active pattern on the substrate, and forming a second active pattern on the first active pattern. The forming of the opening in the insulating layer may include: forming a first opening to expose a portion of the first active pattern, and forming a second opening to expose a portion of the second active pattern. The organic layer pattern may be formed in the first opening.

[0025] In embodiments, an organic layer pattern may be further formed in the second opening.

[0026] A display device according to an embodiment of the present disclosure may include: an insulating layer, which is arranged on an active pattern and defines an opening that exposes a portion of the active pattern; a first conductive layer, including a first conductive pattern and a second conductive pattern, the first conductive pattern is in contact with a side surface of the insulating layer that defines the opening, and the second conductive pattern is arranged in the opening, on the active pattern and disconnected from the first conductive pattern; an organic layer pattern, which is arranged in the opening, in contact with the first conductive pattern and the second conductive pattern, and exposes a portion of the second conductive pattern; and a second conductive layer, which is in contact with the second conductive pattern.

[0027] The organic layer pattern can fill the disconnected space between the first conductive pattern and the second conductive pattern in the opening. Accordingly, the second conductive layer can extend continuously in the opening without disconnection. The second conductive layer can be electrically connected to the active pattern through the second conductive pattern. That is, even if disconnection occurs in the first conductive layer, the second conductive layer can be electrically connected to the active pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0031] Figure 3 yes Figure 2 An enlarged cross-sectional view of area 'A'.

[0032] Figure 4 is a plan view illustrating a display device according to another embodiment of the present disclosure.

[0033] Figure 5 It is along Figure 4 A cross-sectional view taken along line II-II'.

[0034] Figure 6 yes Figure 5 An enlarged cross-sectional view of region 'B'.

[0035] Figure 7 is a flowchart of a method of manufacturing a display device according to an embodiment of the present disclosure.

[0036] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 It is a graphic Figure 7 A view of a method of manufacturing a display device. DETAILED DESCRIPTION

[0037] The terms used herein are only used for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, "one", "the (described)" and "at least one" do not represent the limitation of quantity, but are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. It will be further understood that when used in this specification, the term "includes" and / or its variations or "comprising" and / or its variations indicate the presence of the described features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0038] It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or directly connected to the other element, or intervening elements may exist therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0039] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings herein.

[0040] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0041] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure. As used herein, a “plan view” is a view in the thickness direction (ie, the third direction DR3 ) of the display device DD.

[0042] In the present specification, a plane may be defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. A direction orthogonal to the plane (i.e., a thickness direction of the display device DD) may be a third direction DR3. In other words, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0043] refer to Figure 1 , the display device DD according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA.

[0044] The display area DA may be defined as an area that displays an image by generating light or by adjusting the transmittance of light provided from an external light source. A plurality of pixels PX may be disposed in the display area DA. The pixels PX may generate light according to a driving signal. The pixels PX may be repeatedly disposed along a first direction DR1 and a second direction DR2.

[0045] Data lines, gate lines, and light emitting control lines connected to the pixels PX may be further provided in the display area DA. The data lines may provide data voltages to the pixels PX. The gate lines may provide gate signals to the pixels PX. The light emitting control lines may provide light emitting control signals to the pixels PX.

[0046] The non-display area NDA may be defined as an area where no image is displayed. The non-display area NDA may be located around the display area DA. For example, the non-display area NDA may surround the entire display area DA.

[0047] Figure 2 It is along Figure 1A cross-sectional view taken along line II'. Figure 3 yes Figure 2 An enlarged cross-sectional view of area 'A'.

[0048] refer to Figure 2 and Figure 3 According to an embodiment of the present disclosure, the display device DD may include a substrate SUB, a buffer layer BUF, a first transistor TR1, a second gate electrode GE2, a second transistor TR2, a first insulating layer group ILG1, a first via insulating layer VIA1, a second via insulating layer VIA2, a connecting electrode CNE, a pixel defining layer PDL, a light emitting element LD and an encapsulation layer TFE.

[0049] The first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first source-drain structure SDG1, and a second source-drain structure SDG2. The second transistor TR2 may include a second active pattern ACT2, a third gate electrode GE3, a source electrode SE, and a drain electrode DE. The first insulating layer group ILG1 may include a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2. The light emitting element LD may include a pixel electrode PE, a light emitting layer EML, and a common electrode CTE.

[0050] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be formed of a transparent resin substrate or include a transparent resin substrate. A polyimide substrate may be an example of a transparent resin substrate. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like. Alternatively, the substrate SUB may include a quartz substrate (e.g., a synthetic quartz substrate or a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, a non-alkali glass substrate, and the like. These may be used alone or in combination with each other.

[0051] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB to the upper structure (e.g., the first transistor TR1, the second transistor TR2, etc.). In addition, the buffer layer BUF may control the heat transfer rate during the crystallization process for forming the active layer ACT, so that a substantially uniform active layer ACT may be obtained. In addition, when the surface of the substrate SUB is uneven, the buffer layer BUF may be used to improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the buffer layer BUF may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y) etc. These may be used alone or in combination with each other. Alternatively, the buffer layer BUF may be omitted.

[0052] The first active pattern ACT1 may be disposed on the buffer layer BUF. The first active pattern ACT1 may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. In an embodiment, the first active pattern ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The first active pattern ACT1 may include a first source region, a first drain region, and a first channel region between the first source region and the first drain region.

[0053] The first gate insulating layer GI1 may be disposed on the first active pattern ACT1 and the buffer layer BUF. The first gate insulating layer GI1 may cover the first active pattern ACT1 on the buffer layer BUF, and may be disposed along the contour of the first active pattern ACT1 with a substantially uniform thickness. Alternatively, the first gate insulating layer GI1 may sufficiently cover the first active pattern ACT1 on the buffer layer BUF, and may have a substantially flat upper surface without generating a step difference around the first active pattern ACT1. The first gate insulating layer GI1 may include an inorganic insulating material. Examples of the inorganic insulating material that may be used as the first gate insulating layer GI1 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The first gate insulating layer GI1 may electrically insulate the first active pattern ACT1 from the first gate electrode GE1.

[0054] The first gate electrode GE1 may be disposed on the first gate insulating layer GI1. The first gate electrode GE1 may overlap the first channel region of the first active pattern ACT1. The first gate electrode GE1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that may be used as the first gate electrode GE1 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN x ), tungsten (W), tungsten nitride (WN x ), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN x ), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide ("ITO"), indium zinc oxide ("IZO"), etc. These may be used alone or in combination with each other.

[0055] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may cover the first gate electrode GE1 on the first gate insulating layer GI1, and may be disposed along the contour of the first gate electrode GE1 with a substantially uniform thickness. Alternatively, the second gate insulating layer GI2 may fully cover the first gate electrode GE1 on the first gate insulating layer GI1, and may have a substantially flat upper surface without generating a step difference around the first gate electrode GE1. The second gate insulating layer GI2 may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the second gate insulating layer GI2 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The second gate insulating layer GI2 may electrically insulate the first gate electrode GE1 from the second gate electrode GE2.

[0056] The second gate electrode GE2 may be disposed on the second gate insulating layer GI2. The second gate electrode GE2 may overlap the first gate electrode GE1 in a plan view. The second gate electrode GE2 may form a capacitor (e.g., a storage capacitor) together with the first gate electrode GE1. For example, the second gate electrode GE2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0057] The first interlayer insulating layer ILD1 may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may cover the second gate electrode GE2 on the second gate insulating layer GI2, and may be disposed along the contour of the second gate electrode GE2 with a uniform thickness. Alternatively, the first interlayer insulating layer ILD1 may fully cover the second gate electrode GE2 on the second gate insulating layer GI2, and may have a substantially flat upper surface without generating a step difference around the second gate electrode GE2. The first interlayer insulating layer ILD1 may include an inorganic insulating material. Examples of the inorganic insulating material that may be used as the first interlayer insulating layer ILD1 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0058] The second active pattern ACT2 may be disposed on the first interlayer insulating layer ILD1. The second active pattern ACT2 may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. In an embodiment, the second active pattern ACT2 may include an oxide semiconductor. The oxide semiconductor may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z ) etc. For example, the oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide ("IGO"), indium zinc oxide ("IZO"), indium tin oxide ("ITO"), indium zinc tin oxide ("IZTO"), indium gallium zinc oxide ("IGZO"), etc. These can be used alone or in combination with each other. The second active pattern ACT2 may include a second source region, a second drain region, and a second channel region located between the second source region and the second drain region.

[0059] The third gate insulating layer GI3 may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may cover the second active pattern ACT2 on the first interlayer insulating layer ILD1, and may be disposed along the contour of the second active pattern ACT2 with a uniform thickness. Alternatively, the third gate insulating layer GI3 may fully cover the second active pattern ACT2 on the first interlayer insulating layer ILD1, and may have a substantially flat upper surface without generating a step difference around the second active pattern ACT2. The third gate insulating layer GI3 may include an inorganic insulating material. Examples of the inorganic insulating material that may be used as the third gate insulating layer GI3 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The third gate insulating layer GI3 may electrically insulate the second active pattern ACT2 from the third gate electrode GE3.

[0060] The third gate electrode GE3 may be disposed on the third gate insulating layer GI3. The third gate electrode GE3 may overlap the second channel region of the second active pattern ACT2. For example, the third gate electrode GE3 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0061] The second interlayer insulating layer ILD2 may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may fully cover the third gate electrode GE3 on the third gate insulating layer GI3, and may have a substantially flat upper surface without generating a step difference around the third gate electrode GE3. Alternatively, the second interlayer insulating layer ILD2 may cover the third gate electrode GE3 on the third gate insulating layer GI3, and may be disposed along the contour of the third gate electrode GE3 with a uniform thickness. The second interlayer insulating layer ILD2 may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the second interlayer insulating layer ILD2 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The second interlayer insulating layer ILD2 may electrically insulate the third gate electrode GE3 from the source electrode SE. In addition, the second interlayer insulating layer ILD2 may electrically insulate the third gate electrode GE3 from the drain electrode DE.

[0062] The first opening CNT1 may be defined in the first insulating layer group ILG1. For example, the first opening CNT1 may penetrate at least a portion of each of the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2. The first opening CNT1 may expose a portion of the first active pattern ACT1. The second opening CNT2 may be defined in the third gate insulating layer GI3 and the second interlayer insulating layer ILD2. For example, the second opening CNT2 may penetrate at least a portion of each of the second interlayer insulating layer ILD2 and the third gate insulating layer GI3. The second opening CNT2 may expose a portion of the second active pattern ACT2.

[0063] The first source-drain structure SDG1 and the second source-drain structure SDG2 may be disposed on the second interlayer insulating layer ILD2. The first source-drain structure SDG1 may be connected to the first source region of the first active pattern ACT1 through the first opening CNT1 penetrating the first insulating layer group ILG1. The second source-drain structure SDG2 may be connected to the first drain region of the first active pattern ACT1 through the first opening CNT1 penetrating the first insulating layer group ILG1.

[0064] like Figure 3 As illustrated in FIG. 1 , the first source-drain structure SDG1 may include a first conductive layer SD1, an organic layer pattern OGL, and a second conductive layer SD2. The second source-drain structure SDG2 may have substantially the same structure as the first source-drain structure SDG1. Therefore, hereinafter, the description will focus on the first source-drain structure SDG1, and the description of the first source-drain structure SDG1 may be similarly applied to the second source-drain structure SDG2.

[0065] The first conductive layer SD1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first conductive layer SD1 may be formed by a sputtering process.

[0066] In order to improve the resolution of the display device DD, the diameter of the first opening CNT1 may be designed to be relatively small. Here, the diameter of the first opening CNT1 may be defined as the maximum length of the first opening CNT1 in the first direction DR1 or the maximum length of the first opening CNT1 in the second direction DR2. For example, the first diameter D1 of the first opening CNT1 may be about 1.7 microns to about 2.0 microns. Since the first diameter D1 of the first opening CNT1 is designed to be relatively small, the aspect ratio of the first opening CNT1 may be relatively large. Here, the aspect ratio of the first opening CNT1 may be defined as the ratio of the height of the first opening CNT1 to the diameter of the first opening CNT1. The height of the first opening CNT1 may be defined as the length of the first opening CNT1 in the third direction DR3.

[0067] Since the aspect ratio of the first opening CNT1 becomes relatively large, in the process of forming the first conductive layer SD1 by the sputtering process, the first conductive layer SD1 may be disconnected into the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. That is, the first conductive layer SD1 may include the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 disconnected from each other. Accordingly, the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 may define an undercut structure UC in the first opening CNT1. The undercut structure UC may be defined as a disconnected structure located between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in a region overlapping the first opening CNT1 in a plan view.

[0068] The first conductive pattern SD1-P1 may be disposed on the first insulating layer group ILG1. Specifically, the first conductive pattern SD1-P1 may be disposed on the second interlayer insulating layer ILD2. The first conductive pattern SD1-P1 may contact a side surface of the first insulating layer group ILG1 defining the first opening CNT1.

[0069] In the present specification, the upper surface of the first conductive pattern SD1-P1 may be defined as a surface located at the highest level from the upper surface of the substrate SUB among the surfaces of the first conductive pattern SD1-P1. The lower surface of the first conductive pattern SD1-P1 may be defined as a surface located in the first opening CNT1 at the lowest level from the upper surface of the substrate SUB among the surfaces of the first conductive pattern SD1-P1. The side surface of the first conductive pattern SD1-P1 may be defined as a surface connecting a first edge EG1 of the upper surface of the first conductive pattern SD1-P1 and a second edge EG2 of the lower surface of the first conductive pattern SD1-P1. For example, as Figure 3 As illustrated in FIG. 1 , the side surface of the first conductive pattern SD1-P1 may include a step structure in the cross section. However, the present disclosure is not limited thereto. In another example, the side surface of the first conductive pattern SD1-P1 may have a slanted line shape in the cross section.

[0070] In an embodiment, a first edge EG1 of an upper surface of the first conductive pattern SD1-P1 may protrude more than a second edge EG2 of a lower surface of the first conductive pattern SD1-P1 in a direction toward the center of the first opening CNT1. That is, in a process of forming the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 by a sputtering process, the first edge EG1 may protrude more than the second edge EG2 in a direction toward the center of the first opening CNT1.

[0071] In the first opening CNT1 (or, in a region overlapping the first opening CNT1 in a plan view), a length of an upper surface of the first conductive pattern SD1-P1 in the first direction DR1 may be greater than a length of a lower surface of the first conductive pattern SD1-P1 in the first direction DR1.

[0072] The second conductive pattern SD1-P2 may be disposed in the first opening CNT1 and on the first active pattern ACT1. The height of the upper surface of the second conductive pattern SD1-P2 at the center of the first opening CNT1 may be greater than the height of the upper surface of the second conductive pattern SD1-P2 at the edge of the first opening CNT1. Here, the height of the upper surface of the second conductive pattern SD1-P2 may be defined as a straight-line distance in the third direction DR3 from the upper surface of the first active pattern ACT1 to the upper surface of the second conductive pattern SD1-P2. In the process of forming the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 by a sputtering process, the first edge EG1 may protrude more than the second edge EG2 in a direction toward the center of the first opening CNT1. Accordingly, in a region overlapping with the upper surface of the first conductive pattern SD1-P1 in the first opening CNT1 (or, a region adjacent to the edge of the first opening CNT1) in a plan view, the second conductive pattern SD1-P2 may be deposited in a relatively small amount. As a result, a height of the upper surface of the second conductive pattern SD1 - P2 at the center of the first opening CNT1 may be greater than a height of the upper surface of the second conductive pattern SD1 - P2 at the edge of the first opening CNT1 .

[0073] The organic layer pattern OGL may be disposed in the first opening CNT1 and may contact the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. In an embodiment, the organic layer pattern OGL may fill the space defined by the undercut structure UC. In other words, the organic layer pattern OGL may fill the disconnected space between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in the region overlapping with the upper surface of the first conductive pattern SD1-P1 in the first opening CNT1 in a plan view. Accordingly, the organic layer pattern OGL may connect the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 that are disconnected from each other. Since the organic layer pattern OGL fills the space defined by the undercut structure UC, the organic layer pattern OGL may cover the stepped structure of the side surface of the first conductive pattern SD1-P1.

[0074] The organic layer pattern OGL may expose a portion of the second conductive pattern SD1-P2. Specifically, the organic layer pattern OGL may be disposed to overlap an upper surface of the first conductive pattern SD1-P1 in the first opening CNT1 in a plan view and may expose a portion of an upper surface of the second conductive pattern SD1-P2.

[0075] In an embodiment, the organic layer pattern OGL may include a positive photosensitive organic material. For example, the organic layer pattern OGL may include a photoresist. However, the present disclosure is not limited thereto.

[0076] In another embodiment, the organic layer pattern OGL may include a non-photosensitive organic material. For example, the organic layer pattern OGL may include polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0077] The second conductive layer SD2 may cover the side surface of the first conductive pattern SD1-P1 and the organic layer pattern OGL, and may contact the second conductive pattern SD1-P2. Specifically, the second conductive layer SD2 may cover the upper surface of the second conductive pattern SD1-P2 exposed from the organic layer pattern OGL. Accordingly, the second conductive layer SD2 may be electrically connected to the second conductive pattern SD1-P2. The second conductive layer SD2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the second conductive layer SD2 may be formed by a sputtering process.

[0078] In an embodiment, the second conductive layer SD2 may extend continuously in the first opening CNT1. That is, since the organic layer pattern OGL fills the space defined by the undercut structure UC, the second conductive layer SD2 may extend continuously in the first opening CNT1 without being disconnected.

[0079] When the first conductive layer SD1 does not continuously extend in the first opening CNT1 and is disconnected into the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2, the first conductive pattern SD1-P1 of the first conductive layer SD1 may not be electrically connected to the first source region of the first active pattern ACT1. In other words, since the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 are not electrically connected to each other, the first conductive pattern SD1-P1 of the first conductive layer SD1 may not be electrically connected to the first source region of the first active pattern ACT1.

[0080] In order to compensate for such connection failure, the display device DD according to an embodiment of the present disclosure may include an organic layer pattern OGL filling a disconnected space between the first conductive pattern SD1 - P1 and the second conductive pattern SD1 - P2 in the first opening CNT1 .

[0081] Since the organic layer pattern OGL fills the disconnected space between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in the first opening CNT1, the second conductive layer SD2 can extend continuously in the first opening CNT1 without disconnection. Accordingly, the second conductive layer SD2 can be electrically connected to the first source region of the first active pattern ACT1 through the second conductive pattern SD1-P2. That is, even if disconnection occurs in the first conductive layer SD1, the second conductive layer SD2 can be electrically connected to the first source region of the first active pattern ACT1.

[0082] like Figure 2 As illustrated in FIG. 1 , the source electrode SE and the drain electrode DE may be disposed on the second interlayer insulating layer ILD2. The source electrode SE may be connected to the second source region of the second active pattern ACT2 by penetrating the second opening CNT2 of the third gate insulating layer GI3 and the second interlayer insulating layer ILD2. The drain electrode DE may be connected to the second drain region of the second active pattern ACT2 by penetrating the second opening CNT2 of the third gate insulating layer GI3 and the second interlayer insulating layer ILD2. Each of the source electrode SE and the drain electrode DE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0083] In an embodiment, each of the source electrode SE and the drain electrode DE may be formed using the same material as the first conductive layer SD1 through the same process.

[0084] In another embodiment, each of the source electrode SE and the drain electrode DE may include a first layer formed using the same material as the first conductive layer SD1 and a second layer disposed on the first layer and formed using the same material as the second conductive layer SD2 .

[0085] In an embodiment, the organic layer pattern OGL may be disposed in the first opening CNT1 and may not be disposed in the second opening CNT2. Since the first active pattern ACT1 is disposed below the second active pattern ACT2, the first height H1 of the first opening CNT1 may be greater than the second height H1 of the second opening CNT2 (eg, Figure 6 In other words, the aspect ratio of the first opening CNT1 may be greater than the aspect ratio of the second opening CNT2. Therefore, the organic layer pattern OGL may be disposed in the first opening CNT1 where the probability of disconnection failure of the first conductive layer SD1 is relatively high. In addition, the organic layer pattern OGL may not be disposed in the second opening CNT2 where the probability of disconnection failure of the first conductive layer SD1 is relatively low. However, the present disclosure is not limited thereto, and in another embodiment, the organic layer pattern OGL may also be disposed in the second opening CNT2. This will be referred to below. Figure 6 Describe in more detail.

[0086] Accordingly, a first transistor TR1 including a first active pattern ACT1, a first gate electrode GE1, a first source-drain structure SDG1, and a second source-drain structure SDG2 may be formed. In addition, a second transistor TR2 including a second active pattern ACT2, a third gate electrode GE3, a source electrode SE, and a drain electrode DE may be formed.

[0087] The first via insulating layer VIA1 may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may be disposed to have a relatively thick thickness to fully cover the source electrode SE, the drain electrode DE, the first source-drain structure SDG1 and the second source-drain structure SDG2. The third opening may be defined in the first via insulating layer VIA1. For example, the third opening may penetrate at least a portion of the first via insulating layer VIA1. The third opening may expose a portion of the second source-drain structure SDG2. Specifically, the third opening may expose a portion of the second conductive layer SD2 of the second source-drain structure SDG2. The first via insulating layer VIA1 may include an organic insulating material. Examples of organic insulating materials that may be used as the first via insulating layer VIA1 may include photoresists, polyimide resins, polyamide resins, siloxane resins, acrylic resins, epoxy resins, and the like. These may be used alone or in combination with one another.

[0088] The connection electrode CNE may be disposed on the first via insulating layer VIA1. The connection electrode CNE may be connected to the second conductive layer SD2 of the second source-drain structure SDG2 through a third opening penetrating the first via insulating layer VIA1. Accordingly, the connection electrode CNE may electrically connect the first transistor TR1 to the light emitting element LD. For example, the connection electrode CNE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0089] The second via insulating layer VIA2 may be disposed on the first via insulating layer VIA1. The second via insulating layer VIA2 may be disposed to have a relatively thick thickness to fully cover the connection electrode CNE. A fourth opening may be defined in the second via insulating layer VIA2. The fourth opening may penetrate at least a portion of the second via insulating layer VIA2. The fourth opening may expose a portion of the connection electrode CNE. The second via insulating layer VIA2 may include an organic insulating material. Examples of organic insulating materials that may be used as the second via insulating layer VIA2 may include photoresists, polyimide resins, polyamide resins, siloxane resins, acrylic resins, epoxy resins, and the like. These may be used alone or in combination with each other.

[0090] The pixel electrode PE may be disposed on the second via insulating layer VIA2. The pixel electrode PE may be connected to the connection electrode CNE through a fourth opening penetrating the second via insulating layer VIA2. For example, the pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode PE may be used as an anode electrode.

[0091] The pixel defining layer PDL may be disposed on the second via insulating layer VIA2. The pixel defining layer PDL may cover the edge of the pixel electrode PE and expose a portion of the pixel electrode PE. The pixel defining layer PDL may include an organic insulating material. Examples of organic insulating materials that may be used as the pixel defining layer PDL may include photoresists, polyimide resins, polyamide resins, siloxane resins, acrylic resins, epoxy resins, and the like. These may be used alone or in combination with each other.

[0092] The light emitting layer EML may be disposed on the pixel electrode PE. The light emitting layer EML may include an organic material that emits light of a preset color. For example, the light emitting layer EML may include an organic light emitting material including a fluorescent material or a phosphorescent material that emits red, green, blue, or white light.

[0093] The common electrode CTE may be disposed on the pixel defining layer PDL and the light emitting layer EML. The common electrode CTE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CTE may be used as a cathode electrode.

[0094] Accordingly, a light emitting element LD including the pixel electrode PE, the light emitting layer EML, and the common electrode CTE may be formed.

[0095] The encapsulation layer TFE may be disposed on the common electrode CTE. The encapsulation layer TFE may prevent impurities, moisture, etc. from penetrating into the light emitting element LD from the outside. The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. For example, the organic encapsulation layer may include a cured polymer such as polyacrylate.

[0096] Although the display device DD of the present disclosure is described by being limited to an organic light emitting display ("OLED") device, the configuration of the present disclosure is not limited thereto. In other embodiments, the display device DD may include a liquid crystal display ("LCD") device, a field emission display ("FED") device, a plasma display panel ("PDP") device, an electrophoretic image display ("EPD") device, an inorganic light emitting display ("ILED") device, or a quantum dot display device.

[0097] Figure 4 is a plan view illustrating a display device according to another embodiment of the present disclosure. Figure 5 It is along Figure 4 A cross-sectional view taken along line II-II'. Figure 6 yes Figure 5 An enlarged cross-sectional view of region 'B'.

[0098] refer to Figure 4 , Figure 5 and Figure 6 According to another embodiment of the present disclosure, a display device DD2 may include a substrate SUB, a buffer layer BUF, a first transistor TR1, a second gate electrode GE2, a second transistor TR2, a first insulating layer group ILG1, a second insulating layer group ILG2, a first via insulating layer VIA1, a second via insulating layer VIA2, a connecting electrode CNE, a pixel defining layer PDL, a light emitting element LD and an encapsulation layer TFE.

[0099] The first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first source-drain structure SDG1, and a second source-drain structure SDG2. The second transistor TR2 may include a second active pattern ACT2, a third gate electrode GE3, a third source-drain structure SDG3, and a fourth source-drain structure SDG4. The first insulating layer group ILG1 may include a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2. The second insulating layer group ILG2 may include a third gate insulating layer GI3 and a second interlayer insulating layer ILD2. The light emitting element LD may include a pixel electrode PE, a light emitting layer EML, and a common electrode CTE.

[0100] In addition to the display device DD2 including the third source-drain structure SDG3 and the fourth source-drain structure SDG4 connected to the second active pattern ACT2, the display device DD2 may be connected to the reference pattern ACT2. Figure 1 , Figure 2 and Figure 3 The display device DD described is substantially the same as that described in the reference. Figure 1 , Figure 2 and Figure 3 The description of the display device DD provided coincides with the description.

[0101] The second active pattern ACT2 may be disposed on the first interlayer insulating layer ILD1. In an embodiment, the second active pattern ACT2 may include an oxide semiconductor. The second active pattern ACT2 may include a second source region, a second drain region, and a second channel region between the second source region and the second drain region.

[0102] The third gate insulating layer GI3 may be disposed on the first interlayer insulating layer ILD1, and the third gate electrode GE3 may be disposed on the third gate insulating layer GI3. The third gate electrode GE3 may overlap the second channel region of the second active pattern ACT2. The second interlayer insulating layer ILD2 may be disposed on the third gate insulating layer GI3.

[0103] The first opening CNT1 may be defined in the first insulating layer group ILG1. For example, the first opening CNT1 may penetrate at least a portion of each of the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2. The first opening CNT1 may expose a portion of the first active pattern ACT1.

[0104] The second opening CNT2 may be defined in the second insulating layer group ILG2. For example, the second opening CNT2 may penetrate at least a portion of each of the third gate insulating layer GI3 and the second interlayer insulating layer ILD2. The second opening CNT2 may expose a portion of the second active pattern ACT2.

[0105] The first source-drain structure SDG1 and the second source-drain structure SDG2 may be disposed on the second interlayer insulating layer ILD2. The first source-drain structure SDG1 may be connected to the first source region of the first active pattern ACT1 through the first opening CNT1 penetrating the first insulating layer group ILG1. The second source-drain structure SDG2 may be connected to the first drain region of the first active pattern ACT1 through the first opening CNT1 penetrating the first insulating layer group ILG1.

[0106] The third source-drain structure SDG3 and the fourth source-drain structure SDG4 may be disposed on the second interlayer insulating layer ILD2. The third source-drain structure SDG3 may be connected to the second source region of the second active pattern ACT2 through the second opening CNT2 penetrating the second insulating layer group ILG2. The fourth source-drain structure SDG4 may be connected to the second drain region of the second active pattern ACT2 through the second opening CNT2 penetrating the second insulating layer group ILG2.

[0107] like Figure 6As illustrated in FIG. 1 , the third source-drain structure SDG3 may include a first conductive layer SD1, an organic layer pattern OGL, and a second conductive layer SD2. The fourth source-drain structure SDG4 may have substantially the same structure as the third source-drain structure SDG3. Therefore, hereinafter, the description will focus on the third source-drain structure SDG3, and the description of the third source-drain structure SDG3 may be similarly applied to the fourth source-drain structure SDG4.

[0108] In an embodiment, the first conductive layer SD1 may be formed by a sputtering process. In the process of forming the first conductive layer SD1 by the sputtering process, the first conductive layer SD1 may be disconnected into the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. That is, the first conductive layer SD1 may include the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 disconnected from each other. Accordingly, the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 may define an undercut structure UC in the second opening CNT2. The undercut structure UC may be defined as a disconnected structure located between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in a region overlapping with the second opening CNT2 in a plan view.

[0109] The first conductive pattern SD1-P1 may be disposed on the second insulating layer group ILG2. Specifically, the first conductive pattern SD1-P1 may be disposed on the second interlayer insulating layer ILD2. The first conductive pattern SD1-P1 may contact a side surface of the second insulating layer group ILG2 defining the second opening CNT2.

[0110] The upper surface of the first conductive pattern SD1-P1 may be defined as a surface located at the highest level from the upper surface of the substrate SUB among the surfaces of the first conductive pattern SD1-P1. The lower surface of the first conductive pattern SD1-P1 may be defined as a surface located in the second opening CNT2 at the lowest level from the upper surface of the substrate SUB among the surfaces of the first conductive pattern SD1-P1. The side surface of the first conductive pattern SD1-P1 may be defined as a surface connecting a first edge EG1 of the upper surface of the first conductive pattern SD1-P1 and a second edge EG2 of the lower surface of the first conductive pattern SD1-P1. For example, Figure 6 As illustrated in FIG. 1 , a side surface of the first conductive pattern SD1 - P1 may include a step structure in a cross-section. However, the present disclosure is not limited thereto.

[0111] In an embodiment, a first edge EG1 of an upper surface of the first conductive pattern SD1-P1 may protrude more than a second edge EG2 of a lower surface of the first conductive pattern SD1-P1 in a direction toward the center of the second opening CNT2. That is, in a process of forming the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 by a sputtering process, the first edge EG1 may protrude more than the second edge EG2 in a direction toward the center of the second opening CNT2.

[0112] The second conductive pattern SD1-P2 may be disposed in the second opening CNT2 and on the second active pattern ACT2. The height of the upper surface of the second conductive pattern SD1-P2 at the center of the second opening CNT2 may be greater than the height of the upper surface of the second conductive pattern SD1-P2 at the edge of the second opening CNT2. In the process of forming the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 by a sputtering process, the first edge EG1 may protrude more than the second edge EG2 in a direction toward the center of the second opening CNT2. Accordingly, in a region overlapping with the upper surface of the first conductive pattern SD1-P1 in the second opening CNT2 (or, in a region adjacent to the edge of the second opening CNT2) in a plan view, a relatively small amount of the second conductive pattern SD1-P2 may be deposited.

[0113] In an embodiment, the second diameter D2 of the second opening CNT2 may be equal to the first diameter D2 of the first opening CNT1 (eg, Figure 3 Here, the second diameter D2 of the second opening CNT2 may be defined as the maximum length of the second opening CNT2 in the first direction DR1 or the maximum length of the second opening CNT2 in the second direction DR2. For example, the second diameter D2 of the second opening CNT2 may be about 1.7 microns to about 2.0 microns.

[0114] In an embodiment, the second height H2 of the second opening CNT2 may be smaller than the first height H2 of the first opening CNT1 (eg, Figure 3 The second opening CNT2 may be formed across the third gate insulating layer GI3 and the second interlayer insulating layer ILD2, and the first opening CNT1 may be formed across the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating film ILD1, the third gate insulating layer GI3 and the second interlayer electrical insulating layer ILD2. Accordingly, the second height H2 may be smaller than the first height. As a result, the aspect ratio of the second opening CNT2 may be smaller than the aspect ratio of the first opening CNT1.

[0115] The organic layer pattern OGL may be disposed in the second opening CNT2 and may contact the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. In an embodiment, the organic layer pattern OGL may fill the space defined by the undercut structure UC. In other words, the organic layer pattern OGL may fill the disconnected space between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in the region overlapping with the upper surface of the first conductive pattern SD1-P1 in the second opening CNT2 in a plan view. Accordingly, the organic layer pattern OGL may connect the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 that are disconnected from each other. Since the organic layer pattern OGL fills the space defined by the undercut structure UC, the organic layer pattern OGL may cover the stepped structure of the side surface of the first conductive pattern SD1-P1.

[0116] The organic layer pattern OGL may expose a portion of the second conductive pattern SD1-P2. Specifically, the organic layer pattern OGL may be disposed to overlap an upper surface of the first conductive pattern SD1-P1 in the second opening CNT2 in a plan view and may expose a portion of an upper surface of the second conductive pattern SD1-P2.

[0117] In an embodiment, the organic layer pattern OGL may be disposed in the first openings CNT1 , and may be disposed in the second openings CNT2 .

[0118] The second conductive layer SD2 may cover the side surface of the first conductive pattern SD1-P1 and the organic layer pattern OGL, and may contact the second conductive pattern SD1-P2. Specifically, the second conductive layer SD2 may cover the upper surface of the second conductive pattern SD1-P2 exposed from the organic layer pattern OGL. Accordingly, the second conductive layer SD2 may be electrically connected to the second conductive pattern SD1-P2. In an embodiment, the second conductive layer SD2 may be formed by a sputtering process.

[0119] In an embodiment, the second conductive layer SD2 may extend continuously in the second opening CNT2. That is, since the organic layer pattern OGL fills the space defined by the undercut structure UC, the second conductive layer SD2 may extend continuously in the second opening CNT2 without being disconnected. Accordingly, the second conductive layer SD2 may be electrically connected to the second source region of the second active pattern ACT2 through the second conductive pattern SD1-P2. That is, even if a disconnection occurs in the first conductive layer SD1, the second conductive layer SD2 may be electrically connected to the second source region of the second active pattern ACT2.

[0120] Accordingly, a first transistor TR1 including a first active pattern ACT1, a first gate electrode GE1, a first source-drain structure SDG1 and a second source-drain structure SDG2 may be formed. In addition, a second transistor TR2 including a second active pattern ACT2, a third gate electrode GE3, a third source-drain structure SDG3 and a fourth source-drain structure SDG4 may be formed.

[0121] Figure 7 is a flowchart of a method of manufacturing a display device according to an embodiment of the present disclosure. Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 It is a graphic Figure 7 For example, Figures 8 to 17 It is used to explain the manufacturing reference Figures 1 to 3 Except that the display device DD2 includes a third source-drain structure SDG3 and a fourth source-drain structure SDG4 connected to the second active pattern ACT2, the display device DD2 is shown in FIG. Figures 4 to 6 The display device DD2 described can be used with reference Figures 1 to 3 The display devices DD described are substantially the same. Accordingly, the description of the method of manufacturing the display device DD can be equally applied to the method of manufacturing the display device DD2.

[0122] refer to Figure 7 According to an embodiment of the present disclosure, the method MM for manufacturing a display device may include: forming an active pattern and an insulating layer on the active pattern (step S100); forming an opening in the insulating layer to expose a portion of the active pattern (step S200); forming a source-drain structure on the insulating layer (step S300); and forming a light-emitting element on the source-drain structure (step S400).

[0123] refer to Figure 8 A first active pattern ACT1 may be formed on a substrate SUB, and a first insulating layer group ILG1 may be formed on the first active pattern ACT1 (step S100). The first insulating layer group ILG1 may include a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2.

[0124] A buffer layer BUF may be formed on the substrate SUB, and a first active pattern ACT1 may be formed on the buffer layer BUF. A first gate insulating layer GI1 covering the first active pattern ACT1 may be formed on the buffer layer BUF. A first gate electrode GE1 may be formed on the first gate insulating layer GI1.

[0125] A second gate insulating layer GI2 covering the first gate electrode GE1 may be formed on the first gate insulating layer GI1. A second gate electrode GE2 may be formed on the second gate insulating layer GI2.

[0126] A first interlayer insulating layer ILD1 covering the second gate electrode GE2 may be formed on the second gate insulating layer GI2. A second active pattern ACT2 may be formed on the first interlayer insulating layer ILD1. That is, the second active pattern ACT2 may be formed on the first active pattern ACT1.

[0127] A third gate insulating layer GI3 covering the second active pattern ACT2 may be formed on the first interlayer insulating layer ILD1. A third gate electrode GE3 may be formed on the third gate insulating layer GI3. A second interlayer insulating layer ILD2 covering the third gate electrode GE3 may be formed on the third gate insulating layer GI3.

[0128] refer to Fig. 9 , a first opening CNT1 exposing a portion of the first active pattern ACT1 may be formed in the first insulating layer group ILG1, and a second opening CNT2 exposing a portion of the second active pattern ACT2 may be formed in the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 (step S200). Since the first active pattern ACT1 is disposed under the second active pattern ACT2, the aspect ratio of the first opening CNT1 may be greater than that of the second opening CNT2.

[0129] refer to Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16, forming a first source-drain structure SDG1 and a second source-drain structure SDG2 on the first insulating layer group ILG1 (step S300) may include: forming a first conductive layer SD1, the first conductive layer SD1 including a first conductive pattern SD1-P1 in contact with a side surface of the first insulating layer group ILG1 defining the first opening CNT1 and a second conductive pattern SD1-P2 in contact with the first active pattern ACT1 (step S310); forming a preliminary organic layer POGL on the first conductive layer SD1 (step S320); forming an organic layer pattern OGL by patterning the preliminary organic layer POGL (step S330); and forming a second conductive layer SD2, the second conductive layer SD2 covering the side surface of the first conductive pattern SD1-P1 and the organic layer pattern OGL and in contact with the second conductive pattern SD1-P2 (step S340). Figures 12 to 16 is with Fig.11 An enlarged cross-sectional view corresponding to region 'C'.

[0130] like Fig.12 As shown in FIG. 1 , a first conductive layer SD1 including a first conductive pattern SD1-P1 contacting a side surface of the first insulating layer group ILG1 defining the first opening CNT1 and a second conductive pattern SD1-P2 contacting the first active pattern ACT1 may be formed (step S310). In an embodiment, the first conductive layer SD1 may be formed by a sputtering process.

[0131] In the process of forming the first conductive layer SD1 by the sputtering process, the first conductive layer SD1 may be disconnected into the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. That is, the first conductive layer SD1 may include the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 disconnected from each other. Accordingly, the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 may define an undercut structure UC in the first opening CNT1. The undercut structure UC may be defined as a disconnected structure located between the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 in a region overlapping the first opening CNT1 in a plan view.

[0132] The first conductive pattern SD1-P1 may be formed on the first insulating layer group ILG1. The first conductive pattern SD1-P1 may make contact with a side surface of the first insulating layer group ILG1 defining the first opening CNT1.

[0133] In an embodiment, a first edge EG1 of an upper surface of the first conductive pattern SD1-P1 may protrude more than a second edge EG2 of a lower surface of the first conductive pattern SD1-P1 in a direction toward the center of the first opening CNT1. That is, in a process of forming the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2 by a sputtering process, the first edge EG1 may protrude more than the second edge EG2 in a direction toward the center of the first opening CNT1.

[0134] The second conductive pattern SD1-P2 may be formed in the first opening CNT1 on the first active pattern ACT1. A height of an upper surface of the second conductive pattern SD1-P2 at a center of the first opening CNT1 may be greater than a height of an upper surface of the second conductive pattern SD1-P2 at an edge of the first opening CNT1.

[0135] like Fig.13 As illustrated in FIG. 1 , a preliminary organic layer POGL may be formed on the first conductive layer SD1 (step S320). The preliminary organic layer POGL may be formed to cover the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. In an embodiment, the preliminary organic layer POGL may include a positive photosensitive organic material. In another embodiment, the preliminary organic layer POGL may include a non-photosensitive organic material.

[0136] like Fig.14 and Fig.15 As illustrated in FIG. 2 , an organic layer pattern OGL may be formed by patterning the preliminary organic layer POGL (step S330 ).

[0137] In an embodiment, the organic layer pattern OGL may be formed by exposing the preliminary organic layer POGL using the first conductive pattern SD1-P1 as a mask. In this case, the preliminary organic layer POGL may include a positive photosensitive organic material. That is, by using the first conductive pattern SD1-P1 as an exposure mask, the preliminary organic layer POGL may be patterned by exposure and development. Accordingly, the organic layer pattern OGL may be formed. The first conductive pattern SD1-P1 may block the light UV provided from the outside. Accordingly, the light UV may overlap with the first conductive pattern SD1-P1 in a plan view, and the light UV may not reach the preliminary organic layer POGL located under the first conductive pattern SD1-P1. On the contrary, the light UV may reach the preliminary organic layer POGL located on the first conductive pattern SD1-P1. In addition, the light UV may reach the preliminary organic layer POGL separated from the first conductive pattern SD1-P1 in a plan view.

[0138] When the preliminary organic layer POGL includes a positive photosensitive organic material, the portion where the light UV does not reach may be maintained in a solidified state and may not be dissolved in the developer. In this case, using a predetermined developer, a portion of the preliminary organic layer POGL may be selectively removed depending on the change in chemical properties between the portion where the light UV reaches and the portion where the light UV does not reach. Accordingly, the preliminary organic layer POGL may be patterned by selectively removing the portion of the preliminary organic layer POGL where the light UV reaches. Accordingly, an organic layer pattern OGL may be formed.

[0139] In another embodiment, the organic layer pattern OGL may be formed by etching the preliminary organic layer POGL using the first conductive pattern SD1-P1 as a mask. In this case, the preliminary organic layer POGL may include a non-photosensitive organic material. That is, by using the first conductive pattern SD1-P1 as an etching mask, the preliminary organic layer POGL may be patterned by dry etching. That is, a portion of the preliminary organic layer POGL located on the first conductive pattern SD1-P1 and a portion of the preliminary organic layer POGL separated from the first conductive pattern SD1-P1 in a plan view may be etched. On the contrary, a portion of the preliminary organic layer POGL that overlaps with the first conductive pattern SD1-P1 in a plan view and is disposed under the first conductive pattern SD1-P1 may not be etched. Accordingly, the organic layer pattern OGL may be formed.

[0140] The organic layer pattern OGL may be disposed in the first opening CNT1 and may contact the first conductive pattern SD1-P1 and the second conductive pattern SD1-P2. In an embodiment, the organic layer pattern OGL may fill the space defined by the undercut structure UC. Since the organic layer pattern OGL fills the space defined by the undercut structure UC, the organic layer pattern OGL may cover the stepped structure of the side surface of the first conductive pattern SD1-P1. The organic layer pattern OGL may expose a portion of the second conductive pattern SD1-P2.

[0141] like Fig.16 As shown in FIG. 1 , a second conductive layer SD2 may be formed, which covers the side surfaces of the first conductive patterns SD1-P1 and the organic layer patterns OGL and contacts the second conductive patterns SD1-P2 (step S340). In an embodiment, the second conductive layer SD2 may be formed by a sputtering process.

[0142] The second conductive layer SD2 may cover the side surfaces of the first conductive pattern SD1-P1 and the organic layer pattern OGL, and may contact the second conductive pattern SD1-P2. Specifically, the second conductive layer SD2 may cover the upper surface of the second conductive pattern SD1-P2 exposed from the organic layer pattern OGL.

[0143] In an embodiment, the second conductive layer SD2 may extend continuously in the first opening CNT1. That is, since the organic layer pattern OGL fills the space defined by the undercut structure UC, the second conductive layer SD2 may extend continuously in the first opening CNT1 without being disconnected. Accordingly, the second conductive layer SD2 may be electrically connected to the first source region of the first active pattern ACT1 through the second conductive pattern SD1-P2.

[0144] Accordingly, a first transistor TR1 including the first active pattern ACT1 , the first gate electrode GE1 , the first source-drain structure SDG1 , and the second source-drain structure SDG2 may be formed.

[0145] A source electrode SE and a drain electrode DE may be formed on the second interlayer insulating layer ILD2. The source electrode SE may be connected to the second source region of the second active pattern ACT2 through the second opening CNT2. The drain electrode DE may be connected to the second drain region of the second active pattern ACT2 through the second opening CNT2.

[0146] In an embodiment, each of the source electrode SE and the drain electrode DE may be formed using the same material as the first conductive layer SD1 through the same process. In this case, when the first conductive layer SD1 is formed (step S310), a second transistor TR2 including a second active pattern ACT2, a third gate electrode GE3, a source electrode SE, and a drain electrode DE may be formed.

[0147] In another embodiment, each of the source electrode SE and the drain electrode DE may include a first layer formed using the same material as the first conductive layer SD1 and a second layer disposed on the first layer and formed using the same material as the second conductive layer SD2. In this case, when the second conductive layer SD2 is formed (step S340), a second transistor TR2 including a second active pattern ACT2, a third gate electrode GE3, a source electrode SE, and a drain electrode DE may be formed.

[0148] refer to Fig.17 , a light emitting element LD may be formed on the first source-drain structure SDG1 and the second source-drain structure SDG2 (step S400 ).

[0149] A first via insulating layer VIA1 covering the source electrode SE, the drain electrode DE, the first source-drain structure SDG1 and the second source-drain structure SDG2 may be formed on the second interlayer insulating layer ILD2. A connection electrode CNE may be formed on the first via insulating layer VIA1.

[0150] A second via insulating layer VIA2 covering the connection electrode CNE may be formed on the first via insulating layer VIA1 , and the pixel electrode PE may be formed on the second via insulating layer VIA2 .

[0151] A pixel defining layer PDL may be formed on the second via insulating layer VIA2, and a light emitting layer EML may be formed on the pixel electrode PE. A common electrode CTE may be formed on the pixel defining layer PDL and the light emitting layer EML. Accordingly, a light emitting element LD including the pixel electrode PE, the light emitting layer EML and the common electrode CTE may be formed. An encapsulation layer TFE may be formed on the common electrode CTE.

[0152] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0153] The foregoing is an explanation of embodiments of the present disclosure and should not be construed as limiting thereof. Although some embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily appreciate that many changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as defined in the claims.

Claims

1. A display device, comprising: substrate; an active pattern, disposed on the substrate; an insulating layer disposed on the active pattern and defining an opening exposing a portion of the active pattern; a first conductive layer, comprising a first conductive pattern and a second conductive pattern, wherein the first conductive pattern is disposed on the insulating layer and in contact with a side surface of the insulating layer defining the opening, and the second conductive pattern is disposed in the opening, on the active pattern and disconnected from the first conductive pattern; an organic layer pattern disposed in the opening, contacting the first conductive pattern and the second conductive pattern, and exposing a portion of the second conductive pattern; as well as A second conductive layer covers side surfaces of the first conductive pattern and the organic layer pattern and contacts the second conductive pattern.

2. The display device according to claim 1, wherein: An edge of the upper surface of the first conductive pattern protrudes in a direction toward the center of the opening more than an edge of the lower surface of the first conductive pattern, and The first conductive pattern and the second conductive pattern define an undercut structure in the opening.

3. The display device according to claim 2, wherein: The organic layer pattern is disposed to fill a space defined by the undercut structure.

4. The display device according to claim 1, wherein: The organic layer pattern connects the first conductive pattern and the second conductive pattern that are disconnected from each other.

5. The display device according to claim 1, wherein: The second conductive layer extends continuously in the opening.

6. The display device according to claim 5, wherein: The second conductive layer covers an upper surface of the portion of the second conductive pattern exposed from the organic layer pattern.

7. The display device according to any one of claims 1 to 6, wherein: The organic layer pattern includes a positive photosensitive organic material.

8. The display device according to any one of claims 1 to 6, wherein: The organic layer pattern includes a non-photosensitive organic material.

9. The display device according to any one of claims 1 to 6, wherein: The active pattern includes a first active pattern disposed on the substrate and a second active pattern disposed on the first active pattern, The opening includes a first opening exposing a portion of the first active pattern and a second opening exposing a portion of the second active pattern, and The organic layer pattern is disposed in the first opening.

10. The display device according to claim 9, wherein: The organic layer pattern is further disposed in the second opening.

11. A method for manufacturing a display device, the method comprising: forming an active pattern on a substrate, and forming an insulating layer on the active pattern; forming an opening in the insulating layer to expose a portion of the active pattern; forming a first conductive layer, the first conductive layer comprising a first conductive pattern and a second conductive pattern, wherein the first conductive pattern is disposed on the insulating layer and in contact with a side surface of the insulating layer defining the opening, and the second conductive pattern is disposed in the opening, on the active pattern and disconnected from the first conductive pattern; forming a preliminary organic layer on the first conductive layer; forming an organic layer pattern by patterning the preliminary organic layer, the organic layer pattern contacting the first conductive pattern and the second conductive pattern in the opening and exposing a portion of the second conductive pattern; as well as A second conductive layer is formed, the second conductive layer covering side surfaces of the first conductive pattern and the organic layer pattern and contacting the second conductive pattern.

12. The method according to claim 11, wherein: An edge of the upper surface of the first conductive pattern protrudes in a direction toward the center of the opening more than an edge of the lower surface of the first conductive pattern, and The first conductive pattern and the second conductive pattern define an undercut structure in the opening.

13. The method according to claim 12, wherein: The organic layer pattern is formed to fill a space defined by the undercut structure.

14. The method according to claim 13, wherein: The organic layer pattern is formed by exposing the preliminary organic layer to light using the first conductive pattern as a mask.

15. The method according to claim 13, wherein: The organic layer pattern is formed by etching the preliminary organic layer using the first conductive pattern as a mask.

16. The method according to claim 11, wherein: Each of the first conductive layer and the second conductive layer is formed by a sputtering process.

17. The method according to claim 11, wherein: The second conductive layer is formed to continuously extend in the opening.

18. The method according to claim 17, wherein: The second conductive layer is formed to cover an upper surface of the portion of the second conductive pattern exposed from the organic layer pattern.

19. The method according to any one of claims 11 to 18, wherein: The forming of the active pattern on the substrate includes: forming a first active pattern on the substrate, and forming a second active pattern on the first active pattern, The forming of the opening in the insulating layer includes: forming a first opening exposing a portion of the first active pattern, and forming a second opening exposing a portion of the second active pattern; and The organic layer pattern is formed in the first opening.

20. The method according to claim 19, wherein: The organic layer pattern is further formed in the second opening.

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