Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes: a plurality of data lines; the touch electrode layer comprises a plurality of first touch electrode wires and a plurality of second touch electrode wires which are located on the sides, away from the substrate, of the data lines. The array substrate comprises a plurality of fractures, and electrode wires in the first touch electrode wires are discontinuous at the fractures. And the orthographic projection of the insulating material in the corresponding fracture on the substrate is overlapped with the orthographic projection of a single data line in the plurality of data lines on the substrate. At the positions of the fractures in the plurality of fractures, the orthographic projection of each first touch electrode wire on the substrate is not overlapped with the orthographic projection of the single data line on the substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot topics in the field of flat panel display research today. OLED is driven by a driving current that needs to be kept constant to control the brightness. The OLED display panel includes a plurality of pixel units configured with a pixel driving circuit arranged in multiple rows and columns. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising: a plurality of data lines; and a touch electrode layer, the touch electrode layer comprising a plurality of touch electrode lines located on a side of the plurality of data lines away from a base substrate; wherein the plurality of touch electrode lines comprise a plurality of first touch electrode lines extending in a direction substantially parallel to a first direction and a plurality of second touch electrode lines extending in a direction substantially parallel to a second direction; and the plurality of data lines extend in a direction substantially parallel to the second direction; wherein the array substrate comprises a plurality of breaks, at which the electrode lines among the plurality of first touch electrode lines are discontinuous; the orthographic projection of the insulating material in each of the plurality of breaks on the base substrate overlaps with the orthographic projection of a single data line among the plurality of data lines on the base substrate; and at the position where a break among the plurality of breaks exists, the orthographic projection of each of the plurality of first touch electrode lines on the base substrate does not overlap with the orthographic projection of the single data line on the base substrate.

[0004] Optionally, the plurality of fractures are arranged in an array of multiple rows and columns.

[0005] Optionally, the multiple first touch electrode lines are arranged into multiple rows, the multiple rows include the (2k-1)th row R(2k-1) and the (2k)th row R(2k) in the K rows, K and k are positive integers, 1≤k≤(K / 2); the multiple data lines include a first adjacent data line and a second adjacent data line; the orthographic projection of the first adjacent data line on the substrate substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate substrate; and the orthographic projection of the second adjacent data line on the substrate substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate substrate.

[0006] Optionally, the multiple data lines also include a third adjacent data line; and the orthographic projection of the third adjacent data line on the substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate, and at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate.

[0007] Optionally, the first adjacent data line, the second adjacent data line and the third adjacent data line are three data lines adjacent to each other.

[0008] Optionally, the breaks in the first touch electrode lines in the (2k)th row R(2k) and the breaks in the first touch electrode lines in the (2k-1)th row R(2k-1) are staggered with each other.

[0009] Optionally, a portion of each first touch electrode line located between two adjacent breaks among the multiple breaks intersects with two data lines among the multiple data lines; and an orthographic projection of a portion of each first touch electrode line located between the two adjacent breaks among the multiple breaks on the substrate at least partially overlaps with an orthographic projection of two data lines among the multiple data lines on the substrate.

[0010] Optionally, each of the first touch electrode lines includes a first portion and a second portion separated by a break among the multiple breaks; the orthographic projections of the first portion and the second portion on the substrate substrate do not overlap with the orthographic projection of the single data line on the substrate substrate, wherein the single data line extends through an area having the break; the first portion is separated from the single data line by a first minimum distance; the second portion is separated from the single data line by a second minimum distance; and the first minimum distance and the second minimum distance are greater than 0.5 μm.

[0011] Optionally, orthographic projections of the plurality of second touch electrode lines on the base substrate do not substantially overlap with orthographic projections of the plurality of data lines on the base substrate.

[0012] Optionally, the array substrate further includes a plurality of voltage supply lines and a plurality of constant voltage signal lines; and wherein the orthographic projections of the plurality of second touch electrode lines on the base substrate at least partially overlap with the orthographic projections of the combination of the plurality of voltage supply lines and the plurality of constant voltage signal lines on the base substrate.

[0013] Optionally, the plurality of second touch electrode lines include a plurality of first adjacent second touch electrode lines and a plurality of second adjacent second touch electrode lines arranged alternately; wherein the orthographic projection of a first adjacent second touch electrode line among the plurality of first adjacent second touch electrode lines on the substrate is substantially covered by the orthographic projection of a single voltage supply line among the plurality of voltage supply lines on the substrate; and the orthographic projection of a second adjacent second touch electrode line among the plurality of second adjacent second touch electrode lines on the substrate at least partially overlaps with the orthographic projection of a single constant voltage signal line among the plurality of constant voltage signal lines on the substrate.

[0014] Optionally, each of the first touch electrode lines crosses at least one voltage supply line among the plurality of voltage supply lines, and crosses at least one constant voltage signal line among the plurality of constant voltage signal lines.

[0015] Optionally, the array substrate further includes a plurality of anodes; wherein the orthographic projections of the plurality of touch electrode lines on the base substrate and the orthographic projections of the plurality of anodes of the plurality of light-emitting elements on the base substrate do not substantially overlap.

[0016] Optionally, the array substrate further includes a plurality of anodes and a pixel defining layer defining a plurality of sub-pixel openings; wherein the orthographic projections of the plurality of touch electrode lines on the base substrate are completely non-overlapping with the orthographic projections of the light-emitting materials in the plurality of sub-pixel openings on the base substrate.

[0017] Optionally, an orthographic projection of each of the plurality of data lines on the substrate at least partially overlaps with an orthographic projection of a column of anodes of the plurality of anodes on the substrate.

[0018] Optionally, an orthographic projection of each of the plurality of data lines on the base substrate at least partially overlaps with an orthographic projection of a light-emitting material in a column of sub-pixel openings among the plurality of sub-pixel openings on the base substrate.

[0019] Optionally, the array substrate also includes a plurality of first reset signal lines and a plurality of second reset signal lines, which are located in the following layer: the layer is located on the side of the plurality of data lines close to the base substrate; wherein the plurality of constant voltage signal lines include a plurality of third reset signal lines; wherein the array substrate includes an interconnected reset signal network, the interconnected reset signal network includes the plurality of first reset signal lines, the plurality of second reset signal lines and the plurality of third reset signal lines interconnected together; the plurality of first reset signal lines and the plurality of second reset signal lines extend in a direction substantially parallel to the first direction respectively; the plurality of third reset signal lines extend in a direction substantially parallel to the second direction; each first reset signal line is connected to one or more third reset signal lines among the plurality of third reset signal lines; each second reset signal line is connected to one or more third reset signal lines among the plurality of third reset signal lines; and each third reset signal line among the plurality of third reset signal lines is connected to one or more first reset signal lines among the plurality of first reset signal lines, and is connected to one or more second reset signal lines among the plurality of second reset signal lines.

[0020] Optionally, the multiple first reset signal lines and the multiple second reset signal lines are located in a semiconductor material layer, which includes an active layer of one or more transistors of a pixel driving circuit; and the multiple third reset signal lines are located in a second signal line layer, which is located on a side of the semiconductor material layer away from the substrate.

[0021] Optionally, despite the multiple breaks, the touch electrode lines in the same touch electrode block remain interconnected; and portions of the discontinuous electrode fragments in each first touch electrode line are electrically connected together through an adjacent second touch electrode line and one or more adjacent first touch electrode lines.

[0022] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 2Bis a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 2C is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0029] Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate depicted in FIG.

[0030] Figure 3C It is shown Figure 3A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0031] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0032] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0033] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG.

[0034] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0035] Figure 3H It is shown Figure 3A Schematic diagram of the structure of the passivation layer in the array substrate depicted in FIG.

[0036] Fig. 3I It is shown Figure 3A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0037] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0038] Figure 3K It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0039] Figure 3L It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0040] Figure 3M It is shown Figure 3A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0041] Figure 3N It is shown Figure 3A Schematic diagram of the structure of the touch electrode layer in the array substrate depicted in FIG.

[0042] Figure 4 is along Figure 3A Cross-sectional view along line A-A'.

[0043] Figure 5 is a cross-sectional view showing an array substrate in some embodiments according to the present disclosure.

[0044] Figure 6 A network of interconnected reset signals in accordance with some embodiments of the present disclosure is shown.

[0045] Figure 7 is a schematic diagram showing the structure of a second signal line layer in an array substrate according to some embodiments of the present disclosure.

[0046] Figure 8 A network of interconnected reset signals in accordance with some embodiments of the present disclosure is shown.

[0047] Fig. 9 Detailed structures in a display area of ​​an array substrate according to some embodiments of the present disclosure are shown.

[0048] Fig.10 is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0049] Fig.11 It is shown Figure 3A A schematic diagram of the structure of the second signal line layer and the touch electrode layer in the array substrate depicted in FIG.

[0050] Fig.12 It is shown Figure 3A Schematic diagram of the structure of the anode layer and the touch electrode layer in the array substrate depicted in FIG.

[0051] Fig.13 It is shown Figure 3A Schematic diagram of the structure of the second signal line layer, anode layer and touch electrode layer in the array substrate depicted in FIG.

[0052] Fig.14 is an enlarged view of a touch electrode layer in a region having a line break.

[0053] Fig.15 is a schematic diagram showing the layout of a plurality of touch electrode lines and a plurality of data lines according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0054] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0055] The present disclosure provides, in particular, an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes: a plurality of data lines; and a touch electrode layer, which includes a plurality of touch electrode lines located on a side of the plurality of data lines away from the base substrate. Optionally, the plurality of touch electrode lines include a plurality of first touch electrode lines extending in a direction substantially parallel to the first direction and a plurality of second touch electrode lines extending in a direction substantially parallel to the second direction. Optionally, the plurality of data lines extend in a direction substantially parallel to the second direction. Optionally, the array substrate includes a plurality of breaks, and the electrode lines in the plurality of first touch electrode lines are discontinuous at the breaks. Optionally, the orthographic projection of the insulating material in each of the plurality of breaks on the base substrate overlaps with the orthographic projection of a single data line in the plurality of data lines on the base substrate. Optionally, at the position where the breaks in the plurality of breaks exist, the orthographic projection of each of the plurality of first touch electrode lines on the base substrate does not overlap with the orthographic projection of the single data line on the base substrate.

[0056] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0057] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd. Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through each of a plurality of voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0058] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding first reset control signal line among a plurality of first reset control signal lines rst1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a first electrode connected to the second electrode of the driving transistor Td, and a first electrode connected to the first electrode of the storage capacitor Cst. a capacitor electrode Ce1 and a second electrode of the gate of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 having a gate connected to a corresponding light emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a corresponding second reset control signal line among a plurality of second reset control signal lines rst2, a first electrode connected to a second reset signal line among a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0059] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0060] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is Figure 3D The first transistor T1 is a "double-gate" transistor. The gate of the third transistor T3 is Figure 3D Marked as “G3”, wherein the third transistor T3 is a “dual-gate” transistor.

[0061] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the second electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0062] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0063] Figure 2C is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. FIG. 2A to FIG. 2CDuring one frame of image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the first transistor T1 through a corresponding first reset control signal line among a plurality of first reset control signal lines rst1 to cut off the first transistor T1, and a cut-off reset control signal is provided to the gate of the sixth transistor T6 through a corresponding second reset control signal line among a plurality of second reset control signal lines rst2 to cut off the sixth transistor T6. In the initial sub-stage t0, a corresponding gate line among a plurality of gate lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off.

[0064] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first transistor T1 through the corresponding first reset control signal line in the plurality of first reset control signal lines rst1 to turn on the first transistor T1; to allow the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line in the plurality of voltage supply lines Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-phase t1. In the reset sub-phase t1, the corresponding gate line in the plurality of gate lines GL is provided with a cut-off signal, so the second transistor T2 and the third transistor T3 are cut off. The corresponding light emitting control signal line in the plurality of light emitting control signal lines em is provided with a high voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0065] In the data writing sub-phase t2, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the corresponding first reset control signal line in the plurality of first reset control signal lines rst1 to cut off the first transistor T1. The corresponding gate line in the plurality of gate lines GL is provided with a turn-on signal, so that the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the first electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the second electrode of the third transistor T3. Since the third transistor T3 is turned on in the data writing sub-phase t2, the gate of the driving transistor Td is connected to the second electrode and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The second transistor T2 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through the corresponding data line in the plurality of data lines DL is received by the first electrode of the second transistor T2, and then transmitted to the first electrode of the driving transistor Td, and the first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level at the N1 node gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emitting control signal line among the plurality of light emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0066] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 through a corresponding second reset control signal line among the plurality of second reset control signal lines rst2 to turn on the sixth transistor T6; to allow an initialization voltage signal from a corresponding second reset signal line among the plurality of second reset signal lines Vint2 to be transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to the node N4. The anode of the light emitting element LE is initialized.

[0067] In the light-emitting sub-stage t3, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the corresponding first reset control signal line among the plurality of first reset control signal lines rst1 to cut off the first transistor T1. The corresponding gate line among the plurality of gate lines GL is provided with a cut-off signal, and the second transistor T2 and the third transistor T3 are cut off. The corresponding light-emitting control signal line among the plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting sub-stage t3, the voltage level at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0068] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0069] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0070] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0071] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0072] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate. Figure 3A and Figure 3B Depicting a portion of an array substrate having twelve pixel driving circuits including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12.

[0073] Figure 3C It is shown Figure 3A Schematic diagram of the structure of the semiconductor material layer in the array substrate. Figure 3D It is shown Figure 3A Schematic diagram of the structure of the first conductive layer in the array substrate. Figure 3E It is shown Figure 3A Schematic diagram of the structure of the second conductive layer in the array substrate. Figure 3F It is shown Figure 3A Schematic diagram of the structure of the interlayer dielectric layer in the array substrate. Figure 3G It is shown Figure 3A Schematic diagram of the structure of the first signal line layer in the array substrate. Figure 3H It is shown Figure 3A Schematic diagram of the structure of the passivation layer in the array substrate depicted in FIG. Fig. 3I It is shown Figure 3A Schematic diagram of the structure of the first planarization layer in the array substrate. Figure 3J It is shown Figure 3A Schematic diagram of the structure of the second signal line layer in the array substrate. Figure 3K It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate. Figure 3L It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate. Figure 3M It is shown Figure 3A Schematic diagram of the structure of a pixel defining layer in an array substrate. Figure 3N It is shown Figure 3A Schematic diagram of the structure of the touch electrode layer in the array substrate depicted in FIG.

[0074] Reference FIG. 3A to FIG. 3N and Figure 4In some embodiments, the display panel includes: a base substrate BS; a semiconductor material layer SML located on the base substrate BS; a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1 located on a side of the interlayer dielectric layer ILD away from the semiconductor material layer SML; one side of the second conductive layer CT2; the passivation layer PVX, which is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the first planarization layer PLN1, which is located on the side of the passivation layer PVX away from the first signal line layer SL1; the second signal line layer SL2, which is located on the side of the first planarization layer PLN1 away from the passivation layer PVX; the second planarization layer PLN2, which is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the substrate BS.

[0075] In an alternative embodiment, the array substrate does not include the passivation layer PVX (eg, the passivation layer PVX and the first planarization layer PLN1 are the same layer). Figure 5 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 5 In some embodiments, the display panel includes: a base substrate BS; a semiconductor material layer SML located on the base substrate BS; a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on a side of the second conductive layer CT2 away from the insulating layer IN; and a first signal line layer SL1. , which is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; the first planarization layer PLN1, which is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2, which is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the substrate BS.

[0076] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C , each pixel driving circuit is marked with a number, and the number indicates the area corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also marked with a number, and the number indicates the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located on the same layer.

[0077] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0078] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C In some embodiments, the semiconductor material layer further includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2. Each of the plurality of first reset signal lines Vint1 is configured to provide a reset signal to the first electrode S1 of the first transistor T1. Each of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the first electrode S6 of the sixth transistor T6.

[0079] In some embodiments, a plurality of first reset signal lines Vint1 extend in directions substantially parallel to the first direction DR1; a plurality of second reset signal lines Vint2 extend in directions substantially parallel to the first direction DR1. In some embodiments, each first reset signal line, each second reset signal line, and each active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of a transistor (T1, T2, T3, T4, T5, T6, and Td) in a pixel driving circuit, a first electrode (S1, S2, S3, S4, S5, S6, and Sd), and a second electrode (D1, D2, D3, D4, D5, D6, and Dd) are part of an integral structure. In some embodiments, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, an active layer of a pixel driving circuit, at least a portion of a first electrode, and at least a portion of a second electrode in an array substrate are part of an integral structure. In some embodiments, each first reset signal line connects the first electrodes of the first transistors in the same row of pixel driving circuits together. In some embodiments, each second reset signal line connects the first electrodes of the sixth transistors in the same row of pixel driving circuits together. As used herein, the term "substantially parallel" refers to an angle in the range of 0 to about 45 degrees, such as 0 to about 5 degrees, 0 to about 10 degrees, 0 to about 15 degrees, 0 to about 20 degrees, 0 to about 25 degrees, 0 to about 30 degrees.

[0080] like Figure 3A and Figure 3C As shown, in some embodiments, each first reset signal line is configured to provide a reset signal to the first electrode of the first transistor in the current row pixel driving circuit, and is configured to provide a reset signal to the first electrode of the sixth transistor in the previous row pixel driving circuit. In some embodiments, each second reset signal line is configured to provide a reset signal to the first electrode of the sixth transistor in the current row pixel driving circuit, and is configured to provide a reset signal to the first electrode of the first transistor in the next row pixel driving circuit. In some embodiments, the previous row pixel driving circuit, the current row pixel driving circuit, and the next row pixel driving circuit are three consecutive rows of pixel driving circuits. Optionally, the same row of pixel driving circuits are arranged in a direction substantially parallel to the first direction DR1.

[0081] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3DIn some embodiments, the first conductive layer includes a plurality of light emitting control signal lines em, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, a plurality of light emitting control signal lines em, a first gate pad GEP1, a second gate pad GEP2, a third gate pad GEP3, and a first capacitor electrode Ce1 of a storage capacitor Cst are located in the same layer.

[0082] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of light emitting control lines em and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the light emitting control lines em and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the steps of forming a plurality of light emitting control lines em and forming the first capacitor electrode Ce1 simultaneously, a plurality of light emitting control lines em and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0083] In some embodiments, the first gate pad GEP1 includes the gate G1 of the first transistor T1 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes the gate G3 of the third transistor T3 in the pixel driving circuit. The first gate pad GEP1 is connected to a corresponding first reset control signal line among a plurality of first reset control signal lines rst1. The second gate pad GEP2 is connected to a corresponding gate line among a plurality of gate lines GL. In some embodiments, the third gate pad GEP3 includes the gate G6 of the sixth transistor T6 in the pixel driving circuit. The third gate pad GEP3 is connected to a corresponding second reset control signal line among a plurality of second reset control signal lines rst2.

[0084] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3EIn some embodiments, the second conductive layer includes a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0085] In some embodiments, the second capacitor electrodes of the storage capacitors of the same row of pixel driving circuits are connected to each other to form an integral structure. In some embodiments, the second capacitor electrode Ce2 includes a main body MB and an extension portion EP extending away from the main body MB. Optionally, the integral structure including the second capacitor electrodes of the storage capacitors of the same row of pixel driving circuits extends in a direction substantially parallel to the first direction DR1. Optionally, the extension portion EP extends away from the main body MB in a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. In one example, the second direction DR2 is perpendicular to the first direction DR1. Optionally, the orthographic projection of each of the plurality of voltage supply lines on the substrate substrate covers the orthographic projection of the extension portion EP on the substrate substrate.

[0086] Figure 3F A via extending through the interlayer dielectric layer ILD is depicted in FIG.

[0087] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3G In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of gate lines GL, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a first reset connection pad RCP1, a second reset connection pad RCP2, a relay electrode RE, a voltage connection pad VCP, and a data signal connection pad DCP. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the node connection line Cln, a plurality of gate lines GL, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a first reset connection pad RCP1, a second reset connection pad RCP2, a relay electrode RE, a voltage connection pad VCP, and a data signal connection pad DCP are located in the same layer.

[0088] The node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit with the second electrode of the third transistor T3. The data signal connection pad DCP is configured to connect each of the plurality of data lines to the first electrode of the second transistor T2. The relay electrode RE connects the fourth node N4 with the anode connection pad. The relay electrode is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6. The anode connection pad is located in the second signal line layer and is connected to the anode in each sub-pixel. The voltage connection pad VCP connects each voltage supply line with the second capacitor electrode Ce2 of the storage capacitor. For example, each first voltage supply line is connected to the voltage connection pad VCP, and the voltage connection pad VCP is connected to the second capacitor electrode Ce2 of the storage capacitor.

[0089] In some embodiments, reference Figure 4 , Figure 5 , FIG. 3A to FIG. 3M , except for the hole region H where a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS completely covers and exceeds the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2.

[0090] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate further includes a first via hole v1 and a second via hole v2. The first via hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via hole v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via hole v2. Optionally, as Figure 4 and Figure 5 As depicted, the node connection line Cln is connected to the second electrode D3 of the third transistor.

[0091] In some embodiments, a plurality of first reset control signal lines rst1 extend in directions substantially parallel to the first direction DR1, respectively; and a plurality of second reset control signal lines rst2 extend in directions substantially parallel to the first direction DR1, respectively. In some embodiments, each first reset control signal line is configured to provide a reset control signal to the gate of a first transistor of a same row of pixel driving circuits. In some embodiments, each second reset control signal line is configured to provide a reset control signal to the gate of a sixth transistor of a same row of pixel driving circuits.

[0092] like Figure 3A and Figure 3G As shown, in some embodiments, each first reset control signal line is configured to provide a reset control signal to the gate of the first transistor of the pixel driving circuit in the current row of pixel driving circuits, and is configured to provide a reset control signal to the gate of the sixth transistor in the previous row of pixel driving circuits. In some embodiments, each second reset control signal line is configured to provide a reset control signal to the gate of the sixth transistor in the current row of pixel driving circuits, and is configured to provide a reset control signal to the gate of the first transistor in the next row of pixel driving circuits. In some embodiments, the previous row of pixel driving circuits, the current row of pixel driving circuits, and the next row of pixel driving circuits are three consecutive rows of pixel driving circuits. Optionally, the same row of pixel driving circuits is arranged in a direction substantially parallel to the first direction DR1.

[0093] The first reset connection pad RCP1 connects each first reset signal line to a single third reset signal line among a plurality of third reset signal lines. The second reset connection pad RCP2 connects each second reset signal line to a single third reset signal line among a plurality of third reset signal lines. Each first reset signal line is configured to provide a reset signal to a first electrode of a first transistor in a current row of pixel drive circuits, and is configured to provide a reset signal to a first electrode of a sixth transistor in a previous row of pixel drive circuits. Each second reset signal line is configured to provide a reset signal to a first electrode of a sixth transistor in a current row of pixel drive circuits, and is configured to provide a reset signal to a first electrode of a first transistor in a next row of pixel drive circuits. In some embodiments, the previous row of pixel drive circuits, the current row of pixel drive circuits, and the next row of pixel drive circuits are three consecutive rows of pixel drive circuits. Optionally, the same row of pixel drive circuits are arranged in a direction substantially parallel to the first direction DR1.

[0094] Figure 3H Vias extending through the first planarization layer PVX are shown.

[0095] Fig. 3I Vias extending through the passivation layer PLN1 are shown.

[0096] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3JIn some embodiments, the second signal line layer includes a plurality of voltage supply lines Vdd, a plurality of data lines DL, a plurality of constant voltage signal lines Vc, and an anode contact pad ACP. The anode contact pad ACP is electrically connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in the corresponding pixel driving circuit through a relay electrode. The anode contact pad ACP is electrically connected to the anode of the light-emitting element in the corresponding sub-pixel. As described above, the plurality of voltage supply lines Vdd are connected to the voltage supply pad in the first signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 through a data signal connection pad.

[0097] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of voltage supply lines Vdd, a plurality of data lines DL, a plurality of constant voltage signal lines Vc, and an anode contact pad ACP are located on the same layer.

[0098] In some embodiments, the plurality of constant voltage signal lines Vc are a plurality of third reset signal lines. As described above, the first reset connection pad connects each first reset signal line to a single third reset signal line among the plurality of third reset signal lines. The second reset connection pad connects each second reset signal line to a single third reset signal line among the plurality of third reset signal lines. In some embodiments, the plurality of first reset signal lines, the plurality of second reset signal lines, and the plurality of third reset signal lines (e.g., the plurality of constant voltage signal lines Vc) form an interconnected reset signal network.

[0099] Figure 6 FIG. 2 shows an interconnected reset signal network in accordance with some embodiments of the present disclosure. Figure 6In some embodiments, the interconnected reset signal network includes a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, and a plurality of third reset signal lines Vint3 interconnected together. The plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1; the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1; and the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to the second direction DR2. In one example, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are located in the semiconductor material layer. In another example, the plurality of third reset signal lines Vint3 are located in the second signal line layer. Optionally, each first reset signal line is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each second reset signal line is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each third reset signal line in the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1, and is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0100] In an alternative embodiment, the plurality of constant voltage signal lines Vc are a plurality of low voltage signal lines, for example, configured to provide low voltage signals to cathodes of light emitting elements in the array substrate.

[0101] In an alternative embodiment, the plurality of constant voltage signal lines Vc include a plurality of third reset signal lines and a plurality of low voltage signal lines that are alternately arranged. Figure 7 Schematic diagram showing the structure of the second signal line layer in the array substrate according to some embodiments of the present disclosure. Figure 7 In some embodiments, the array substrate includes a plurality of voltage supply lines Vdd, a plurality of low voltage signal lines Vss, a plurality of third reset signal lines Vint3, and a plurality of data lines DL. In some embodiments, the plurality of pixel driving circuits are arranged in a plurality of columns, including the (2k-1)th column C(2k-1) and the (2k)th column C(2k) in the K columns, where k and K are positive integers, 1≤k≤K / 2. Figure 7 In some embodiments, a plurality of third reset signal lines Vint3 exist in the (2k-1)th column C(2k-1) but not in the (2k)th column C(2k). A plurality of low voltage signal lines Vss exist in the (2k)th column C(2k) but not in the (2k-1)th column C(2k-1). In some embodiments, a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of third reset signal lines Vin3 form an interconnected reset signal network.

[0102] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The array substrate may or may not include additional columns before the first column in column K and / or additional columns after the last column in column K. In the context of the array substrate, the term "column (2k-1)" does not necessarily mean an odd column, and the term "column (2k)" does not necessarily mean an even column. In one example, the column (2k-1) is an odd column in the context of column K, but may be an even column in the context of the array substrate. In another example, the column (2k-1) is an odd column in the context of column K, and is also an odd column in the context of the array substrate. In one example, the column (2k) is an even column in the context of column K, but may be an odd column in the context of the array substrate. In another example, the column (2k) is an even column in the context of column K, and is also an even column in the context of the array substrate.

[0103] Figure 8 FIG. 2 shows an interconnected reset signal network in accordance with some embodiments of the present disclosure. Figure 8 In some embodiments, the interconnected reset signal network includes a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, and a plurality of third reset signal lines Vint3 that are interconnected. The plurality of third reset signal lines Vint3 exist in the (2k-1)th column C(2k-1) but not in the (2k)th column C(2k). Optionally, each first reset signal line is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each second reset signal line is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each third reset signal line in the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1, and is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0104] Figure 3K A via extending through the second planarization layer PLN2 is depicted.

[0105] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3L , the array substrate further includes an anode layer ADL. Figure 3L A plurality of sub-pixel openings SA corresponding to the plurality of anodes are indicated in FIG. Figure 3K Vias extending through the second planarization layer PLN2 are depicted. Respective anodes are connected to respective anode contact pads through respective vias extending through the second planarization layer PLN2.

[0106] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3M The array substrate further includes a pixel defining layer PDL defining a plurality of sub-pixel openings SA.

[0107] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3N In some embodiments, the touch electrode layer includes a plurality of touch electrode lines TEL, such as a plurality of touch electrode grid lines. In some embodiments, the plurality of touch electrode lines TEL include a plurality of first touch electrode lines TEL1 and a plurality of second touch electrode lines TEL2. Optionally, the plurality of first touch electrode lines TEL1 extend in a direction substantially parallel to the first direction DR1, and the plurality of second touch electrode lines TEL2 extend in a direction substantially parallel to the second direction DR2, and the first direction DR1 and the second direction DR2 are different from each other.

[0108] Fig. 9 Detailed structures in the display area of ​​the array substrate in some embodiments of the present disclosure are shown. Fig. 9In some embodiments, the display substrate includes in the display area: a base substrate BS (for example, a flexible base substrate); an active layer ACT of each thin film transistor among a plurality of thin film transistors TFT located on the base substrate BS; a gate insulating layer GI located on a side of the active layer ACT away from the base substrate BS; a gate G and a first capacitor electrode Ce1 (both are parts of the first gate metal layer) located on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of the second gate metal layer) located on a side of the insulating layer IN away from the gate insulating layer GI; a second capacitor electrode Ce2 located on a side of the second capacitor electrode Ce2 away from the gate insulating layer GI; an interlayer dielectric layer ILD; a source electrode S and a drain electrode D (part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX located on the side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a relay electrode RE (part of the second SD metal layer) located on the side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 located on the side of the relay electrode RE away from the passivation layer PVX; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate BS; and a light emitting element LE located in the sub-pixel opening. The light emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light emitting layer EL away from the anode AD. The array substrate further includes an encapsulation layer EN in the display area, which encapsulates the light emitting element LE and is located on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. In the display area, the array substrate further includes a buffer layer BUF located on the side of the encapsulation layer EN away from the base substrate BS, a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN, a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF, a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF, and an overcoat layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.Optionally, in the display area, the array substrate does not include the passivation layer PVX, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0109] Reference Fig. 9 The array substrate includes a semiconductor material layer SML, a first conductive layer CT1, a second conductive layer CT2, a first signal line layer SL1, and a second signal line layer SL2. The array substrate also includes an insulating layer IN between the first conductive layer CT1 and the second conductive layer CT2, an interlayer dielectric layer ILD between the second conductive layer CT2 and the first signal line layer SL1, and at least a passivation layer PVX or a first planarization layer PLN1 between the first signal line layer SL1 and the second signal line layer SL2.

[0110] Reference Fig. 9 , a plurality of first touch electrodes TE1 are located in the first metal layer ML1, and a plurality of second electrode bridges BR2 are located in the second metal layer ML2. In some embodiments, a plurality of first touch electrode lines TEL1 and a plurality of second touch electrode lines TEL2 are located in the second metal layer ML2. In an alternative embodiment, a plurality of first touch electrode lines TEL1 and a plurality of second touch electrode lines TEL2 are located in the first metal layer ML1. In an alternative embodiment, a plurality of first touch electrode lines TEL1 and a plurality of second touch electrode lines TEL2 are partially located in the first metal layer ML1 and partially located in the second metal layer ML2.

[0111] Fig.10 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.10 In some embodiments, the touch structure includes a plurality of first grid electrodes TE1 arranged in a plurality of rows and a plurality of second grid electrodes TE2 arranged in a plurality of columns. The plurality of first grid electrodes TE1 are arranged in a plurality of rows, and each row in the plurality of rows is a corresponding first grid electrode in the plurality of first grid electrodes TE1. The plurality of second grid electrodes TE2 are arranged in a plurality of columns, and each column in the plurality of columns is a corresponding second grid electrode in the plurality of second grid electrodes TE2. Optionally, the touch structure is a mutual capacitive touch structure. Optionally, the plurality of first grid electrodes TE1 are a plurality of touch sensing electrodes, and the plurality of second grid electrodes TE2 are a plurality of touch scanning electrodes. Optionally, the plurality of first grid electrodes TE1 are a plurality of touch scanning electrodes, and the plurality of second grid electrodes TE2 are a plurality of touch sensing electrodes.

[0112] like Fig.10As shown, each of the plurality of first grid electrodes TE1 includes a plurality of first grid blocks MB1 electrically connected in sequence along a first direction DR1 in a corresponding row, and each of the plurality of second grid electrodes TE2 includes a plurality of second grid blocks MB2 electrically connected in sequence along a second direction DR2 in a corresponding column. Fig.10 , a corresponding one of the plurality of first grid blocks MB1 and a corresponding one of the plurality of second grid blocks MB2 are depicted as blocks respectively surrounded by dotted lines.

[0113] Fig.11 It is shown Figure 3A Schematic diagram of the structure of the second signal line layer and the touch electrode layer of the array substrate depicted in FIG. Fig.12 It is shown Figure 3A Schematic diagram of the structure of the anode layer and the touch electrode layer in the array substrate depicted in FIG. Fig.13 It is shown Figure 3A Schematic diagram of the structure of the second signal line layer, anode layer and touch electrode layer of the array substrate depicted in FIG. Figures 11 to 13 In some embodiments, the orthographic projections of the plurality of touch electrode lines on the substrate substrate do not substantially overlap with the orthographic projections of the light-emitting materials in the plurality of sub-pixel openings SA on the substrate substrate (e.g., at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping). In one example, the orthographic projections of the plurality of touch electrode lines on the substrate substrate do not overlap at all with the orthographic projections of the light-emitting materials in the plurality of sub-pixel openings SA on the substrate substrate. In some embodiments, in at least 4 adjacent pixels (for example, in at least 8 adjacent pixels, in at least 16 adjacent pixels, in at least 32 adjacent pixels, in at least 64 adjacent pixels, in at least 128 adjacent pixels, or in at least 264 adjacent pixels), the orthographic projections of the plurality of touch electrode lines on the substrate substrate and the orthographic projections of the light-emitting materials in the plurality of sub-pixel openings SA on the substrate substrate do not substantially overlap (for example, at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping). Optionally, in at least 4 adjacent pixels (for example, in at least 8 adjacent pixels, in at least 16 adjacent pixels, in at least 32 adjacent pixels, in at least 64 adjacent pixels, in at least 128 adjacent pixels, or in at least 264 adjacent pixels), the orthographic projections of the plurality of touch electrode lines on the substrate substrate do not overlap at all with the orthographic projections of the light-emitting materials in the plurality of sub-pixel openings SA on the substrate substrate. Each pixel includes one or more sub-pixels. Each sub-pixel includes an anode.

[0114] In some embodiments, the orthographic projections of the plurality of touch electrode lines on the substrate substrate do not substantially overlap with the orthographic projections of the plurality of anodes of the plurality of light emitting elements on the substrate substrate (e.g., at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping). In some embodiments, in at least 4 adjacent pixels (e.g., in at least 8 adjacent pixels, in at least 16 adjacent pixels, in at least 32 adjacent pixels, in at least 64 adjacent pixels, in at least 128 adjacent pixels, or in at least 264 adjacent pixels), the orthographic projections of the plurality of touch electrode lines on the substrate substrate do not substantially overlap with the orthographic projections of the plurality of anodes of the plurality of light emitting elements on the substrate substrate (e.g., at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping). Each pixel includes one or more sub-pixels. Each sub-pixel includes an anode.

[0115] In some embodiments, the orthographic projections of the plurality of second touch electrode lines TEL2 on the substrate overlap at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projections of the combination of the plurality of voltage supply lines Vdd and the plurality of constant voltage signal lines Vc on the substrate. In some embodiments, in at least 4 adjacent pixels (e.g., in at least 8 adjacent pixels, in at least 16 adjacent pixels, in at least 32 adjacent pixels, in at least 64 adjacent pixels, in at least 128 adjacent pixels, or in at least 264 adjacent pixels), the positive projections of the plurality of second touch electrode lines TEL2 on the substrate substrate overlap at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the positive projections of the combination of the plurality of voltage supply lines Vdd and the plurality of constant voltage signal lines Vc on the substrate substrate. Each pixel includes one or more sub-pixels. Each sub-pixel includes an anode.

[0116] In some embodiments, the orthographic projections of the plurality of second touch electrode lines TEL2 on the substrate substrate do not substantially overlap with the orthographic projections of the plurality of data lines DL on the substrate substrate (e.g., at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping). In some embodiments, in at least 4 adjacent pixels (e.g., in at least 8 adjacent pixels, in at least 16 adjacent pixels, in at least 32 adjacent pixels, in at least 64 adjacent pixels, in at least 128 adjacent pixels, or in at least 264 adjacent pixels), the orthographic projections of the plurality of second touch electrode lines TEL2 on the substrate substrate do not substantially overlap with the orthographic projections of the plurality of data lines DL on the substrate substrate (e.g., at least 75% non-overlapping, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or 100% non-overlapping).

[0117] The inventors of the present disclosure discovered that by making the orthographic projections of the multiple second touch electrode lines TEL2 on the base substrate basically non-overlapping with the orthographic projections of the multiple data lines DL on the base substrate, the interference between the data signals transmitted in the multiple data lines DL and the touch signals transmitted in the multiple touch electrode lines can be significantly reduced.

[0118] In some embodiments, the plurality of second touch electrode lines TEL2 include a plurality of first adjacent second touch electrode lines and a plurality of second adjacent second touch electrode lines arranged alternately. In some embodiments, the orthographic projection of a first adjacent second touch electrode line among the plurality of first adjacent second touch electrode lines on the substrate substrate is substantially covered by the orthographic projection of a single voltage supply line among the plurality of voltage supply lines Vdd on the substrate substrate (for example, at least 75% covered, at least 80% covered, at least 85% covered, at least 90% covered, at least 95% covered, at least 99% covered, or 100% covered). In some embodiments, the orthographic projection of a second adjacent second touch electrode line among the plurality of second adjacent second touch electrode lines on the substrate substrate overlaps at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of a single constant voltage signal line among the plurality of constant voltage signal lines Vc on the substrate substrate.

[0119] In some embodiments, each of the plurality of first touch electrode lines TE1 crosses at least one of the plurality of voltage supply lines Vdd and crosses at least one of the plurality of constant voltage signal lines Vc. In some embodiments, each of the first touch electrode lines does not cross at least one of the plurality of data lines DL.

[0120] In some embodiments, the array substrate includes a plurality of breaks LB, and the electrode lines in the plurality of first touch electrode lines TE1 are discontinuous at the plurality of breaks LB. In some embodiments, the orthographic projection of the insulating material in each of the plurality of breaks LB on the base substrate overlaps with the orthographic projection of a single data line in the plurality of data lines DL on the base substrate.

[0121] In some embodiments, the orthographic projection of each of the plurality of first touch electrode lines TE1 on the substrate substrate does not overlap with the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate. In some embodiments, at a location where a break among the plurality of break points LB exists, the orthographic projection of each of the first touch electrode lines on the substrate substrate does not overlap with the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate. Optionally, the orthographic projection of each of the first touch electrode lines on the substrate substrate at least partially overlaps with the orthographic projection of at least another of the plurality of data lines DL on the substrate substrate. Optionally, at a location where the plurality of break points LB do not exist, the orthographic projection of each of the first touch electrode lines on the substrate substrate at least partially overlaps with the orthographic projection of at least another of the plurality of data lines DL on the substrate substrate.

[0122] The inventors of the present disclosure discovered that by making the orthographic projection of each first touch electrode line on the substrate non-overlap with the orthographic projection of at least one data line among the multiple data lines DL on the substrate, the interference between the data signals transmitted in the multiple data lines DL and the touch signals transmitted in the multiple touch electrode lines can be further reduced.

[0123] Although there are a plurality of break points LB, each touch electrode block (eg, Fig.10 The touch electrode lines in each of the plurality of first grid blocks MB1 and each of the plurality of second grid blocks MB2 shown in FIG. 1 remain interconnected. Figure 3N , Figures 11 to 13 As shown, the discontinuous electrode segments in each first touch electrode line are electrically connected through an adjacent second touch electrode line and one or more adjacent first touch electrode lines.

[0124] In some embodiments, the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of one or more of the plurality of anodes on the substrate substrate. Optionally, the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of one or more of the plurality of anodes on the substrate substrate. Optionally, the orthographic projection of each of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of one or more of the plurality of anodes on the substrate substrate. Optionally, the orthographic projection of each of the plurality of data lines DL on the substrate substrate overlaps at least partially with the orthographic projection of a column of anodes on the substrate substrate.

[0125] In some embodiments, the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the luminescent material in one or more of the plurality of sub-pixel openings SA on the substrate substrate. Optionally, the orthographic projection of at least one of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the luminescent material in one or more of the plurality of sub-pixel openings SA on the substrate substrate. Optionally, the orthographic projection of each of the plurality of data lines DL on the substrate substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the luminescent material in one or more of the plurality of sub-pixel openings SA on the substrate substrate. Optionally, an orthographic projection of each of the plurality of data lines DL on the base substrate at least partially overlaps with an orthographic projection of the light emitting material in a column of sub-pixel openings on the base substrate.

[0126] Fig.14 is an enlarged view of the touch electrode layer in the area with the fracture. Fig.14In some embodiments, each first touch electrode line includes a first portion P1 and a second portion P2 separated by a break in a plurality of breaks LB. The orthographic projections of the first portion P1 and the second portion P2 on the substrate substrate do not overlap with the orthographic projection of a single data line iDL in a plurality of data lines on the substrate substrate, wherein the single data line iDL extends through the region with the break. Optionally, the first portion P1 is separated from the single data line iDL by a first minimum distance d1. Optionally, the second portion P2 is separated from the single data line iDL by a second minimum distance d2. Optionally, the first minimum distance d1 is greater than a threshold distance to minimize interference between a data signal transmitted in the single data line iDL and a touch signal transmitted in the first portion P1. Optionally, the second minimum distance d2 is greater than a threshold distance to minimize interference between a data signal transmitted in the single data line iDL and a touch signal transmitted in the second portion P2. Optionally, the threshold distance is greater than 0.5 μm, for example, greater than 0.5 μm, greater than 1.0 μm, greater than 1.5 μm, or greater than 2.0 μm. In one example, the threshold distance is 2.0 μm.

[0127] Fig.15 is a schematic diagram showing the layout of a plurality of touch electrode lines and a plurality of data lines according to some embodiments of the present disclosure. Fig.15 In some embodiments, a plurality of first touch electrode lines are arranged in a plurality of rows, including the (2k-1)th row R(2k-1) and the (2k)th row R(2k) in the K row, where K and k are positive integers, 1≤k≤K / 2. As used herein, the terms "row (2k-1)th" and "row (2k)th" are used in the context of the K row. The touch electrode layer may or may not include additional rows before the first row in the K row and / or additional rows after the last row in the K row. In the context of the touch electrode layer, the term "row (2k-1)th" does not necessarily mean an odd row, and the term "row (2k)th" does not necessarily mean an even row. In one example, the (2k-1)th row is an odd row in the context of the K row, but may be an even row in the context of the touch electrode layer. In another example, the (2k-1)th row is an odd row in the context of the K row, and is also an odd row in the context of the touch electrode layer. In one example, the (2k)th row is an even row in the context of the K row, but may be an odd row in the context of the touch electrode layer. In another example, the (2k)th row is an even row in the context of the K row, and is also an even row in the context of the touch electrode layer.

[0128] In some embodiments, the plurality of data lines include a first adjacent data line ADL1 and a second adjacent data line ADL2. In some embodiments, the orthographic projection of the first adjacent data line ADL1 on the substrate substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate substrate. In some embodiments, the orthographic projection of the second adjacent data line ADL2 on the substrate substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate substrate. The inventors of the present disclosure have found that by having such a structure, display brightness unevenness (mura) in the array substrate can be significantly reduced.

[0129] In some embodiments, the plurality of data lines further include a third adjacent data line ADL3. In some embodiments, the orthographic projection of the third adjacent data line ADL3 on the substrate substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate substrate, and at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate substrate.

[0130] In some embodiments, the first adjacent data line ADL1, the second adjacent data line ADL2 and the third adjacent data line ADL3 are three data lines adjacent to each other. In one example, the first adjacent data line ADL1, the second adjacent data line ADL2 and the third adjacent data line ADL3 are arranged in sequence.

[0131] In some embodiments, the breaks in the first touch electrode lines in the (2k)th row R(2k) and the breaks in the first touch electrode lines in the (2k-1)th row R(2k-1) are staggered with each other.

[0132] In some embodiments, a portion of each of the plurality of first touch electrode lines TEL1 located between two adjacent breaks in the plurality of breaks LB crosses two data lines in the plurality of data lines DL. An orthographic projection of a portion of each of the plurality of first touch electrode lines located between two adjacent breaks in the plurality of breaks LB on the substrate at least partially overlaps with an orthographic projection of two data lines in the plurality of data lines DL on the substrate.

[0133] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0134] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of data lines; forming a touch electrode layer including a plurality of touch electrode lines on a side of the plurality of data lines away from the base substrate. Optionally, forming a plurality of touch electrode lines includes: forming a plurality of first touch electrode lines extending in a direction substantially parallel to the first direction, and forming a plurality of second touch electrode lines extending in a direction substantially parallel to the second direction. Optionally, the plurality of data lines extend in a direction substantially parallel to the second direction. Optionally, the method further includes: forming a plurality of breaks at positions where the electrode lines in the plurality of first touch electrode lines are discontinuous. Optionally, the orthographic projection of the insulating material in each of the plurality of breaks on the base substrate overlaps with the orthographic projection of a single data line in the plurality of data lines on the base substrate. Optionally, at positions where the breaks in the plurality of breaks exist, the orthographic projection of each of the plurality of first touch electrode lines on the base substrate does not overlap with the orthographic projection of the single data line on the base substrate.

[0135] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: A plurality of data lines; and a touch electrode layer, the touch electrode layer comprising a plurality of touch electrode lines located on a side of the plurality of data lines away from the base substrate; wherein the plurality of touch electrode lines include a plurality of first touch electrode lines extending in a direction substantially parallel to the first direction and a plurality of second touch electrode lines extending in a direction substantially parallel to the second direction; and The plurality of data lines extend in a direction substantially parallel to the second direction; Wherein, the array substrate comprises a plurality of fractures, and at the plurality of fractures, the electrode lines in the plurality of first touch electrode lines are discontinuous; An orthographic projection of the insulating material in each of the plurality of breaks on the base substrate overlaps with an orthographic projection of a single data line among the plurality of data lines on the base substrate; and At the position where the break among the multiple break exists, the orthographic projection of each of the multiple first touch electrode lines on the base substrate does not overlap with the orthographic projection of the single data line on the base substrate.

2. The array substrate according to claim 1, wherein: The plurality of fractures are arranged in an array of multiple rows and columns.

3. The array substrate according to claim 1, wherein: The plurality of first touch electrode lines are arranged into a plurality of rows, the plurality of rows including the (2k-1)th row R(2k-1) and the (2k)th row R(2k) in the K rows, K and k are positive integers, 1≤k≤(K / 2); The plurality of data lines include a first adjacent data line and a second adjacent data line; The orthographic projection of the first adjacent data line on the base substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the base substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the base substrate; as well as The orthographic projection of the second adjacent data line on the substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate, and does not overlap with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate.

4. The array substrate according to claim 3, wherein: The plurality of data lines further includes a third adjacent data line; and The orthographic projection of the third adjacent data line on the substrate at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k)th row R(2k) on the substrate, and at least partially overlaps with the orthographic projection of the first touch electrode line in the (2k-1)th row R(2k-1) on the substrate.

5. The array substrate according to claim 4, wherein: The first adjacent data line, the second adjacent data line, and the third adjacent data line are three data lines adjacent to each other.

6. The array substrate according to any one of claims 3 to 5, wherein: The breaks in the first touch electrode lines in the (2k)th row R(2k) and the breaks in the first touch electrode lines in the (2k-1)th row R(2k-1) are interlaced with each other.

7. The array substrate according to any one of claims 3 to 6, wherein: A portion of each first touch electrode line located between two adjacent breaks among the plurality of breaks crosses two data lines among the plurality of data lines; and An orthographic projection of a portion of each first touch electrode line located between two adjacent breaks among the plurality of breaks on the base substrate at least partially overlaps with an orthographic projection of two data lines among the plurality of data lines on the base substrate.

8. The array substrate according to any one of claims 1 to 7, wherein: Each of the first touch electrode lines comprises a first portion and a second portion separated by a break in the plurality of break; The orthographic projections of the first portion and the second portion on the substrate substrate do not overlap with the orthographic projection of the single data line on the substrate substrate, wherein the single data line extends through the region having the break; the first portion being spaced apart from the single data line by a first minimum distance; the second portion is spaced apart from the single data line by a second minimum distance; and The first minimum distance and the second minimum distance are greater than 0.5 μm.

9. The array substrate according to any one of claims 1 to 8, wherein: The orthographic projections of the plurality of second touch electrode lines on the base substrate do not substantially overlap with the orthographic projections of the plurality of data lines on the base substrate.

10. The array substrate according to claim 9, further comprising a plurality of voltage supply lines and a plurality of constant voltage signal lines; and in, An orthographic projection of the plurality of second touch electrode lines on the base substrate at least partially overlaps with an orthographic projection of a combination of the plurality of voltage supply lines and the plurality of constant voltage signal lines on the base substrate.

11. The array substrate according to claim 10, wherein: The plurality of second touch electrode lines include a plurality of first adjacent second touch electrode lines and a plurality of second adjacent second touch electrode lines that are alternately arranged; wherein an orthographic projection of a first adjacent second touch electrode line among the plurality of first adjacent second touch electrode lines on the base substrate is substantially covered by an orthographic projection of a single voltage supply line among the plurality of voltage supply lines on the base substrate; and An orthographic projection of a second adjacent second touch electrode line among the plurality of second adjacent second touch electrode lines on the base substrate at least partially overlaps with an orthographic projection of a single constant voltage signal line among the plurality of constant voltage signal lines on the base substrate.

12. The array substrate according to claim 10, wherein: Each of the first touch electrode lines crosses at least one voltage supply line among the plurality of voltage supply lines, and crosses at least one constant voltage signal line among the plurality of constant voltage signal lines.

13. The array substrate according to any one of claims 1 to 12, further comprising a plurality of anodes; in, The orthographic projections of the plurality of touch electrode lines on the base substrate and the orthographic projections of the plurality of anodes of the plurality of light emitting elements on the base substrate do not substantially overlap.

14. The array substrate according to any one of claims 1 to 12, further comprising a plurality of anodes and a pixel defining layer defining a plurality of sub-pixel openings; in, The orthographic projections of the plurality of touch electrode lines on the base substrate do not overlap at all with the orthographic projections of the light emitting materials in the plurality of sub-pixel openings on the base substrate.

15. The array substrate according to claim 14, wherein: An orthographic projection of each of the plurality of data lines on the base substrate at least partially overlaps with an orthographic projection of a column of the plurality of anodes on the base substrate.

16. The array substrate according to claim 14, wherein: An orthographic projection of each of the plurality of data lines on the base substrate at least partially overlaps with an orthographic projection of the light emitting material in a column of sub-pixel openings among the plurality of sub-pixel openings on the base substrate.

17. The array substrate according to claim 10, further comprising a plurality of first reset signal lines and a plurality of second reset signal lines, which are located in the following layer: the layer is located on a side of the plurality of data lines close to the base substrate; in, The plurality of constant voltage signal lines include a plurality of third reset signal lines; Wherein, the array substrate comprises an interconnected reset signal network, and the interconnected reset signal network comprises the plurality of first reset signal lines, the plurality of second reset signal lines and the plurality of third reset signal lines interconnected together; The plurality of first reset signal lines and the plurality of second reset signal lines extend respectively in directions substantially parallel to the first direction; the plurality of third reset signal lines extend in a direction substantially parallel to the second direction; Each first reset signal line is connected to one or more third reset signal lines among the plurality of third reset signal lines; Each second reset signal line is connected to one or more third reset signal lines among the plurality of third reset signal lines; and Each of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines and is connected to one or more second reset signal lines of the plurality of second reset signal lines.

18. The array substrate according to claim 17, wherein: The plurality of first reset signal lines and the plurality of second reset signal lines are located in a semiconductor material layer, and the semiconductor material layer includes an active layer of one or more transistors of a pixel driving circuit; as well as The plurality of third reset signal lines are located in a second signal line layer, and the second signal line layer is located on a side of the semiconductor material layer away from the base substrate.

19. The array substrate according to any one of claims 1 to 18, wherein: Despite the plurality of breaks, the touch electrode lines in the same touch electrode block remain interconnected; and Parts of discontinuous electrode segments in each of the first touch electrode lines are electrically connected together through an adjacent second touch electrode line and one or more adjacent first touch electrode lines.

20. A display device comprising the array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

Images