Method for suppressing change in background luminous intensity in photoluminescence measurements and method for evaluating semiconductor substrate

Abstract

The problem to be solved by the present invention is to provide a novel technique capable of suppressing changes in background light emission intensity in photoluminescence measurement. The present invention is a method for suppressing a change in background light emission intensity in photoluminescence measurement, the method comprising: a process-modified layer removal step (S10) for removing at least a part of a process-modified layer (11) present on a semiconductor substrate (10); and a photoluminescence measurement step (S30) for acquiring distribution information of crystal defects in the semiconductor substrate (10) by photoluminescence measurement.

Description

Technical Field

[0001] The present invention relates to a method for suppressing variation in background luminescence intensity in photoluminescence measurement and a method for evaluating a semiconductor substrate. Background Art

[0002] Silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), aluminum nitride (AlN) and other compound semiconductors are attracting attention as the next-generation semiconductor materials to replace silicon (Si).

[0003] For example, SiC has an insulation breakdown field that is one order of magnitude larger than Si, a band gap that is three times larger, and a thermal conductivity that is about three times higher. Therefore, SiC is expected to be used in power devices, high-frequency devices, high-temperature working devices, etc.

[0004] However, it is known that there are still many crystal defects in SiC substrates and SiC epitaxial substrates, and these crystal defects have an adverse effect on the characteristics of SiC devices.

[0005] Conventionally, methods for obtaining distribution information of crystal defects include: an etch pit method that uses a strong alkaline melt to preferentially etch crystal defect sites to form pit shapes; and a synchrotron radiation device that uses topography to perform dislocation density evaluation.

[0006] However, since the etching pit method is a destructive inspection that forms a pit shape on the substrate, there is a problem that the inspected substrate cannot be used to manufacture SiC devices. In addition, the dislocation density evaluation using morphology using a synchrotron radiation device requires the use of a large-scale device called a synchrotron radiation device, which makes it difficult to perform simple evaluation.

[0007] In response to such problems, Patent Document 1 describes the use of photoluminescence measurement as a crystal defect evaluation method that does not require destructive inspection and does not use a large-scale synchrotron radiation device.

[0008] Prior art documents

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2021-88469 Summary of the invention

[0011] Problems to be solved by the present invention

[0012] Photoluminescence measurement is a method that irradiates excitation light onto a semiconductor substrate to be measured and measures the light emitted when the excited electrons return to the ground state. In the captured image obtained by photoluminescence measurement, the distribution information of crystal defects can be obtained by comparing the luminescence intensity of the part where crystal defects such as dislocations and stacking faults are observed with the luminescence intensity of the background where these crystal defects are not observed.

[0013] In this specification, the term "background" refers to a region that forms the background of a portion where crystal defects such as dislocations and stacking faults are observed when distribution information of crystal defects in a semiconductor substrate is obtained by photoluminescence measurement, in other words, refers to a region where these crystal defects are not observed.

[0014] As a result of extensive studies, the present inventors have found that when a process-degraded layer and / or macro step bunching (MSB) exists in a semiconductor substrate to be measured, the background emission intensity changes, making it impossible to obtain an accurate captured image.

[0015] The problem to be solved by the present invention is to provide a new technology capable of suppressing the variation of background luminescence intensity in photoluminescence measurement.

[0016] Solutions to the problem

[0017] The present invention for solving the above-mentioned problem is a method for suppressing the change of background luminescence intensity in photoluminescence measurement, the method comprising: a process of removing a processed deteriorated layer for removing at least a portion of a processed deteriorated layer existing on a semiconductor substrate; and a photoluminescence measurement process for acquiring distribution information of crystal defects in the semiconductor substrate by photoluminescence measurement.

[0018] The present invention for solving the above-mentioned problem is a method for suppressing the variation of background luminescence intensity in photoluminescence measurement, the method comprising: a macro-step bunching removal process for removing at least a portion of macro-step bunching existing on a semiconductor substrate; and a photoluminescence measurement process for acquiring distribution information of crystal defects in the semiconductor substrate through photoluminescence measurement.

[0019] The present invention for solving the above-mentioned problem is a method for suppressing the change of background luminescence intensity in photoluminescence measurement, the method comprising: a process of removing a processed deteriorated layer existing on a semiconductor substrate; a macro-step bunching removal process of removing at least a part of the macro-step bunching existing on the semiconductor substrate; and a photoluminescence measurement process of acquiring distribution information of crystal defects in the semiconductor substrate through photoluminescence measurement.

[0020] In a preferred embodiment of the present invention, the process of removing the machine-degraded layer is a process of removing the machine-degraded layer by a thermal etching method.

[0021] In a preferred embodiment of the present invention, the process of removing the machine-degraded layer is a process of removing at least a portion of the machine-degraded layer by wet etching and / or chemical mechanical polishing.

[0022] In a preferred embodiment of the present invention, the macro-step bunching removal process is a process of removing the macro-step bunching by a thermal etching method.

[0023] In a preferred embodiment of the present invention, the macro-step bunching removal process is a process of heating the semiconductor substrate in a SiC—Si equilibrium vapor pressure environment.

[0024] In a preferred embodiment of the present invention, the macro-step bunching removal step is a step of forming a step having a height of less than one unit cell on the surface of the semiconductor substrate.

[0025] In a preferred embodiment of the present invention, the semiconductor substrate is a compound semiconductor.

[0026] The present invention also relates to a method for evaluating a semiconductor substrate. That is, the present invention for solving the above-mentioned problems is a method for evaluating a semiconductor substrate, which measures photoluminescence of a semiconductor substrate from which at least a part of a process-degraded layer has been removed.

[0027] The present invention which solves the above-mentioned problems is a method for evaluating a semiconductor substrate, which performs photoluminescence measurement on a semiconductor substrate from which at least a part of macro-step bunching has been removed.

[0028] The present invention which solves the above-mentioned problems is a semiconductor substrate evaluation method which performs photoluminescence measurement on a semiconductor substrate from which a process-deteriorated layer and macro-step bunching have been removed.

[0029] In a preferred embodiment of the present invention, the semiconductor substrate has a step with a height of less than one unit cell.

[0030] In a preferred embodiment of the present invention, the semiconductor substrate is a compound semiconductor.

[0031] Effects of the Invention

[0032] According to the disclosed technology, a new technology capable of suppressing the variation of background luminescence intensity in photoluminescence measurement can be provided.

[0033] Other objects, features and advantages will become apparent when the following detailed description is read in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is an explanatory diagram showing a process-degraded layer removing step and a macro-step bunching removing step according to the present invention.

[0035] Figure 2 It is an explanatory diagram showing a process-degraded layer removing step and a macro-step bunching removing step according to the present invention.

[0036] Figure 3 It is an explanatory diagram showing the steps of Example 1 and Example 2.

[0037] Figure 4 It is an explanatory diagram showing the process-degraded layer removal step and the macro-step bunching removal step in the first embodiment.

[0038] Figure 5 This is an explanatory diagram showing the macro step cluster forming process in the second embodiment.

[0039] Figure 6 Shown are captured images and intensity distribution obtained in the photoluminescence measurement process of the comparative example.

[0040] Figure 7 A captured image and intensity distribution obtained in the photoluminescence measurement process of Example 1 are shown.

[0041] Figure 8 A captured image and intensity distribution obtained in the photoluminescence measurement process of Example 2 are shown. DETAILED DESCRIPTION

[0042] A preferred embodiment of a method for suppressing changes in background luminescence intensity in photoluminescence measurement and a method for evaluating a semiconductor substrate according to the present invention will be described in detail below with reference to the accompanying drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and can be appropriately modified within the scope of the claims. In addition, in the present specification and the accompanying drawings, in the representation of the Miller index, "-" represents a horizontal line attached to the index immediately following it, and adding "-" in front of the index represents a negative index. In addition, in the description of the following embodiments and the accompanying drawings, similar components are represented by the same reference numerals, and repeated descriptions will be omitted.

[0043] The method for suppressing the variation of background luminescence intensity in photoluminescence measurement according to the present invention may include: a process-deteriorated layer removal step S10 of removing at least a portion of the process-deteriorated layer 11 existing on the semiconductor substrate 10; a macro-step bunching removal step S20 of removing at least a portion of the macro-step bunching MSB on the semiconductor substrate 10; and a photoluminescence measurement step S30 of acquiring distribution information of crystal defects in the semiconductor substrate 10 through photoluminescence measurement.

[0044] Figure 1The embodiment of performing the macro-step bunching removal step S20 after performing the process-deteriorated layer removal step S10 is shown. In this embodiment, the process-deteriorated layer removal step S10 and the macro-step bunching removal step S20 can be understood as separate steps. For example, the macro-step bunching removal step S20 can be performed only on the semiconductor substrate 10 from which the process-deteriorated layer 11 has been removed.

[0045] Figure 2 The embodiment of performing the process-degraded layer removal step S10 and the macro-step bunching removal step S20 simultaneously is shown. In this embodiment, the process-degraded layer 11 and the macro-step bunching MSB can be reduced or removed in one process.

[0046] In the present invention, by performing photoluminescence measurement on the semiconductor substrate 10 from which at least a portion of the process-deteriorated layer 11 has been removed, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed, and a more accurate captured image can be obtained. In addition, the variation of the background luminescence intensity is expected to increase with the increase of the introduction depth of the process-deteriorated layer 11. Therefore, even if the process-deteriorated layer 11 is not completely removed, by removing at least a portion of the process-deteriorated layer 11, the variation of the background luminescence intensity can be suppressed.

[0047] In other words, the present invention is a semiconductor substrate evaluation method including a photoluminescence measurement step of measuring photoluminescence of a semiconductor substrate 10 from which at least a portion of a process-degraded layer 11 has been removed.

[0048] In addition, the term "process-degraded layer" in this specification refers to a layer introduced by mechanical processing of the surface of the semiconductor substrate 10. In addition, whether this "process-degraded layer" is reduced or removed can be confirmed by performing epitaxial growth on the semiconductor substrate 10 from which the process-degraded layer 11 has been removed and observing and evaluating the stacking faults formed during the growth of the epitaxial layer. On the surface from which the process-degraded layer 11 has been reduced or removed, the occurrence of stacking faults formed during the growth of the epitaxial layer is suppressed.

[0049] According to the present invention, by performing photoluminescence measurement on the semiconductor substrate 10 from which at least a portion of the macro step bunching MSB has been removed, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed, and a more accurate captured image can be obtained. In addition, it is expected that the higher the density of the macro step bunching MSB, the greater the variation of the background luminescence intensity. Therefore, even if all the macro step bunching MSBs are not removed, the variation of the background luminescence intensity can be suppressed by removing at least a portion of the macro step bunching MSBs.

[0050] In other words, the present invention is a semiconductor substrate evaluation method including a photoluminescence measurement step of measuring photoluminescence of a semiconductor substrate 10 from which at least a portion of a macro step bunching MSB has been removed.

[0051] In addition, "macro-step bunching" in this specification refers to bunching having a height exceeding one unit cell in a step terrace structure formed on the surface of the semiconductor substrate 10. For example, the following step structure is formed on the surface of SiC: steps 13, which are height difference portions of one or more molecular layers, and step faces 14, which are flat portions exposed by the {0001} plane, are arranged alternately. The steps 13 in the SiC surface have a minimum height (minimum unit) of one molecular layer (0.25 nm), and steps 13 of various heights are formed by bunching (bundling) this one molecular layer into multiple layers. Among the bunched steps 13, those having a height exceeding one unit cell of each polytype are referred to as macro-step bunching MSB. In other words, macro-step bunching MSB is a process 13 of bunching over more than 4 molecular layers (more than 5 molecular layers) in the case of 4H-SiC, and a process 13 of bunching over more than 6 molecular layers (more than 7 molecular layers) in the case of 6H-SiC.

[0052] Furthermore, the present invention is a semiconductor substrate evaluation method, which includes a photoluminescence measurement step of measuring photoluminescence of a semiconductor substrate 10 from which a process-degraded layer 11 and macro-step bunching MSB have been removed.

[0053] Any commonly used material can be used as the material of the semiconductor substrate 10. The material of the semiconductor substrate 10 is, for example, a well-known IV group material such as silicon (Si), germanium (Ge) or diamond (C). In addition, the material of the semiconductor substrate 10 is, for example, a well-known IV-IV group compound semiconductor material such as silicon carbide (SiC). In addition, the material of the semiconductor substrate 10 is, for example, a well-known II-VI group compound semiconductor such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), cadmium telluride (CdTe), etc. Further, the material of the semiconductor substrate 10 is, for example, boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), indium antimonide (InSb), etc. Well-known III-V group compound semiconductor materials. In addition, the material of the semiconductor substrate 10 is, for example, aluminum oxide (Al 2 O 3 ) or gallium oxide (Ga 2 O 3 ) etc. In addition, the semiconductor substrate 10 may have a structure to which known additional atoms used according to the material thereof are appropriately added.

[0054] In addition, as a preferred material for the semiconductor substrate 10 used in the present invention, the above-mentioned silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), aluminum nitride (AlN) and other compound semiconductors. Among them, SiC is a hard and brittle material and is classified as a material that is extremely difficult to process. Therefore, it is not easy to reduce or remove the processing-degraded layer 11 and the macro-step bunching MSB, and the semiconductor substrate 10 with the processing-degraded layer 11 and the macro-step bunching MSB remaining is put on the market, and causes a change in the background luminescence intensity in the photoluminescence measurement.

[0055] The process-degraded layer removal step S10 according to the present invention is a step of removing at least a portion of the process-degraded layer 11 introduced by a process involving mechanical processing such as slicing, rough grinding, fine grinding, chemical mechanical polishing, etc. More preferably, it is a step of removing the process-degraded layer 11 of the semiconductor substrate 10 and exposing the bulk layer 12.

[0056] For the process-degraded layer removal step S10, a conventional method capable of removing at least a portion of the process-degraded layer 11 may be used. For example, thermal etching, wet etching, CMP chemical polishing (so-called chemical mechanical polishing), and other gas etching methods may be used. As a thermal etching method, for example, H 2 Etching, Si vapor pressure etching, sublimation etching, etc. More preferably, the sublimation etching method described in the examples is used.

[0057] In addition, since chemical mechanical polishing involves mechanical processing, the processing-degraded layer 11 can be introduced during the chemical mechanical polishing process, but since it is milder than the processing-degraded layer 11 introduced in previous processes (such as slicing, rough grinding and final grinding), it can be used as a method capable of removing at least a portion of the processing-degraded layer 11.

[0058] By performing the process-degraded layer removing step S10 , the process-degraded layer 11 introduced near the surface of the semiconductor substrate 10 can be reduced or removed, and changes in the background emission intensity in the photoluminescence measurement can be suppressed.

[0059] The macro step bunching removal process S20 according to the present invention is a process of removing at least a portion of the macro step bunching MSB present on the surface of the semiconductor substrate 10. More preferably, it is a process of removing the macro step bunching MSB of the semiconductor substrate 10 and forming a step 13 having a height of less than 1 unit cell on the surface.

[0060] The macro step bunching removal step S20 may adopt an existing method capable of removing at least a portion of the macro step bunching MSB. For example, a thermal etching method and an epitaxial growth method may be cited. As a thermal etching method, for example, H2 Etching, Si vapor pressure etching, sublimation etching, etc. As the epitaxial growth method, a sublimation method such as a CVD method and a near sublimation method can be used. More preferably, the sublimation etching method described in the examples described later is preferably used.

[0061] By performing the macro-step bunching removal process S20 , macro-step bunching MSB formed on the surface of the semiconductor substrate 10 may be reduced or removed, and variation in background luminescence intensity in photoluminescence measurement may be suppressed.

[0062] In addition, the macro-step bunching removal step S20 can be performed simultaneously with the process-deteriorated layer removal step S10 (see Figure 2 ).

[0063] The photoluminescence measurement process S30 according to the present invention may adopt existing photoluminescence measurement, and is a process of performing photoluminescence measurement using an apparatus conventionally used to measure crystal defects in the semiconductor substrate 10 .

[0064] In the photoluminescence measurement, excitation light having energy greater than the band gap of the semiconductor substrate 10 is irradiated. This excites holes and electrons present in the semiconductor substrate 10, and emits light when they recombine. Since the characteristics of the emitted light differ depending on the type of crystal defect, the presence or absence of various crystal defects can be determined by measuring the emitted light.

[0065] In addition, PL mapping can be used to measure the in-plane distribution of photoluminescence intensity by two-dimensionally scanning the semiconductor substrate 10 with excitation light, or PL mapping can be used to simultaneously excite a specific area of ​​the semiconductor substrate 10 by irradiating a large range with excitation light and using a CCD camera or the like to measure the in-plane distribution of photoluminescence intensity.

[0066] Example

[0067] Hereinafter, the present invention will be described in more detail based on Example 1, Example 2 and Comparative Example. In addition, the present invention is not limited to the following contents.

[0068] In Example 1, Example 2 and Comparative Example, a 6-inch wafer of single-crystal n-type 4H-SiC after chemical mechanical polishing was used as semiconductor substrate 10. This semiconductor substrate 10 had a main surface inclined at an off angle of 4° in the <11-20> direction relative to the (0001) plane.

[0069] Figure 3 It is an explanatory diagram showing each process of the Example and the comparative example of this invention.

[0070] First, the photoluminescence measurement step S30 is performed on the semiconductor substrate 10 (comparative example).

[0071] Next, the semiconductor substrate 10 subjected to the photoluminescence measurement as a comparative example was subjected to the process-degraded layer removal step S10 and the macro-step bunching removal step S20 , and was subjected to the photoluminescence measurement step S30 under the same conditions as in Example 1 (Example 1).

[0072] Finally, the semiconductor substrate 10 subjected to the photoluminescence measurement as in Example 1 is subjected to a macro step bunching forming step S40 for forming a macro step bunching MSB, and the photoluminescence measurement step S30 is subjected to the same conditions as in the comparative example and Example 1.

[0073] The apparatus used in the process-deteriorated layer removal step S10, the macro-step bunching removal step S20, and the macro-step bunching formation step S40 is, for example, the apparatus disclosed in International Publication No. 2021 / 025085, and is equipped with a main body container 20, a high melting point container 30, and a heating furnace (not shown) that can accommodate the main body container 20 and the high melting point container 30 and can be heated to form a temperature gradient (see Figure 4 and Figure 5 ).

[0074] The main body container 20 can be configured to accommodate the semiconductor substrate 10, and it can be configured as long as it is a structure that generates vapor pressure of gas phase seeds containing Si element and gas phase seeds containing C element in the internal space during heat treatment. For example, the main body container 20 is made of a material containing SiC, preferably a material containing single crystal SiC and / or polycrystalline SiC. In addition, preferably, the main body container 20 has a form in which SiC is exposed on at least a part of the inner surface of the container.

[0075] exist Figure 4 and Figure 5 In the embodiment shown, the entire main body container 20 is made of single crystal SiC and / or polycrystalline SiC. By heating the main body container 20 made of such a material, vapor pressure of gas phase seeds containing Si element and gas phase seeds containing C element can be generated in the main body container 20.

[0076] That is, the atmosphere in the main body container 20 after the heat treatment is preferably a vapor pressure atmosphere of a mixed system of gas phase seeds containing Si element and gas phase seeds containing C element. Examples of gas phase seeds containing Si element include Si, Si 2 、Si 3 、Si 2 C. SiC 2 , SiC. In addition, as the gas phase seeds containing the C element, Si 2 C. SiC 2 , SiC, C. That is, the main body container 20 is in a state where the SiC-based gas exists.

[0077] In addition, any structure may be used as long as the vapor pressure of the gas phase seeds containing Si element and the gas phase seeds containing C element can be generated in the internal space during the heat treatment of the main body container 20. For example, a structure in which single crystal SiC or polycrystalline SiC is exposed on a part of the inner surface, or a structure in which single crystal SiC or polycrystalline SiC is arranged alone inside the main body container 20 may be shown.

[0078] like Figure 4 and Figure 5 As shown, the main body container 20 is a fitting container of an upper container 21 and a lower container 22 that can fit together. A small gap 33 is formed at the fitting portion of the upper container 21 and the lower container 22, and the main body container 20 is configured to be able to be exhausted (vacuumed) through the gap 23. That is, when exhausting, the interior of the main body container 20 is configured as a semi-enclosed space during exhaust.

[0079] The term "semi-enclosed space" used herein refers to a space in which the interior of a container can be evacuated but at least a portion of the steam generated in the container can be restricted. Such a semi-enclosed space can be formed in a container.

[0080] In addition, depending on whether the Si vapor supply source 24 is configured in the main container 20, a method of heating the semiconductor substrate 10 in a SiC-Si equilibrium vapor pressure environment or a method of heating the semiconductor substrate 10 in a SiC-C equilibrium vapor pressure environment can be selected.

[0081] The SiC—Si equilibrium vapor pressure environment refers to a vapor pressure environment when SiC (solid) and Si (liquid phase) are in phase equilibrium via a gas phase, and by performing etching or growth in this environment, macro step bunching MSB on the surface of the semiconductor substrate 10 can be removed.

[0082] The SiC-Si equilibrium vapor pressure environment can be formed by placing the semiconductor substrate 10 in a semi-enclosed space where the atomic ratio Si / C exceeds 1 and heating it. For example, when the semiconductor substrate 10 and the Si vapor supply source 24 (Si particles, etc.) satisfying the stoichiometric ratio of 1:1 are placed in a container (main body container 20) made of SiC satisfying the stoichiometric ratio of 1:1, the atomic ratio Si / C in the semi-enclosed space exceeds 1 (see Figure 4 ).

[0083] The SiC—C equilibrium vapor pressure environment is a vapor pressure environment when SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase, and by etching or growing in this environment, macro step bunching MSB can be formed on the surface of the semiconductor substrate 10 .

[0084] The SiC-C equilibrium vapor pressure environment can be formed by placing the semiconductor substrate 10 in a semi-enclosed space with an atomic ratio Si / C of 1 or less and heating it. For example, when the semiconductor substrate 10 satisfying the stoichiometric ratio of 1:1 is placed in a container (main body container 20) made of SiC satisfying the stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body container 20 is 1 (see Figure 5 ). In addition, the atomic ratio Si / C may be set to 1 or less by configuring a C vapor supply source (C particles, etc.).

[0085] By heating the main body container 20 with a temperature gradient in the heating furnace, the semiconductor substrate 10 can be etched by transporting Si atoms and C atoms on the semiconductor substrate 10 side to the main body container 20 side, using the temperature difference generated between the semiconductor substrate 10 and the main body container 20 as a driving force. That is, due to the temperature gradient formed by the heating furnace, the temperature of at least a portion of the main body container 20 (for example, the bottom surface of the lower container 22) becomes lower than that of the semiconductor substrate 10, thereby generating a driving force to transport Si atoms and C atoms on the semiconductor substrate 10 side to the main body container 20 side.

[0086] More specifically, when the temperature of the surface to be etched of the semiconductor substrate 10 is compared with the temperature of the bottom surface of the lower container 22 facing the surface, heating is performed so that the temperature on the semiconductor substrate 10 side is higher and the temperature on the lower container 22 side is lower. In this way, by forming a space having a temperature difference between the semiconductor substrate 10 and the lower container 22 in the main body container 20, the Si atoms and C atoms on the semiconductor substrate 10 side can be transported to the lower container 22 using the temperature difference as a driving force. In addition, although not shown, a substrate holder for holding the semiconductor substrate 10 may be provided.

[0087] In addition, epitaxial growth may be performed on the surface of the semiconductor substrate 10 by reversing the temperature gradient. For example, as the macro-step bunching removal step S20, epitaxial growth may be performed in a SiC-Si equilibrium vapor pressure environment to remove the macro-step bunching MSB on the surface of the semiconductor substrate 10. Furthermore, as the macro-step bunching formation step S40, epitaxial growth may be performed in a SiC-C equilibrium vapor pressure environment to form the macro-step bunching MSB on the surface of the semiconductor substrate 10.

[0088] The high melting point container 30 is configured to contain a high melting point material. For example, C as a general heat-resistant component, W, Re, Os, Ta, Mo as a high melting point metal, and Ta as a carbide can be cited. 9 C 8 、HfC、TaC、NbC、ZrC、Ta 2 C, TiC, WC, MoC, HfN as nitride, TaN, BN, Ta2 N, ZrN, TiN, HfB as boride 2 , TaB 2 , ZrB 2 NB 2 , TiB 2 , polycrystalline SiC, etc.

[0089] Similar to the main body container 20, the high melting point container 30 is a fitting container including an upper container 31 and a lower container 32 that can fit together, and is configured to accommodate the main body container 20. A small gap 33 is formed at the fitting portion of the upper container 31 and the lower container 32, and the interior of the high melting point container 30 is exhausted (vacuumed) through the gap 33. In other words, the interior of the high melting point container 30 is configured as a semi-enclosed space when vacuuming.

[0090] The high melting point container 30 has a Si vapor supply source 34 capable of supplying a vapor pressure of a gas phase seed containing Si element into the high melting point container 30. The Si vapor supply source 34 can be any structure that generates Si vapor in the high melting point container 30 during heat treatment, and examples thereof include solid Si (single crystal Si wafer, Si particles such as Si powder), Si compounds, etc. For example, a layer made of a silicided high melting point material can be provided inside the high melting point container 30.

[0091] In addition to this, any structure may be used as long as the vapor pressure of the gaseous species containing the Si element is generated in the high melting point container 30 during the heat treatment.

[0092] (Comparative Example)

[0093] For the 4H-SiC after chemical mechanical polishing, which is believed to have a residual process-degraded layer 11, a PL image of the comparative example is obtained by PL imaging using a commercially available photoluminescence measurement device (photoluminescence measurement step S30). In the photoluminescence measurement, the wavelength of the excitation light is 313 nm, and the receiving filter uses a 750 nm high-pass filter.

[0094] (Example 1)

[0095] For the semiconductor substrate 10 that has completed the photoluminescence measurement step S30 in the comparative example, etching was performed at 1800 degrees for 2 hours in a SiC-Si equilibrium vapor pressure environment to manufacture a semiconductor substrate 1 in which the process-deteriorated layer 11 was removed and there was no macro-step bunching MSB on the surface (process-deteriorated layer removal step S10 and macro-step bunching removal step S20, see Figure 3 and Figure 4). Thereafter, photoluminescence measurement was performed under the same conditions as in the comparative example, and a captured image of Example 1 was obtained (photoluminescence measurement process S30). In addition, the presence or absence of macro step bunching MSB was confirmed by SEM and AFM. A step 13 having a height of 1.0 nm or less was formed on the surface of the semiconductor substrate 10 of Example 1.

[0096] (Example 2)

[0097] The semiconductor substrate 10 having completed the photoluminescence measurement step S30 in Example 1 is etched at 1600 degrees for 10 minutes in a SiC-C equilibrium vapor pressure environment to manufacture a semiconductor substrate 10 in which the process-degraded layer 11 is removed and macro-step bunching MSB exists on the surface (macro-step bunching forming step S40, see Figure 3 and Figure 5 ). Thereafter, photoluminescence measurement was performed under the same conditions as those of the comparative example and the embodiment 1, and a photographed image of the embodiment 2 was obtained (photoluminescence measurement process S30). In addition, the presence or absence of macro step bunching MSB was confirmed by SEM and AFM. On the surface of the semiconductor substrate 10 of the embodiment 2, a step 13 having a height greater than 1.0 nm (i.e., macro step bunching MSB) was formed.

[0098] Figure 6 The captured image and the intensity distribution obtained in the photoluminescence measurement step S30 of the comparative example are shown.

[0099] Figure 7 The captured image and intensity distribution obtained in the photoluminescence measurement step S30 of Example 1 are shown.

[0100] Figure 8 The captured image and intensity distribution obtained in the photoluminescence measurement step S30 of Example 2 are shown.

[0101] also, Figure 6 , Figure 7 and Figure 8 The captured image and intensity distribution in the figure are observed at the same point. The portion that looks like a black line in the captured image is a basal plane dislocation, and the portion that looks like a black dot is a threading dislocation. In the intensity distribution, PL intensity information (PL intensity) and position information (distance) are extracted in a manner that crosses the same basal plane dislocation.

[0102] From the captured image and intensity distribution of the comparative example ( Figure 6 ) It can be seen that in the semiconductor substrate 10 where the processed altered layer 11 remains, the background luminescence intensity varies greatly, and it can be seen that the luminescence intensity of the part where the crystal defects are observed is larger than the background, making it difficult to obtain a contrast in luminescence intensity.

[0103] From the captured images and intensity distribution of Example 1 ( Figure 7 ) from the semiconductor substrate 10 in which the processed degenerate layer 11 and the macro-step bunching MSB have been removed, it can be seen that the change in the background luminescence intensity is suppressed, and the contrast between the luminescence intensity of the part where the crystal defects are observed and the background luminescence intensity is clearly visible.

[0104] From the captured images and intensity distribution diagram of Example 2 ( Figure 8 ) It can be seen that in the semiconductor substrate 10 formed with the macro step bunching MSB, the variation of the background luminous intensity is suppressed, and the contrast between the luminous intensity of the portion where the crystal defect is observed and the luminous intensity of the background is obtained compared with the comparative example.

[0105] That is, when the comparative example, Example 1, and Example 2 are compared, it can be seen that in Example 1 in which the process-degraded layer 11 and the macro-step bunching MSB have been removed, the change in the background luminescence intensity is suppressed (see Figure 7 ).

[0106] As described above, it is clear that by removing the process-degraded layer 11 of the semiconductor substrate 10, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed. In addition, it is suggested that by reducing the process-degraded layer 11 of the semiconductor substrate 10, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed.

[0107] Furthermore, when the comparative example and the embodiment 2 are compared, it can be seen that in the comparative example 2 in which the process-deteriorated layer 11 has been removed, the change in the background luminescence intensity is suppressed (see Figure 8 ).

[0108] As described above, it is known that by removing the macro step bunching MSB of the semiconductor substrate 10, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed. In addition, it is suggested that by reducing the macro step bunching MSB of the semiconductor substrate 10, the variation of the background luminescence intensity in the photoluminescence measurement can be suppressed.

[0109] Furthermore, the present invention is an evaluation method of a semiconductor substrate, which includes a photoluminescence measurement step S30 before and after the processing deteriorated layer removal step S10 and / or the macro-step bunching removal step S20.

[0110] For example, Embodiment 1 includes: a first photoluminescence measurement step S31 of obtaining distribution information of crystal defects in a semiconductor substrate by photoluminescence measurement; a process-deteriorated layer removal step S10 of removing at least a portion of a process-deteriorated layer 11 present in the semiconductor; a macro-step bunching removal step S20 of removing at least a portion of macro-step bunching MSB present in the semiconductor substrate 10; and a second photoluminescence measurement step S32 of obtaining distribution information of crystal defects in the semiconductor substrate by photoluminescence measurement.

[0111] In this way, by including the photoluminescence measurement step S30 before and after the processing deteriorated layer removal step S10 and / or the macro-step bunching removal step S20 , crystal defects in the semiconductor substrate 10 can be appropriately evaluated.

[0112] Specifically, in the first photoluminescence measurement step S31, if it is difficult to evaluate crystal defects due to changes in background luminescence intensity, by performing the second photoluminescence measurement step S32 after performing the processing deterioration layer removal step S10 and / or the macro-step bunching removal step S20, crystal defects present in the bulk layer 12 of the semiconductor substrate 10 can be evaluated.

[0113] In addition, in the comparative example and the embodiment, the crystal defects in the bulk layer 12 of the SiC substrate are observed as an example of the semiconductor substrate 10, but the present invention is not limited thereto. For example, the semiconductor substrate 10 may be a SiC epitaxial substrate having an epitaxial layer, or may be made of other compound semiconductor materials.

[0114] Explanation of symbols

[0115] 10 Semiconductor substrate

[0116] 11 Processing metamorphic layer

[0117] 12 Body layer

[0118] 13 steps

[0119] 14 Step

[0120] 20 Main container

[0121] 30 High Melting Point Container

[0122] S10 Machining Deteriorated Layer Removal Process

[0123] S20 Macro-step bunching removal process

[0124] S30 Photoluminescence Measurement Process

[0125] S40 Macro step bunching process

[0126] MSB macro step bunching.

Claims

1. A method for suppressing changes in background luminescence intensity in photoluminescence measurement, the method comprising: a process of removing a layer damaged by machining to remove at least a portion of a layer damaged by machining on the semiconductor substrate; A photoluminescence measurement process for acquiring distribution information of crystal defects in the semiconductor substrate by photoluminescence measurement.

2. A method for suppressing changes in background luminescence intensity in photoluminescence measurement, the method comprising: a macro-step bunching removal step of removing at least a portion of the macro-step bunching present on the semiconductor substrate; A photoluminescence measurement process for acquiring distribution information of crystal defects in the semiconductor substrate by photoluminescence measurement.

3. A method for suppressing changes in background luminescence intensity in photoluminescence measurement, the method comprising: a process of removing a layer damaged by machining to remove at least a portion of a layer damaged by machining on the semiconductor substrate; a macro-step bunching removal step of removing at least a portion of the macro-step bunching present on the semiconductor substrate; A photoluminescence measurement process for acquiring distribution information of crystal defects in the semiconductor substrate by photoluminescence measurement.

4. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to claim 1 or 3, wherein: The process-degraded layer removal step is a step of removing the process-degraded layer by a thermal etching method.

5. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to claim 1 or 3, wherein: The process of removing the process-degraded layer is a process of removing at least a portion of the process-degraded layer by wet etching and / or chemical mechanical polishing.

6. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to claim 2 or 3, wherein: The macro-step bunching removal process is a process of removing the macro-step bunching by a thermal etching method.

7. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to claim 2 or 3, wherein: The macro-step bunching removal process is a process of heating the semiconductor substrate in a SiC—Si equilibrium vapor pressure environment.

8. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to claim 2 or 3, wherein: The macro-step bunching removal step is a step of forming a step having a height of one unit cell or less on the surface of the semiconductor substrate.

9. The method for suppressing changes in background luminescence intensity in photoluminescence measurement according to any one of claims 1 to 3, wherein: The semiconductor substrate is a compound semiconductor.

10. A method for evaluating a semiconductor substrate, comprising measuring photoluminescence of a semiconductor substrate from which at least a portion of a process-deteriorated layer has been removed.

11. A method for evaluating a semiconductor substrate, comprising performing photoluminescence measurement on a semiconductor substrate from which at least a portion of macro-step bunching has been removed.

12. A method for evaluating a semiconductor substrate, comprising measuring photoluminescence of a semiconductor substrate from which a process-deteriorated layer and macro-step bunching have been removed.

13. The semiconductor substrate evaluation method according to any one of claims 10 to 12, wherein: The semiconductor substrate has a step with a height less than one unit cell.

14. The method for evaluating a semiconductor substrate according to any one of claims 10 to 12, wherein: The semiconductor substrate is a compound semiconductor.

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