Oxidized barrier layer for CVD immersion treatment

Abstract

A method of forming an oxidized barrier layer in a semiconductor structure includes forming a contact layer on an exposed surface of a semiconductor region of the semiconductor structure in a first processing chamber, where the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) having a germanium (Ge) ratio ranging between 60% and 100%, and forming an oxidation barrier layer including gallium (Ga) on the contact layer by applying a liquid precursor containing gallium (Ga) to a surface of the contact layer in a first processing chamber.

Description

Technical Field

[0001] Embodiments described herein relate generally to semiconductor device fabrication and, more particularly, to systems and methods for forming contacts within semiconductor structures. Background Art

[0002] Multi-gate metal oxide semiconductor field effect transistors (MOSFETs), such as complementary metal oxide semiconductor (CMOS) devices, face challenges in manufacturability due to their three-dimensional (3D) design and small size. In advanced CMOS devices, an epitaxial layer of silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) is often used to reduce the contact resistivity to 10 -9 Ω·cm 2 range, and achieve the performance required to achieve advanced CMOS technology. Typically, the p-type epitaxial layer is formed of silicon germanium (SiGe) with a high germanium (Ge) concentration, such as about 60% and about 80%, or in some cases 100%, in order to minimize contact resistance. However, it is known that silicon germanium (SiGe) epitaxial layers with high germanium (Ge) concentrations undergo rapid surface oxidation in an atmospheric environment, resulting in the formation of germanium oxides and sub-oxides. These oxide layers may produce residual oxygen at the interface between the silicon germanium (SiGe) epitaxial layer and the silicide metal layer formed on the epitaxial layer, thereby increasing the contact resistivity. These oxide layers can be removed by using a sputtering-based pre-cleaning process, but this may result in adverse effects, such as the generation of crystal defects, deactivation of dopants, and removal of materials in the epitaxial layer, all of which can lead to reduced electrical performance. Sputtering-based pre-cleaning processes may also result in degradation of surrounding dielectric structures (e.g., enlargement of trench critical dimensions (CD), rounding of top corners).

[0003] Therefore, there is a need for methods and systems that can prevent or delay oxidation of a portion of a silicon germanium (SiGe) semiconductor device having a high germanium (Ge) concentration in an atmospheric environment. Summary of the invention

[0004] Embodiments of the present disclosure provide a method for forming an oxidation barrier layer in a semiconductor structure. The method includes forming a contact layer on an exposed surface of a semiconductor region of the semiconductor structure in a first processing chamber, wherein the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) with a germanium (Ge) ratio ranging between 60% and 100%, and forming an oxidation barrier layer including gallium (Ga) on the contact layer by applying a liquid precursor containing gallium (Ga) to the surface of the contact layer in the first processing chamber.

[0005] Embodiments of the present disclosure also provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor region including a first material, wherein the exposed surface of the semiconductor region is disposed in an opening formed in a dielectric layer disposed above the semiconductor region, performing a selective epitaxial deposition process including a first deposition process and a first etching process to form a contact layer including a second material on the exposed surface of the semiconductor region, performing an immersion process to form an oxidation barrier layer on the contact layer, performing a second deposition process to form a metal layer on the oxidation barrier layer, and performing a metal filling process to form a contact plug in the opening in the dielectric layer, wherein the selective epitaxial deposition process and the immersion process are performed without destroying a vacuum environment.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber and a system controller, wherein the system controller is configured to cause the processing system to form a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in the first processing chamber, wherein the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) with a germanium (Ge) ratio ranging between 60% and 100%, and to form an oxidation barrier layer including gallium (Ga) on the contact layer in the first processing chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0008] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0009] Figure 2A is a cross-sectional view of a processing chamber according to one or more embodiments.

[0010] Figure 2B yes Figure 2A An enlarged view of a portion of a processing chamber.

[0011] Figure 3 is a cross-sectional view of a processing chamber according to one or more embodiments.

[0012] Figure 4 A process flow diagram of a method of forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure is depicted.

[0013] Figure 5A, 5B , 5C, 5D and 5E correspond to Figure 4 Cross-sectional views of a portion of a semiconductor structure at various stages of the process.

[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0015] Embodiments described herein provide methods and systems for forming contacts including an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium) having an oxidation barrier layer at selected portions of a structure used to form a CMOS device (e.g., on an exposed surface of a silicon germanium layer). These methods and systems may be particularly useful for forming an epitaxial layer including silicon germanium with a high germanium concentration in a semiconductor structure having a region including silicon germanium and a dielectric layer formed thereon, the epitaxial layer being selectively located over an opening or feature (e.g., a contact trench) formed in the dielectric layer. Unlike conventional processes that require an etching process to remove germanium oxides on the surface of the epitaxial layer (which tend to damage the fabricated semiconductor structure after exposure to an atmospheric environment), the processes described herein are configured to form an oxidation barrier layer over the epitaxial layer, which avoids or delays oxidation of the epitaxial layer in an atmospheric environment during transition from epitaxial processing to subsequent processing such as silicidation, patterning, etc.

[0016] Figure 1 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in and transferred between the various chambers without exposing the substrates to an environment external to the processing system 100 (e.g., an atmospheric environment that may exist in a wafer fab). For example, substrates can be processed in and transferred between the various chambers that are maintained in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment in various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of substrates.

[0017] Examples of processing systems that may be appropriately modified in accordance with the teachings provided herein include the commercially available RT-PCR system from Applied Materials, Inc. located in Santa Clara, California. or Integrated processing system or other suitable processing system. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0018] exist Figure 1 In the illustrated example of FIG. 1 , the factory interface 102 includes a docking station 132 and a factory interface robot 134 for transferring substrates. The docking station 132 is adapted to receive one or more front opening wafer transfer boxes (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the corresponding factory interface robot 134, the blade being adapted to transfer the substrate from the factory interface 102 to the load lock chambers 104, 106.

[0019] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102, and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118, and respective ports 152, 154 coupled to the processing chambers 120, 122. Likewise, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118, and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 may be, for example, slit valve openings having slit valves for transferring substrates therethrough by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from being transferred between the respective chambers. In general, any port may be open to transfer a substrate therethrough. Otherwise, the port is closed.

[0020] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, coarse pumps), gas sources, various valves, and conduits that are fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from a FOUP 136 to a load lock chamber 104 or 106 via a port 140 or 142. The gas and pressure control system then pumps down the pressure of the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 with an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down of the load lock chamber 104 or 106 facilitates transferring substrates between the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 , for example.

[0021] When the substrate is in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 via the port 144 or 146. The transfer robot 112 can then transfer the substrate to any processing chamber 120, 122 and / or between any processing chambers 120, 122 via the corresponding ports 152, 154 for processing, and transfer the substrate to the holding chamber 116, 118 via the corresponding ports 148, 150 to hold and await further transfer. Likewise, the transfer robot 114 can access substrates in the holding chamber 116 or 118 via the port 156 or 158, and can transfer the substrates to any processing chamber 124, 126, 128, 130 and / or between any processing chamber 124, 126, 128, 130 via the corresponding ports 160, 162, 164, 166 for processing, and transfer the substrates to the holding chamber 116, 118 via the corresponding ports 156, 158 for holding awaiting further transfer. The transfer and holding of substrates within and between chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0022] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing a substrate. In some examples, the processing chamber 120 may be capable of performing an etching process, the processing chamber 122 may be capable of performing a cleaning process, and the processing chambers 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. The processing chamber 120 may be a Selectra® chamber available from Applied Materials, Inc., Santa Clara, California. TMThe processing chamber 122 may be a SiCoNi etch chamber from Applied Materials, Inc., Santa Clara, California. TM The processing chamber 126, 128 or 130 may be a Centura 1000 from Applied Materials, Inc., Santa Clara, California. TM Epi chamber.

[0023] The system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 can control the operation of the processing system 100 by directly controlling the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate the performance of the processing system 100.

[0024] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuits 174. The CPU 170 may be one of any form of general purpose processor that may be used in an industrial environment. The memory 172 or non-transitory computer readable medium may be accessed by the CPU 170 and may be one or more of memories such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The support circuits 174 are coupled to the CPU 170 and may include caches, clock circuits, input / output subsystems, power supplies, etc. The various methods disclosed herein may generally be implemented by the CPU 170 executing computer instruction codes, such as software routines, stored in the memory 172 (or the memory of a particular processing chamber) under the control of the CPU 170. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to perform processing according to the various methods.

[0025] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as a transfer device in a processing system.

[0026] Figure 2A2 is a cross-sectional view of a processing chamber 200 suitable for performing a pre-cleaning process described in detail below, according to one or more embodiments. The processing chamber 200 may be Figure 1 The processing chamber 122 is shown in FIG. Figure 2B yes Figure 2A An enlarged view of a portion of the processing chamber 200 is shown.

[0027] The processing chamber 200 may be particularly useful for performing a thermal or plasma-based cleaning process and / or a plasma-assisted dry etching process. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system may be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208, which is coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling a process within the processing chamber 200.

[0028] The lid assembly 204 includes a stack of components adapted to provide precursor gases and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power source (not shown) to provide plasma to a conical chamber 222 formed in the lid assembly 204. The lid assembly 204 may also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. A remote plasma chamber (e.g., Figure 2A-2B The processing region 214, the first plate 216 and the second plate 218 in the processing chamber 200 are coupled to the gas source 226 via the remote plasma source 224 (or in the absence of the remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 may include a gas source suitable for providing helium, argon or other inert gas. In some configurations, the gas provided by the gas source 226 can be excited into a plasma, and the plasma is provided to the lid assembly 204 using the remote plasma source 224. In alternative embodiments, the gas source 226 can provide a processing gas, which can be activated by the remote plasma source 224 before being introduced to the surface of the substrate disposed in the processing chamber 200. Reference Figure 2B The tapered chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 to the volume 230 formed in the fourth plate 232 of the lid assembly 204 .

[0029] In some configurations of the lid assembly 204, plasma is generated within the conical chamber 222 by applying energy delivered from a plasma source. In one example, the energy may be generated by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas located in the conical chamber 222. In such configurations of the lid assembly 204, the remote plasma source 224 may not be used or may not be mounted within the lid assembly 204.

[0030] The central conduit 234 formed in the fourth plate 232 is adapted to provide plasma generated species from the volume 230 via the fifth plate 236 to a mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204. The central conduit 234 communicates with the mixing chamber 238 via an opening 242 in the fifth plate 236. The opening 242 may have a diameter that is less than, greater than, or the same as the diameter of the central conduit 234. Figure 2B In the embodiment of FIG. 2 , the opening 242 has a diameter that is the same as the diameter of the central conduit 234 .

[0031] The fourth plate 232 also includes inlets 244 and 246, which are suitable for providing gas to the mixing chamber 238. The inlet 244 is coupled to the first gas source 248, and the inlet 246 is coupled to the second gas source 250. The first gas source 248 and the second gas source 250 may include a process gas and an inert gas, such as an inert gas used as a carrier gas, such as argon and / or helium. The first gas source 248 may include ammonia (NH3) and argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) and argon (Ar).

[0032] like Figure 2BAs shown, in some configurations, the inlet 244 is coupled to the mixing chamber 238 via a cylindrical passage 252 (shown in phantom) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 via a cylindrical passage 256 (shown in phantom) and a hole 258 formed in the fifth plate 236. The size of the holes 254, 258 formed in the fifth plate 236 is generally such that it can uniformly flow the gas provided from its respective gas source 248, 250 into the mixing chamber 238. In one configuration, the diameter of the hole 258 is smaller than the width of the opening defined by the opposite side walls of the cylindrical passage 256 formed in the fourth plate 232. The holes 258 are generally distributed around the circumference of the centerline of the cylindrical passage 256 to provide a uniform fluid flow into the mixing chamber 238. In one configuration, the diameter of the hole 254 is smaller than the width of the opening defined by the opposite side walls of the cylindrical passage 252 formed in the fourth plate 232. The holes 254 are generally distributed circumferentially about the centerline of the cylindrical passage 252 to provide uniform fluid flow into the mixing chamber 238 .

[0033] Inlets 244 and 246 provide respective fluid flow paths that traverse the fourth plate 232 and then turn and penetrate the fifth plate 236 to the mixing chamber 238. The lid assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, wherein the various gases mixed in the lid assembly 204 flow through perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238, providing a flow path from the mixing chamber 238 through the first gas distributor 260. Return to Reference Figure 2A , a baffle plate 264 and a gas distribution plate, such as a second gas distributor 266, are disposed below the lid assembly 204, wherein the second gas distributor may be a gas distribution plate, such as a showerhead.

[0034] Alternatively, a different cleaning process may be used to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 via the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via an independent gas inlet 268 disposed on a side of the chamber body 202 and coupled to a gas source (not shown).

[0035] The support assembly 206 may include a substrate support 270 for supporting a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 via a shaft 276 that extends through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by a bellows (not shown) to prevent vacuum leaks around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0036] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. For some processing operations, the substrate support 270 can be raised to a position close to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated by radiation emitted from the second gas distributor 266 or other radiation source, or by convection or conduction through an intervening gas from the second gas distributor 266. In some processing operations, the substrate can be placed on lift pins 278 to perform additional thermal processing steps, such as performing an annealing step.

[0037] Figure 3 is a cross-sectional view of a processing chamber 300 suitable for performing an epitaxial (Epi) deposition process described below, according to one or more embodiments. The processing chamber 300 may be Figure 1 The processing chamber 126, 128 or 130 is shown in FIG.

[0038] The processing chamber 300 includes an enclosure structure 302 made of a process resistant material, such as aluminum or stainless steel, such as 316L stainless steel. The enclosure structure 302 surrounds various functional elements of the processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, which include a processing volume 310. Reactive species are provided to the quartz chamber 304 by a gas distribution assembly 312, and process byproducts are removed from the processing volume 310 by an outlet port 314, which is typically connected to a vacuum source (not shown).

[0039] The substrate support 316 is adapted to receive a substrate 318 for transfer to the processing volume 310. The substrate support 316 is disposed along a longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be made of a ceramic material or a graphite material coated with a silicon material such as silicon carbide, or other processing resistant material. Reactive species of a precursor reactant material are applied to a surface 322 of the substrate 318, and byproducts may subsequently be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing volume 310 may be provided by a radiation source, such as an upper lamp module 324A and a lower lamp module 324B.

[0040] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 324A and 324B travels through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. If necessary, cooling gas for the upper quartz chamber 306 enters via the inlet 330 and is exhausted via the outlet 332. Precursor reactant materials and dilution, purge and exhaust gases for the processing chamber 300 enter via the gas distribution assembly 312 and are exhausted via the outlet port 314. Although the upper quartz window 326 is shown as curved or convex, since the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure), the upper quartz window 326 can be flat or concave.

[0041] In the processing volume 310, low wavelength radiation used to excite reactive species and assist in adsorption of reactants and desorption of processing byproducts from the surface 322 of the substrate 318 typically ranges from about 0.8 μm to about 1.2 μm, for example, from about 0.95 μm to about 1.05 μm, with various wavelength combinations being provided depending on, for example, the composition of the film on which epitaxial growth is being performed.

[0042] Component gases enter the processing volume 310 via the gas distribution assembly 312. Gases flow from the gas distribution assembly 312 and exit via the outlet port 314, as generally indicated by the flow path 334. The combination of component gases used to clean / passivate the substrate surface or to form the silicon and / or germanium containing film being epitaxially grown is typically mixed before entering the processing volume 310. The overall pressure within the processing volume 310 can be adjusted by adjusting a valve (not shown) on the outlet port 314. At least a portion of the interior surface of the processing volume 310 is covered by a liner 336. In one embodiment, the liner 336 comprises an opaque quartz material. In this way, the chamber wall is insulated from the heat in the processing volume 310.

[0043] The surface temperature in the processing volume 310 can be controlled within a temperature range of about 200° C. to about 600° C. or higher by the flow of cooling gas (which enters through the inlet 330 and exits through the outlet 332) in combination with radiation from the upper lamp module 324A positioned above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of about 200° C. to about 600° C. or higher by adjusting the speed of a blower unit, not shown, and by radiation from a lower lamp module 324B disposed below the lower quartz chamber 308. The pressure in the processing volume 310 can be between about 0.1 Torr and about 600 Torr, such as between about 5 Torr and about 30 Torr.

[0044] The temperature on the surface 322 of the substrate 318 can be controlled by adjusting the power of the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power of both the upper lamp module 324A overlying the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing volume 310 can be about 40 W / cm 2 To about 400W / cm 2 Between, for example, about 80W / cm 2 To about 120W / cm 2 .

[0045] In one aspect, the gas distribution assembly 312 is disposed normal to or in a radial direction 338 relative to a longitudinal axis 320 of the process chamber 300 or substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas across or parallel to a surface 322 of the substrate 318 in the radial direction 338. In one processing application, the process gas is preheated at the point of introduction into the process chamber body 300 to initiate preheating of the gas prior to introduction into the processing volume 310, and / or to break specific bonds in the gas. In this manner, the surface reaction kinetics may be modified independent of the thermal temperature of the substrate 318.

[0046] In operation, precursors for forming blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are provided to the gas distribution assembly 312 from one or more gas sources 340A and 340B. Infrared lamp 342 ( Figure 3 334) can be used to heat the precursor within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in a manner suitable for facilitating introduction into a zone within the gas distribution assembly 312, such as a radially outer zone and a radially inner zone between the outer zones when viewed from a top view. The gas sources 340A, 340B may include valves (not shown) to control the rate of introduction into each zone.

[0047] Gas sources 340A, 340B may include silicon precursors, such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher-order silanes, derivatives thereof, and combinations thereof. Gas sources 340A, 340B may also include germanium-containing precursors, such as germanium (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof. Precursors containing silicon and / or germanium may be used in combination with hydrogen chloride (HCl), chlorine (Cl2), hydrogen bromide (HBr), and combinations thereof. Gas sources 340A, 340B may include one or more of silicon- and germanium-containing precursors in one or both of gas sources 340A, 340B.

[0048] The precursor material is passed through the openings or holes 344 ( Figure 3 346) enters the processing volume 310, wherein in one embodiment, the perforated plate 346 is a quartz material and has holes 344 formed therethrough. The perforated plate 346 is transparent to infrared energy and can be made of a transparent quartz material. In other embodiments, the perforated plate 346 can be any material that is transparent to infrared energy and resistant to processing chemicals and other processing chemicals. The excited precursor material is passed through the holes 344 in the perforated plate 346 and through the channel 348 ( Figure 3 344, and the non-thermal energy from the infrared lamp 342 also passes through the hole 344, the perforated plate 346, and the channel 348, which is facilitated by the reflective material and / or surface disposed on the interior surface of the gas distribution assembly 312, thereby illuminating the flow path 334 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the introduction point to the processing volume 310.

[0049] Figure 4 A process flow diagram of a method 400 for forming a contact layer in a semiconductor structure 500 formed on a substrate according to one embodiment of the present disclosure is depicted. Figure 5A , 5B , 5C, 5D, and 5E are cross-sectional views of a portion of semiconductor structure 500 corresponding to various states of method 400. It should be understood that Figure 5A , 5B 5C, 5D, and 5E illustrate only a portion of the semiconductor structure 500, and the semiconductor structure 500 may contain any number of transistor portions and additional materials having aspects as shown in the figures. It should also be noted that although Figure 4The methods depicted in are described sequentially, but other processing sequences including one or more operations that have been omitted and / or added and / or one or more operations that have been rearranged in another desired order fall within the scope of the embodiments of the present disclosure provided herein.

[0050] The term "substrate" as used herein refers to a material layer that serves as a basis for subsequent processing operations and includes the surface to be cleaned. The substrate may be a silicon-based material or any suitable insulating or conductive material as desired. The substrate may include materials such as: crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire.

[0051] like Figure 5A As shown, the semiconductor structure 500 includes a semiconductor region 502 formed on a substrate (not shown). The semiconductor region 502 may be formed of a first material such as silicon germanium (SiGe) or germanium tin (GeSn) and doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of about 10 20 cm -3 and 5x 10 21 cm -3 between.

[0052] The semiconductor structure 500 further includes a dielectric layer 504 having an opening 506 formed on the semiconductor region 502. The dielectric layer 504 may be formed of a dielectric material such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0053] The semiconductor region 502 may be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the opening 506 may be formed by patterning techniques such as photolithography and etching processes.

[0054] The method 400 begins with a pre-cleaning process at block 410. The pre-cleaning process may be performed in an etching chamber, such as Figure 1 The processing chamber 122 shown in FIG. 2 or the processing chamber 200 shown in FIG.

[0055] The pre-cleaning process removes contaminants, such as a native oxide layer or patterning residues (e.g., fluorocarbons), formed on the exposed surface of the semiconductor region 502 within the opening 506. The pre-cleaning process is used to prepare the exposed surface of the semiconductor region 502 within the opening 506, on which an epitaxial layer may be formed in a subsequent epitaxial deposition process.

[0056] The pre-clean process may include an anisotropic remote plasma assisted dry etching process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluents directionally bombard and remove the epitaxial dielectric layer within the opening 506 .

[0057] The pre-cleaning process may include an isotropic plasma etch process such as SiCoNi TM A dry chemical etching process that uses a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process is selective to oxide layers and therefore does not readily etch silicon, germanium, or nitride layers, whether such layers are amorphous, crystalline, or polycrystalline. The dry chemical etching process has a selectivity of at least about 3:1, typically 5:1 or better, and sometimes 10:1, for oxides relative to silicon or germanium. The dry chemical etching process is also highly selective for oxides relative to nitrides. The dry chemical etching process has a selectivity of at least about 3:1, typically 5:1 or better, and sometimes 10:1, for nitrides.

[0058] The pre-cleaning process may include an inductively coupled plasma (ICP) etching process using plasma formed from gases including chlorine (Cl 2 ) and hydrogen (H 2 ), and a carrier gas including argon (Ar) and helium (He).

[0059] In block 420, a selective epitaxial deposition process is performed to epitaxially form a contact layer 508 on the exposed surface of the semiconductor region 502 within the opening 506, such as Figure 5B The selective epitaxial deposition process can be performed in an epitaxial chamber, such as Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The processing chamber 300 is shown in FIG.

[0060] The contact layer 508 is formed as an interface between the semiconductor region 502 and a metal contact plug to be formed in the opening 506 to minimize parasitic resistance. The contact layer 508 may be formed of a second material, such as silicon germanium (SiGe), having a germanium (Ge) ratio ranging from about 20% to about 100%, for example, between about 60% and about 80%, between about 60% and about 100%, or between about 80% and about 100%. The contact layer 508 may be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of about 10 20 cm -3 and 5x 10 21 cm -3between 0.1 and 0.2, depending on the desired conductive properties of the contact layer 508.

[0061] In some embodiments, the selective epitaxial deposition process includes a first deposition process and a first etching process. The first deposition process is an epitaxial deposition process. The selectivity in the selective epitaxial deposition process can come from the difference in nucleation of the second material on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)) and on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). When the semiconductor structure 500 is exposed to the deposition gas in the first deposition process, the nucleation on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)) can occur at a faster rate than on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), so that an epitaxial layer of the second material can be formed on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)), while an amorphous layer of the second material can be formed on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). In the subsequent first etching process, by means of an appropriate etching gas, the amorphous layer of the second material formed on the exposed surface of the dielectric layer 504 can be removed at a faster rate than the epitaxial layer of the second material formed on the exposed surface of the semiconductor region 502. Therefore, the overall result of the combination of the first deposition process and the first etching process can be the epitaxial growth of the second material on the exposed surface of the semiconductor region 502 while minimizing the growth of the second material (if any) on the exposed surface of the dielectric layer 504.

[0062] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ) or a combination thereof. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4) and digermane (Ge2H6). Depending on the desired conductive properties of the contact layer 508, the dopant source may include, for example, boron or gallium. The dopant source may include the precursor diborane (B2H6). The etching gas includes an etching gas and a carrier gas. The etching gas may include a halogen-containing gas, such as hydrogen chloride (HCl), chlorine (Cl2) or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He) or hydrogen (H2).

[0063] The first deposition process and the first etching process may be performed at a low temperature below about 450° C. and a pressure between 5 Torr and 600 Torr.

[0064] The cycle of the first deposition and the first etching process may be repeated as needed to obtain a desired thickness of the contact layer 508. The thickness of the contact layer 508 may be between about 30 angstroms and about 100 angstroms.

[0065] In block 430, a CVD soak process is performed to form an oxidation barrier layer 510 on the contact layer 508, such as Figure 5C The CVD soak process may be performed in the same epitaxial chamber as the selective epitaxial deposition process in block 420, for example, Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 The processing chamber 300 is shown in FIG.

[0066] In the CVD soak process, the surface of the contact layer 508 is exposed to a gallium (Ga)-containing liquid precursor at a temperature in the range of about 300° C. to about 400° C. to form a thin gallium layer (e.g., an oxidation barrier layer 510) on the contact layer 508. The processing chamber or the semiconductor structure 500 may be heated to a temperature in the range of about 300° C. to about 400° C. The CVD soak process may last for a time of about 1 second to about 60 seconds, for example, about 2 seconds to about 30 seconds. In the CVD soak process, gallium atoms in the gallium-containing liquid precursor diffuse and deposit on the surface of the contact layer 508 to form a thin gallium layer. This thin gallium layer may act as an oxidation barrier layer 510 and prevent or delay oxidation of the contact layer 508 during an air break, which is used to transfer the semiconductor structure 500 from the epitaxial chamber to another processing chamber for subsequent processing, such as a deposition process or a patterning process in block 440.

[0067] In block 440, a second deposition process is performed, such as Figure 5D The second deposition process may be performed in a process chamber different from the epitaxial chamber in blocks 420 and 430, for example Figure 1 The processing chamber 126, 128 or 130 shown in FIG. Figure 3 . During the transfer of the semiconductor structure 500 from the epitaxial chamber used in blocks 420 and 430 to the processing chamber used in block 440, the semiconductor structure 500 may be exposed to the atmosphere. However, due to the oxidation barrier layer 510 thereon, the contact layer 508 may be protected from oxidation during the transfer, or its oxidation may be delayed.

[0068] In the second deposition process, a metal layer 512 is formed on the oxidation barrier layer 510. The metal layer 512 contacts the contact layer 508 and provides electrical connection between the contact plug to be formed in the opening 506 and the semiconductor region 602 while maintaining electrical connection therethrough. The metal layer 512 may be formed of a metal material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), tantalum (Ta), or silicides thereof.

[0069] In some embodiments, the metal source may include a precursor including titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), molybdenum (Mo), or a combination thereof. The second deposition processes may each be performed at a temperature of about 300° C. to about 800° C. and a pressure of 1 to 50 torr.

[0070] The second deposition process performed in block 440 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like, performed at a temperature between about 100° C. and about 300° C.

[0071] In block 450, a metal filling process is performed to form a contact plug 514 in the opening 506, such as Figure 5E As shown. The contact plug 514 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The contact plug 514 may include a metal having a desired work function. The metal filling process in block 450 may include a process chamber, such as in Figure 1 In the process chamber 126, 128 or 130 shown in FIG. 1 , a chemical vapor deposition (CVD) process using a tungsten-containing precursor or a cobalt-containing precursor such as WF6 is performed.

[0072] After the metal filling process, a chemical mechanical planarization (CMP) process may be used to planarize the semiconductor structure 500 .

[0073] Embodiments described herein provide methods and systems for forming a contact epitaxial layer having an oxidation barrier layer thereon in a trench of a semiconductor device. The contact trench structure includes a metal contact plug formed in the trench, and a contact between the contact plug and a silicon-based channel in the semiconductor device. The contact is formed of silicon germanium with a high germanium concentration by a selective epitaxial deposition process, reducing parasitic resistance. The oxidation barrier layer is formed of gallium (Ga) by a CVD immersion process. These methods and systems do not require an etching process to remove the oxide of germanium (Ge), thereby reducing damage to the manufactured semiconductor structure.

[0074] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope, and the scope of the same is determined by the claims that follow.

Claims

1. A method for forming an oxidation barrier layer in a semiconductor structure, comprising: forming, in a first processing chamber, a contact layer on an exposed surface of a semiconductor region of a semiconductor structure, wherein the semiconductor region comprises silicon germanium doped with a p-type dopant, and the contact layer comprises silicon germanium (SiGe) having a germanium (Ge) ratio ranging between 60% and 100%; and In the first process chamber, an oxidation barrier layer including gallium (Ga) is formed on the contact layer by applying a liquid precursor containing gallium (Ga) to a surface of the contact layer.

2. The method according to claim 1, wherein forming the contact layer comprises: Silicon germanium (SiGe) is selectively epitaxially deposited on the exposed surface of the semiconductor region. 3 . The method of claim 1 , wherein the applying the gallium (Ga)-containing liquid precursor is performed at a temperature in a range of 300° C. to 400° C.

4. The method according to claim 1, further comprising: performing a pre-cleaning process on the exposed surface of the semiconductor region in a second processing chamber before forming the contact layer, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed above the semiconductor region; as well as After the oxidation barrier layer is formed, a deposition process is performed in a third process chamber to form a metal layer on the oxidation barrier layer.

5. The method according to claim 4, further comprising: A metal filling process is performed to form contact plugs in the openings in the dielectric layer.

6. The method according to claim 5, wherein The metal layer includes a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

7. The method according to claim 5, wherein The contact plug includes a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

8. A method of forming an electrical contact in a semiconductor structure, comprising: performing a pre-cleaning process on an exposed surface of a semiconductor region comprising a first material, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed above the semiconductor region; performing a selective epitaxial deposition process including a first deposition process and a first etching process to form a contact layer including a second material on the exposed surface of the semiconductor region; performing a soaking process to form an oxidation barrier layer on the contact layer; performing a second deposition process to form a metal layer on the oxidation barrier layer; as well as performing a metal filling process to form a contact plug in the opening of the dielectric layer, The selective epitaxial deposition process and the immersion process are performed without destroying a vacuum environment.

9. The method according to claim 8, wherein The first material includes silicon germanium doped with a p-type dopant.

10. The method according to claim 8, wherein The second material includes silicon germanium (SiGe) having a germanium (Ge) ratio ranging between 60% and 100%.

11. The method according to claim 8, wherein The first deposition process comprises epitaxially depositing the second material on the exposed surface of the semiconductor region, and The first etching process includes an etching process to remove an amorphous layer of the second material formed on the exposed surface of the dielectric layer.

12. The method according to claim 8, wherein The soaking treatment includes applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer at a temperature in a range of 300° C. to 400° C., and The oxidation barrier layer includes gallium (Ga).

13. The method according to claim 8, wherein The metal layer includes a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

14. The method according to claim 8, wherein The contact plug includes a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

15. A processing system comprising: a first processing chamber; as well as A system controller is configured to cause the processing system to: In the first processing chamber, forming a contact layer on an exposed surface of a semiconductor region of a semiconductor structure, the semiconductor region comprising silicon germanium doped with a p-type dopant, and the contact layer comprising silicon germanium (SiGe) having a germanium (Ge) ratio ranging from 60% to 100%; and In the first process chamber, an oxidation barrier layer including gallium (Ga) is formed on the contact layer.

16. The processing system of claim 15, wherein said applying said gallium (Ga) containing liquid precursor is performed at a temperature in a range of 300°C to 400°C.

17. The processing system of claim 15, further comprising: a second processing chamber; and a third processing chamber, wherein the system controller is further configured to cause the processing system to: performing a pre-cleaning process on the exposed surface of the semiconductor region in the second processing chamber before forming the contact layer, wherein the exposed surface of the semiconductor region is disposed within an opening formed in a dielectric layer disposed above the semiconductor region; as well as After forming the oxidation barrier layer, a deposition process is performed in the third process chamber to form a metal layer on the oxidation barrier layer.

18. The processing system of claim 15, further comprising: a fourth processing chamber, wherein the system controller is further configured to cause the processing system to: A metal filling process is performed to form a contact plug within the opening in the dielectric layer.

19. The processing system of claim 18, wherein The metal layer includes a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

20. The processing system of claim 18, wherein The contact plug includes a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

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