Reducing duty cycle mismatch of clock signal of clock tracking circuit

Abstract

One or more embodiments relate to a method. The method includes receiving an uplink / downlink error signal indicating a duty cycle mismatch between a reference clock signal and a changed feedback clock signal representing an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of the changed feedback clock signal to reduce a duty cycle mismatch indicated by the uplink / downlink error signal; and providing a changed feedback clock having a set duty cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 367,434, filed on June 30, 2022, entitled “DUTY CYCLECORRECTION AND MATCHING TECHNIQUE,” under 35 U.S.C. §119(e), the contents and disclosure of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments generally relate to a clock tracking circuit for tracking an output clock to a reference clock. More specifically, one or more embodiments relate to reducing a duty cycle mismatch between a reference clock and a feedback clock representing an output clock generated by the clock tracking circuit to track the reference clock. Background Art

[0004] Clock tracking circuits, such as phase locked loops and delay locked loops, are circuits that are utilized to track clocks and other oscillating signals. The output signal of the clock tracking circuit is locked to the phase and frequency of a reference signal. Clock tracking circuits are utilized in a variety of operating environments, including when two signals having a known relationship are utilized to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram depicting an apparatus to track a clock according to one or more embodiments.

[0007] Figure 2 is a block diagram illustrating an apparatus for matching a duty cycle of a clock according to one or more embodiments.

[0008] Figure 3 is a block diagram depicting an apparatus for generating a changed feedback clock.

[0009] Figure 4A is a timing diagram depicting signals in an example generation of settings, and more specifically delay settings and waveform shaping settings, under the following circumstances, wherein an uplink / downlink error signal indicates a duty cycle mismatch between a changed feedback clock signal and a reference clock signal, and a pulse width of the changed feedback clock signal is narrower than a pulse width of the reference clock signal.

[0010] Figure 4Bis a timing diagram depicting signals in an example generation of a second modified clock signal in a case where the up / down error signal indicates a duty cycle mismatch between the modified feedback clock signal and the reference clock signal, and the pulse width of the modified feedback clock signal is narrower than the pulse width of the reference clock signal (e.g., Figure 4A ).

[0011] Figure 5A is a timing diagram depicting signals in an example generation of settings, and more specifically delay settings and waveform shaping settings, under the following circumstances, wherein an uplink / downlink error signal indicates a duty cycle mismatch between a changed feedback clock signal and a reference clock signal, and a pulse width of the changed feedback clock signal is wider than a pulse width of the reference clock signal.

[0012] Figure 5B is a timing diagram depicting an example generation of a first modified clock signal in a case where the up / down error signal indicates a duty cycle mismatch between the modified feedback clock signal and the reference clock signal, and the pulse width of the modified feedback clock signal is wider than the pulse width reference clock signal (e.g., Figure 5A ).

[0013] Figure 6 is a diagram depicting a calibration process according to one or more embodiments.

[0014] Figure 7 is a flow chart depicting a process to change the duty cycle of a clock to match the duty cycle of another clock.

[0015] Figure 8 is a flow chart depicting a process for setting the duty cycle of a modified feedback clock signal to reduce a duty cycle mismatch indicated by an uplink / downlink error signal.

[0016] Fig. 9 is a flow chart depicting a process to shape the waveform of a changed feedback clock according to one or more embodiments.

[0017] Fig.10 is a flow chart depicting a process for generating settings for a duty cycle shaping circuit.

[0018] Fig.11 is a block diagram depicting an apparatus for generating a changed clock.

[0019] Fig. 12A and Fig. 12B are depicted in Fig.11 A timing diagram of signals during corresponding example operations of the device.

[0020] Fig.13is a flow chart depicting a process to generate a delay setting to set an amount of delay at a variable delay circuit in accordance with one or more embodiments.

[0021] Fig.14 is a diagram illustrating a method for transmitting a signal through a Fig.11 Flowchart of the process of using a waveform shaping circuit to generate a modified feedback clock.

[0022] Fig.15 is a block diagram of an apparatus for detecting duty cycle mismatch and determining settings for controlling pulse width shaping according to one or more embodiments.

[0023] Fig.16 is a block diagram depicting an apparatus to detect duty cycle mismatch and determine settings to control pulse width shaping according to one or more embodiments.

[0024] Fig.17 is a block diagram of circuitry that may be used, in some embodiments, to implement various functions, operations, actions, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0025] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings, specific embodiments in which the present disclosure may be practiced are shown by way of example. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0026] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0027] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary", "by way of example", and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the embodiments of the present disclosure to the specified components, steps, features, functions, etc.

[0028] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0029] In addition, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an embodiment of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0030] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0031] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0032] Embodiments can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operable actions as continuous processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. A process can correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein can be implemented by hardware, software, or both. If implemented in software, the function can be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, and the communication media include any media that is conducive to transferring a computer program from one location to another.

[0033] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0034] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, by at least 95%, or even by at least 99%.

[0035] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0036] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0037] A clock signal, or just "clock," is a signal that oscillates between a high state and a low state in a reliably predictable manner. One or more circuits may respond to the rising or falling edge of the clock to coordinate their actions.

[0038] Clock tracking circuits (e.g., phase-locked loops (PLLs) or delay-locked loops (DLLs), but not limited thereto) are typically used to generate an output clock that tracks a reference clock (e.g., phase and frequency are locked to the reference clock, but not limited thereto). In a typical clock tracking circuit, an oscillator is controlled via one or more control paths to generate an output clock having the phase and frequency of the reference clock. When the phase or frequency of the feedback clock differs from the phase or frequency of the reference clock (also referred to as a phase or frequency "offset" or "error"), the clock tracking circuit generates a control signal via one or more control paths to correct the phase difference and cause the natural frequency of the oscillator to move toward the frequency of the reference clock. The PLL is considered to be "locked" when one or both of the corresponding rising and falling edges of the output clock and the reference clock are aligned within a suitable duration. Single-edge-locked clock tracking circuits use a single edge (i.e., a rising edge or a falling edge) of the output clock and the reference clock to determine the lock state. Double-edge-locked clock tracking circuits use two edges (i.e., a rising edge and a falling edge) of the output clock and the reference clock to determine the lock state.

[0039] At certain frequency ranges, a clock tracking circuit may exhibit jitter, which is the integration of the phase noise in a specific bandwidth.

[0040] Duty cycle distortion and duty cycle mismatch may contribute to jitter or spurs in a clock tracking circuit that compares an output clock (or a feedback signal representing an output clock signal) to a reference clock. Duty cycle distortion is the difference between the duty cycle of a clock signal and an ideal duty cycle, which may be 50%. Duty cycle mismatch is the difference between the respective duty cycles of oscillating signals (e.g., clock signals) that are compared at least in terms of phase or frequency. Some clock tracking circuits individually correct for duty cycle distortion present in a reference clock, an output clock, or both, and assume that they will correct for the duty cycle mismatch between the reference clock and the output clock. However, the inventors of the present disclosure recognized that when the results of individually correcting the duty cycle distortion in two clock signals (e.g., the result for the reference clock and the result for the output clock) are combined, the errors introduced during the respective duty cycle distortion correction processes may be additive (increasing the overall error).

[0041] The inventors of the present disclosure recognized that, as a non-limiting example, it would be desirable to utilize duty cycle mismatch correction of two clock signals by avoiding or reducing at least some of the undesirable effects of applying a separate process to correct the duty cycle distortion discussed above.

[0042] Figure 1 1 is a block diagram depicting an apparatus 100 for tracking a clock (and may also be referred to herein as a "clock tracking circuit 100") according to one or more embodiments. As non-limiting examples, the clock tracking circuit 100 may be a hybrid phase-locked loop (PLL), an analog PLL, a digital PLL, a delay-locked loop (DLL), an injection-locked loop (ILL), or a frequency synthesizer.

[0043] The apparatus 100 includes a phase frequency detector 102, a controller 104, a controlled oscillator 106, and a duty cycle matching circuit 108. The apparatus 100 generally operates to generate an output clock signal 112 that is phase- and frequency-locked to a reference clock signal 110.

[0044] The phase frequency detector 102 generates an up / down error signal 116 that includes information about the phase and frequency difference between the changed feedback clock signal 120 (“changed FB CLK 122”) and the reference clock signal 110. The up / down error signal 116 includes two signals: an up signal and a down signal as discussed below. The phase frequency detector 102 is edge triggered and resets when an edge of the reference clock signal 110 and an edge of the changed feedback clock signal 120 are detected. The phase frequency detector 102 does not distinguish between rising edges or falling edges. As non-limiting examples, the phase frequency detector 102 may be or may include one or more of the following: a phase-frequency detector, a bang-bang phase detector, or a double sampling phase detector.

[0045] The uplink / downlink error signal 116 includes direction information and magnitude information. Such direction information indicates whether the changed feedback clock signal 120 is lagging in phase or leading in phase relative to the reference clock signal 110. Such magnitude information of the uplink / downlink error signal 116 indicates the degree to which the changed feedback clock signal 120 is lagging in phase or leading in phase relative to the reference clock signal 110.

[0046] The modified feedback clock signal 120 matches the feedback clock signal 114 in terms of phase and frequency, and the feedback clock signal 114 indicates the phase and frequency of the output clock signal 112, so the up / down error signal 116 can be used to determine the phase and frequency information about the modified feedback clock signal 120, the feedback clock signal 114, the output clock signal 112, the reference clock signal 110, and the difference between them. The up / down error signal 116 can also be used to determine the pulse width and duty cycle information about the modified feedback clock signal 120, the feedback clock signal 114, the output clock signal 112, the reference clock signal 110, and the difference between them, as discussed below. The up / down error signal 116 is directly provided to the input of the duty cycle matching circuit 108.

[0047] The reference clock signal 110 may be generated by any suitable clock source for a given operating environment. The feedback clock signal 114 may be the same as the output clock signal 112 (e.g., the output clock signal 112 is provided directly to the input of the duty cycle matching circuit 108, but is not limited thereto), or may be a clock signal that indicates the phase, frequency, pulse width, and duty cycle of the output clock signal 112. For example, the phase, frequency, pulse width, and duty cycle of the feedback clock signal 114 may be the same as or different from the output clock signal 112, but in either case, can be related back to the phase, frequency, pulse width, and duty cycle of the output clock signal 112. As a non-limiting example, the feedback clock signal 114 may be a divided version of the output clock signal 112 (frequency divider / buffer not depicted).

[0048] The controlled oscillator 106 is an electronic oscillator for generating an output clock signal 112 at least partially in response to a control signal 118, which can be a digital control signal (i.e., in the case of a digitally controlled oscillator (DCO)), a voltage control signal (i.e., in the case of a voltage controlled oscillator (VCO)), a current control signal (i.e., in the case of a current controlled oscillator (CCO)), or a combination thereof (i.e., a hybrid controlled oscillator (e.g., any combination of digital, voltage, or current controlled, but not limited to such)).

[0049] exist Figure 1In the specific non-limiting embodiment depicted, the device 100 includes a controller 104 to provide a control signal 118 to the controlled oscillator 106 to adjust the output clock signal 112 in response, at least in part, to the up / down error signal 116. The controller 104 may include circuitry (analog, digital, or both) to provide proportional and integral control of the controlled oscillator 106. The controller 104 may include a proportional control path for instantaneously correcting a phase difference between the feedback clock signal 114 and the reference clock signal 110 as indicated by the up / down error signal 116. The controller 104 may include an integral control path to urge the average frequency of the controlled oscillator 106 toward a target frequency (e.g., the frequency of the reference clock signal 110 or a multiple thereof, but not limited thereto) in response to a frequency difference between the feedback clock signal 114 and the reference clock signal 110 as indicated by the up / down error signal 116.

[0050] The lock detection signal 122 indicates whether there is a double edge lock of the device 100. When the lock detection signal 122 indicates double edge lock, the device 100 will naturally align the center of the pulses of the modified feedback clock signal 120 with the center of the pulses of the reference clock signal 110. If the duty cycle of the modified feedback clock signal 120 matches the duty cycle of the reference clock signal 110, the rising and falling edges of the modified feedback clock signal 120 will be aligned with the rising and falling edges of the reference clock signal 110. If the duty cycle of the modified feedback clock signal 120 does not match the duty cycle reference clock signal 110, the increments between the rising and falling edges of the modified feedback clock signal 120 and the rising and falling edges of the reference clock signal 110 will be substantially the same because the centers of the corresponding pulses are aligned by the device 100, as described below. Figure 4A and Figure 4B as discussed in the depicted embodiments.

[0051] In one or more embodiments, lock detect signal 122 is provided to duty cycle matching circuit 108 to indicate conditions for duty cycle matching and reducing duty cycle mismatch between altered feedback clock signal 120 and reference clock signal 110 as discussed below.

[0052] The duty cycle matching circuit 108 generates a modified feedback clock signal 120 in response, at least in part, to the feedback clock signal 114 and the uplink / downlink error signal 116. The modified feedback clock signal 120 is provided to the phase frequency detector 102 for comparison with the reference clock signal 110. The duty cycle matching circuit 108 may generate a modified feedback clock signal 120 having a duty cycle that more closely matches the duty cycle of the reference clock signal 110 than the duty cycle of the feedback clock signal 114. In other words, the modified feedback clock signal 120 and the reference clock signal 110 may exhibit a reduced duty cycle mismatch compared to the feedback clock signal 114 and the reference clock signal 110. The reduced duty cycle mismatch may reduce jitter or spurious exhibited by the device 100.

[0053] Figure 2 2 is a block diagram illustrating an apparatus 200 for matching a duty cycle of a clock according to one or more embodiments. Figure 1 Non-limiting embodiment of the duty cycle matching circuit 108.

[0054] The apparatus 200 generates a modified feedback clock signal 120 having a modified pulse width and duty cycle compared to the feedback clock signal 114. As discussed below, the pulse width and duty cycle of the modified feedback clock signal 120 are set at the apparatus 200 to reduce the duty cycle mismatch between the modified feedback clock signal 120 and the reference clock signal 110 as compared to the duty cycle mismatch between the feedback clock signal 114 and the reference clock signal 110. Thus, when the modified feedback clock signal 120 is provided in place of the feedback clock signal 114, the apparatus 200 may be understood to reduce the duty cycle mismatch between the feedback clock signal 114 and the reference clock signal 110.

[0055] Changing the duty cycle of a clock (e.g., the changed feedback clock signal 120, but not limited thereto) may be referred to herein as “calibrating the duty cycle of the clock,” and the process for performing the duty cycle of the changed clock may be referred to herein as a “calibration process.” In one or more embodiments, the calibration process may include multiple calibration cycles, and during at least some of the calibration cycles, the duty cycle of the changed feedback clock signal 120 may be incrementally set, as discussed below.

[0056] The number of calibration cycles implemented is a matter of design choice and, as a non-limiting embodiment, can be set based on specific operating conditions. In one or more embodiments, as a non-limiting embodiment, the number of calibration cycles can vary when a given calibration process is performed until the duty cycle mismatch is below a predetermined threshold. In one or more embodiments, the number of calibration cycles can vary up to a predetermined upper limit (e.g., counting calibration cycles and exiting when the count value is greater than a predetermined upper limit, but not limited to this). In one or more embodiments, the number of calibration cycles can vary with a predetermined lower limit (e.g., counting calibration cycles, performing at least a lower limit number of calibration cycles before determining that the duty cycle mismatch is below a predetermined threshold, but not limited to this).

[0057] The device 200 includes a logic circuit 202 and a duty cycle shaping circuit 204. In one or more embodiments, the logic circuit 202 and the duty cycle shaping circuit 204 can be synchronized with each other via a local clock signal 212. In one or more embodiments, the local clock signal 212 can be responsive to the reference clock signal 110 (e.g., a delayed version of the reference clock signal 110, but not limited thereto). The calibration cycle can be synchronized with the clock cycle of the local clock signal 212.

[0058] Logic circuit 202 receives lock detect signal 122, uplink signal 208, and downlink signal 210 (which are respectively uplink and downlink of uplink / downlink error signal 116 generated by phase frequency detector 102), determines whether uplink signal 208 or downlink signal 210 leads the other in phase, and generates setting 206 at least in part in response to the determination.

[0059] As discussed above, when the lock detection signal 122 indicates double edge lock, the device 100 will have naturally aligned the center of the pulses of the modified feedback clock signal 120 with the center of the pulses of the reference clock signal 110. If the uplink signal 208 leads the downlink signal 210 in phase, the pulse width of the modified feedback clock signal 120 is wider than the pulse width of the reference clock signal 110, and there is a duty cycle mismatch. If the downlink signal 210 leads the uplink signal 208 in phase, the pulse width of the modified feedback clock signal 120 is narrower than the pulse width of the reference clock signal 110, and there is a duty cycle mismatch.

[0060] Thus, when the lock detection signal 122 indicates double-edge lock, the logic circuit 202 may detect a duty cycle mismatch between the modified feedback clock signal 120 and the reference clock signal 110 in response, at least in part, to an order (e.g., a time order, but not limited thereto) according to which pulses on the uplink signal 208 or the downlink signal 210 are received. Additionally, when the lock detection signal 122 indicates double-edge lock, the logic circuit 202 may determine whether the pulse width of the modified feedback clock signal 120 is narrower or wider than the pulse width of the reference clock signal 110, and generate a setting 206 to instruct the duty cycle shaping circuit 204 to lengthen or shorten the pulse width of the modified feedback clock signal 120.

[0061] In one or more embodiments, the logic circuit 202 may instruct the duty cycle shaping circuit 204 to lengthen or shorten the pulse width of the changed feedback clock signal 120 by a predetermined amount over one or more calibration cycles of the calibration process. Over multiple calibration cycles, the duty cycle of the lock detection signal 122 will change as the pulse width changes, and the duty cycle mismatch between the changed feedback clock signal 120 and the reference clock signal 110 may be reduced.

[0062] The duty cycle shaping circuit 204 is disposed in a signal path of the feedback clock signal 114 and generates the modified feedback clock signal 120 in response at least in part to the feedback clock signal 114 and the setting 206 generated by the logic circuit 202 .

[0063] The modified feedback clock signal 120 is provided to the phase frequency detector 102 (e.g., in place of the feedback clock signal 114). During a given calibration process, as the pulse width and duty cycle of the modified feedback clock signal 120 change, the up / down error signal 116 generated by the phase frequency detector 102 may change, and the changes in the up / down error signal 116 are received at the device 200 and may be utilized to optionally further change the pulse width and duty cycle of the modified feedback clock signal 120. By the end of the given calibration process, the duty cycle mismatch between the modified feedback clock signal 120 and the feedback clock signal 114 is reduced.

[0064] In one or more embodiments, the calibration process may be performed until the duty cycle of the changed feedback clock signal 120 matches the duty cycle of the reference clock signal 110. Alternatively, in one or more embodiments, the calibration process may be performed for only a predetermined number of calibration cycles and then terminate. While performing the calibration process, the duty cycle of the changed feedback clock signal 120 may be changed to be generally more like the duty cycle of the reference clock signal 110, although the respective duty cycles may not necessarily match at the end of the calibration process. In other words, while performing the calibration process, the mismatch between the respective duty cycles of the changed feedback clock signal 120 and the reference clock signal 110 may be reduced, although not completely eliminated.

[0065] Figure 3 1 is a block diagram depicting an apparatus 300 for generating a modified feedback clock, and more specifically, a modified feedback clock signal 120 having a modified duty cycle compared to the duty cycle of the feedback clock signal 114, and more specifically, a modified feedback clock signal 120 having a modified pulse width compared to the pulse width of the feedback clock signal 114, according to one or more embodiments. The apparatus 300 is a block diagram comprising Figure 2 The logic circuit 202 and the duty cycle shaping circuit 204 are non-limiting examples of a portion of a portion of the device 200 .

[0066] The apparatus 300 includes a logic circuit 302, a variable delay circuit 304, a fixed delay circuit 306, and a waveform shaping circuit 330. The waveform shaping circuit 330 includes a wide logic circuit 314, a narrow logic circuit 316, and a multiplexer 308. The logic circuit 302 is Figure 2 The variable delay circuit 304, the fixed delay circuit 306 and the waveform shaping circuit 330 are together a non-limiting embodiment of the logic circuit 202. Figure 2 1 is a non-limiting embodiment of the duty cycle shaping circuit 204 of FIG. 1. The logic circuit 302 receives the binary error signal 1510 and the local clock signal 212, as discussed above. The logic circuit 302 may also receive the lock detection signal 122, but only for ease of discussion and to avoid unnecessarily obscuring the figure, in FIG. Figure 3 The lock detection signal 122 is omitted.

[0067] The variable delay circuit 304 and the fixed delay circuit 306 generate a first delayed clock signal 318 and a second delayed clock signal 320, which are waveform shaped signals utilized by the waveform shaping circuit 330 to shape the waveform of the modified feedback clock signal 120 as discussed below.

[0068] The variable delay circuit 304 receives the local clock signal 212, the delay setting 322, and the feedback clock signal 114, and generates the first delayed clock signal 318 at least in part in response to the delay setting 322 and the feedback clock signal 114. The respective delays implemented by the variable delay circuit 304 correspond to the delay setting 322 generated by the logic circuit 302, which generates the delay setting 322 at least in part in response to the binary error signal 1510.

[0069] Fixed delay circuit 306 receives feedback clock signal 114 and generates second delayed clock signal 320 at least partially in response to feedback clock signal 114. Fixed delay circuit 306 implements a fixed delay. In one or more embodiments, the delay implemented by fixed delay circuit 306 can be hardwired or encoded, or fixed delay circuit 306 can be a variable delay circuit set by a control signal indicating a substantially constant delay (e.g., generated by logic circuit 302 or another logic circuit not depicted, but not limited thereto). In one or more embodiments, the delay implemented by fixed delay circuit 306 corresponds to an internal delay of device 300.

[0070] In one or more embodiments, the variable delay circuit 304 and the fixed delay circuit 306 may internally implement any suitable technique to generate the first delayed clock signal 318 and the second delayed clock signal 320, respectively, based on the feedback clock signal 114. Non-limiting examples of suitable techniques may include enabling multiple buffers or inverters in the signal path to increase delay, and disabling multiple buffers or inverters in the signal path to decrease delay.

[0071] In one or more embodiments, the variable delay circuit 304 or the fixed delay circuit 306 may include a delay unit 326 / delay unit 328, respectively, to achieve the corresponding delay. In one or more embodiments, the delay unit 326 / delay unit 328 may utilize any suitable technology to achieve the delay. By way of non-limiting embodiment, the delay unit 326 / delay unit 328 may be or may include a logic gate or device (e.g., an inverter, a buffer, but not limited thereto) that enables a variable number of such gates or devices to be cascaded. By way of another non-limiting embodiment, the delay unit 326 / delay unit 328 may be or may include a circuit, such as a resistor-capacitor circuit, in which a variable number of resistors are selectively coupled in parallel. The delay presented by the resistor-capacitor circuit is a function of the time constant of the circuit and is inversely proportional to the number of resistors selectively coupled in parallel.

[0072] The first delayed clock signal 318 and the second delayed clock signal 320 are both provided to a waveform shaping circuit 330, and more specifically the wide logic circuit 314 and the narrow logic circuit 316. In general, the waveform shaping circuit 330 performs waveform shaping as discussed below, e.g., the waveform shaping circuit 330 generates a modified feedback clock signal 120 having a modified pulse width and, therefore, a modified duty cycle.

[0073] The wide logic circuit 314 and the narrow logic circuit 316 respectively provide the waveform shaping function of the waveform shaping circuit 330. The wide logic circuit 314 shortens the wide pulse (e.g., generates a first changed clock signal 310 whose waveform has a shorter pulse width than the feedback clock signal 114 and thus has a lower duty cycle than the first delayed clock signal 318, which has the same pulse width and duty cycle as the feedback clock signal 114), and the narrow logic circuit 316 widens the short pulse (e.g., generates a second changed clock signal 312 whose waveform has a wider pulse width than the feedback clock signal 114 and thus has a larger duty cycle than the second delayed clock signal 320, which has the same pulse width and duty cycle as the feedback clock signal 114), as discussed below. Here, "wide" means that the pulse width of the changed feedback clock signal 120 is longer than the desired pulse width, and "narrow" means that the pulse width of the changed feedback clock signal 120 is shorter than the desired pulse width. As used herein, a “desired duty cycle” is the duty cycle of the reference clock signal 110 , and a “desired pulse width” is the pulse width of the reference clock signal 110 .

[0074] The multiplexer 308 selects one of the first altered clock signal 310 or the second altered clock signal 312 in response, at least in part, to the waveform shaping setting 324 generated by the logic circuit 302. As such, the waveform shaping setting 324 sets the waveform shaping function of the waveform shaping circuit 330.

[0075] The logic circuit 302 generates the delay setting 322 and the waveform shaping setting 324 to reduce the duty cycle mismatch between the feedback clock signal 114 and the reference clock signal 110 as indicated by the binary error signal 1510. The internal logic of the logic circuit 302 is described above with respect to the logic circuit 202 and hereinafter with reference to Figure 4A , Figure 4B , Figure 5A and Figure 5B was discussed and is not repeated here.

[0076] In one or more embodiments, settings 206 include waveform shaping settings 324 and delay settings 322 .

[0077] The first delayed clock signal 318 differs in phase from the second delayed clock signal 320 by an amount corresponding to the delay implemented at the variable delay circuit 304 in response to the delay setting 322. The waveform shaping circuit 330, and more specifically the wide logic circuit 314 and the narrow logic circuit 316 as selectable by the waveform shaping setting 324, utilizes the amount of the phase difference to set the pulse width and duty cycle of the first changed clock signal 310 and the second changed clock signal 312, and the multiplexer 308 selects one of the first changed clock signal 310 and the second changed clock signal 312 to provide as the changed feedback clock signal 120, and thus sets the pulse width and duty cycle of the changed feedback clock signal 120.

[0078] In one or more embodiments, the amount of delay that the variable delay circuit 304 increments or decrements may be fixed to a predetermined amount (also referred to herein as a “delay step size”) per calibration cycle. For a given calibration cycle, the predetermined amount of delay may be less than the total difference between the pulse width of the changed feedback clock signal 120 and the desired pulse width (or the pulse widths of the feedback clock signal 114 and the reference clock signal 110). The device 300 may perform multiple calibration cycles to generate a changed feedback clock signal 120 having a desired pulse width or a changed feedback clock signal 120 having a pulse width that exhibits a reduced duty cycle mismatch with respect to the duty cycle of the reference clock signal 110. The operation of the logic circuit 302 and the variable delay circuit 304 may be synchronized by the local clock signal 212, and the respective calibration cycles may correspond to clock cycles of the local clock signal 212.

[0079] In various embodiments, the total number of calibration cycles may be limited to a predetermined number (a predetermined upper limit), and in some cases, the pulse width of the changed feedback clock signal 120 produced by the calibration process may substantially match or mismatch the pulse width of the reference clock signal 110.

[0080] For a given calibration cycle, if the binary error signal 1510 indicates that the duty cycle of the changed feedback clock signal 120 is greater than the duty cycle of the reference clock signal 110, the logic circuit 302 generates the delay setting 322 and the waveform shaping setting 324 to shorten the pulse width of the changed feedback clock signal 120 by a predetermined amount. If the binary error signal 1510 indicates that the duty cycle of the changed feedback clock signal 120 is less than the duty cycle of the reference clock signal 110, the logic circuit 302 generates the delay setting 322 and the waveform shaping setting 324 to extend the pulse width of the changed feedback clock signal 120 by a predetermined amount.

[0081] If the logic circuit 302 determines, based at least in part on the binary error signal 1510, that the pulse width of the second delayed clock signal 320 is narrower than the expected pulse width, the logic circuit 302 generates a waveform shaping setting 324 to select the second altered clock signal 312 input at the multiplexer 308. If the logic circuit 302 determines, based at least in part on the binary error signal 1510, that the pulse width of the second delayed clock signal 320 is wider than the expected pulse width, the logic circuit 302 generates a waveform shaping setting 324 to select the first altered clock signal 310 input at the multiplexer 308.

[0082] Figure 4A is a timing diagram depicting signal 400a in an example generation of setting 206, and more specifically delay setting 322 and waveform shaping setting 324, in the following situation, wherein the up / down error signal 116 indicates a duty cycle mismatch between the changed feedback clock signal 120 and the reference clock signal 110, and the pulse width of the changed feedback clock signal 120 is narrower than the pulse width of the reference clock signal 110.

[0083] Signal 400a includes reference clock signal 110, modified feedback clock signal 120, uplink signal 208, and downlink signal 210. Notably, vertical line 402 is depicted extending through respective center points of pulses of reference clock signal 110 and modified feedback clock signal 120 to illustrate the alignment of respective pulses when reference clock signal 110 and modified feedback clock signal 120 are dual-edge locked.

[0084] At time T1 , the phase frequency detector 102 asserts the up signal 208 and deasserts the down signal 210 to indicate that the edge (here, the rising edge) of the reference clock signal 110 leads the edge of the altered feedback clock signal 120 in phase.

[0085] At time T1, logic circuit 202 detects a duty cycle mismatch between reference clock signal 110 and modified feedback clock signal 120 at least in part in response to assertion of uplink signal 208 leading in phase with downlink signal 210. Logic circuit 202 determines that the pulse width of modified feedback clock signal 120 is narrower than the pulse width of reference clock signal 110 at least in part in response to assertion of uplink signal 208 leading in phase with downlink signal 210, indicating that the edge of reference clock signal 110 leads in phase with the edge of downlink signal 210. Based at least in part on this determination, logic circuit 202 generates setting 206 to instruct duty cycle shaping circuit 204 to lengthen the pulse width of modified feedback clock signal 120. More specifically, logic circuit 202 may generate settings 206 to include a delay setting 322 to indicate an “incremental delay” at variable delay circuit 304 by a predetermined amount, and to include a waveform shaping setting 324 to indicate waveform shaping circuit 330 to “widen” the pulse width of the changed feedback clock signal 120.

[0086] At time T2 , the phase frequency detector 102 asserts the down signal 210 to indicate an edge (here, a rising edge) of the changed feedback clock signal 120 , and resets, which de-asserts the up signal 208 and the down signal 210 .

[0087] At time T3 , the phase frequency detector 102 asserts the down signal 210 and continues to de-assert the up signal 208 to indicate that the edge (here, the falling edge) of the changed feedback clock signal 120 leads the edge of the reference clock signal 110 in phase.

[0088] Notably, at time T3, logic circuit 202 does not respond to the assertion of down signal 210 because at time T1, logic circuit 202 detected a duty cycle mismatch between reference clock signal 110 and modified feedback clock signal 120 and determined setting 206. In one or more embodiments, logic circuit 202 may optionally acknowledge the detected duty cycle mismatch between reference clock signal 110 and modified feedback clock signal 120 at time T3.

[0089] At time T4 , the phase frequency detector 102 asserts the up signal 208 to indicate an edge (here, a falling edge) of the reference clock signal 110 , and resets, which de-asserts the up signal 208 and the down signal 210 .

[0090] The duration from T1 to T2 or from T3 to T4 substantially corresponds to one-half (1 / 2) the difference in pulse width between the changed feedback clock signal 120 and the reference clock signal 110 due to the double-edge locking between the reference clock signal 110 and the changed feedback clock signal 120 performed by the device 100.

[0091] although Figure 4A The setting 206 is depicted as being transmitted between time T1 and T4, but the setting 206 may be transmitted later than time T4 without exceeding this range. In one or more embodiments, the duty cycle matching circuit 108 may observe the duty cycle of the changed feedback clock signal 120 and the reference clock signal 110, and every N cycles of the reference clock signal 110 and the changed feedback clock signal 120 implement the changes to the changed feedback clock signal 120 discussed herein, where N is an integer greater than or equal to 2. In the case where N is greater than or equal to 2, the setting 206 may be transmitted in a cycle later than the cycle in which the duty cycle is observed but before the next cycle in which the duty cycle is observed.

[0092] Figure 4B 4 is a timing diagram depicting a signal 400b in an example generation of the second modified clock signal 312 in a case where the up / down error signal 116 indicates a duty cycle mismatch between the modified feedback clock signal 120 and the reference clock signal 110, and the pulse width of the modified feedback clock signal 120 is narrower than the pulse width of the reference clock signal 110 (e.g., Figure 4A ).

[0093] More specifically, as a non-limiting example, Figure 4A As depicted, logic circuit 302 determines to detect a duty cycle mismatch at least in part in response to the order of assertions of uplink signal 208 and downlink signal 210. Logic circuit 302 determines that the pulse width of the altered feedback clock signal 120 is narrower than the pulse width of the reference clock signal 110 at least in part in response to the order of assertions of uplink signal 208 and downlink signal 210. In response to the determination, logic circuit 302 generates a delay setting 322 to indicate to increment the delay amount at variable delay circuit 304, and generates a waveform shaping setting 324 to instruct waveform shaping circuit 330 to utilize a pulse width widening waveform shaping function, i.e., narrow logic circuit 316.

[0094] In an example operation of wide logic circuit 314, signal 400b includes second delayed clock signal 320, first delayed clock signal 318, and second altered clock signal 312. In the following embodiments, narrow logic circuit 316 operates as an OR gate or is an OR gate.

[0095] At time T1, the second delayed clock signal 320 exhibits a change from the first state to a different second state, here a rising edge, while the first delayed clock signal 318 remains in the first state. At time T1, the narrow logic circuit 316 generates the second changed clock signal 312 that exhibits a change from the first state to the second state because at least one of the second delayed clock signal 320 and the first delayed clock signal 318 is in the first state.

[0096] At time T2, the first delayed clock signal 318 exhibits a change from the first state to the second state, i.e., a rising edge. As discussed above, the duration ΔT from time T1 to time T2 is substantially equal to one or more delay increments. The duration ΔT may correspond to one or more delay increments of the variable delay circuit 304.

[0097] Due to the delay setting 322, the rising edge of the first delayed clock signal 318 is "behind" (in terms of time) the rising edge of the second delayed clock signal 320. At time T2, the narrow logic circuit 316 maintains the second altered clock signal 312 in the second state because at least one of the second delayed clock signal 320 and the first delayed clock signal 318 is in the second state.

[0098] At time T3, the second delayed clock signal 320 exhibits a change from the second state to the first state, here a falling edge, while the first delayed clock signal 318 remains in the second state. At time T3, the narrow logic circuit 316 maintains the second changed clock signal 312 in the second state because at least one of the second delayed clock signal 320 and the first delayed clock signal 318 is in the second state.

[0099] At time T4, the first delayed clock signal 318 exhibits a change from the second state to the first state, here a falling edge. At time T4, the narrow logic circuit 316 generates a falling edge for the second changed clock signal 312, i.e., the second changed clock signal 312 changes from the second state to the first state, because neither the second delayed clock signal 320 nor the first delayed clock signal 318 is in the second state.

[0100] The duration between times T1 and T4 (ie, the pulse width of the second altered clock signal 312 ) is longer than the duration between T1 and T3 (ie, the pulse width of the second delayed clock signal 320 ).

[0101] Figure 5Ais a timing diagram depicting signal 400a in an example generation of setting 206, and more specifically delay setting 322 and waveform shaping setting 324, in the following situation, wherein the up / down error signal 116 indicates a duty cycle mismatch between the changed feedback clock signal 120 and the reference clock signal 110, and the pulse width of the changed feedback clock signal 120 is wider than the pulse width of the reference clock signal 110.

[0102] Figure 5B is a timing diagram depicting signal 500 b in an example generation of a modified feedback clock signal 120 having a shorter pulse width than the modified feedback clock signal 120 .

[0103] Signal 500a includes reference clock signal 110, modified feedback clock signal 120, uplink signal 208, and downlink signal 210. Notably, vertical line 502 is depicted extending through respective center points of pulses of reference clock signal 110 and modified feedback clock signal 120 to illustrate the alignment of respective pulses when reference clock signal 110 and modified feedback clock signal 120 are dual-edge locked.

[0104] At time T1 , the phase frequency detector 102 asserts the down signal 210 and continues to de-assert the up signal 208 to indicate that the edge (here, the rising edge) of the changed feedback clock signal 120 leads the edge of the reference clock signal 110 in phase.

[0105] At time T1, logic circuit 202 detects a duty cycle mismatch between reference clock signal 110 and changed feedback clock signal 120 at least in part in response to assertion of downlink signal 210 leading in phase with uplink signal 208. Logic circuit 202 determines that the pulse width of changed feedback clock signal 120 is wider than the pulse width of reference clock signal 110 at least in part in response to assertion of uplink signal 208 leading in phase with downlink signal 210, indicating that the edge of changed feedback clock signal 120 leads in phase with the edge of reference clock signal 110. Based at least in part on this determination, logic circuit 202 generates setting 206 to instruct duty cycle shaping circuit 204 to shorten the pulse width of changed feedback clock signal 120. More specifically, logic circuit 202 may generate settings 206 to include a delay setting 322 to indicate an “incremental delay” at variable delay circuit 304 by a predetermined amount, and to include a waveform shaping setting 324 to indicate waveform shaping circuit 330 to “shorten” the pulse width of the changed feedback clock signal 120.

[0106] At time T2 , the phase frequency detector 102 asserts the up signal 208 to indicate an edge (here, a rising edge) of the reference clock signal 110 , and resets, which de-asserts the up signal 208 and the down signal 210 .

[0107] At time T3 , the phase frequency detector 102 asserts the up signal 208 and continues to de-assert the down signal 210 to indicate that the edge (here, the falling edge) of the reference clock signal 110 leads the edge of the altered feedback clock signal 120 in phase.

[0108] Notably, at time T3, logic circuit 202 does not respond to assertion of uplink signal 208 because at time T1, logic circuit 202 detected a duty cycle mismatch between reference clock signal 110 and modified feedback clock signal 120 and determined setting 206. In one or more embodiments, logic circuit 202 may optionally acknowledge the detected duty cycle mismatch between reference clock signal 110 and modified feedback clock signal 120 at time T3.

[0109] At time T4 , the phase frequency detector 102 asserts the down signal 210 to indicate an edge (here, a falling edge) of the changed feedback clock signal 120 , and resets, which de-asserts the up signal 208 and the down signal 210 .

[0110] The durations from T1 to T2 and from T3 to T4 substantially correspond to one-half (1 / 2) the difference in pulse width between the changed feedback clock signal 120 and the reference clock signal 110 due to the double-edge locking between the reference clock signal 110 and the changed feedback clock signal 120 performed by the device 100.

[0111] although Figure 5A The setting 206 is depicted as being transmitted between time T1 and T4, but the setting 206 may be transmitted later than time T4 without exceeding this range. In one or more embodiments, the duty cycle matching circuit 108 may observe the duty cycle of the changed feedback clock signal 120 and the reference clock signal 110, and every N cycles of the reference clock signal 110 and the changed feedback clock signal 120 implement the changes to the changed feedback clock signal 120 discussed herein, where N is an integer greater than or equal to 2. In the case where N is greater than or equal to 2, the setting 206 may be transmitted in a cycle later than the cycle in which the duty cycle is observed but before the next cycle in which the duty cycle is observed.

[0112] Figure 5Bis a timing diagram depicting signal 500 b in an example generation of first modified clock signal 310 in a case where up / down error signal 116 indicates a duty cycle mismatch between modified feedback clock signal 120 and reference clock signal 110, and a pulse width of modified feedback clock signal 120 is wider than a pulse width of reference clock signal 110 (e.g., Figure 5A ).

[0113] More specifically, as a non-limiting example, Figure 5A As depicted, the logic circuit 302 determines to detect a duty cycle mismatch at least in part in response to the order of assertions of the uplink signal 208 and the downlink signal 210. The logic circuit 302 determines that the pulse width of the altered feedback clock signal 120 is wider than the pulse width of the reference clock signal 110 at least in part in response to the order of assertions of the uplink signal 208 and the downlink signal 210. In response to the determination, the logic circuit 302 generates a delay setting 322 to indicate to increment the delay amount at the variable delay circuit 304, and generates a waveform shaping setting 324 to instruct the waveform shaping circuit 330 to utilize a pulse width shortening waveform shaping function, i.e., the wide logic circuit 314.

[0114] Signal 500b includes second delayed clock signal 320, first delayed clock signal 318, and first altered clock signal 310. In the following embodiments, wide logic circuit 314 operates as or is an AND gate.

[0115] At time T1, the second delayed clock signal 320 exhibits a change, here a rising edge, from the first state to a different second state, while the first delayed clock signal 318 remains in the first state. Because the second delayed clock signal 320 and the first delayed clock signal 318 exhibit different states, the wide logic circuit 314 continues to generate the first changed clock signal 310 exhibiting the first state.

[0116] At time T2, the first delayed clock signal 318 exhibits a change (rising edge) from the first state to the second state, while the second delayed clock signal 320 remains in the second state, so the wide logic circuit 314 generates the first changed clock signal 310 that exhibits a change from the first state to the second state because both the second delayed clock signal 320 and the first delayed clock signal 318 are in the second state.

[0117] Notably, the duration ΔT between time T1 and time T2 may be substantially equal to one or more delay increments implemented by variable delay circuit 304 , as discussed above.

[0118] At time T3, the second delayed clock signal 320 exhibits a change (falling edge) from the second state to the first state, while the first delayed clock signal 318 remains in the second state, so the wide logic circuit 314 generates the first changed clock signal 310 exhibiting a falling edge from the second state to the first state because at least one of the second delayed clock signal 320 and the first delayed clock signal 318 is in the first state.

[0119] At time T4, the first delayed clock signal 318 exhibits a falling edge from the second state to the first state, while the second delayed clock signal 320 remains in the first state, so the wide logic circuit 314 generates the second changed clock signal 312 exhibiting a falling edge from the second state to the first state because both the second delayed clock signal 320 and the first delayed clock signal 318 are in the first state. Because the second delayed clock signal 320 and the first delayed clock signal 318 exhibit the first state, the wide logic circuit 314 continues to generate the second changed clock signal 312 exhibiting the first state.

[0120] The duration between times T2 and T3 (ie, the pulse width of the first altered clock signal 310 ) is shorter than the pulse width of the first delayed clock signal 318 or the second delayed clock signal 320 .

[0121] Figure 6 6 is a diagram depicting a calibration process 600 according to one or more embodiments. Delay line update numbers ("Delay Line Update #") are depicted, which identify a sequence of corresponding calibration cycles of the calibration process 600. Also depicted are corresponding delay values ​​("Delay Line Values") applied during corresponding calibration cycles. Each delay line value represents a multiple of a predetermined delay amount. For example, "1" represents 1x the predetermined delay amount, "2" represents 2x the predetermined delay amount, and so on.

[0122] exist Figure 6 In the specific embodiment depicted, the corresponding delay values ​​are incremented from delay line update number 0 to delay line update number 5, decremented from delay line update number 5 to delay line update number 7, and incremented from delay line update number 7 to delay line update number 8. From delay line update number 8 to 1023, the delay line update numbers toggle back and forth between incrementing and decrementing, indicating that the duty cycle is matched for purposes of the calibration process 600.

[0123] Figure 7 is a flow chart depicting a process 700 for changing a duty cycle of a clock to match a duty cycle of another clock, wherein the clock may be the output clock signal 112, the feedback clock signal 114, or the changed feedback clock signal 120, and the other clock may be the reference clock signal 110, according to one or more embodiments.

[0124] Some or all of process 700 may be performed by duty cycle matching circuit 108 , device 200 , device 300 , or device 1100 , but is not limited thereto.

[0125] although Figure 7 Process 700 is depicted as a particular sequence of operations, but the sequence may be altered without departing from the scope of the present disclosure. In one or more embodiments, some of the depicted operations may be performed in parallel or in a different sequence that does not substantially affect the functionality of process 700. In one or more embodiments, different components of an apparatus or system implementing some or all of the operations of process 700 may perform functions at substantially the same time or in a specific sequence.

[0126] At operation 702, process 700 receives an up / down error signal (e.g., up / down error signal 116 generated via phase frequency detector 102, but not limited thereto) indicating a duty cycle mismatch between a reference clock (e.g., reference clock signal 110, but not limited thereto) and a changed feedback clock (e.g., changed feedback clock signal 120, but not limited thereto), the changed feedback clock representing an output clock generated by a clock tracking circuit (e.g., clock tracking circuit 100, but not limited thereto) to track the reference clock.

[0127] At operation 704 , process 700 sets (eg, via setting 206 provided to duty cycle shaping circuit 204 , but not limited thereto) the duty cycle of the altered feedback clock to reduce the duty cycle mismatch indicated by the uplink / downlink error signal.

[0128] In one or more embodiments, process 700 can set the duty cycle of the altered clock via a calibration process including a plurality of calibration cycles.The duty cycle mismatch can be incrementally reduced via process 700 at least in part in response to respective calibration cycles.

[0129] At operation 706, process 700 provides a changed feedback clock having a set duty cycle. In one or more embodiments, process 700 provides a changed feedback clock having a set duty cycle to a phase frequency detector (e.g., phase frequency detector 102) in place of the output clock (or a feedback clock representative thereof) generated by the clock tracking circuit.

[0130] Figure 8 is a flow chart depicting a process 800 for setting the duty cycle of a modified feedback clock signal to reduce a duty cycle mismatch indicated by an uplink / downlink error signal.

[0131] although Figure 8The process 800 is depicted in a particular sequence of operations, but the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not materially affect the functionality of the process 800. In other embodiments, different components of an example device or system implementing the routine may perform functions at substantially the same time or in a specific sequence.

[0132] At operation 802, process 800 determines settings for generating a waveform shaping signal for shaping the changed feedback clock signal to reduce the duty cycle mismatch indicated by the uplink / downlink error signal. In one or more embodiments, the waveform shaping signal for shaping the changed feedback clock signal may be the first delayed clock signal 318 generated by the variable delay circuit 304, the second delayed clock signal 320 generated by the fixed delay circuit 1106, the first delayed clock 1114 generated by the variable delay circuit 306, or the second delayed clock 1116 generated by the fixed delay circuit 1104.

[0133] At operation 804, process 800 determines a waveform shaping function for shaping the changed feedback clock signal to reduce the duty cycle mismatch indicated by the uplink / downlink error signal. In one or more embodiments, the waveform shaping function may include lengthening the pulse width (e.g., via narrow logic circuit 316 or waveform shaping circuit 1112, but not limited thereto) or shortening the pulse width (e.g., via wide logic circuit 314 or waveform shaping circuit 1112, but not limited thereto).

[0134] At operation 806, process 800 provides settings to a duty cycle shaping circuit to set the duty cycle of the changed feedback clock, the settings including the determined settings to generate a waveform shaping signal and the determined waveform shaping function. In one or more embodiments, process 800 may provide settings to a variable delay circuit (e.g., variable delay circuit 304 or variable delay circuit 1104, but not limited thereto) to generate a waveform shaping signal for shaping the changed feedback clock signal, and provide settings for the determined waveform shaping function to a waveform shaping circuit (e.g., waveform shaping circuit 330, but not limited thereto).

[0135] In one or more embodiments, process 800 may determine settings for generating a waveform shaping signal or for a waveform shaping function in response, at least in part, to an order in which the uplink / downlink error signals are received, where the order indicates a duty cycle mismatch and whether the altered feedback clock signal is narrower or wider than the reference clock signal.

[0136] Fig. 99 is a flow chart depicting a process 900 for shaping the waveform of a changed feedback clock according to one or more embodiments. Some or all of the operations of process 900 may be performed by duty cycle shaping circuit 204, variable delay circuit 304, variable delay circuit 1104, fixed delay circuit 306, fixed delay circuit 1106, waveform shaping circuit 330, or waveform shaping circuit 1112.

[0137] although Fig. 9 The process 900 is depicted in a particular sequence of operations, but the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not materially affect the functionality of the process 900. In other embodiments, different components of an example device or system implementing the routine may perform functions at substantially the same time or in a specific sequence.

[0138] At operation 902, process 900 sets (e.g., delay setting 322 generated via logic circuit 302 or delay setting 1122 generated via logic circuit 1102 discussed below, but not limited thereto) a delay at a variable delay circuit (e.g., variable delay circuit 304 or variable delay circuit 1104, but not limited thereto).

[0139] At operation 904, process 900 delays the feedback clock at the variable delay circuit to generate a first delayed clock (e.g., first delayed clock signal 318, but not limited thereto). The delay implemented by the variable delay circuit to delay the reference clock or output clock and generate the first delayed clock signal 318 has increased or decreased the delay amount that the variable delay circuit incremented or decremented in operation 902.

[0140] At operation 906 , process 900 delays the feedback clock at a fixed delay circuit (eg, fixed delay circuit 306 , but not limited thereto) to generate a second delayed clock (eg, second delayed clock signal 320 , but not limited thereto).

[0141] At operation 908, process 900 shapes a waveform of the changed feedback clock in response, at least in part, to the first delayed clock and the second delayed clock. The waveform shaping may be performed in response, at least in part, to the binary up / down error signal and the binary down / up error signal and a determination of whether to shorten or lengthen a pulse width, and thus a duty cycle, of the changed feedback clock.

[0142] Fig.101000 is a flowchart depicting a process 1000 for generating settings for a duty cycle shaping circuit (such as duty cycle shaping circuit 204) and more specifically generating delay settings and waveform shaping settings for variable delay circuits and waveform shaping circuits (such as variable delay circuit 304 and waveform shaping circuit 330 or variable delay circuit 1104 and waveform shaping circuit 1112) according to one or more embodiments.

[0143] Some or all of the operations of process 700 may be performed by logic circuit 202 , logic circuit 302 , or logic circuit 1102 , but are not limited thereto.

[0144] although Fig.10 The process 1000 is depicted in a particular sequence of operations, but the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not materially affect the functionality of the process 900. In other embodiments, different components of an example device or system implementing the routine may perform functions at substantially the same time or in a specific sequence.

[0145] At operation 1002, process 1000 detects a duty cycle mismatch between a reference clock signal and a changed feedback clock signal in response, at least in part, to an assertion order of an uplink signal and a downlink signal of an uplink / downlink error signal generated by a phase frequency detector (e.g., uplink / downlink error signal 116 generated by phase frequency detector 102, but not limited thereto).

[0146] At operation 1004, process 1000 generates a delay setting for a variable delay circuit disposed in a signal path of a feedback clock. The delay indicated by the delay setting may represent a predetermined delay amount.

[0147] At operation 1006 , process 1000 determines whether the pulse width of the changed feedback clock is narrower or wider than the pulse width of the reference clock signal.

[0148] At operation 1008 , upon determining that the pulse width of the changed feedback clock signal is narrower than the pulse width of the reference clock signal, process 1000 instructs the waveform shaping circuit to lengthen the pulse width of the changed feedback clock signal.

[0149] At optional operation 1010 , upon determining that the pulse width of the modified feedback clock signal is wider than the pulse width of the reference clock signal, process 1000 instructs the waveform shaping circuit to shorten the pulse width of the modified feedback clock signal.

[0150] In one or more embodiments, a changed feedback clock signal having an extended pulse width (e.g., first changed clock signal 310, but not limited thereto) or a shortened pulse width (e.g., second changed clock signal 312, but not limited thereto) is provided (e.g., via multiplexer 308, but not limited thereto) as changed feedback clock signal 120.

[0151] Fig.11 1 is a block diagram depicting an apparatus 1100 for generating a changed clock, and more specifically, a clock having a changed duty cycle compared to the duty cycle of an original clock, and more specifically, a clock having a changed pulse width compared to the pulse width of the original clock, according to one or more embodiments.

[0152] Device 100 includes logic circuit 1102, variable delay circuit 1104, fixed delay circuit 1106, and waveform shaping circuit 1112. Variable delay circuit 1104, delay unit 1108, fixed delay circuit 1106, and delay unit 1110 are similar to variable delay circuit 304, delay unit 326, fixed delay circuit 306, and delay unit 328, and therefore, will not be re-described here. Logic circuit 1102 is a non-limiting embodiment of logic circuit 202, and delay setting 1122 is a non-limiting embodiment of setting 206 or a portion thereof. Variable delay circuit 1104, fixed delay circuit 1106, and waveform shaping circuit 1112 together are non-limiting embodiments of duty cycle shaping circuit 204.

[0153] Initially, the respective delays at the variable delay circuit 1104 and the fixed delay circuit 1106 may be set to the 1 / 2 delay range. Once set to 1 In the / 2 delay range, the logic circuit 1102 can use the delay setting 1122 to increase or decrease the delay amount at the variable delay circuit 1104 by one or more delay amounts.

[0154] The waveform shaping circuit 1112 generates a changed feedback clock signal 120 at least in part in response to signals received at a first input 1118 and a second input 1120 of the waveform shaping circuit 1112. More specifically, the waveform shaping circuit 1112 generates a changed feedback clock signal 120 exhibiting a change from a first state to a second state (a rising edge) at least in part in response to the signal received at the first input 1118, and generates a changed feedback clock signal 120 exhibiting a change from a second state to a first state (a falling edge) at least in part in response to the signal received at the second input 1120. The first input 1118 may be characterized as a “rising edge control input” of the waveform shaping circuit 1112, and the second input 1120 may be characterized as a “falling edge control input” of the waveform shaping circuit 1112.

[0155] The first input 1118 is coupled to the output of the variable delay circuit 1104, and the second input 1120 is coupled to the output of the fixed delay circuit 1106, so the first input 1118 receives the first delayed clock 1114, and the second input 1120 receives the second delayed clock 1116. The logic of the waveform shaping circuit 1112 generates the first changed clock signal 310 exhibiting a rising edge at least in part in response to the first delayed clock 1114 exhibiting a rising edge, and generates the first changed clock signal 310 exhibiting a falling edge at least in part in response to the second delayed clock 1116 exhibiting a falling edge. As a non-limiting example, the waveform shaping circuit 1112 may include a combinational logic circuit to implement the generation of the first changed clock signal 310 based on the first delayed clock 1114 and the second delayed clock 1116 as described herein.

[0156] If binary error signal 1510 indicates that the pulse width of modified feedback clock signal 120 is too short (relative to reference clock signal 110 ), logic circuit 1102 may generate delay setting 1122 to reduce the amount of delay at variable delay circuit 1104 and thereby increase the pulse width of first modified clock signal 310 .

[0157] If binary error signal 1510 indicates that the pulse width of feedback clock signal 114 is too long (relative to reference clock signal 110 ), logic circuit 1102 may generate delay setting 1122 to increment the delay amount at waveform shaping circuit 1112 and thereby shorten the pulse width of first altered clock signal 310 .

[0158] Fig. 12A and Fig. 12B 1100 are timing diagrams respectively depicting signal 1200a and signal 1200b during respective example operations of apparatus 1100.

[0159] Fig. 12A Depicted is an embodiment where the pulse width of the feedback clock signal 114 is shorter than the pulse width of the reference clock signal 110 , where the signal 1200 a includes: the second delayed clock 1116 , the first delayed clock 1114 , and the altered feedback clock signal 120 .

[0160] Fig. 12B Depicted is an embodiment where the pulse width of the feedback clock signal 114 is longer than the expected pulse width of the reference clock signal 110 , the signal 1200 b includes: the second delayed clock 1116 , the first delayed clock 1114 , and the altered feedback clock signal 120 .

[0161] Steering Fig. 12A Example broadening of a short pulse depicted:

[0162] At time T1, the first delayed clock 1114 exhibits a change from a first state to a different second state, here a rising edge. At time T1, the waveform shaping circuit 1112 generates a changed feedback clock signal 120 exhibiting a change from a first state to a second state, at least in part in response to detecting the change (rising edge) of the first delayed clock 1114 from the first state to the second state.

[0163] At time T1, the second delayed clock 1116 exhibits a change from the first state to the second state, here a rising edge, but this change of the second delayed clock 1116 does not affect the generation of the changed feedback clock signal 120 performed by the waveform shaping circuit 1112 because it is received at the second input 1120 of the waveform shaping circuit 1112.

[0164] At time T3, the first delayed clock 1114 exhibits a change from the second state to the first state, here a falling edge, but this change of the second delayed clock 1116 does not affect the generation of the changed feedback clock signal 120 performed by the waveform shaping circuit 1112 because it is received at the first input 1118 of the waveform shaping circuit 1112.

[0165] At time T4, the second delayed clock 1116 exhibits a change from the second state to the first state, here a falling edge. At time T4, the waveform shaping circuit 1112 generates a changed feedback clock signal 120 exhibiting a change from the second state to the first state at least in part in response to detecting the change (falling edge) of the second delayed clock 1116 from the first state to the second state. Fig. 12A The duration ΔT in may be substantially equal to one or more delay increments implemented by the waveform shaping circuit 1112 discussed above.

[0166] The duration from T2 to T4 (the pulse width of the changed feedback clock signal 120 ) is longer than the duration between T1 and T3 (the pulse width of the first delayed clock 1114 ) and the duration between T2 and T4 (the pulse width of the second delayed clock 1116 ).

[0167] Steering Fig. 12B Example shortening of the long pulse depicted:

[0168] At time T1, the second delayed clock 1116 exhibits a change from a first state to a different second state, here a rising edge, but this change of the second delayed clock 1116 does not affect the generation of the changed feedback clock signal 120 performed by the waveform shaping circuit 1112 because it is received at the second input 1120 of the waveform shaping circuit 1112.

[0169] At time T2, the first delayed clock 1114 exhibits a change from the first state to a different second state, here a rising edge. At time T2, the waveform shaping circuit 1112 generates a changed feedback clock signal 120 exhibiting a change (rising edge) from the first state to the second state in response, at least in part, to detecting the change of the first delayed clock 1114 from the first state to the second state.

[0170] Fig. 12B The duration ΔT from time T1 to time T2 depicted in may be substantially equal to one or more delay increments implemented by the variable delay circuit 1104 discussed above.

[0171] At time T3, the second delayed clock 1116 exhibits a change from the second state to the first state, here a falling edge. At time T3, the waveform shaping circuit 1112 generates a changed feedback clock signal 120 exhibiting a change (falling edge) from the second state to the first state in response, at least in part, to detecting the change of the first delayed clock 1114 from the first state to the second state.

[0172] At time T4, the first delayed clock 1114 exhibits a change from the second state to the first state, here a falling edge, but this change of the first delayed clock 1114 does not affect the generation of the changed feedback clock signal 120 by the waveform shaping circuit 1112. The duration from T2 to T3 (the pulse width of the changed feedback clock signal 120) is shorter than the duration between T1 and T3 (the pulse width of the second delayed clock 1116) and the duration between T2 and T4 (the pulse width of the first delayed clock 1114).

[0173] Fig.13is a flow chart depicting a process 1300 to generate a delay setting 1122 to set an amount of delay at a variable delay circuit 1104 in accordance with one or more embodiments.

[0174] Although the example process 1300 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not materially affect the functionality of the process 1300. In other embodiments, different components of the example device or system implementing the process 1300 may perform functions at substantially the same time or in a specific sequence.

[0175] At operation 1302, process 1300 sets the delay amount at the variable delay circuit to approximately 1 / 2 delay range.

[0176] At operation 1304, process 1300 may optionally set the fixed delay amount at the additional variable delay circuit to approximately 1 Alternatively, the delay range of the fixed delay circuit is pre-set to approximately 1 / 2 delay range.

[0177] At operation 1306, process 1300 generates a delay setting that reduces the delay of the variable delay circuit when the pulse width of the changed feedback clock is narrower than the pulse width of the reference clock. This causes the rising edge of the delayed clock generated by the variable delay circuit to occur earlier in time than before the delay was reduced.

[0178] At operation 1308, process 1300 generates a delay setting that increments the delay of the variable delay circuit when the pulse width of the changed feedback clock is wider than the pulse width of the reference clock. This causes the rising edge of the delayed clock generated by the variable delay circuit to occur later in time than before the delay was incremented.

[0179] Fig.14 is a diagram illustrating a method for transmitting a signal through a Fig.11 Flowchart of process 1400 for generating a modified feedback clock by waveform shaping circuit 1112.

[0180] Although the example process 1400 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not materially affect the functionality of the process 1400. In other embodiments, different components of the example device or system implementing the process 1400 may perform functions at substantially the same time or in a specific sequence.

[0181] At operation 1402 , process 1400 receives a first delayed clock (eg, first delayed clock 1114 , but not limited thereto) via a variable delay circuit (eg, variable delay circuit 1104 , but not limited thereto).

[0182] At operation 1404 , process 1400 receives a second delayed clock (eg, second delayed clock 1116 , but not limited thereto) via a fixed delay circuit (eg, fixed delay circuit 1106 , but not limited thereto).

[0183] At operation 1406, process 1400 generates a changed feedback clock (e.g., changed feedback clock signal 120, but not limited thereto) exhibiting a change (rising edge) from a first state to a second state at least in part in response to a first delayed clock (e.g., first delayed clock 1114, but not limited thereto) exhibiting a change (rising edge) from a first state to a second state.

[0184] At operation 1408, process 1400 generates a changed feedback clock (e.g., changed feedback clock signal 120, but not limited thereto) that exhibits a second state. Process 1400 generates a changed feedback clock that exhibits the second state for a duration between when the process generates the changed feedback clock exhibiting a rising edge in operation 1406 and when the process generates the changed feedback clock exhibiting a falling edge in the following operation 1410.

[0185] At operation 1410, process 1400 generates a changed feedback clock (e.g., changed feedback clock signal 120, but not limited thereto) exhibiting a change (falling edge) from a second state to a first state, at least in part in response to a second delayed clock (e.g., second delayed clock 1116, but not limited thereto) exhibiting a change (falling edge) from a second state to a first state.

[0186] Fig.15 is a block diagram of an apparatus 1500 for detecting duty cycle mismatch and determining settings for controlling pulse width shaping according to one or more embodiments. Apparatus 1500 is a non-limiting embodiment of logic circuit 202, logic circuit 302, or logic circuit 1102.

[0187] The apparatus 1500 includes a bang-bang phase detector 1502 (“BBPD” 1502 ) and a duty cycle mismatch detection and duty cycle shaping control circuit 1504 .

[0188] BBPD 1502 receives upstream signal 208 and downstream signal 210 and generates two signals, increment signal 1506 and decrement signal 1508. In response to receiving a pulse on upstream signal 208 that leads in phase the pulse in downstream signal 210, BBPD 1502 asserts increment signal 1506 and de-asserts decrement signal 1508. In response to receiving a pulse on downstream signal 210 that leads in phase the pulse upstream signal 208, BBPD 1502 de-asserts increment signal 1506 and asserts decrement signal 1508.

[0189] The duty cycle mismatch detection and duty cycle shaping control circuit 1504 receives the increment signal 1506 and the reduction signal 1508 generated by the BBPD 1502. If the increment signal 1506 is asserted and the reduction signal 1508 is de-asserted, the duty cycle mismatch detection and duty cycle shaping control circuit 1504 determines that the pulse width of the changed feedback clock signal 120 is narrower than the pulse width of the reference clock signal 110, and generates the setting 206 to extend the pulse width of the changed feedback clock signal 120. If the increment signal 1506 is de-asserted and the reduction signal 1508 is asserted, the duty cycle mismatch detection and duty cycle shaping control circuit 1504 determines that the pulse width of the changed feedback clock signal 120 is wider than the pulse width of the changed feedback clock signal 120, and generates the setting 206 to shorten the pulse width of the changed feedback clock signal 120.

[0190] If the increment signal 1506 and the decrement signal 1508 are both asserted or both deasserted, the duty cycle mismatch detection and duty cycle shaping control circuit 1504 does nothing because these signal states would indicate that the uplink signal 208 and the downlink signal 210 are being received at the BBPD 1502 simultaneously.

[0191] Fig.16 is a block diagram illustrating an apparatus 1600 for detecting duty cycle mismatch and determining settings for controlling pulse width shaping according to one or more embodiments. Apparatus 1600 is a non-limiting embodiment of logic circuit 202, logic circuit 302, or logic circuit 1102.

[0192] Apparatus 1600 includes a time-to-digital converter 1602 ("TDC 1602").

[0193] The TDC 1602 receives the upstream signal 208 and the downstream signal 210 and generates digital phase information 1604. The digital phase information 1604 is a digital representation of the direction and magnitude information in the upstream signal 208 and the downstream signal 210 of the upstream / downstream error signal 116. The digital phase information 1604 may be provided directly to the duty cycle shaping circuit 204, the variable delay circuit 304, the variable delay circuit 1104, the waveform shaping circuit 330, or the waveform shaping circuit 1112. The magnitude information in the digital phase information 1604 may be utilized to directly perform the delay in the variable delay circuit, and the sign information (direction information) may be utilized to directly set the waveform shaping function at the waveform shaping circuit.

[0194] Those skilled in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.17 Non-limiting examples of specific implementations of the functional elements disclosed herein are shown.In some examples, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0195] Fig.17 1700 is a block diagram of a circuit 1700 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some embodiments. The circuit 1700 includes one or more processors 1702 (sometimes referred to herein as "processors 1702") operably coupled to one or more data storage devices 1704 (sometimes referred to herein as "storage devices 1704"). The storage devices 1704 include machine executable code 1706 stored thereon, and the processor 1702 includes logic circuits 1708. The machine executable code 1706 information describes functional elements that can be implemented by (e.g., executed by) the logic circuits 1708. The logic circuits 1708 are adapted to implement (e.g., execute) the functional elements described by the machine executable code 1706. When executing the functional elements described by the machine executable code 1706, the circuit 1700 should be regarded as dedicated hardware configured to perform the functional elements disclosed herein. In some embodiments, processor 1702 may be configured to execute the functional elements described by machine executable code 1706 sequentially, simultaneously (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0196] When implemented by logic circuitry 1708 of processor 1702, machine executable code 1706 adapts processor 1702 to perform operations of the embodiments disclosed herein. By way of non-limiting example, machine executable code 1706 may adapt processor 1702 to perform some or all operations of one or more of the following: process 700, process 900, process 1000, process 1300, or process 1400.

[0197] Also by way of non-limiting example, the machine executable code 1706 may adapt the processor 1702 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: device 100, including 102, controller 104, controlled oscillator 106, or duty cycle matching circuit 108; device 200, including logic circuit 202 or duty cycle shaping circuit 204; device 300, including logic circuit 302, variable delay circuit 304, delay unit 326, fixed delay circuit 306, delay unit 328, waveform shaping circuit 330, wide logic circuit 314, narrow logic circuit 316, or multiplexer 308; device 1100, including logic circuit 1102, variable delay circuit 1104, delay unit 1108, fixed delay circuit 1106, delay unit 1110, second input 1120, first input 1118, or second input 1120; device 1500, including BBPD 1502 or duty cycle mismatch detection and duty cycle shaping control circuit 1504 ; or device 1600 , including TDC 1602 .

[0198] Processor 1702 may include a general purpose processor, a special purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general purpose computer including a processor is considered a special purpose computer, and the general purpose computer is configured to execute functional elements corresponding to machine executable code 1706 (e.g., software code, firmware code, hardware description) associated with an embodiment of the present disclosure. It should be noted that a general purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, processor 1702 may include any conventional processor, controller, microcontroller, or state machine. Processor 1702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0199] In some embodiments, the storage device 1704 includes a volatile data storage device (e.g., a random access memory (RAM)), a non-volatile data storage device (e.g., a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), but not limited thereto). In some embodiments, the processor 1702 and the storage device 1704 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SOC), but not limited thereto). In some embodiments, the processor 1702 and the storage device 1704 may be implemented as independent devices.

[0200] In some embodiments, machine executable code 1706 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 1704, directly accessed by processor 1702, and executed by processor 1702 using at least logic circuit 1708. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 1704, transferred to a memory device (not shown) for execution, and executed by processor 1702 using at least logic circuit 1708. Thus, in some embodiments, logic circuit 1708 includes electrically configurable logic circuit 1708.

[0201] In some embodiments, machine executable code 1706 may describe hardware (e.g., circuitry) to be implemented in logic circuit 1708 to perform a functional element. The hardware may be described at any of a variety of abstraction levels from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). By way of non-limiting example, VERILOG, SystemVerilog, or a very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0202] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting embodiment, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 1708 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic, discrete hardware components, or a combination thereof of a programmable logic device. Therefore, in some embodiments, the machine executable code 1706 may include an HDL, RTL, GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0203] In embodiments where the machine executable code 1706 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1704) may implement the hardware description described by the machine executable code 1706. By way of non-limiting example, the processor 1702 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1708 may be electronically controlled to implement circuits corresponding to the hardware description into the logic circuit 1708. Also by way of non-limiting example, the logic circuit 1708 may include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage device 1704) according to the hardware description of the machine executable code 1706.

[0204] Regardless of whether the machine executable code 1706 includes computer readable instructions or a hardware description, the logic circuit 1708 is adapted to perform the functional elements described by the machine executable code 1706 when implementing the functional elements of the machine executable code 1706. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0205] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0206] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0207] The terms used in this disclosure and in particular in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means some or all. As used herein, the terms "each and every" mean all.

[0208] Additionally, if a specific number of introduced claim statements is intended, such intent will be expressly recited in the claim, and in the absence of such a statement, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that a claim statement introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (for example, "a" and / or "an" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim statement is introduced using a definite article.

[0209] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers is intended to mean at least two recitations, or two or more recitations, but not limited thereto). Moreover, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0210] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0211] Additional non-limiting examples include:

[0212] Embodiment 1: A device comprising: a duty cycle shaping circuit, which is used to set the duty cycle of a changed feedback clock, wherein the changed feedback clock represents an output clock generated by a clock tracking circuit to track a reference clock; and a logic circuit, which is used to set the duty cycle shaping circuit to reduce the duty cycle mismatch between the reference clock indicated by an up / down error signal and the changed feedback clock.

[0213] Embodiment 2: An apparatus according to embodiment 1, wherein the duty cycle shaping circuit comprises: a variable delay circuit for generating a first delayed clock at least partially in response to a changed feedback clock; a fixed delay circuit for generating a second delayed clock at least partially in response to a changed feedback clock; and a waveform shaping circuit for shaping the waveform of the changed feedback clock at least partially in response to the first delayed clock and the second delayed clock.

[0214] Embodiment 3: The apparatus according to embodiments 1 and 2, wherein the logic circuit sets the duty cycle shaping circuit by: generating a delay setting to set the delay of the variable delay circuit; and generating a waveform shaping setting to set the waveform shaping function of the waveform shaping circuit.

[0215] Embodiment 4: The apparatus according to embodiments 1 to 3, wherein the delay setting indicates an increment or a decrement.

[0216] Embodiment 5: An apparatus according to embodiments 1 to 4, wherein the waveform shaping circuit comprises: a wide logic circuit for generating a first changed clock having a pulse width shorter than a pulse width of a changed feedback clock; a narrow logic circuit for generating a second changed clock having a pulse width longer than the pulse width of the changed feedback clock; and a multiplexer for selectively providing one of the first changed clock or the second changed clock as the changed feedback clock as indicated by the waveform shaping setting.

[0217] Embodiment 6: An apparatus according to embodiments 1 to 5, wherein the logic circuit sets the delay at the variable delay circuit in the following manner: when the pulse width of the changed feedback clock signal is narrower than the pulse width of the reference clock signal, a delay setting is generated to reduce the delay of the variable delay circuit; when the pulse width of the changed feedback clock signal is wider than the pulse width of the reference clock signal, a delay setting is generated to increase the delay of the variable delay circuit.

[0218] Embodiment 7: The apparatus according to embodiments 1 to 6, wherein the waveform shaping circuit comprises: a first input coupled to receive a first delayed clock from a variable delay circuit; and a second input coupled to receive a second delayed clock from a fixed delay circuit.

[0219] Embodiment 8: An apparatus according to embodiments 1 to 7, wherein the waveform shaping circuit is used to: generate a changed feedback clock showing a change from a first state to a second state at least partially in response to a first delayed clock showing a change from a first state to a second state; and generate a changed feedback clock showing a change from a second state to a first state at least partially in response to a second delayed clock showing a change from a second state to a first state.

[0220] Embodiment 9: The apparatus of embodiments 1 to 8, wherein the clock tracking circuit is selected from a group consisting of a hybrid phase-locked loop (PLL), an analog PLL, a digital PLL, a delay-locked loop, an injection-locked loop, or a frequency synthesizer.

[0221] Embodiment 10: The apparatus of embodiments 1 to 9, wherein the logic circuit comprises: a bang-bang phase detector; and a duty cycle mismatch detection and duty cycle shaping control circuit.

[0222] Embodiment 11: The device according to embodiments 1 to 10, wherein the logic circuit comprises: a time-to-digital converter.

[0223] Embodiment 12: A method, comprising: receiving an uplink / downlink error signal indicating a duty cycle mismatch between a reference clock signal and a changed feedback clock signal, the changed feedback clock signal representing an output clock signal generated by a clock tracking circuit to track a reference clock signal; setting the duty cycle of the changed feedback clock signal to reduce the duty cycle mismatch indicated by the uplink / downlink error signal; and providing a changed feedback clock having a set duty cycle.

[0224] Embodiment 13: A method according to embodiment 12, wherein setting the duty cycle of the changed feedback clock signal to reduce the duty cycle mismatch indicated by the uplink / downlink error signal includes: determining a setting for generating a waveform shaping signal for shaping the changed feedback clock signal to reduce the duty cycle mismatch between the changed feedback clock signal and a reference signal; determining a waveform shaping function for shaping the changed feedback clock signal to reduce the duty cycle mismatch between the changed feedback clock signal and the reference signal; and providing a setting to the duty cycle shaping circuit to set the duty cycle of the changed feedback clock, the setting including the determined setting for generating the waveform shaping signal and the determined waveform shaping function.

[0225] Embodiment 14: A method according to embodiments 12 and 13, wherein setting the duty cycle of the changed feedback clock to reduce the duty cycle mismatch indicated by the uplink / downlink error signal includes: setting a delay at a variable delay circuit; delaying the feedback clock at the variable delay circuit to generate a first delayed clock; delaying the feedback clock at the fixed delay circuit to generate a second delayed clock; and shaping the waveform of the changed feedback clock at least partially in response to the first delayed clock and the second delayed clock.

[0226] Embodiment 15: The method according to embodiments 12 to 14, wherein the delay amount by which the delay at the variable delay circuit is set is a predetermined delay amount.

[0227] Embodiment 16: A method according to embodiments 12 to 15, wherein shaping the waveform of the changed feedback clock at least partially in response to the first delayed clock and the second delayed clock includes: when the pulse width of the changed feedback clock signal is narrower than the pulse width of the reference clock signal, instructing the waveform shaping circuit to extend the pulse width of the changed feedback clock signal.

[0228] Embodiment 17: A method according to embodiments 12 to 16, wherein shaping the waveform of the changed feedback clock at least partially in response to the first delayed clock and the second delayed clock includes: when the pulse width of the changed feedback clock signal is wider than the pulse width of the reference clock signal, instructing the waveform shaping circuit to shorten the pulse width of the changed feedback clock signal.

[0229] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: a duty cycle shaping circuit to set a duty cycle of a modified feedback clock, the modified feedback clock representing an output clock generated by a clock tracking circuit to track a reference clock; and A logic circuit is provided to set the duty cycle shaping circuit to reduce a duty cycle mismatch between the reference clock and the modified feedback clock as indicated by an uplink / downlink error signal.

2. The apparatus of claim 1 , wherein the duty cycle shaping circuit comprises: a variable delay circuit to generate a first delayed clock responsive at least in part to the changed feedback clock; a fixed delay circuit to generate a second delayed clock responsive at least in part to the changed feedback clock; and A waveform shaping circuit is provided to shape a waveform of the changed feedback clock in response at least in part to the first delayed clock and the second delayed clock.

3. The apparatus of claim 2, wherein the logic circuit is configured to set the duty cycle shaping circuit in the following manner: generating a delay setting to set a delay of the variable delay circuit; and A waveform shaping setting is generated to set a waveform shaping function of the waveform shaping circuit. The apparatus of claim 3 , wherein the delay setting indicates an increment or a decrement.

5. The apparatus of claim 3, wherein the waveform shaping circuit comprises: a wide logic circuit to generate a first changed clock having a pulse width shorter than a pulse width of the changed feedback clock; a narrow logic circuit to generate a second changed clock having a pulse width longer than the pulse width of the changed feedback clock; and A multiplexer to selectively provide one of the first changed clock or the second changed clock as the changed feedback clock as indicated by the waveform shaping setting.

6. The apparatus of claim 2, wherein the logic circuit is configured to set the delay at the variable delay circuit by: generating a delay setting to reduce the delay of the variable delay circuit when the pulse width of the changed feedback clock signal is narrower than the pulse width of the reference clock signal; and In the event that a pulse width of the altered feedback clock signal is wider than a pulse width of the reference clock signal, a delay setting is generated to increment the delay of the variable delay circuit.

7. The apparatus of claim 6, wherein the waveform shaping circuit comprises: a first input coupled to receive a first delayed clock from a variable delay circuit; and A second input is coupled to receive the second delayed clock from the fixed delay circuit.

8. The apparatus of claim 6, wherein the waveform shaping circuit is configured to: generating the changed feedback clock exhibiting a change from the first state to the second state in response, at least in part, to the first delayed clock exhibiting a change from a first state to a second state; and The changed feedback clock exhibiting a change from the second state to the first state is generated at least in part in response to the second delayed clock exhibiting a change from the second state to the first state.

9. The apparatus of claim 1, wherein the clock tracking circuit is selected from the group consisting of: Hybrid phase-locked loop (PLL), analog PLL, digital PLL, delay-locked loop, injection-locked loop, or frequency synthesizer.

10. The apparatus of claim 1, wherein the logic circuit comprises: bang-bang phase detector; and Duty cycle mismatch detection and duty cycle shaping control circuit.

11. The apparatus of claim 1 , wherein the logic circuit comprises: Time-to-digital converter.

12. A method comprising: receiving an uplink / downlink error signal indicative of a duty cycle mismatch between a reference clock signal and a modified feedback clock signal representing an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of the modified feedback clock signal to reduce a duty cycle mismatch indicated by the uplink / downlink error signal; as well as A modified feedback clock having a set duty cycle is provided.

13. The method of claim 12, wherein setting the duty cycle of the changed feedback clock signal to reduce a duty cycle mismatch indicated by the uplink / downlink error signal comprises: determining settings for generating a waveform shaping signal for shaping the changed feedback clock signal to reduce a duty cycle mismatch between the changed feedback clock signal and the reference clock signal; determining a waveform shaping function for shaping the modified feedback clock signal to reduce a duty cycle mismatch between the modified feedback clock signal and the reference clock signal; as well as Settings are provided to a duty cycle shaping circuit to set the duty cycle of the changed feedback clock, the settings including the determined settings and the determined waveform shaping function to generate a waveform shaped signal.

14. The method of claim 12, wherein setting the duty cycle of the changed feedback clock to reduce a duty cycle mismatch indicated by the uplink / downlink error signal comprises: setting a delay at a variable delay circuit; delaying a feedback clock at the variable delay circuit to generate a first delayed clock; delaying the feedback clock at a fixed delay circuit to generate a second delayed clock; as well as The waveform of the changed feedback clock is shaped at least in part in response to the first delayed clock and the second delayed clock.

15. The method according to claim 14, wherein the delay amount by which the delay at the variable delay circuit is set is a predetermined delay amount.

16. The method of claim 14, wherein shaping the waveform of the changed feedback clock in response at least in part to the first delayed clock and the second delayed clock comprises: In the event that the pulse width of the changed feedback clock signal is narrower than the pulse width of the reference clock signal, a waveform shaping circuit is instructed to lengthen the pulse width of the changed feedback clock signal.

17. The method of claim 14, wherein shaping the waveform of the changed feedback clock in response at least in part to the first delayed clock and the second delayed clock comprises: In the event that the pulse width of the changed feedback clock signal is wider than the pulse width of the reference clock signal, the waveform shaping circuit is instructed to shorten the pulse width of the changed feedback clock signal.

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