Solid-state imaging element and method for controlling solid-state imaging element

Abstract

Image quality is improved by a solid-state imaging element for acquiring an inter-frame difference. A solid-state imaging device includes a pixel signal generating section, first and second sample-and-hold circuits, and a vertical scanning circuit. The pixel signal generation section sequentially generates first and second pixel signals. The first sample hold circuit holds a first pixel signal. The second sample hold circuit holds a second pixel signal. The vertical scan circuit controls the first and second sample hold circuits to generate a composite signal of the first and second pixel signals.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. In particular, the present technology relates to a solid-state imaging element that samples and holds a pixel signal and a method for controlling the solid-state imaging element. Background Art

[0002] Conventionally, in solid-state imaging elements, an inter-frame difference method is used to obtain an inter-frame difference in order to detect a moving object, etc. For example, a solid-state imaging element is proposed in which two capacitor elements are provided for each pixel, one of which is made to hold the signal level of the previous frame, and the other is made to hold the signal level of the current frame (for example, see Patent Document 1). In this solid-state imaging element, the difference between the signal levels of the previous frame and the current frame is calculated by a differential circuit in the subsequent stage. Citation List Patent Literature

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-171666 Summary of the invention Problems to be solved by the present invention

[0004] In the above conventional technology, each pixel maintains the corresponding signal level of the previous frame and the current frame, thereby reducing the frame memory for maintaining the previous frame. However, in order to obtain the difference between the signal levels, when the reset level is different between the previous frame and the current frame, there is a problem that the noise of the differential image increases and its image quality deteriorates.

[0005] The present technology has been made in view of such circumstances, and an object of the present technology is to improve the image quality of a solid-state imaging element that obtains inter-frame differences. Solution to the problem

[0006] The present technology is proposed to solve the above-mentioned problems, and its first aspect is a solid-state imaging element, which includes: a pixel signal generating section, which sequentially generates a first pixel signal and a second pixel signal; a first sampling and holding circuit, which holds the first pixel signal; a second sampling and holding circuit, which holds the second pixel signal; and a vertical scanning circuit, which controls the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal. This brings about the effect of improving the image quality of differential data.

[0007] Furthermore, in the first aspect, the first pixel signal may include a first reset level and a first signal level, the second pixel signal may include a second reset level and a second signal level, and the vertical scanning circuit may cause each of a signal obtained by adding the first reset level to the second signal level and a signal obtained by adding the first signal level to the second reset level to be generated as the synthetic signal. Therefore, there is an effect that a difference between pixel signals after correlated double sampling (CDS) processing can be obtained in a subsequent circuit.

[0008] In addition, in the first aspect, a third sample-and-hold circuit for holding the second pixel signal and a fourth sample-and-hold circuit for holding the second pixel signal may be further included. This brings about an effect that differential data can be generated for each frame.

[0009] In addition, in the first aspect, the pixel signal generating section may also generate a third pixel signal, and the vertical scanning circuit may perform: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and causing one of the third sampling and holding circuit and the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the third sampling and holding circuit and the fourth sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and causing one of the first sampling and holding circuit and the second sampling and holding circuit to output the third pixel signal. This brings about the effect of outputting differential data and the current frame at each exposure.

[0010] In addition, in the first aspect, the pixel signal generating section can also generate a third pixel signal, and the vertical scanning circuit can perform: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and causing the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the second sampling and holding circuit and the third sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and causing the fourth sampling and holding circuit to output the third pixel signal. This brings about the effect of outputting differential data and the current frame at each exposure.

[0011] Furthermore, in the first aspect, the pixel signal generating section may include a first front stage circuit and a second front stage circuit, the first front stage circuit may include a first transfer transistor that transfers charge from the first photoelectric conversion element to the first floating diffusion layer and a first connection transistor that connects the first floating diffusion layer and a predetermined node, and the second front stage circuit may include a second transfer transistor that transfers charge from the second photoelectric conversion element to the second floating diffusion layer and a second connection transistor that connects the second floating diffusion layer and a predetermined node. This brings about an effect of improving resolution in normal imaging where a difference is not obtained.

[0012] Furthermore, in the first aspect, the pixel signal generating section may include a front-stage circuit, and the front-stage circuit may include a transfer transistor that transfers charge from the photoelectric conversion element to the floating diffusion layer. This brings about an effect of reducing the circuit scale of the pixel signal generating section.

[0013] In addition, in the first aspect, the present invention may further include: a motion determination unit that determines whether the subject is moving based on the synthesized signal; and an interface that outputs the second pixel signal when the motion occurs. This reduces the processing and communication volume of the host.

[0014] In addition, in the first aspect, the present invention may further include a column signal processing circuit that outputs the second pixel signal when receiving a determination result indicating that the subject is moving from the outside. This brings about an effect of reducing the processing load of the solid-state imaging element.

[0015] In addition, the second aspect of the present technology is a solid-state imaging element, which includes: a predetermined number of pixels, which sequentially hold and sequentially output a first signal level and a second signal level according to an exposure amount, generate a reset level, and sequentially output the second signal level and the reset level; a differential circuit, which obtains a difference between the first signal level and the second signal level; a comparison section, which compares the absolute value of the difference with a predetermined threshold value and outputs a comparison result; an area determination section, which determines whether each of the pixels is located in an area of ​​a moving body based on the difference and the comparison result; and an analog-to-digital converter, which sequentially converts the second signal level and the reset level into digital signals. This generates an effect of reducing power consumption.

[0016] In addition, in the second aspect, it may further include: an analog-to-digital converter that converts each of the reset level and the second signal level into a digital signal; a vertical scanning circuit that drives a predetermined number of the pixels; and a control circuit that controls the vertical scanning circuit and the analog-to-digital converter to generate the digital signal in a cropped area including the area of ​​the moving body when any of the pixels is determined to be located in the area of ​​the moving body. This brings about the effect of reducing the processing amount and communication amount of the host.

[0017] In addition, in the second aspect, the control circuit may receive cropping region information indicating the cropping region from the outside. This brings about the effect of improving versatility and convenience.

[0018] In addition, in the second aspect, the device may further include a control circuit that changes the analog gain of the region of the moving object when any of the pixels is determined to be located in the region of the moving object. This leads to an effect of improving image quality.

[0019] Furthermore, in the second aspect, the reset level may include a first reset level and a second reset level, the pixel may maintain the first reset level, the first signal level, the second reset level, and the second signal level and sequentially output the first signal level and the second signal level, and in the case where any of the pixels is determined to be located within the area of ​​the moving body, the pixel may sequentially output the second reset level and the second signal level. This brings about an effect of improving image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram showing a configuration example of an imaging system according to a first embodiment of the present technology. Figure 2 : is a diagram showing a configuration example of a pixel block according to the first embodiment of the present technology. Figure 3 : is a diagram showing a layout example of a color filter according to the first embodiment of the present technology. Figure 4 is a circuit diagram showing a configuration example of a pixel signal generating section according to the first embodiment of the present technology. Figure 5 is a circuit diagram showing a configuration example of a sample and hold block according to the first embodiment of the present technology. Figure 6 : is a block diagram showing a configuration example of a load metal oxide semiconductor (MOS) circuit block and a column signal processing circuit according to the first embodiment of the present technology. Figure 7 is a timing chart showing an operation example of the solid-state imaging element in the imaging mode according to the first embodiment of the present technology. Figure 8 : is a timing chart showing an example of global shutter control in the imaging mode according to the first embodiment of the present technology. Fig. 9 : is a timing chart showing an example of a read operation of the solid-state imaging element in the imaging mode according to the first embodiment of the present technology. Fig.10is a diagram showing a state example of the sample and hold block in the imaging mode according to the first embodiment of the present technology. Fig.11 1 is a timing chart showing an operation example until IG2 exposure in the differential output mode of the solid-state imaging element according to the first embodiment of the present technology. Fig.12 1 is a timing chart showing an operation example after IG3 exposure in the differential output mode of the solid-state imaging element according to the first embodiment of the present technology. Fig.13 : is a timing chart showing an example of global shutter control in the differential output mode according to the first embodiment of the present technology. Fig.14 : is a timing chart showing an example of differential data between IG0 and IG1 and a read operation of IG1 according to the first embodiment of the present technology. Fig.15 : is a timing chart showing an example of differential data between IG1 and IG2 and a read operation of IG2 according to the first embodiment of the present technology. Fig.16 is a diagram showing a state example of the sample and hold block in the differential output mode according to the first embodiment of the present technology. Fig.17 is a diagram illustrating an example of image data, difference data, and cropping data according to the first embodiment of the present technology. Fig.18 is a flowchart showing an operation example of the solid-state imaging element according to the first embodiment of the present technology. Fig.19 1 is a timing chart showing an operation example of the solid-state imaging element according to the first modification example of the first embodiment of the present technology until IG2 exposure in the differential output mode. Fig. 20 : is a timing chart showing an operation example after IG3 exposure in the differential output mode of the solid-state imaging element according to the first modification example of the first embodiment of the present technology. Fig.21 : is a diagram showing a layout example of color filters according to a second modification example of the first embodiment of the present technology. Fig. 22 is a circuit diagram showing a configuration example of a pixel signal generating section according to a second modification example of the first embodiment of the present technology. Fig.23 : is a circuit diagram showing a configuration example of a sample and hold block according to a second modification example of the first embodiment of the present technology. Fig.24 : is a block diagram showing a configuration example of a column signal processing circuit according to a third modification example of the first embodiment of the present technology. Fig.25 : is a timing chart showing an operation example of the solid-state imaging element according to the third modification example of the first embodiment of the present technology in the differential output mode. Fig.26 is a block diagram showing a configuration example of a host according to a fourth modification example of the first embodiment of the present technology. Fig. 27 : is a timing chart showing an operation example of the solid-state imaging element according to the fourth modification example of the first embodiment of the present technology in the differential output mode. Fig.28 is a circuit diagram showing a configuration example of a pixel block according to a fifth modification example of the first embodiment of the present technology. Fig.29 is a block diagram showing a configuration example of an imaging system according to a second embodiment of the present technology. Fig.30 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology. Fig.31 : is a block diagram showing a configuration example of a load MOS circuit block and a column signal processing circuit according to a second embodiment of the present technology. Fig.32 is a block diagram showing a configuration example of a column circuit according to a second embodiment of the present technology. Fig.33 : is a circuit diagram showing a configuration example of a selector, a differential circuit, and a comparison section according to a second embodiment of the present technology. Fig.34 2 is a diagram illustrating an operation example of a data conversion section according to the second embodiment of the present technology. Fig.35 is a circuit diagram showing a configuration example of an area determination section according to a second embodiment of the present technology. Fig.36 : is a timing chart showing an operation example of the area determination section according to the second embodiment of the present technology. Fig.37 : is a timing chart showing a first global shutter control example of the solid-state imaging element according to the second embodiment of the present technology. Fig.38 : is a timing chart showing a second global shutter control example of the solid-state imaging element according to the second embodiment of the present technology. Fig.39 : is a timing chart showing an operation example of the solid-state imaging element at the region judgment timing according to the second embodiment of the present technology. Fig.40 : is a timing chart showing an example of a reading operation of the solid-state imaging element according to the second embodiment of the present technology. Fig.41: is a diagram showing an example of states of pixels and selectors at the time of area judgment and at the time of reading according to the second embodiment of the present technology. Fig.42 : is a diagram illustrating an example of image data, difference data, and cropping data according to the second embodiment of the present technology. Fig.43 is a flowchart showing an operation example of the solid-state imaging element according to the second embodiment of the present technology. Fig.44 is a block diagram illustrating a configuration example of an imaging system according to a first modification example of the second embodiment of the present technology. Fig.45 : is a diagram illustrating an example of image data and difference data according to a second modification example of the second embodiment of the present technology. Fig.46 is a circuit diagram showing a configuration example of a pixel according to a third modification example of the second embodiment of the present technology. Fig.47 : is a timing chart showing a first global shutter control example of the solid-state imaging element according to the third modification example of the second embodiment of the present technology. Fig.48 : is a timing chart showing a second global shutter control example of the solid-state imaging element according to the third modification example of the second embodiment of the present technology. Fig.49 : is a timing chart showing an operation example of the solid-state imaging element at the region judgment timing according to the third modification example of the second embodiment of the present technology. Fig.50 : is a timing chart showing an example of a reading operation of a solid-state imaging element according to a third modification example of the second embodiment of the present technology. Fig.51 : is a diagram showing a stacking structure example of a solid-state imaging element according to a fourth modification example of the second embodiment of the present technology. Fig.52 is a circuit diagram showing a configuration example of a pixel according to a fourth modification example of the second embodiment of the present technology. Fig.53 : is a diagram showing a stacking structure example of a solid-state imaging element according to a fifth modification example of the second embodiment of the present technology. Fig.54 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology. Fig.55 : is a timing chart showing an example of a global shutter operation according to the third embodiment of the present technology. Fig.56 is a circuit diagram showing a configuration example of a pixel according to a fourth embodiment of the present technology. Fig.57: is a timing chart showing a voltage control example according to the fourth embodiment of the present technology. Fig.58 : is a timing chart showing an example of a rolling shutter operation according to the fifth embodiment of the present technology. Fig.59 is a block diagram showing a configuration example of a solid-state imaging element according to a sixth embodiment of the present technology. Fig.60 : is a circuit diagram showing a configuration example of a dummy pixel, a regulator, and a switching section according to a sixth embodiment of the present technology. Fig.61 : is a timing chart showing an operation example of a dummy pixel and a regulator according to a sixth embodiment of the present technology. Fig.62 is a circuit diagram showing a configuration example of an effective pixel according to a sixth embodiment of the present technology. Fig.63 is a block diagram showing a schematic configuration example of a vehicle control system. Fig.64 1 is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0021] A mode for implementing the present technology (hereinafter referred to as an embodiment) will be described below. The description will be made in the following order. 1. First Embodiment (Example of Making Two Sample-and-Hold Circuits Generate a Synthesized Signal) 2. Second Embodiment (Example of Making a Differential Circuit Obtain Signal Level Differentiation) 3. Third embodiment (example of adding a discharge transistor) 4. Fourth Embodiment (Example of Controlling Reset Power Supply Voltage) 5. Fifth Embodiment (Example of Executing Rolling Shutter Operation) 6. Sixth embodiment (noise reduction example) 7. Application examples on mobile objects

[0022] <1. First embodiment> [Configuration Example of Imaging System] Figure 1 1 is a block diagram showing a configuration example of an imaging system according to a first embodiment of the present technology. The imaging system includes a solid-state imaging element 200 and a host 100. The solid-state imaging element 200 includes a vertical scanning circuit 211, a control circuit 212, a digital-to-analog converter (DAC) 213, a pixel array section 220, a load MOS circuit block 250, and a column signal processing circuit 260.

[0023] In the pixel array section 220, a plurality of pixels are arranged in a two-dimensional grid. In addition, the pixel array section 220 is divided into a plurality of pixel blocks 500. In each pixel block 500, a plurality of pixels (eg, four pixels in two rows×two columns) are arranged, and these pixels share some circuits.

[0024] The control circuit 212 controls the operation timing of each of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 in synchronization with a vertical synchronization signal or the like.

[0025] The DAC 213 generates a sawtooth ramp signal through digital-to-analog (DA) conversion and supplies the generated ramp signal to the column signal processing circuit 260 .

[0026] The vertical scanning circuit 211 sequentially selects and drives the pixel blocks 500 of each row to output analog pixel signals. The pixels in each row supply the pixel signals to the column signal processing circuit 260 through the load MOS circuit block 250.

[0027] In the load MOS circuit block 250 , there is a MOS transistor provided for supplying a constant current for each column.

[0028] The column signal processing circuit 260 performs signal processing such as AD conversion processing and CDS processing on the pixel signal for each column of the pixel block 500 .

[0029] Here, in the solid-state imaging element 200 , one of a plurality of modes including an imaging mode and a differential output mode is set by the mode signal MODE.

[0030] The imaging mode is a mode in which the solid-state imaging element 200 continuously captures a plurality of image data (frames) and outputs each frame to the host 100. On the other hand, the differential output mode is a mode in which the solid-state imaging element 200 continuously captures a plurality of image data (frames) and outputs differential data (which is the difference between two consecutive frames) and each frame to the host 100.

[0031] The host 100 performs various types of processing on the differential data and the frame as needed.

[0032] [Configuration example of pixel block] Figure 2 201 and 202. It is a diagram showing a configuration example of a pixel block 500 according to the first embodiment of the present technology. Here, it is assumed that circuits and elements in the solid-state imaging element 200 are dispersedly arranged on a stacked pixel chip 201 and a circuit chip 202.

[0033] The pixel block 500 includes a pixel signal generating section 501 and a sampling and holding block 502. Among these components, the pixel signal generating section 501 is arranged on the pixel chip 201, and the sampling and holding block 502 is arranged on the circuit chip 202. In addition, circuits located outside the pixel array section 220 such as the control circuit 212 are also arranged on the circuit chip 202.

[0034] The pixel signal generating section 501 includes front-stage circuits 510, 520, 530, and 540. In addition, the sampling and holding block 502 includes sampling and holding circuits 550, 560, 570, and 580 and a rear-stage circuit 590. These circuits serve as four pixels. The rear-stage circuit 590 is shared by the four pixels.

[0035] Note that although the solid-state imaging element 200 has a stacked structure, circuits and elements in the solid-state imaging element 200 may be arranged on a single semiconductor chip.

[0036] Figure 3 1 is a diagram showing a layout example of a color filter according to the first embodiment of the present technology. FIG. a shows a layout example of a color filter in a pixel chip 201 , and FIG. b shows a layout example of a sample-and-hold circuit in a circuit chip 202 .

[0037] As shown in a of the figure, a red (R), green (G) or blue (B) color filter is set for each pixel. In addition, the color filters of the same color are arranged in two rows and two columns, and the R or B group and the G group are arranged alternately in the horizontal direction and the vertical direction. This array is called a quadruple Bayer array. The above-mentioned pixel signal generation unit 501 is arranged directly below the color filters of two rows and two columns of the same color.

[0038] In addition, as shown in b of the figure, in the circuit chip 202, the sampling and holding block 502 is arranged directly below four color filters of the same color. "SHa", "SHb", "SHc" and "SHd" represent the sampling and holding circuits 550, 560, 570 and 580 in the sampling and holding block 502.

[0039] [Configuration Example of Pixel Signal Generating Section] Figure 4 1 is a circuit diagram showing a configuration example of a pixel signal generating section 501 according to a first embodiment of the present technology. A front-stage circuit 510 includes a photoelectric conversion element 511, a transfer transistor 512, a floating diffusion (FD) reset transistor 513, an FD 514, a front-stage amplifier transistor 515, a precharge transistor 516, and a connection transistor 517.

[0040] The front-stage circuit 520 includes a photoelectric conversion element 521, a transfer transistor 522, an FD reset transistor 523, an FD 524, a front-stage amplifier transistor 525, a precharge transistor 526, and a connection transistor 527. The front-stage circuit 530 includes a photoelectric conversion element 531, a transfer transistor 532, an FD reset transistor 533, an FD 534, a front-stage amplifier transistor 535, a precharge transistor 536, and a connection transistor 537. The front-stage circuit 540 includes a photoelectric conversion element 541, a transfer transistor 542, an FD reset transistor 543, an FD 544, a front-stage amplifier transistor 545, a precharge transistor 546, and a connection transistor 547.

[0041] In the preceding stage circuit 510 , the photoelectric conversion element 511 generates electric charge by photoelectric conversion. The transfer transistor 512 transfers the electric charge from the photoelectric conversion element 511 to the FD 514 according to the transfer signal TXa received from the vertical scanning circuit 211 .

[0042] The FD reset transistor 513 extracts charge from the FD 514 and initializes it according to the FD reset signal RSTa from the vertical scanning circuit 211. The FD 514 accumulates charge and generates a voltage corresponding to the amount of charge. The pre-stage amplifier transistor 515 amplifies the voltage level of the FD 514 and outputs the amplified voltage as V1a to the sample and hold block 502.

[0043] In addition, the sources of the FD reset transistor 513 and the pre-stage amplifier transistor 515 are respectively connected to the power supply voltage VDD. The precharge transistor 516 opens and closes the path between the drain of the pre-stage amplifier transistor 515 and the ground node according to the control signal PC from the vertical scanning circuit 211.

[0044] The connection transistor 517 connects the FD 514 to the common node 505 according to the control signal MG from the vertical scanning circuit 211 .

[0045] The circuit structure of the front-stage circuits 520, 530 and 540 is similar to that of the front-stage circuit 510, but the transmission transistors 522, 532 and 542 are provided with transmission signals TXb, TXc and TXd, and the FD reset transistors 523, 533 and 543 are provided with FD reset signals RSTb, RSTc and RSTd. In addition, V1b, V1c and V1d are output from the front-stage amplifying transistors 525, 535 and 545 to the sampling and holding block 502.

[0046] [Sample and Hold Block Configuration Example] Figure 5is a circuit diagram showing a configuration example of a sample-and-hold block 502 according to a first embodiment of the present technology. The sample-and-hold circuit 550 includes capacitor elements 551 and 552 and selection transistors 553 and 554. The sample-and-hold circuit 560 includes capacitor elements 561 and 562 and selection transistors 563 and 564. The sample-and-hold circuit 570 includes capacitor elements 571 and 572 and selection transistors 573 and 574. The sample-and-hold circuit 580 includes capacitor elements 581 and 582 and selection transistors 583 and 584.

[0047] In addition, the subsequent-stage circuit 590 includes a subsequent-stage reset transistor 591 , a subsequent-stage amplification transistor 592 , and a subsequent-stage selection transistor 593 .

[0048] In the sample-and-hold circuit 550, one ends of the capacitors 551 and 552 are commonly connected to the preceding stage circuit 510. The selection transistor 553 opens and closes the path between the other end of the capacitor 551 and the subsequent stage node 595 according to the selection signal S1a from the vertical scanning circuit 211. The selection transistor 554 opens and closes the path between the other end of the capacitor 552 and the subsequent stage node 595 according to the selection signal S2a from the vertical scanning circuit 211.

[0049] The circuit structure of each of the sample-and-hold circuits 560, 570, and 580 is similar to that of the sample-and-hold circuit 550, but one end of each of the capacitor elements 561 and 562 is connected to the preceding stage circuit 520, and one end of each of the capacitor elements 571 and 572 is connected to the preceding stage circuit 530. One end of each of the capacitor elements 581 and 582 is connected to the preceding stage circuit 540. In addition, the sample-and-hold circuit 560 is supplied with selection signals S1b and S2b, the sample-and-hold circuit 570 is supplied with selection signals S1c and S2c, and the sample-and-hold circuit 580 is supplied with selection signals S1d and S2d.

[0050] The subsequent reset transistor 591 initializes the level of the subsequent node 595 to a predetermined potential Vreg according to a subsequent reset signal RB received from the vertical scanning circuit 211. A potential different from the power supply voltage VDD (eg, a potential lower than VDD) is set as the potential Vreg.

[0051] The post-stage amplifier transistor 592 amplifies the level of the post-stage node 595. The post-stage selection transistor 593 outputs a signal indicating the level amplified by the post-stage amplifier transistor 592 to the vertical signal line 309 as a pixel signal according to the post-stage selection signal SEL received from the vertical scanning circuit 211.

[0052] [Configuration Example of Column Signal Processing Circuit] Figure 6is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0053] In the load MOS circuit block 250, a vertical signal line 309 is wired for each column of the pixel block 500. If the number of columns is I (I is an integer), I vertical signal lines 309 are wired. In addition, a load MOS transistor 251 for supplying a constant current id2 is connected to each vertical signal line 309.

[0054] A plurality of ADCs 261 and a digital signal processing unit 262 are provided in the column signal processing circuit 260. The ADC 261 is provided for each column of the pixel block 500. If the number of columns is 1, one ADC 261 is arranged.

[0055] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. As the ADC 261, for example, a single slope ADC including a comparator and a counter is arranged.

[0056] The digital signal processing section 262 performs predetermined signal processing such as CDS processing on each digital signal for each column. The digital signal processing section 262 outputs image data (frame) or differential data including the processed digital signal to the host 100 .

[0057] [Operation Example of Solid-State Imaging Element] Figure 7 1 is a timing chart showing an operation example of the solid-state imaging element 200 in the imaging mode according to the first embodiment of the present technology. Assume that the imaging mode is set at time T0.

[0058] During the exposure period from time T0 to time T1 , all pixel signal generating sections 501 (in other words, all pixels) are exposed at the same time, and image data (frame) IG0 is generated.

[0059] At time T1 just before the end of exposure, the sample-and-hold circuits 550, 560, 570, and 580 sample and hold the reset levels P0a, P0b, P0c, and P1d, i.e., the pixel signal levels at the time of initialization. In addition, at time T2 when the exposure ends, the sample-and-hold circuits 550, 560, 570, and 580 sample and hold the signal levels D0a, D0b, D0c, and D1d, i.e., the pixel signal levels corresponding to the exposure amount.

[0060] During the reading period from time T2 to time T3, the vertical scanning circuit 211 sequentially selects the rows of the pixel block 500 to output pixel signals (reset level and signal level). In addition, the column signal processing circuit 260 performs AD conversion on the pixel signals from the selected rows and performs CDS processing, etc. Thus, the first image data IG0 is read.

[0061] During the exposure period from time T3 to time T5 , all pixels are exposed simultaneously, and image data IG1 is generated.

[0062] At time T4 before the exposure is about to end, the sampling and holding circuits 550, 560, 570 and 580 sample and hold the reset levels P1a, P1b, P1c and P1d. In addition, at time T5 when the exposure ends, the sampling and holding circuits 550, 560, 570 and 580 sample and hold the signal levels D1a, D1b, D1c and D1d.

[0063] During the reading period from time T5 to time T6, the vertical scanning circuit 211 sequentially selects the rows of the pixel block 500 to output pixel signals. In addition, the column signal processing circuit 260 performs AD conversion on the pixel signals from the selected rows, and performs CDS processing, etc. Thus, the second image data IG1 is read. Thereafter, a plurality of pieces of image data are continuously generated by similar control.

[0064] Figure 8 2 is a timing diagram showing an example of global shutter control in imaging mode according to the first embodiment of the present technology. From the moment T10 immediately before exposure starts to the moment T11 after the pulse period has passed, the vertical scanning circuit 211 provides a high-level FD reset signal RST and a high-level transfer signal TX to all rows (in other words, all pixels). This process is hereinafter referred to as "PD reset". By resetting the PD of all pixels, all rows start exposure at the same time.

[0065] Then, at time T12 just before the end of the exposure period, the vertical scanning circuit 211 provides a high-level FD reset signal RST during the pulse period, and sets the subsequent reset signal RB to a high level in all pixels. This process is hereinafter referred to as "FD reset". In addition, during the period from time T12 to time T13, the vertical scanning circuit 211 provides high-level selection signals S1a, S1b, S1c, and S1d to all pixel blocks 500. Therefore, the reset level is sampled and maintained in all pixels.

[0066] At the moment T14 when the exposure ends, the vertical scanning circuit 211 provides a high-level transmission signal TX to all pixels during the pulse period. Therefore, a signal level is generated. In addition, during the period from the moment T14 to the moment T15, the vertical scanning circuit 211 provides high-level selection signals S2a, S2b, S2c and S2d to all pixel blocks 500. Therefore, the signal level is sampled and maintained in all pixels.

[0067] At time T16 after time T15 , the vertical scanning circuit 211 sets the FD reset signal RST and the transfer signal TX to the high level, and sets the subsequent-stage reset signal RB to the low level.

[0068] In addition, in the imaging mode, the control signal MG is controlled to a low level. Therefore, the FD of four pixels is separated, and the reset level and the signal level of each pixel are generated and held.

[0069] Fig. 9 1 is a timing diagram showing an example of a read operation of the solid-state imaging element 200 in the imaging mode according to the first embodiment of the present technology. In the figure, Rn represents the read period of the n-th row pixel block 500. Here, n is an integer from 0 to N-1. During the read period of each row, the FD reset signal RST and the transmission signal TX are controlled to a high level.

[0070] In the reading period of the n-th row from the time T20 to the time T29 , the vertical scanning circuit 211 sets the subsequent-stage selection signal SEL of the n-th row to the high level.

[0071] In addition, in the pulse period directly after the moment T20, the vertical scanning circuit 211 provides the high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T21 directly after the above-mentioned provision, the vertical scanning circuit 211 provides the high-level selection signal S1a to the n-th row. Therefore, the reset level of the upper left pixel in the pixel block 500 is read. In the pulse period directly after the reset level reading, the vertical scanning circuit 211 provides the high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T22 directly after the above-mentioned provision, the vertical scanning circuit 211 provides the high-level selection signal S2a to the n-th row. Therefore, the signal level of the upper left pixel in the pixel block 500 is read.

[0072] Then, by similar control of the subsequent-stage reset signal RB and the selection signals S1b and S2b, the reset level and the signal level of the upper right pixel are read during a predetermined period starting from the timing T23 and during a predetermined period starting from the timing T24.

[0073] Under the control of the subsequent-stage reset signal RB and the selection signals S1c and S2c, the reset level and the signal level of the lower left pixel are read during a predetermined period starting from the time T25 and during a predetermined period starting from the time T26.

[0074] Under the control of the subsequent-stage reset signal RB and the selection signals S1d and S2d, the reset level and the signal level of the lower right pixel are read during a predetermined period starting from the time T27 and during a predetermined period starting from the time T28.

[0075] Fig.10 5 is a diagram showing a state example of the sample and hold block 502 in the imaging mode according to the first embodiment of the present technology. In the figure, selection transistors 553, 554, 563, 564, 573, 574, 583, and 584 are represented by switch graphic symbols.

[0076] FIG. a shows the state of the sampling and holding block 502 just after the exposure ends. All the selection transistors are controlled to be in the off state. FIG. b shows the state of the sampling and holding block 502 during the reading period of the reset level P0a of the upper left pixel in the nth row. The vertical scanning circuit 211 turns on only the selection transistor 553 to output P0a.

[0077] c of the diagram shows the state of the sample hold block 502 during the reading period of the signal level D0a of the upper left pixel in the n-th row. The vertical scanning circuit 211 turns on only the selection transistor 554 to output D0a.

[0078] d of the figure shows the state of the sample hold block 502 during the reading period of the reset level P0b of the upper right pixel in the nth row. The vertical scanning circuit 211 turns on only the selection transistor 563 to output P0b.

[0079] Figure e shows the state of the sampling and holding block 502 during the reading period of the signal level D0b of the upper right pixel in the nth row. The vertical scanning circuit 211 turns on only the selection transistor 564 to output D0b. Thereafter, the reset level and signal level of the lower left and lower right pixels are read in a similar control sequence. For the (n+1)th row and subsequent rows, the pixel signals (reset level and signal level) of the four pixels are read in a similar control sequence.

[0080] Fig.11 1 is a timing chart showing an operation example until IG2 is exposed in the differential output mode of the solid-state imaging element 200 according to the first embodiment of the present technology. It is assumed that the differential output mode is set at time T0.

[0081] During the exposure period from time T0 to time T2 , all pixels are exposed simultaneously, and the first image data IG0 is generated.

[0082] At time T1 just before the end of exposure, the sample-and-hold circuits 550, 560 and 580 sample and hold reset levels P0a, P0b and P0d. Also, at time T2 when the exposure ends, the sample-and-hold circuits 550, 560 and 580 sample and hold signal levels D0a, D0b and D0d.

[0083] During the exposure period from time T3 to time T6 , all pixels are exposed simultaneously, and the second image data IG1 is generated.

[0084] At time T5 just before the end of exposure, the sample-and-hold circuits 560, 570 and 580 sample and hold the reset levels P1b, P1c and P1d. Also, at time T6 when the exposure ends, the sample-and-hold circuits 560, 570 and 580 sample and hold the signal levels D1b, D1c and D1d.

[0085] During the reading period from time T4 to time T5 in the second exposure period, the vertical scanning circuit 211 controls the sample-and-hold circuit 560 to output a pixel signal. The ADC 261 of each column reads the image data IG0.

[0086] Then, during the period from time T6 to time T8, the vertical scanning circuit 211 controls the sample-and-hold circuits 550 and 560 to output differential data between the image data IG0 and IG1. The ADC 261 of each column reads the differential data.

[0087] Furthermore, during the exposure period from time T7 to time T10 , all pixels are exposed at the same time, and third image data (frame) IG2 is generated.

[0088] At time T9 just before the end of exposure, the sample-and-hold circuits 550, 560 and 580 sample and hold the reset levels P2a, P2b and P2d. Also, at time T10 when the exposure ends, the sample-and-hold circuits 550, 560 and 580 sample and hold the signal levels D2a, D2b and D2d.

[0089] During the reading period from time T8 to time T9 in the third exposure period, the vertical scanning circuit 211 controls the sample-and-hold circuit 580 to output a pixel signal. The ADC 261 of each column reads the image data IG1.

[0090] Then, during a period after the timing T10, the vertical scanning circuit 211 controls the sample-and-hold circuits 570 and 580 to output differential data between the image data IG1 and IG2. The ADC 261 of each column reads the differential data.

[0091] Fig.121 is a timing chart showing an operation example after IG3 exposure in the differential output mode of the solid-state imaging element 200 according to the first embodiment of the present technology.

[0092] During the exposure period from time T11 to time T14 , all pixels are exposed simultaneously, and fourth image data IG3 is generated.

[0093] At time T13 just before the end of exposure, the sample-hold circuits 560, 570 and 580 sample and hold the reset levels P3b, P3c and P3d. Also, at time T14 when the exposure ends, the sample-hold circuits 560, 570 and 580 sample and hold the signal levels D3b, D3c and D3d.

[0094] During the reading period from time T12 to time T13 in the fourth exposure period, the vertical scanning circuit 211 controls the sample-and-hold circuit 560 to output a pixel signal. The ADC 261 of each column reads the image data IG2.

[0095] Then, during the period from time T14 to time T16, the vertical scanning circuit 211 controls the sample-and-hold circuits 550 and 560 to output differential data between the image data IG2 and IG3. The ADC 261 of each column reads the differential data.

[0096] Furthermore, during the exposure period from time T15 to time T18 , all pixels are exposed at the same time, and fifth image data IG4 is generated.

[0097] At time T17 just before the end of exposure, the sample-and-hold circuits 550, 560 and 580 sample and hold the reset levels P4a, P4b and P4d. Also, at time T18 when the exposure ends, the sample-and-hold circuits 550, 560 and 580 sample and hold the signal levels D4a, D4b and D4d.

[0098] During the reading period from time T16 to time T17 in the fifth exposure period, the vertical scanning circuit 211 controls the sample-and-hold circuit 580 to output a pixel signal. The ADC 261 of each column reads the image data IG3.

[0099] Then, during the period from time T18 to time T20, the vertical scanning circuit 211 controls the sample-and-hold circuits 570 and 580 to output differential data between the image data IG3 and IG4. The ADC 261 of each column reads the differential data.

[0100] In addition, during the exposure period from time T19 to time T22, all pixels are exposed at the same time, and the sixth image data IG5 is generated. During the reading period from time T20 to time T21 in the exposure period, the vertical scanning circuit 211 controls the sampling and holding circuit 560 to output the pixel signal. The ADC 261 of each column reads the image data IG4.

[0101] like Fig.11 and 12 As shown, at the end of exposure, three of the four sampling and holding circuits in the pixel block 500 sample and hold the pixel signal of the current frame, that is, the current image data. The remaining sampling and holding circuit holds the pixel signal of the previous frame, that is, the previous image data. Two of the three sampling and holding circuits holding the current frame are used to generate differential data, and the remaining sampling and holding circuit is used to output the current frame. In this way, the solid-state imaging element 200 can output differential data and frames to the host 100 each time a frame is imaged.

[0102] Note that although the solid-state imaging element 200 outputs the differential frame and the entire frame, a portion of the frame may be output in the second frame and subsequent frames. In this case, for example, the column signal processing circuit 260 or the like extracts a rectangular area including an area where the absolute value of the differential is equal to or greater than the threshold value in the differential frame as a region of interest (ROI) area. The control circuit 212 controls the vertical scanning circuit 211 and the column signal processing circuit 260 to output only the ROI area. Therefore, only the ROI area can be read, and the reading speed can be made faster than in the case of reading the entire frame.

[0103] Fig.13 1 is a timing chart showing an example of global shutter control in differential output mode according to the first embodiment of the present technology. Figure 8 The control in the imaging mode shown is similar, but the difference is that the control signal MG is controlled to a high level, and the pixel signals of the current frame are held in the three sample-and-hold circuits. For example, at the end of IG1 exposure, the selection signals S1a and S1b are controlled to a low level, and the pixel signals of the previous frame are held in the sample-and-hold circuits corresponding to these selection signals. The remaining three sample-and-hold circuits hold the pixel signals of the current frame.

[0104] In addition, the FDs of the four pixels are connected by a high-level control signal MG, and a pixel signal obtained by adding the signals of the four pixels is held in the FD. By this pixel addition, the number of pixels in the differential output mode becomes 1 / 4 of that in the imaging mode.

[0105] Fig.141 is a timing chart showing a read operation example of differential data between IG0 and IG1 and IG1 according to the first embodiment of the present technology. During the read period of each row, the FD reset signal RST and the transmission signal TX are controlled to a high level.

[0106] In the reading period of differential data of the n-th row from the time T20 to the time T23 , the vertical scanning circuit 211 sets the subsequent-stage selection signal SEL of the n-th row to the high level.

[0107] In addition, in the pulse period directly after the moment T20, the vertical scanning circuit 211 provides a high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T21 directly after the provision, the vertical scanning circuit 211 provides high-level selection signals S1a and S2b to the n-th row. Therefore, a composite signal obtained by synthesizing the reset level and the signal level is read. In the pulse period directly after the first reading of the mixed signal, the vertical scanning circuit 211 provides a high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T22 directly after the above-mentioned provision, the vertical scanning circuit 211 provides high-level selection signals S2a and S1b to the n-th row. Therefore, a composite signal of the signal level and the reset level is read. Differential data is obtained by performing CDS processing on these composite signals. The reason will be explained later.

[0108] In addition, during the reading period of the pixel signal of the n-th row from the time T24 to the time T27 , the vertical scanning circuit 211 sets the subsequent-stage selection signal SEL of the n-th row to the high level.

[0109] In addition, in the pulse period directly after the moment T24, the vertical scanning circuit 211 provides the high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T25 directly after the above-mentioned provision, the vertical scanning circuit 211 provides the high-level selection signal S1d to the n-th row. Therefore, the reset level of the current frame (IG1) is read. In the pulse period directly after the reset level reading, the vertical scanning circuit 211 provides the high-level rear-stage reset signal RB to the n-th row. In the predetermined period starting from the moment T26 directly after the provision, the vertical scanning circuit 211 provides the high-level selection signal S2d to the n-th row. Therefore, the signal level of the current frame (IG1) is read.

[0110] Fig.15 is a timing chart showing an example of a read operation of differential data between IG1 and IG2 and IG2 according to the first embodiment of the present technology. After reading the differential data between IG0 and IG1 and IG1, Fig.14 Similar control is used to read the differential data of IG1 and IG2 as well as IG2.

[0111] Fig.16 1 is a diagram showing an example of the state of the sampling and holding block 502 in the differential output mode according to the first embodiment of the present technology. FIG. a shows the state of the sampling and holding block 502 just after the exposure of IG1 ends. All selection transistors are controlled to be in the off state. The sampling and holding circuits 560, 570, and 580 hold the reset levels P1b, P1c, and P1d and the signal levels D1b, D1c, and D1d of the current frame. The remaining sampling and holding circuits 550 hold the reset signal P0a and the signal level D0a of the previous frame.

[0112] The state of the sampling and holding block 502 when the first composite signal is read after the exposure of IG1 is completed is shown in b. The vertical scanning circuit 211 controls the selection transistors 553 and 564 to be turned on. Therefore, a composite signal obtained by adding the reset level P0a of the previous frame and the signal level D1b of the current frame is generated. The composite signal MIX1 is represented by the following expression. MIX1 = P0a + D1b ... Expression 1

[0113] Figure c shows the state of the sampling and holding block 502 when the second composite signal is read after the exposure of IG1 is completed. The vertical scanning circuit 211 controls the selection transistors 554 and 563 to be turned on. Therefore, a composite signal obtained by adding the signal level D0a of the previous frame and the reset level P1b of the current frame is generated. The composite signal MIX2 is represented by the following expression. MIX2 = D0a + P1b ... Expression 2

[0114] The column signal processing circuit 260 in the subsequent stage performs processing for currently performing the first synthesized signal into the second synthesized signal as CDS processing. The subtraction result C1 is expressed by the following expression based on Expressions 1 and 2. C1 = MIX1 - MIX2 ... Expression 3

[0115] When the right sides of Expressions 1 and 2 are substituted into Expression 3 and transformed, the following expression is obtained. C1 = (P0a + D1b) - (D0a + P1b) = (D1b - P1b) - (D0a - P0a) ... Expression 4

[0116] "D1b - P1b" in Expression 4 represents the pixel signal SIG1 after CDS processing of the current frame, and "D0a - P0a" represents the pixel signal SIG0 after CDS processing of the previous frame. Therefore, the CDS processing result C1 of the first and second synthesized signals corresponds to the difference between the pixel signals SIG1 and SIG0. The data arranged with C1 in each pixel block 500 corresponds to the inter-frame difference data of IG0 and IG1.

[0117] After outputting the differential data, the vertical scanning circuit 211 controls the sample and hold circuit 580 to output the pixel signal of the current frame.

[0118] Here, a solid-state imaging element that obtains the difference between the signal level of the previous frame (D0a, etc.) and the signal level of the current frame (D1b, etc.) is assumed as a comparative example. In this comparative example, if the reset level of the previous frame is different from the reset level of the current frame, the noise of the differential data will increase due to the difference in reset level.

[0119] On the other hand, as shown in Expressions 1 and 2, in the solid-state imaging element 200 that outputs a composite signal of a signal level and a reset level, even if there is a difference in the reset level, the potential difference is eliminated from the differential data as shown in Expression 4. Therefore, the noise of the differential data is reduced compared to the comparative example, and its image quality can be improved.

[0120] D of the figure shows the state of the sample and hold block 502 just after the exposure of IG2 is completed. The sample and hold circuits 550, 560 and 580 hold the reset levels P2a, P2b and P2d and the signal levels D2a, D2b and D2d of the current frame. The remaining sample and hold circuit 570 holds the reset signal P1c and the signal level D1c of the previous frame.

[0121] Fig. e shows the state of the sample hold block 502 when the first composite signal is read after the exposure of IG2 ends. The vertical scanning circuit 211 controls the selection transistors 573 and 584 to be turned on. Thus, a composite signal obtained by adding the reset level P1c of the previous frame and the signal level D2d of the current frame is generated.

[0122] f in the figure shows the state of the sample hold block 502 when the second composite signal is read after the exposure of IG2 ends. The vertical scanning circuit 211 controls the selection transistors 574 and 583 to be turned on. Therefore, a composite signal obtained by adding the signal level D1c of the previous frame and the reset level P2d of the current frame is generated.

[0123] By performing CDS processing on these synthesized signals, inter-frame difference data of IG1 and IG2 are obtained.

[0124] In summary, the pixel signal generating section 501 sequentially generates pixel signals such as IG0, IG1 and IG2. As shown in a of the figure, the sampling and holding circuit 550 holds the pixel signal of the previous frame IG0, and the sampling and holding circuits 560, 570 and 580 hold the pixel signal of the current frame IG1.

[0125] Then, as shown in b and c of the figure, the vertical scanning circuit 211 controls the sampling and holding circuits 550 and 560 to generate a composite signal of the pixel signal of IG0 and the pixel signal of IG1. At this time, the vertical scanning circuit 211 generates a composite signal obtained by adding the reset level P0a and the signal level D1b, and then generates a composite signal obtained by adding the signal level D0a and the reset level P1b.

[0126] After outputting the differential data, the vertical scanning circuit 211 controls the sample and hold circuit 580 to output the pixel signal of the current frame IG1.

[0127] Subsequently, as shown in d of the drawing, the sample-and-hold circuit 570 holds the pixel signal of the previous frame IG1, and the sample-and-hold circuits 550, 560, and 580 hold the pixel signal of the current frame IG2.

[0128] Then, as shown in Figures e and f, the vertical scanning circuit 211 controls the sampling and holding circuits 570 and 580 to generate a composite signal of the pixel signal of IG1 and the pixel signal of IG2. After outputting the differential data, the vertical scanning circuit 211 controls the sampling and holding circuit 560 to output the pixel signal of the current frame (IG2).

[0129] Note that the sample-and-hold circuits 550, 560, 570, and 580 are examples of the first, second, third, and fourth sample-and-hold circuits described in the claims. The pixel signals IG0, IG1, and IG2 are examples of the first, second, and third pixel signals described in the claims. The reset level P0a and the signal level D0a are examples of the first reset level and the first signal level described in the claims. The reset level P1a and the signal level D1a are examples of the second reset level and the second signal level described in the claims.

[0130] Fig.17 1 is a diagram showing examples of image data, differential data, and cropped data according to the first embodiment of the present technology. a of the figure shows an example of image data 610 , and b shows an example of image data 620 generated after the image data 610 .

[0131] The image data 610 includes subjects 611 and 612, and the image data 620 includes subjects 621 and 622. The subjects 611 and 621 are the same moving object and have different positions in the respective image data. For example, the subject 611 is located in an area having coordinates (X1, Y1), (X1, Y3), (X3, Y1), and (X3, Y3) as vertices, and the subject 621 is located in an area having coordinates (X2, Y2), (X2, Y4), (X4, Y2), and (X4, Y4) as vertices.

[0132] On the other hand, the subjects 612 and 622 are the same stationary object and have the same position.

[0133] In addition, c of the figure shows an example of difference data 630. Since the positions of the objects 612 and 622 do not change, the absolute value of the difference is smaller than the threshold value in the area corresponding to the object.

[0134] On the other hand, since the positions of the objects 611 and 621 are different, the absolute value of the difference exceeds the threshold in the region having the coordinates (X1, Y1), (X1, Y4), (X4, Y1), and (X4, Y4) as vertices.

[0135] For example, the solid-state imaging element 200 outputs the differential data 630 , and then outputs the image data 620 .

[0136] Note that after outputting the differential data 630, the solid-state imaging element 200 may also output a rectangular region including a region where the absolute value of the differential exceeds a threshold as a ROI region. In this case, as shown in d of the figure, the cropped data 625 obtained by cropping the ROI region from the image data 620 is output. The rough single-point dashed line indicates the region where the differential exceeds the threshold.

[0137] Fig.18 1 is a flowchart showing an operation example of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when a predetermined application for capturing image data is executed, the operation starts.

[0138] The solid-state imaging element 200 determines whether the set mode is the differential output mode (step S901). In the case of the differential output mode (step S901: Yes), the solid-state imaging element 200 exposes all pixels by the global shutter method and holds the pixel signal of each sample-and-hold circuit (step S902). Then, the solid-state imaging element 200 outputs differential data (step S903) and outputs the pixel signals of all pixels or the ROI area (step S904).

[0139] In the case of the imaging mode (step S901: No), the solid-state imaging element 200 exposes all pixels by the global shutter method and holds the pixel signal of each pixel (step S906). Then, the solid-state imaging element 200 outputs the pixel signals of all pixels (step S907).

[0140] After step S904 or S907, the solid-state imaging element 200 determines whether the host 100 indicates the end of imaging (step S905). In the case of indicating the end of imaging (step S905: Yes), the solid-state imaging element 200 terminates the imaging operation. On the other hand, in the case of not indicating the end of imaging (step S905: No), the solid-state imaging element 200 repeatedly executes step S901 and subsequent steps.

[0141] As described above, according to the first embodiment of the present technology, since the vertical scanning circuit 211 controls two sample-and-hold circuits to generate a composite signal, the noise of differential data can be reduced and the image quality can be improved.

[0142] [First Modification] In the first embodiment described above, the sampling and holding circuit that outputs the current frame varies for each frame, but may also be fixed. The solid-state imaging element 200 according to the first variation of the first embodiment is different from the first embodiment in that the sampling and holding circuit that outputs the current frame is fixed.

[0143] Fig.19 1 is a timing chart showing an operation example of the solid-state imaging element according to the first modification of the first embodiment of the present technology until exposure of IG2 in the differential output mode. The operation of the first modification of the first embodiment is different from that of the first embodiment in that, in the period after the time T10, the vertical scanning circuit 211 controls the sampling and holding circuits 560 and 570 to output the differential data between the image data IG1 and IG2.

[0144] Fig. 20 1 is a timing chart showing an operation example after IG3 exposure in the differential output mode of the solid-state imaging element according to the first modification example of the first embodiment of the present technology. Differences from the first embodiment will be described.

[0145] During the reading period from time T12 to time T13 , the vertical scanning circuit 211 controls the sample-and-hold circuit 580 to output a pixel signal.

[0146] Furthermore, during the period from time T18 to time T20 , the vertical scanning circuit 211 controls the sample-and-hold circuits 560 and 570 to output differential data between the image data IG3 and IG4 .

[0147] Then, during the reading period from time T20 to time T21 , the vertical scanning circuit 211 controls the sample-and-hold circuit 580 to output a pixel signal.

[0148] like Fig.19 and 20 As shown, the vertical scanning circuit 211 alternately performs control for causing the sample-hold circuits 550 and 560 to generate a composite signal and control for causing the sample-hold circuits 560 and 570 to generate a composite signal. Therefore, the current frame can be output by controlling the sample-hold circuit 580 for each frame. That is, the sample-hold circuit that outputs the current frame can be fixed.

[0149] As described above, according to the first variation of the first embodiment of the present technology, the vertical scanning circuit 211 alternately performs control for causing the sample-hold circuits 550 and 560 to generate a composite signal and control for causing the sample-hold circuits 560 and 570 to generate a composite signal. Therefore, the sample-hold circuit that outputs the current frame can be fixed.

[0150] [Second Modification] In the first embodiment described above, a sample-and-hold circuit is provided for each pixel, but it is preferable to further reduce the circuit scale of the pixel chip 201. The solid-state imaging element 200 according to the second modification of the first embodiment is different from the first embodiment in that the circuit scale of the pixel chip 201 is reduced.

[0151] Fig.21 1 is a diagram showing a layout example of a color filter according to a second modification of the first embodiment of the present technology. FIG. a shows a layout example of a color filter in a pixel chip 201, and FIG. b shows a layout example of a sample-and-hold circuit in a circuit chip 202.

[0152] As shown in a of the figure, in the second modification of the first embodiment, R, G and B color filters are arranged in a Bayer array. The pixel signal generating section 501 is arranged directly below one color filter.

[0153] Furthermore, as shown in b of the figure, in the circuit chip 202, four holding circuits (SHa, SHb, SHc, and SHd) are arranged right below one color filter.

[0154] Fig. 22 1 is a circuit diagram showing a configuration example of a pixel signal generating unit 501 according to a second modification of the first embodiment of the present technology. The pixel signal generating unit 501 of the second modification of the first embodiment is different from the first embodiment in that only the front-stage circuit 510 is arranged. In addition, in the front-stage circuit 510, the connection transistor 517 is reduced.

[0155] Fig.231 is a circuit diagram showing a configuration example of a sampling and holding block 502 according to a second modification of the first embodiment of the present technology. The sampling and holding block 502 of the second modification of the first embodiment is different from that of the first embodiment in that one end of each of the capacitive elements 551, 552, 561, 562, 571, 572, 581, and 582 is commonly connected to the pixel signal generating section 501.

[0156] include Fig. 22 The pixel signal generating unit 501 and Fig.23 The circuit in the sample and hold block 502 acts as a pixel.

[0157] like Fig.23 and 24 As shown, by arranging four sample-and-hold circuits for each pixel, three previous circuits in the pixel signal generating section 501 can be reduced, and the circuit scale of the pixel chip 201 can be reduced. In addition, the light receiving area of ​​each pixel can be increased without changing the chip area.

[0158] Note that the first modification example of the first embodiment can be applied to the second modification example of the first embodiment.

[0159] As described above, according to the second modification example of the first embodiment of the present technology, since four sample-and-hold circuits are arranged for each pixel, the circuit scale of the pixel chip 201 can be reduced.

[0160] [Third Modification] In the above-mentioned first embodiment, the solid-state imaging element 200 outputs all frames to the host 100, but it is preferable to further reduce the processing amount and communication amount of the host 100. The solid-state imaging element 200 according to the third modification of the first embodiment is different from the first embodiment in that the solid-state imaging element 200 outputs frames in the case of motion.

[0161] Fig.24 1 is a block diagram showing a configuration example of a column signal processing circuit 260 according to a third modification of the first embodiment of the present technology. The column signal processing circuit 260 of the third modification of the first embodiment is different from the first embodiment in that it further includes a selector 263, a motion determination unit 264, and a communication interface 265.

[0162] Under the control of the control circuit 212 , the selector 263 supplies the differential data to the motion determination section 264 and supplies the frame to the communication interface 265 .

[0163] The motion determination unit 264 determines whether the subject is moving based on the differential data. For example, the motion determination unit 264 calculates the difference between the pixel signal of the previous frame and the pixel signal of the current frame for each pixel, and determines whether the absolute value of the difference exceeds a predetermined threshold for each pixel. Then, if the number of pixels whose absolute value of the difference exceeds the threshold is greater than a predetermined number, the motion determination unit 264 determines that the subject is moving. The motion determination unit 264 provides the determination result to the communication interface 265.

[0164] In the case where it is determined that there is motion, the communication interface 265 outputs a frame to the host 100. On the other hand, in the case where it is determined that there is no motion, the communication interface 265 outputs invalid NULL data to the host 100. Note that the communication interface 265 is an example of an interface described in the claims.

[0165] Furthermore, in the third modification of the first embodiment, the column signal processing circuit 260 does not output differential data to the host 100 .

[0166] Fig.25 3 is a timing chart showing an operation example of the solid-state imaging element according to the third modification example of the first embodiment of the present technology in the differential output mode. It is assumed that the differential output mode is set at time T0.

[0167] During the exposure period from time T0 to time T1, all pixels are exposed at the same time, and image data (frame) IG1 is generated. During the period from time 1 to time T2, the solid-state imaging element 200 reads the differential data between IG1 and the previous frame, and during the period from time T2 to time T3, it is determined whether there is motion. At this time, it is assumed that it is determined that there is no motion. In this case, during the period from time T3 to time T4, the solid-state imaging element 200 outputs NULL data to the host 100. Note that the read differential data is not output to the host 100.

[0168] Then, during the exposure period from time T4 to time T5, all pixels are exposed at the same time, and the next frame IG2 is generated. During the period from time 5 to time T6, the solid-state imaging element 200 reads the differential data between IG1 and IG2, and during the period from time T6 to time T7, it is determined whether there is motion. At this time, it is assumed that it is determined that there is motion. In this case, during the period after time T7, the solid-state imaging element 200 outputs the current frame IG2 to the host 100.

[0169] As shown in the figure, since frames are output only when there is motion, the host 100 does not need to process frames during the period when there is no motion. Therefore, the processing amount of the host 100 can be reduced. In addition, since the solid-state imaging element 200 does not output differential data to the host 100, the communication amount with the host 100 can be reduced accordingly.

[0170] Note that the first and second modifications of the first embodiment can be applied to the third modification of the first embodiment.

[0171] As described above, according to the third modification of the first embodiment of the present technology, since the solid-state imaging element 200 determines whether there is motion and outputs a frame when there is motion, the processing amount and communication amount of the host 100 can be reduced.

[0172] [Fourth Modification] In the third modification of the first embodiment, the solid-state imaging element 200 determines whether there is motion, but the determination process may be performed by the host 100. The fourth modification of the first embodiment differs from the third modification of the first embodiment in that the host 100 determines whether there is motion.

[0173] Fig.26 1 is a block diagram showing a configuration example of the host computer 100 according to the fourth modification example of the first embodiment of the present technology. The host computer 100 includes a motion determination section 111 , an image processing section 112 , and a recording section 113 .

[0174] The column signal processing circuit 260 in the solid-state imaging element 200 of the fourth modification example of the first embodiment outputs differential data to the host 100 .

[0175] The motion determination section 111 determines whether or not there is motion of the subject based on the difference data, and supplies the determination result to the solid-state imaging element 200 .

[0176] The column signal processing circuit 260 in the solid-state imaging element 200 of the fourth modification of the first embodiment receives the determination result and outputs a frame to the host 100 when it is determined that there is motion. On the other hand, when it is determined that there is no motion, the column signal processing circuit 260 outputs NULL data to the host 100.

[0177] The image processing unit 112 in the host computer 100 performs various image processing on the frame. The image processing unit 112 supplies the processed frame to the recording unit 113. The recording unit 113 records the frame.

[0178] Fig. 27 4 is a timing chart showing an operation example of the solid-state imaging element according to the fourth modification example of the first embodiment of the present technology in the differential output mode. It is assumed that the differential output mode is set at time T0.

[0179] During the exposure period from time T0 to time T1, all pixels are simultaneously exposed and image data (frame) IG1 is generated. During the period from time T1 to time T2, the solid-state imaging element 200 reads differential data of IG1 and the previous frame and outputs the differential data to the host 100.

[0180] During the period from time T2 to time T3, the host 100 determines whether there is motion based on the differential data. At this time, it is assumed that there is no motion. The host 100 provides the determination result to the solid-state imaging element 200. During the period from time T3 to time T4, the solid-state imaging element 200 outputs NULL data to the host 100.

[0181] Then, during the exposure period from time T4 to time T5, all pixels are simultaneously exposed and IG2 of the next frame is generated. During the period from time 5 to time T6, the solid-state imaging element 200 reads the differential data between IG1 and IG2 and outputs the differential data to the host 100.

[0182] During the period from time T6 to time T7, the host 100 determines whether there is motion. At this time, it is assumed that it is determined that there is motion. The host 100 provides the determination result to the solid-state imaging element 200. The solid-state imaging element 200 outputs the current frame IG2 to the host 100 during the period after time T7.

[0183] Note that, in the case of motion, the solid-state imaging element 200 outputs a frame, but the present invention is not limited to this configuration. For example, the host 100 may provide information indicating a predetermined rectangular area (i.e., ROI area) containing a subject in motion to the solid-state imaging element 200, and the solid-state imaging element 200 may cut out the ROI area from the frame and output the ROI area to the host 100. Therefore, the amount of communication can be further reduced.

[0184] As shown in the figure, the host 100 determines whether there is motion, so that the processing amount of the solid-state imaging element 200 can be reduced.

[0185] Note that the first modification example and the second modification example of the first embodiment can be applied to the fourth modification example of the first embodiment.

[0186] As described above, according to the fourth modification example of the present technology, since the host 100 determines whether there is motion, the processing amount of the solid-state imaging element 200 can be reduced.

[0187] [Fifth Modification] In the first embodiment described above, the number of sample-hold circuits sharing the rear-stage circuit 590 is four, but the number is not limited to four. The solid-state imaging element 200 according to the fifth modification of the first embodiment is different from the first embodiment in that the number of sample-hold circuits sharing the rear-stage circuit 590 is two.

[0188] Fig.28 1 is a circuit diagram showing a configuration example of a pixel block 500 according to a fifth modification of the first embodiment of the present technology. The pixel block 500 of the fifth modification of the first embodiment is different from the first embodiment in that the previous stage circuits 530 and 540 and the sample-hold circuits 570 and 580 are reduced.

[0189] In the case where the number of sample-and-hold circuits is reduced to two, differential data is output not for every frame but for every two frames.

[0190] Note that the first, second, third, and fourth modifications of the first embodiment can be applied to the fifth modification of the first embodiment.

[0191] As described above, according to the fifth modification example of the first embodiment of the present technology, the number of sample-and-hold circuits that share the subsequent-stage circuit 590 is reduced to two.

[0192] <2. Second Embodiment> In the above-mentioned first embodiment, the solid-state imaging element 200 generates a composite signal of a reset level and a signal level twice for each row, but in this configuration, when generating differential data, AD conversion is required twice for each row. The solid-state imaging element 200 according to the second embodiment is different from the first embodiment in that, when generating differential data, it is not necessary to perform AD conversion on the composite signal to reduce power consumption.

[0193] Fig.29 is a block diagram showing a configuration example of an imaging system according to a second embodiment of the present technology. In the second embodiment, the pixel array section 220 is not divided into a plurality of pixel blocks 500. In addition, the column signal processing circuit 260 of the second embodiment detects whether a moving body is present, and when a moving body is detected, outputs cropped data obtained by cropping a region of the moving body in a frame to the host 100. In addition, in the second embodiment, circuits and elements in the solid-state imaging element 200 are provided on a single semiconductor chip.

[0194] Fig.30 is a circuit diagram showing a configuration example of a pixel 300 according to a second embodiment of the present technology. The pixel 300 of the second embodiment includes a front-stage circuit 310, a sample-and-hold circuit 320, and a rear-stage circuit 340. In the second embodiment, the rear-stage circuit 340 is not shared by a plurality of pixels, and the rear-stage circuit 340 is arranged for each pixel.

[0195] The previous-stage circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , an FD reset transistor 313 , an FD 314 , a previous-stage amplifier transistor 315 , and a current source transistor 316 .

[0196] The connection configuration of the photoelectric conversion element 311 , the transfer transistor 312 , the FD reset transistor 313 , the FD 314 , and the pre-stage amplifier transistor 315 is similar to that of the first embodiment. The current source transistor 316 supplies the current id1 under the control of the vertical scanning circuit 211 .

[0197] The sample-and-hold circuit 320 includes capacitance elements 321 and 322 and selection transistors 331 and 332. The connection configuration of these elements is similar to that of the first embodiment.

[0198] The subsequent-stage circuit 340 includes a subsequent-stage reset transistor 341, a subsequent-stage amplifying transistor 351, and a subsequent-stage selecting transistor 352. The connection configuration of these elements is similar to that of the first embodiment.

[0199] Fig.31 : is a block diagram showing a configuration example of a load MOS circuit block 250 and a column signal processing circuit 260 according to the second embodiment of the present technology.

[0200] In the first embodiment, the vertical signal line 309 is wired for each column of the pixel block 500. On the other hand, in the second embodiment, the vertical signal line 309 is wired for each column of pixels, and the load MOS transistor 251 is provided for each column of pixels.

[0201] Furthermore, the column signal processing circuit 260 of the second embodiment includes a plurality of column circuits 700, an area determination section 750, a flag holding section 760, and a digital signal processing section 262. The column circuits 700 are arranged for each column of pixels.

[0202] Fig.32 7 is a block diagram showing a configuration example of a column circuit 700 according to a second embodiment of the present technology. The column circuit 700 includes a selector 710 , an ADC 741 , a differential circuit 720 , a comparison section 730 , and a data conversion section 742 .

[0203] The selector 710 switches the output destination of the signal from the pixel 300 to the ADC 741 or the differential circuit 720 according to the detection signal DET from the control circuit 212 .

[0204] Here, the detection signal DET is a signal indicating whether a moving body is detected. For example, in the case where a moving body is detected, the detection signal is set to a logic value "1", and in the case where a moving body is not detected, the detection signal is set to a logic value "0". In an initial state, the detection signal DET is set to "0". In the case where the detection signal DET is "0", the selector 710 outputs a signal to the differential circuit 720, and in the case where the detection signal DET is "1", the selector 710 outputs a signal to the ADC 741.

[0205] In addition, the control circuit 212 sets the detection signal DET based on the area flag flg_area held in the flag holding unit 760 .

[0206] Here, the area flag flg_area is a flag generated for each pixel and indicates whether the pixel is located in the area of ​​the moving body. The area flag of the nth row and the mth column is flg_area[n][m]. n is an integer from 0 to N-1, and m is an integer from 0 to M-1. For example, when the corresponding pixel is a pixel located in the area of ​​the moving body, the area flag flg_area is set to a logical value "1", otherwise, the area flag flg_area is set to a logical value "0". In the initial state, the area flag flg_area of ​​all pixels is set to "0".

[0207] When the area flag flg_area of ​​all pixels is "0", that is, when no moving object is detected, the control circuit 212 controls the pixel 300 through the vertical scanning circuit 211 to generate and maintain the signal level at each exposure. Since two capacitor elements (321 and 322) are set for each pixel, the pixel 300 can maintain the signal level of each frame in two consecutive frames. In addition, the pixel 300 sequentially outputs two signal levels after the exposure is completed, and the control circuit 212 sets the detection signal DET to "0". According to the detection signal, the selector 710 outputs the signal level to the differential circuit 720.

[0208] In addition, when the area flag flg_area of ​​any pixel is "1", that is, when a moving body is detected, the control circuit 212 sets a cropping area including an area where the area flag flg_area is "1". The vertical scanning circuit 211 controls the rows in the cropping area and causes the pixels 300 in the row to regenerate the reset level. As described above, since two signal levels can be maintained for each pixel, the older one of the signal levels is discarded and updated to the reset level. In addition, the control circuit 212 sets the detection signal DET to "1". Based on the detection signal, the selector 710 outputs the reset level and the signal level to the ADC 741. In addition, the control circuit 212 sets the ADC 741 of each column in the read area to be valid and invalidates the other columns. Therefore, only the digital signal in the cropping area is read.

[0209] The ADC 741 sequentially converts the reset level and the signal level into digital signals using the ramp signal Rmp, and supplies the converted digital signals to the digital signal processing unit 262 .

[0210] The difference circuit 720 obtains a difference ΔD between two consecutive signal levels and provides the difference ΔD to the comparison section 730 .

[0211] The comparison section 730 compares the absolute value of the difference ΔD with a predetermined threshold value α, and supplies the comparison result and the difference ΔD to the data conversion section 742 .

[0212] The data conversion section 742 converts the comparison result and the difference ΔD into 2-bit output data chg_sign. It is assumed that one of the two bits is chg_sign0 and the other is chg_sign1.

[0213] The area determination unit 750 determines whether each pixel is located in the area of ​​the moving object based on the output data chg_sign of each column, and generates an area flag flg_area. The area determination unit 750 causes the flag holding unit 760 to hold the generated area flag flg_area. The flag holding unit 760 uses, for example, a static random access memory (SRAM).

[0214] Fig.33 is a circuit diagram showing a configuration example of a selector 710 , a differential circuit 720 , and a comparison section 730 according to the second embodiment of the present technology.

[0215] The selector 710 includes switches 711 and 712. The switch 711 opens or closes the path between the pixel 300 and the ADC 741 according to the detection signal DET. The switch 712 opens or closes the path between the pixel 300 and the differential circuit 720 according to the detection signal DET.

[0216] When the detection signal DET is "0" (i.e., when no moving object is detected), the switch 711 is opened and the switch 712 is closed. On the other hand, when the detection signal DET is "1" (i.e., when a moving object is detected), the switch 711 is closed and the switch 712 is opened.

[0217] The differential circuit 720 includes capacitor elements 721 and 722, an operational amplifier 723, and an auto-zero switch 724. The capacitor element 721 is inserted between the input terminal of the operational amplifier 723 and the input terminal of the differential circuit 720. The output terminal of the operational amplifier 723 is connected to the output terminal of the differential circuit 720. The capacitor element 722 is inserted between the input terminal of the differential circuit 720 and the output terminal of the operational amplifier 723. The auto-zero switch 724 opens and closes the path between the input terminal of the differential circuit 720 and the output terminal of the operational amplifier 723 according to the auto-zero signal AZ from the control circuit 212.

[0218] The comparison section 730 includes an absolute value circuit 731 and a comparator 732 . The absolute value circuit 731 obtains the absolute value of the difference ΔD from the difference circuit 720 , and outputs the absolute value to the comparator 732 .

[0219] The comparator 732 compares the absolute value of ΔD with α. The comparator 732 outputs the comparison result COMP to the data conversion section 742. In addition, the difference ΔD is also input to the data conversion section 742.

[0220] Fig.34 is a diagram showing an operation example of the data conversion section 742 according to the second embodiment of the present technology. The comparison result COMP and the difference ΔD are input to the data conversion section 742. The comparison result COMP represents the comparison result between the absolute value of the difference ΔD and α. The difference ΔD represents the difference between the corresponding signal levels of two consecutive frames.

[0221] Assume that the signal level of a certain frame fm0 is Dfm0, and the signal level of the next frame fm1 is Dfm1. The pixel 300 sequentially outputs Dfm0 and Dfm1, and the differential circuit 720 outputs their changes as ΔD.

[0222] For example, when Dfm1 is less than or equal to Dfm0, the differential circuit 720 outputs a differential ΔD having a negative sign. On the other hand, when Dfm1 is greater than Dfm0, the differential circuit 720 outputs a differential ΔD having a positive sign.

[0223] In addition, the comparison section 730 outputs a low level comparison result COMP when the difference absolute value (|Dfm0 − Dfm1|) is less than or equal to α, and outputs a high level comparison result COMP when the difference absolute value (|Dfm0 − Dfm1|) is not less than or equal to α.

[0224] When the comparison result COMP is at a low level, the data conversion section 742 outputs chg_sign0 equal to “0” and chg_sign1 equal to “0” regardless of the sign of the difference ΔD. These output data indicate that the corresponding pixel is within a constant region with small variations.

[0225] In addition, when the comparison result COMP is at a high level and the sign of ΔD is negative, the data conversion section 742 outputs chg_sign0 equal to “0” and chg_sign1 equal to “1.” These output data indicate that the corresponding pixel is within the disappearance region where the signal disappears.

[0226] Furthermore, when the comparison result COMP is at a high level and the sign of ΔD is positive, the data conversion section 742 outputs chg_sign0 equal to “1” and chg_sign1 equal to “0.” These output data indicate that the corresponding pixel is within the occurrence region where the signal occurs.

[0227] Fig.35 750 includes line buffers 751 and 752 , an output control section 753 , rise detection sections 754 and 755 , an XOR (logical exclusive OR) gate 756 , and an OR (logical OR) gate 757 .

[0228] The row buffer 751 holds output data chg_sign0 for each column. Assume that chg_sign0 in the m-th column is chg_sign0[m]. M bits from the 0th column to the (M−1)th column are held in the row buffer 751 .

[0229] The row buffer 752 holds output data chg_sign1 for each column. Assume that chg_sign1 in the m-th column is chg_sign1[m]. M bits from the 0th column to the (M−1)th column are held in the row buffer 752 .

[0230] The output control section 753 controls the line buffers 751 and 752 to sequentially output chg_sign0[m] and chg_sign1[m] from the 0th column to the (M−1)th column. chg_sign0[m] is output to the XOR gate 756 and the rising detection section 754 , and chg_sign1[m] is output to the XOR gate 756 and the rising detection section 755 .

[0231] The rising detection unit 754 detects the rising of chg_sign0[m]. When chg_sign0[m] rises from a low level to a high level, the rising detection unit 754 generates a pulse chg_sign0_pls[m] and supplies it to the OR gate 757.

[0232] The rising detection unit 755 detects the rising of chg_sign1[m]. When chg_sign1[m] rises from a low level to a high level, the rising detection unit 754 generates a pulse chg_sign1_pls[m] and supplies it to the OR gate 757.

[0233] The XOR gate 756 outputs the exclusive OR of chg_sign0[m] and chg_sign1[m] to the OR gate 757 as XOR_out[m].

[0234] The OR gate 757 outputs the logical OR of chg_sign0_pls[m], chg_sign1_pls[m], and XOR_out[m] to the flag holding unit 760 as the area flag flg_area[n][m].

[0235] Fig.36 is a timing chart showing an operation example of the area determination section 750 according to the second embodiment of the present technology. The row buffers 751 and 752 sequentially output chg_sign0[m] and chg_sign1[m] from the 0th column to the (M-1)th column of the nth row.

[0236] Assume that chg_sign0[m] rises in column a, and chg_sign1[m] rises in column b. The rising detection unit 754 generates only one pulse chg_sign0_pls[m] in column a. The rising detection unit 755 generates only one pulse chg_sign1_pls[m] in column b. The XOR gate 756 outputs a high level XOR_out[m] during the period from column a to column b-1. The OR gate 757 outputs a high level area flag flg_area[n][m] during the period from column a to column b. For the (n+1)th column and subsequent columns, the area flag flg_area[n][m] corresponding to the M columns in the row is generated by similar control.

[0237] like Figure 31 to Figure 36 As shown, in the second embodiment, since the differential circuit 720 obtains the difference between the signal levels, it is not necessary to perform two AD conversions when generating differential data as in the first embodiment. Therefore, power consumption can be reduced.

[0238] Furthermore, since a reset level is generated when a moving body is detected and is read together with the signal level, high-quality cropping data can be generated like the first embodiment.

[0239] Note that the difference between the next frame and the held frame can also be obtained by a method for holding a frame after AD conversion in a frame memory. However, in this method, AD conversion needs to be performed for each pixel and a frame memory needs to be set, which increases power consumption and cost.

[0240] Fig.37 1 is a timing chart showing a first global shutter control example of the solid-state imaging element 200 according to the second embodiment of the present technology. It is assumed that the first exposure is performed during the period from the time T1 to the time T2.

[0241] From time T10 immediately before exposure starts to time T1 when exposure starts, the vertical scanning circuit 211 supplies a high-level FD reset signal RST and a high-level transfer signal TX to all rows. Therefore, all pixels are PD reset, and all rows start exposure simultaneously.

[0242] Then, at time T11 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal RST in the pulse period, and sets the subsequent-stage reset signal RB to the high level in all pixels. Therefore, all pixels are reset by FD.

[0243] At the moment T2 when the exposure ends, the vertical scanning circuit 211 provides a high-level transmission signal TX to all pixels during the pulse period. Therefore, a signal level is generated. In addition, during the period from the moment T2 to the moment T12, the vertical scanning circuit 211 provides a high-level selection signal S1 to all pixels. Therefore, the signal level of the first frame is sampled and maintained in all pixels.

[0244] Fig.38 2 is a timing chart showing a second global shutter control example of the solid-state imaging element 200 according to the second embodiment of the present technology. It is assumed that the second exposure is performed during the period from the time T3 to the time T4.

[0245] From time T20 immediately before exposure starts to time T3 when exposure starts, the vertical scanning circuit 211 supplies a high-level FD reset signal RST and a high-level transfer signal TX to all rows. Therefore, all pixels are PD reset, and all rows start exposure simultaneously.

[0246] Then, at time T21 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal RST in the pulse period, and sets the subsequent-stage reset signal RB to the high level in all pixels. Therefore, all pixels are reset by FD.

[0247] At the moment T4 when the exposure ends, the vertical scanning circuit 211 provides a high-level transmission signal TX to all pixels in the pulse period. Therefore, a signal level is generated. In addition, during the period from the moment T4 to the moment T22, the vertical scanning circuit 211 provides a high-level selection signal S2 to all pixels. Therefore, the signal level of the second frame is sampled and maintained in all pixels.

[0248] Similarly, in the following exposure, Fig.37 and 38 As shown, the selection signals S1 and S2 are alternately supplied, and the signal level of each of two consecutive frames is maintained for each pixel.

[0249] Fig.39 2 is a timing chart showing an operation example of the solid-state imaging element 200 at the time of area determination according to the second embodiment of the present technology. During the period from time T4 to time T5 when the second exposure ends, the vertical scanning circuit 211 sequentially selects rows and sequentially outputs the pixel signal of the first frame and the pixel signal of the second frame. It is assumed that the nth row is selected during the period from time T41 to time T46.

[0250] During the period from time T41 to time T46, the vertical scanning circuit 211 provides a high-level subsequent selection signal SEL to the n-th row. During the period from time T42 to time T43 in this period, the vertical scanning circuit 211 provides a high-level selection signal S1 to the n-th row. Therefore, the signal level of the first frame is output. Subsequently, during the period from time T44 to time T45, the vertical scanning circuit 211 provides a high-level selection signal S2 to the n-th row. Therefore, the signal level of the second frame is output.

[0251] In addition, the control circuit 212 sets the detection signal DET to a low level. Therefore, the selector 710 supplies the signal levels of each of the first frame and the second frame to the differential circuit 720. In addition, the area determination unit 750 determines whether each pixel is located in the area of ​​the moving object based on chg_sign obtained from the differential ΔD output from the differential circuit 720.

[0252] Fig.40 2 is a timing chart showing an example of a read operation of the solid-state imaging element 200 according to the second embodiment of the present technology. Assume that during the period from time T4 to time T5, the area determination section 750 updates any area flag flg_area to "1".

[0253] The control circuit 212 sets a cropping area including an area with area flag flg_area of ​​"1" and controls the vertical scanning circuit 211 and the column signal processing circuit 260 to perform reading in this area. After setting the cropping area, the control circuit 212 initializes the area flag flg_area of ​​all pixels to "0".

[0254] During the reading period from time T5 to time T6, the vertical scanning circuit 211 sequentially selects rows in the cropping area and outputs the reset level and signal level of the second frame. For example, it is assumed that the area after the 10th row (R10) is set as the cropping area. It is assumed that the nth row (Rn) in the cropping area is selected during the period from time T51 to time T57.

[0255] During the period from time T51 to time T57, the vertical scanning circuit 211 provides a high-level post-stage selection signal SEL to the n-th row. During the pulse period starting from time T52 during this period, the vertical scanning circuit 211 provides a high-level FD reset signal RST to the n-th row. Therefore, the n-th row is reset by FD, and the reset level of the second frame is generated. In addition, during the period from time T52 to time T53, the vertical scanning circuit 211 provides a high-level selection signal S1 to the n-th row. Therefore, the signal level of the first frame is updated to the reset level of the second frame, and the reset level is output.

[0256] The control circuit 212 sets the detection signal DET to a low level. Therefore, a reset level is provided to the ADC 741. The ADC 741 of each column in the cropping area AD-converts the output reset level.

[0257] Then, the vertical scanning circuit 211 provides a high-level rear-stage reset signal RB to the n-th row in the pulse period starting from the time T54. Subsequently, a high-level selection signal S2 is provided to the n-th row in the period from the time T55 to the time T56. Therefore, the signal level of the second frame is output, and AD conversion is performed by the ADC 741 of each column in the cropping area. By performing CDS processing on the reset level and signal level of the second frame, cropping data is generated. The cropping data is output to the host 100.

[0258] Furthermore, when the reading of the last row of the cropped data is completed, the control circuit 212 returns the detection signal DET to the low level.

[0259] Then, during the exposure period from time T6 to time T7, the third exposure is performed. At the end of the exposure, the reset level of the second frame is updated to the signal level of the third frame by the selection signal S1.

[0260] Subsequently, since the detection signal DET is at a low level, the signal levels of the second frame and the third frame are output to the differential circuit 720 during the period from time T7 to time T8. The area determination unit 750 determines whether each pixel is located within the area of ​​the moving body based on the difference. Here, it is assumed that the area flag flg_area of ​​all pixels remains "0". In this case, the reset level and the signal level in the cropped area are not read, and the next exposure starts after time T9.

[0261] Fig.41 : is a diagram showing an example of the state of the pixel 300 and the selector 710 at the time of area determination and reading according to the second embodiment of the present technology. In a and b of the figure, the area flag flg_area of ​​all pixels is "0" (in other words, no moving body is detected), and the state when the area determination unit 750 operates after the exposure of two frames is completed is shown. In the figure, c and d represent the state when any area flag flg_area is updated to "1" and the pixel signal in the cropped area is read. In the figure, the selection transistors 331 and 332 are represented by switch graphic symbols.

[0262] As shown in a of the figure, the vertical scanning circuit 211 closes the selection transistor 331 and outputs the signal level Dfm0 of the first frame. When no moving object is detected, the control circuit 212 controls the selector 710 to provide the signal level Dfm0 to the differential circuit 720.

[0263] Next, as shown in b of the figure, the vertical scanning circuit 211 closes the selection transistor 332 and outputs the signal level Dfm1 of the second frame. The control circuit 212 controls the selector 710 to provide the signal level Dfm1 to the differential circuit 720. Then, the differential circuit 720 obtains the difference ΔD between the signal levels Dfm0 and Dfm1.

[0264] Then, assuming that the area determination unit 750 updates one of the area flags flg_area to “1” (in other words, a moving object is detected), the vertical scanning circuit 211 initializes the FD of the pixels 300 in the cropped area and causes the capacitive element 321 to hold the reset level Pfm1 of the second frame.

[0265] As shown in c of the figure, the vertical scanning circuit 211 closes the selection transistor 331 of the pixel 300 in the cropped area and outputs the reset level Pfm1. Since a moving body is detected, the control circuit 212 controls the selector 710 to provide the ADC 741 with the reset level Pfm0.

[0266] Next, as shown in d of the figure, the vertical scanning circuit 211 turns on the selection transistor 332 of the pixel 300 in the cropped area and outputs the signal level Dfm1. The control circuit 212 controls the selector 710 to provide the signal level Dfm0 to the ADC 741.

[0267] The reset level and the signal level in the trimmed area are AD-converted by the ADC 741, and trimmed data is generated.

[0268] Fig.42 1 is a diagram showing examples of image data, differential data, and cropped data according to the second embodiment of the present technology. FIG. a is an example of image data (frame) 810 generated by the first exposure. FIG. b is an example of image data (frame) 820 generated by the second exposure.

[0269] Image data 810 includes a subject 811, and image data 820 includes a subject 821. The dotted line in image data 820 indicates the outline of subject 811. Subjects 811 and 821 are the same moving body and have different positions in each frame. In addition, each pixel holds the signal level of each of image data 810 and 820. Differential circuit 720 obtains the difference between these signal levels.

[0270] FIG. c shows difference data 830 in which differences in signal levels of respective pixels are arranged. The dot-dash lines indicate rows within the regions of the objects 811 and 821.

[0271] D of the figure shows an enlarged view of the single-point dashed line of c of the figure. A part of the subject 811 is lost in the next image data 820 due to movement, and this area corresponds to the disappearance area. In addition, a part of each of the subjects 811 and 821 overlaps, and this area corresponds to the unchanged area. A part of the subject 821 does not appear in the previous image data 810, and this area corresponds to the appearance area. The area determination unit 750 sets the area flag flg_area from the end of the disappearance area to the end of the appearance area to "1".

[0272] Then, the control circuit 212 sets a cropping area including an area whose area flag flg_area is “1.” Furthermore, under the control of the control circuit 212 , the vertical scanning circuit 211 and the ADC 741 convert the reset level and the signal level in the area into digital signals and generate cropping data.

[0273] e of the figure shows an example of the clipping data 835. The clipping data 835 includes the subject 821 which is a moving object. In addition, the thick dotted line indicates the area where the area flag flg_area is "1".

[0274] As shown in the figure, when a moving object is detected, the solid-state imaging element 200 can cut out and output the area containing the moving object. This function of the solid-state imaging element 200 can be used for crime prevention and monitoring.

[0275] Fig.43 2 is a flowchart showing an operation example of the solid-state imaging element 200 according to the second embodiment of the present technology. For example, when a predetermined application for detecting a moving body is executed, the operation is started.

[0276] The solid-state imaging element 200 exposes all pixels by the global shutter method and holds the signal level of each pixel (step S911). Next, the solid-state imaging element 200 exposes all pixels by the global shutter method again and holds the signal level of each pixel (step S912). Then, the solid-state imaging element 200 determines whether it is located in the area of ​​the moving object based on the difference between the signal levels for each pixel (step S913).

[0277] As a result of the determination, the solid-state imaging element determines whether the area flag of any pixel has been updated to “1” (step S914 ).

[0278] If the region flag of any pixel is "1" (step S914: Yes), the solid-state imaging element 200 cuts out a cut region including the region of the moving object (step S915). The region flag is initialized after cutting. In the case where the region flags of all pixels are "0" (step S914: No), or after step S915, the solid-state imaging element 200 repeats step S912 and subsequent steps.

[0279] As described above, according to the second embodiment of the present technology, since the differential circuit 720 obtains the difference between the signal levels of two frames, AD conversion is not required when generating differential data, so that power consumption can be reduced.

[0280] [First Modification] In the second embodiment described above, the solid-state imaging element 200 sets the cropping area, but with this configuration, it is difficult to change the cropping area from the outside. The imaging system of the first modification of the second embodiment is different from the first embodiment in that the host 100 sets the cropping area.

[0281] Fig.44 1 is a block diagram showing a configuration example of an imaging system according to a first modification of the second embodiment of the present technology. In the first modification of the second embodiment, the host 100 includes a cropping region setting section 115 , a synthesis section 116 , a background data holding section 117 , and a recording section 113 .

[0282] In addition, the column signal processing circuit 260 of the second embodiment supplies the area flag flg_area to the cropping area setting section 115 .

[0283] The cropping area setting unit 115 sets a predetermined area including an area whose area flag flg_area is “1” as a cropping area. The cropping area setting unit 115 supplies cropping area information indicating the set cropping area to the control circuit 212 .

[0284] The control circuit 212 of the first modification of the second embodiment controls the vertical scanning circuit 211 and the column signal processing circuit 260 based on the cropping region information to generate cropping data. The column signal processing circuit 260 of the first modification of the second embodiment supplies the cropping data to the synthesis section 116 .

[0285] The synthesis unit 116 synthesizes the cropping data and the background data. The synthesis unit 116 records the synthesized data in the recording unit 113. The background data storage unit 117 stores the background data.

[0286] As shown in the figure, when the host 100 sets the cropping area, it becomes easy to change the cropping area on the host 100 side, and the convenience and versatility of the imaging system are improved.

[0287] As described above, according to the first modification example of the second embodiment of the present technology, since the host 100 sets the trimming area, convenience and versatility can be improved.

[0288] [Second Modification] In the second embodiment described above, the solid-state imaging element 200 cuts out the cropping area based on the area flag flg_area, but the analog gain can also be controlled based on the area flag flg_area. The solid-state imaging element 200 according to the second modification of the second embodiment is different from the second embodiment in that the analog gain is controlled based on the area flag flg_area.

[0289] Fig.45 1 is a diagram showing examples of image data and differential data according to a second modification of the second embodiment of the present technology. FIG. a is an example of image data (frame) 810 generated by a first exposure. FIG. b is an example of image data (frame) 820 generated by a second exposure. FIG. c shows differential data 830 in which differences in signal levels in respective pixels are arranged.

[0290] The vertical scanning circuit 211 of the second modified example of the second embodiment generates a reset level for all pixels, and outputs the reset level and signal level for all pixels when a moving body is detected. In addition, the control circuit 212 sets the analog gain of the pixel signal (reset level and signal level) in the area where the area flag flg_area is "1" to be higher than the analog gain in other areas. For example, the control circuit 212 controls the DAC 213 to relax the slope of the ramp signal when performing AD conversion of the pixel signal in the area where the area flag flg_area is "1". The gentler the slope of the ramp signal, the greater the analog gain of the pixel signal.

[0291] For example, as shown in the figure, image data 825 identical to image data 820 is read. The region of subject 826 where region flag flg_area is "1" becomes brighter than the surrounding area due to the increase in analog gain. By changing the analog gain of the moving object region, the image quality of image data 825 including the moving object can be improved.

[0292] As described above, according to the second modification example of the second embodiment of the present technology, since the analog gain of the moving body area is changed, the image quality of the image data can be improved.

[0293] [Third Modification] In the above-described second embodiment, the pixel 300 regenerates the reset level when a moving object is detected after the exposure ends. Fig.38 As shown, a reset level corresponding to the signal level is generated at a time T21 just before the end of exposure (which is different from the time after the end of exposure). Due to this time shift, the image quality of the cropped data may be degraded. The solid-state imaging element 200 according to the third modification of the second embodiment is different from the second embodiment in that the reset level and the signal level of each of the two frames are maintained for each pixel.

[0294] Fig.46 : is a circuit diagram showing a configuration example of a pixel 300 according to a third modification example of the second embodiment of the present technology. The pixel 300 of the third modification example of the second embodiment is different from that of the second embodiment in that four capacitance elements and four selection transistors are arranged.

[0295] The sample-and-hold circuit 320 includes capacitive elements 325 , 326 , 327 , and 328 and selection transistors 335 , 336 , 337 , and 338 .

[0296] One end of each of the capacitive elements 325 , 326 , 327 , and 328 is commonly connected to the previous stage circuit 310 .

[0297] In accordance with the selection signal S1p from the vertical scanning circuit 211, the selection transistor 335 opens and closes the path between the other end of the capacitor element 325 and the subsequent circuit 340. In accordance with the selection signal S1d from the vertical scanning circuit 211, the selection transistor 336 opens and closes the path between the other end of the capacitor element 326 and the subsequent circuit 340. In accordance with the selection signal S2p from the vertical scanning circuit 211, the selection transistor 337 opens and closes the path between the other end of the capacitor element 327 and the subsequent circuit 340. In accordance with the selection signal S2d from the vertical scanning circuit 211, the selection transistor 338 opens and closes the path between the other end of the capacitor element 328 and the subsequent circuit 340.

[0298] Fig.47 1 is a timing chart showing a first global shutter control example of the solid-state imaging element 200 according to the third modification example of the second embodiment of the present technology. Differences from the second embodiment will be described.

[0299] During the period from time T11 to time T12 immediately before the end of exposure, the vertical scanning circuit 211 supplies the high-level selection signal S1p to all pixels. Therefore, the reset level of the first frame is sampled and held in all pixels.

[0300] Fig.48 3 is a timing chart showing a second global shutter control example of the solid-state imaging element 200 according to the third modification example of the second embodiment of the present technology. Differences from the second embodiment will be described.

[0301] During the period from time T21 to time T22 immediately before the end of exposure, the vertical scanning circuit 211 supplies the high-level selection signal S2p to all pixels. Therefore, the reset level of the second frame is sampled and held in all pixels.

[0302] Fig.49 : is a timing chart showing an operation example of the solid-state imaging element 200 at the time of area determination according to the third modification example of the second embodiment of the present technology.

[0303] During the period from time T42 to time T43, the vertical scanning circuit 211 provides a high-level selection signal S1d to the n-th row. Therefore, the signal level of the first frame is output. Then, during the period from time T44 to time T45, the vertical scanning circuit 211 provides a high-level selection signal S2d to the n-th row. Therefore, the signal level of the second frame is output.

[0304] Fig.50 : is a timing chart showing an example of a reading operation of the solid-state imaging element 200 according to the third modification example of the second embodiment of the present technology.

[0305] During the period from time T52 to time T53, the vertical scanning circuit 211 supplies the high-level selection signal S2p to the n-th row. Therefore, the reset level of the second frame is output. Note that the FD reset signal RST remains at a low level and the reset level is not regenerated.

[0306] Furthermore, during the period from the time T55 to the time T56, the vertical scanning circuit 211 supplies the high-level selection signal S2d to the n-th row. Thus, the signal level of the second frame is output.

[0307] Note that, in the case where a moving object is detected after exposure of the next frame fm2, the reset level and the signal level of the frame are read by selecting the signals S1p and S1d.

[0308] like Figures 46 to 50 As shown, since the pixel 300 maintains the reset level and the signal level in each of the two frames, it is not necessary to regenerate the reset level at the time of reading. Therefore, it is possible to suppress image quality degradation caused by a time shift in generating the reset level.

[0309] Note that each of the first modification example and the second modification example of the second embodiment can be applied to the third modification example of the second embodiment.

[0310] As described above, according to the third modification example of the second embodiment of the present technology, since the pixel 300 maintains the reset level and the signal level in each of two frames, degradation in image quality can be suppressed.

[0311] [Fourth Modification] In the above-described second embodiment, the circuit in the solid-state imaging element 200 is provided in a single semiconductor chip, but this configuration may prevent the element from being fitted in a semiconductor chip when the pixel 300 is miniaturized. The solid-state imaging element 200 of the fourth modification of the first embodiment is different from that of the second embodiment in that the circuit in the solid-state imaging element 200 is dispersedly arranged in two semiconductor chips.

[0312] Fig.51 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to a fourth modification of the second embodiment of the present technology. The solid-state imaging element 200 of the fourth modification of the second embodiment includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, connection can also be achieved using a through-hole interconnect or a bump.

[0313] The pixel chip 201 is provided with an upper pixel array section 221. The circuit chip 202 is provided with a lower pixel array section 222 and a column signal processing circuit 260. For each pixel in the pixel array section 220, a part of the pixel is arranged in the upper pixel array section 221, and the rest of the pixel is arranged in the lower pixel array section 222.

[0314] Furthermore, the circuit chip 202 is also provided with a vertical scanning circuit 211, a control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are not shown in the figure.

[0315] Furthermore, the pixel chip 201 is manufactured, for example, using a pixel-specific process, and the circuit chip 202 is manufactured, for example, using a complementary MOS (CMOS) process.

[0316] Fig.52 is a circuit diagram showing a configuration example of a pixel 300 according to a fourth modification of the second embodiment of the present technology. In the pixel 300, the pre-stage circuit 310 is arranged in the pixel chip 201, and other circuits and elements (such as capacitor elements 321 to 322) are arranged in the circuit chip 202. Note that the current source transistor 316 may be further arranged in the circuit chip 202. As shown in the figure, by dispersing the elements belonging to the pixel 300 in the pixel chip 201 and the circuit chip 202 stacked on each other, the pixel area can be reduced, which is conducive to pixel miniaturization.

[0317] As described above, according to the fourth modification of the second embodiment of the present technology, the circuits and elements belonging to the pixel 300 are dispersedly arranged in two semiconductor chips to facilitate pixel miniaturization.

[0318] [Fifth Modification] In the fourth modification of the second embodiment described above, a part of the pixel 300 and the peripheral circuits (e.g., the column signal processing circuit 260) are arranged in the circuit chip 202 on the lower side. However, in the case of such a configuration, the arrangement area of ​​the circuits and elements on the circuit chip 202 side is larger than the arrangement area on the pixel chip 201 due to the peripheral circuits, and there is a possibility that an unnecessary space without circuits and elements is generated in the pixel chip 201. The solid-state imaging element 200 of the fifth modification of the second embodiment is different from the fourth modification of the second embodiment in that the circuits belonging to the solid-state imaging element 200 are dispersedly arranged in three semiconductor chips.

[0319] Fig.532 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to a fifth modification of the second embodiment of the present technology. The solid-state imaging element 200 of the fifth modification of the second embodiment includes an upper pixel chip 203, a lower pixel chip 204, and a circuit chip 202. These chips are stacked together and electrically connected by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, connection can also be achieved using a through-hole interconnect or a bump.

[0320] The upper pixel chip 203 is provided with an upper pixel array section 221. The lower pixel chip 204 is provided with a lower pixel array section 222. For each pixel in the pixel array section 220, a part of the pixel is arranged in the upper pixel array section 221, and the rest is arranged in the lower pixel array section 222.

[0321] Furthermore, the circuit chip 202 is provided with a column signal processing circuit 260, a vertical scanning circuit 211, a control circuit 212, a DAC 213, and a load MOS circuit block 250. Circuits other than the column signal processing circuit 260 are not shown in the figure.

[0322] This three-layer structure as shown in the figure can reduce unnecessary space and can further achieve pixel miniaturization compared to a two-layer structure. In addition, the lower pixel chip 204 of the second layer can be manufactured by a dedicated process for capacitors and switches. Note that the first embodiment and each variant can have a three-layer structure.

[0323] As described above, in the fifth modification of the second embodiment of the present technology, since the circuits belonging to the solid-state imaging element 200 are dispersedly arranged in three semiconductor chips, the pixels can be further miniaturized compared to the case where the circuits are dispersedly arranged in two semiconductor chips.

[0324] <3. Third embodiment> In the third modification of the second embodiment described above, the reset level is sampled and held during the exposure period, but in this configuration, the exposure period cannot become shorter than the sampling and holding period of the reset level. The solid-state imaging element 200 of the third embodiment is different from the third modification of the second embodiment in that the exposure period is further shortened by adding a transistor that releases charge from the photoelectric conversion element.

[0325] Fig.54 3 is a circuit diagram showing a configuration example of a pixel 300 according to a third embodiment of the present technology. The pixel 300 of the third embodiment is different from the third modification of the second embodiment in that a discharge transistor 317 is further provided in the previous stage circuit 310 .

[0326] The discharge transistor 317 functions as an overflow drain that discharges electric charge from the photoelectric conversion element 311 in accordance with a discharge signal ofg from the vertical scanning circuit 211. As the discharge transistor 317, for example, an nMOS transistor is used.

[0327] When the charge is transferred from the photoelectric conversion element 311 to the FD 314 for all pixels, the configuration without the discharge transistor 317 as in the third modification of the second embodiment may suffer from halo. Then, when the FD is reset, the potential of the FD 314 and the previous stage node drops. The previous stage node is the output node of the previous stage circuit 310. In response to the potential drop, the charging and discharging currents of the capacitor elements 321 and 322 continue to occur, and the IR drop in the power supply or ground starts to change from a stable state without halo.

[0328] On the other hand, when the signal levels of all pixels are sampled and held, the photoelectric conversion element 311 has no charge after the signal charge is transferred, so blooming does not occur, and the IR drop in the power supply or ground enters a stable state without blooming. Since there is a difference between the IR drop when the reset level is sampled and held and the IR drop when the signal level is sampled and held, streaking noise occurs.

[0329] On the other hand, in the second embodiment provided with the discharge transistor 317, the charge in the photoelectric conversion element 311 is discharged to the overflow drain. Therefore, the IR drop becomes almost the same when sampling and holding the reset level and the signal level, so that the stripe noise can be suppressed.

[0330] Fig.55 is a timing diagram showing an example of global shutter operation according to the third embodiment of the present technology. At time T0 before exposure starts, the vertical scanning circuit 211 provides a high-level FD reset signal RST to all pixels during the pulse period, and at the same time sets the discharge signal ofg to a high level for all pixels. Therefore, PD reset and FD reset are performed on all pixels. In addition, the reset level is sampled and held. Among them, ofg_[n] in the figure represents a signal sent to a pixel in the nth row among N rows.

[0331] Then, at time T1 when exposure starts, the vertical scanning circuit 211 returns the discharge signal ofg to a low level for all pixels. Then, during the period from time T2 just before the end of exposure to time T3 when exposure ends, the vertical scanning circuit 211 provides a high-level transfer signal TX to all pixels. Thus, the signal level is sampled and held.

[0332] The configuration without the discharge transistor 317 as in the third modification of the second embodiment requires turning on the transfer transistor 312 and the FD reset transistor 313 at the start of exposure (i.e., at the time of PD reset). With this control, when the PD is reset, the FD 314 also needs to be reset at the same time. Therefore, it is necessary to perform FD reset again during the exposure period to sample and hold the reset level so that the exposure period cannot be shorter than the sampling and holding period of the reset level. When sampling and holding the reset levels of all pixels, a certain waiting time is required until the voltage and current stabilize, and, for example, a sampling and holding period of several microseconds (μs) to tens of microseconds (μs) is required.

[0333] On the other hand, in the third embodiment provided with the discharge transistor 317, the PD reset and the FD reset can be performed separately. Therefore, as shown in the example in the figure, by performing the FD reset before canceling the PD reset (starting exposure), the reset level can be sampled and held. Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0334] In addition, the third embodiment is also applicable to the first embodiment and its modified examples.

[0335] As described above, according to the third embodiment of the present technology, since the discharge transistor 317 that discharges the charge from the photoelectric conversion element 311 is provided, the reset level can be sampled and held by performing FD reset before the exposure starts. Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0336] <4. Fourth embodiment> In the above-described second embodiment, the FD 314 is initialized with the power supply voltage VDD, but this configuration may cause degradation of photo response non-uniformity (PRNU) due to differences in the capacitance elements 321 and 322 or parasitic capacitance. The solid-state imaging element 200 of this fourth embodiment is different from the second embodiment in that PRNU is improved by reducing the power supply of the FD reset transistor 313 during reading.

[0337] Fig.56 3 is a circuit diagram showing a configuration example of a pixel 300 according to a fourth embodiment of the present technology. The pixel 300 of the third embodiment is different from the second embodiment in that the power supply of the FD reset transistor 313 is separated from the power supply voltage VDD of the pixel 300 .

[0338] The drain of the FD reset transistor 313 of the fourth embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by the control circuit 212, for example.

[0339] Here, the degradation of PRNU in the pixel 300 of the second embodiment will be considered. In the second embodiment, at time T0 immediately before the exposure start time, the potential of the FD 314 drops due to the reset feedthrough of the FD reset transistor 313. It is assumed that the amount of this fluctuation is represented as Vft.

[0340] In the second embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 changes from VDD to VDD - Vft at time T0. In addition, the potential of the previous stage node during exposure is VDD - Vft - Vgs.

[0341] In addition, in the second embodiment, the FD reset transistor 313 is shifted to the on state at the time of reading, and the FD 314 is fixed to the power supply voltage VDD. The potentials of the previous stage node and the subsequent stage node are shifted higher by about Vft due to the fluctuation amount Vft of the FD 314 at the time of reading. The subsequent stage node is an input node of the subsequent stage circuit 340. However, due to the difference in the capacitance value or parasitic capacitance of the capacitance elements 321 and 322, the shift voltage amount varies for each pixel, which causes degradation of PRNU.

[0342] In particular, in order to reduce the kTC noise during the sampling and holding of the input conversion capacitance, it is necessary to improve the charge-to-voltage conversion efficiency of FD 314. In order to improve the charge-to-voltage conversion efficiency, it is necessary to reduce the capacitance of FD 314, but the smaller the capacitance of FD 314, the greater the fluctuation of Vft, which may reach several hundred millivolts (mV). In this case, the influence of PRNU may be at a non-negligible level.

[0343] Fig.57 : is a timing chart showing a voltage control example according to the fourth embodiment of the present technology.

[0344] The control circuit 212 performs control so that the reset power supply voltage VRST becomes different between during the row-by-row reading period after the timing T9 and during the exposure period.

[0345] For example, during the exposure period, the control circuit 212 makes the reset power supply voltage VRST the same as the power supply voltage VDD. On the other hand, during the reading period, the control circuit 212 reduces the reset power supply voltage VRST to VDD-Vft. That is, during the reading period, the control circuit 212 reduces the reset power supply voltage VRST by an amount that substantially matches the Vft fluctuation amount caused by reset feedthrough. By this control, the reset level of the FD 314 can be made the same during the exposure period and during the reading period.

[0346] By controlling the reset power supply voltage VRST, as shown in the figure, the voltage fluctuation amount between the FD 314 and the previous stage node can be reduced, thereby suppressing the difference between the capacitor elements 321 and 322 caused by the parasitic capacitance and the degradation of PRNU.

[0347] In addition, the fourth embodiment can also be applied to the first embodiment and its modified examples. In addition, the second embodiment and the modified examples of the third embodiment can also be applied to the fourth embodiment.

[0348] As described above, according to the fourth embodiment of the present technology, the control circuit 212 reduces the reset power supply voltage VRST by the amount of the fluctuation Vft caused by the reset feedthrough at the time of reading, so that the reset level can be equalized between exposure and reading. Therefore, it is possible to prevent the degradation of the photoresponse non-uniformity (PRNU).

[0349] <5. Fifth embodiment> In the above-mentioned second embodiment, the vertical scanning circuit 211 controls to expose all rows (all pixels) at the same time (i.e., global shutter operation). However, in the case where simultaneous exposure is not required during testing or analysis and low noise is required, rolling shutter operation is desirable. The solid-state imaging element 200 of the sixth embodiment is different from the second embodiment in that the rolling shutter operation is performed at the time of testing, etc.

[0350] Fig.58 1 is a timing chart showing an example of rolling shutter operation according to the fifth embodiment of the present technology. The vertical scanning circuit 211 performs control to sequentially select a plurality of rows and start exposure. This figure shows exposure control of the n-th row.

[0351] During the period from time T0 to time T2, the vertical scanning circuit 211 provides a high-level rear-stage selection signal SEL, a selection signal S1, and a selection signal S2 to the n-th row. In addition, at time T0 when exposure starts, the vertical scanning circuit 211 provides a high-level FD reset signal RST and a rear-stage reset signal RB to the n-th row within the pulse period. At time T1 when exposure ends, the vertical scanning circuit 211 provides a transmission signal TX to the n-th row. The rolling shutter operation in the figure allows the solid-state imaging element 200 to generate low-noise image data.

[0352] Note that during normal imaging, the solid-state imaging element 200 according to the fifth embodiment performs a global shutter operation similarly to the second embodiment.

[0353] Furthermore, the sixth embodiment can be applied to each of the first embodiment and its modified examples.

[0354] In addition, the modification of the second embodiment and the third and fourth embodiments can also be applied to the fifth embodiment.

[0355] As described above, according to the fifth embodiment of the present technology, the vertical scanning circuit 211 performs control (ie, rolling shutter operation) to sequentially select a plurality of rows and start exposure, and thus low-noise image data can be generated.

[0356] <6. Sixth embodiment> In the above-mentioned second embodiment, the source of the front-stage source follower (the front-stage amplifier transistor 315 and the current source transistor 316) is connected to the power supply voltage VDD, and the line-by-line reading is performed with the source follower in the on state. However, this driving method has the possibility that the circuit noise of the front-stage source follower during the line-by-line reading is propagated to the subsequent stage, and the random noise is increased accordingly. The solid-state imaging element 200 of the sixth embodiment is different from the second embodiment in that the noise is reduced by turning off the source follower of the front stage when reading.

[0357] Fig.59 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a sixth embodiment of the present technology. The solid-state imaging element 200 of the sixth embodiment is different from that of the second embodiment in that a regulator 420 and a switching section 440 are further included. In addition, in the pixel array section 220 of the sixth embodiment, a plurality of effective pixels 301 and a predetermined number of dummy pixels 430 are arranged. The dummy pixels 430 are arranged around the arrangement area of ​​the effective pixels 301.

[0358] In addition, a power supply voltage VDD is supplied to each dummy pixel 430, and a power supply voltage VDD and a source voltage Vs are supplied to each effective pixel 301. The figure omits a signal line for supplying the power supply voltage VDD to the effective pixel 301. In addition, the power supply voltage VDD is supplied from a pad 410 located outside the solid-state imaging element 200.

[0359] The regulator 420 generates a constant generated voltage Vgen based on the input voltage Vi from the dummy pixel 430, and supplies the generated voltage Vgen to the switching section 440. The switching section 440 selects the power supply voltage VDD received from the pad 410 or the generated voltage Vgen received from the regulator 420, and supplies the selected voltage as the source voltage Vs to the effective pixel 301 of each column.

[0360] Fig.60 1 is a circuit diagram showing a configuration example of a dummy pixel 430, a regulator 420, and a switch 440 according to a sixth embodiment of the present technology. FIG. a is a circuit diagram of the dummy pixel 430 and the regulator 420, and FIG. b is a circuit diagram of the switch 440.

[0361] As shown in a of the figure, the dummy pixel 430 includes a reset transistor 431, an FD 432, an amplifier transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the FD reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifier transistor 433 amplifies the voltage level of the FD 432 and provides the amplified voltage as the input voltage Vi to the regulator 420.

[0362] In addition, the source of each of the reset transistor 431 and the amplifier transistor 433 is connected to the power supply voltage VDD. The current source transistor 434 is connected to the drain of the amplifier transistor 433. The current source transistor 434 supplies the current id1 under the control of the vertical scanning circuit 211.

[0363] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitive element 423. The low-pass filter 421 allows a component of a low frequency band lower than a predetermined frequency in a signal of an input voltage Vi to pass as an output voltage Vj.

[0364] The output voltage Vj is input to the non-inverting input terminal (+) of the buffer amplifier 422 . The inverting input terminal (−) of the buffer amplifier 422 is connected to its output terminal. The capacitor 423 holds the voltage of the output terminal of the buffer amplifier 422 at Vgen. This Vgen is provided to the switch unit 440 .

[0365] As shown in b of the figure, the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442. The switching circuits 442 are arranged for corresponding columns of the effective pixels 301, respectively.

[0366] The inverter 441 inverts the switching signal SW from the control circuit 212 . The inverter 441 supplies the inverted signal to each switching circuit 442 .

[0367] The switching circuit 442 selects the power supply voltage VDD or the generated voltage Vgen, respectively, and supplies the selected voltage as the source voltage Vs to the corresponding column in the pixel array section 220. The switching circuit 442 includes switches 443 and 444. The switch 443 opens and closes the path between the node of the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes the path between the node of the generated voltage Vgen and the corresponding column according to the inverted signal of the switching signal SW.

[0368] Fig.61is a timing diagram showing an operation example of the dummy pixel 430 and the regulator 420 according to the sixth embodiment of the present technology. At time T10 immediately before reading of a certain row, the vertical scanning circuit 211 provides an FD reset signal RST (here, the power supply voltage VDD) to each dummy pixel 430. The potential Vfd of the FD 432 in each dummy pixel 430 is initialized to the power supply voltage VDD. Then, when the FD reset signal RST becomes a low level, the FD reset signal RST fluctuates to VDD - Vft due to reset feedthrough.

[0369] In addition, the input voltage Vi drops to VDD - Vgs - Vsig after reset. Due to passing through the low-pass filter 421, Vj and Vgen are almost constant.

[0370] After the time T20 immediately before reading of the next row is performed, similar control is performed for each row, and a constant generated voltage Vgen is supplied.

[0371] Fig.62 : is a circuit diagram showing a configuration example of an effective pixel 301 according to a sixth embodiment of the present technology. The circuit configuration of the effective pixel 301 is similar to that of the pixel 300 of the second embodiment, but differs in that the source voltage Vs from the switching section 440 is supplied to the source of the pre-stage amplifier transistor 315.

[0372] In the sixth embodiment, when exposure is performed simultaneously in all pixels, the switching section 440 selects the power supply voltage VDD and provides the power supply voltage VDD as the source voltage Vs. In addition, the voltage of the previous node is reduced from VDD - Vgs - Vth to VDD - Vgs - Vsig at time T4. Here, Vth represents the threshold voltage of the transfer transistor 312.

[0373] In addition, in the sixth embodiment, at the time of reading, the switching section 440 selects the generated voltage Vgen and provides the generated voltage Vgen as the source voltage Vs. The generated voltage Vgen is adjusted to VDD - Vgs - Vft. In addition, in the seventh embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop providing the current id1.

[0374] As described above, according to the sixth embodiment of the present technology, since the source follower of the preceding stage is turned off at the time of reading, noise generated in the source follower can be reduced.

[0375] <7. Application examples on mobile objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot.

[0376] Fig.63 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0377] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.63 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0378] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force, etc.

[0379] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device as a key substitute may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, or the lights of the vehicle.

[0380] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0381] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0382] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0383] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), such as collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0384] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0385] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control intended for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0386] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.63 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0387] Fig.64 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0388] exist Fig.64 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0389] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at locations such as the front nose, rearview mirror, rear bumper, rear door and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 disposed at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0390] Notice, Fig.64 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0391] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0392] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the travel path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0393] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0394] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

[0395] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, for example, Figure 1 The solid-state imaging element 200 in can be applied to the imaging section 12031. By applying the disclosed technology to the imaging section 12031, a captured image that is easier to view can be obtained, thereby reducing driver fatigue.

[0396] Note that the above-described embodiments illustrate examples for implementing the present technology, and the matters in the embodiments have a corresponding relationship with the matters for specifying the invention in the claims. Similarly, the matters for specifying the invention in the claims have a corresponding relationship with the matters of the same name in the embodiments of the present technology, respectively. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the scope of the present technology.

[0397] Note that the effects described in this specification are merely examples and are not restrictive, and other effects can also be achieved.

[0398] Note that the present technology may also have the following configurations. (1) A solid-state imaging element comprising: a pixel signal generating unit which sequentially generates a first pixel signal and a second pixel signal; A first sample-and-hold circuit, which holds the first pixel signal; a second sample-and-hold circuit, which holds the second pixel signal; and A vertical scanning circuit controls the first sample-and-hold circuit and the second sample-and-hold circuit to generate a composite signal of the first pixel signal and the second pixel signal. (2) The solid-state imaging element according to (1) above, wherein: The first pixel signal includes a first reset level and a first signal level, The second pixel signal includes a second reset level and a second signal level, and The vertical scanning circuit generates each of a signal obtained by adding the first reset level and the second signal level and a signal obtained by adding the first signal level and the second reset level as the synthetic signal. (3) The solid-state imaging device according to (1) or (2) above, further comprising: a third sample-and-hold circuit, which holds the second pixel signal; and A fourth sample-and-hold circuit holds the second pixel signal. (4) The solid-state imaging element according to (3) above, wherein: The pixel signal generating section further generates a third pixel signal, and The vertical scanning circuit performs: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and causing one of the third sampling and holding circuit and the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the third sampling and holding circuit and the fourth sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and causing one of the first sampling and holding circuit and the second sampling and holding circuit to output the third pixel signal. (5) The solid-state imaging element according to (3) above, wherein: The pixel signal generating section further generates a third pixel signal, and The vertical scanning circuit performs: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and for causing the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the second sampling and holding circuit and the third sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and for causing the fourth sampling and holding circuit to output the third pixel signal. (6) The solid-state imaging element according to any one of (1) to (5) above, wherein: The pixel signal generating unit includes a first front stage circuit and a second front stage circuit. The first front stage circuit comprises: a first transfer transistor that transfers charges from the first photoelectric conversion element to the first floating diffusion layer, and a first connection transistor connecting the first floating diffusion layer and a predetermined node, and The second front stage circuit comprises: a second transfer transistor that transfers charges from the second photoelectric conversion element to the second floating diffusion layer, and The second connection transistor connects the second floating diffusion layer and a predetermined node. (7) The solid-state imaging element according to any one of (1) to (5) above, wherein: The pixel signal generating section includes a front-stage circuit, and The preceding stage circuit includes a transfer transistor that transfers charges from a photoelectric conversion element to a floating diffusion layer. (8) The solid-state imaging element according to any one of (1) to (7) above, further comprising: a motion determination unit that determines whether the subject is moving based on the synthesized signal; and An interface outputs the second pixel signal when the motion occurs. (9) The solid-state imaging element according to any one of (1) to (7) above, further comprising: The column signal processing circuit outputs the second pixel signal when receiving a determination result indicating that the subject is moving from the outside. (10) A method for controlling a solid-state imaging element, the method comprising: A pixel signal generating process for sequentially generating a first pixel signal and a second pixel signal; A first sampling and holding process of holding the first pixel signal by a first sampling and holding circuit; a second sampling and holding process of holding the second pixel signal by a second sampling and holding circuit; and A vertical scanning process of controlling the first sample-and-hold circuit and the second sample-and-hold circuit to generate a composite signal of the first pixel signal and the second pixel signal. (11) A solid-state imaging element comprising: a predetermined number of pixels that sequentially maintain and sequentially output a first signal level and a second signal level according to an exposure amount, generate a reset level, and sequentially output the second signal level and the reset level; a differential circuit that obtains a difference between the first signal level and the second signal level; a comparing unit, which compares the absolute value of the difference with a predetermined threshold value and outputs a comparison result; an area determination unit that determines whether each of the pixels is located in an area of ​​a moving object based on the difference and the comparison result; and An analog-to-digital converter sequentially converts the second signal level and the reset level into digital signals. (12) The solid-state imaging device according to (11) above, further comprising: an analog-to-digital converter that converts each of the reset level and the second signal level into a digital signal; a vertical scanning circuit that drives a predetermined number of the pixels; and A control circuit controls the vertical scanning circuit and the analog-to-digital converter to generate the digital signal in a cropped area including the area of ​​the moving object when any of the pixels is determined to be located in the area of ​​the moving object. (13) The solid-state imaging element according to (12) above, wherein The control circuit receives cropping area information indicating the cropping area from the outside. (14) The solid-state imaging device according to (11) above, further comprising: A control circuit changes an analog gain of the region of the moving object when any of the pixels is determined to be located in the region of the moving object. (15) The solid-state imaging element according to any one of (11) to (14) above, The reset level includes a first reset level and a second reset level, The pixel maintains the first reset level, the first signal level, the second reset level and the second signal level, and sequentially outputs the first signal level and the second signal level, and when any of the pixels is determined to be located within the area of ​​the moving object, the pixel sequentially outputs the second reset level and the second signal level. (16) A method for controlling a solid-state imaging element, the method comprising: A process of causing a predetermined number of pixels to sequentially maintain and sequentially output a first signal level and a second signal level according to an exposure amount, generate a reset level, and sequentially output the second signal level and the reset level; a differential process of obtaining a difference between the first signal level and the second signal level; A comparison process of comparing the absolute value of the difference with a predetermined threshold value and outputting a comparison result; An area determination process of determining whether each of the pixels is located within an area of ​​a moving body based on the difference and the comparison result; and The analog-to-digital conversion process sequentially converts the second signal level and the reset level into digital signals. Reference numerals list

[0399] 100 hosts 111, 264 Motion determination unit 112 Image Processing Department 113 Records Department 115 Cropping area setting unit 116 Combination Department 117 Background data storage unit 200 Solid-state imaging element 201 pixel chip 202 Circuit Chip 203 pixel chip 204 lower pixel chip 211 vertical scanning circuit 212 Control Circuit 213 DAC 220 Pixel Array Section 221 upper pixel array portion 222 lower pixel array portion 250 Load MOS circuit block 251 Load MOS transistor 260 columns of signal processing circuits 261, 741 ADC 262 Digital Signal Processing Department 263, 710 selectors 265 Communication Interface 300 pixels 301 effective pixels 310, 510, 520, 530, 540 preamplifier circuit 311, 511, 521, 531, 541 Photoelectric conversion element 312, 512, 522, 532, 542 pass transistors 313, 513, 523, 533, 543 FD reset transistor 314, 432, 514, 524, 534, 544 FD 315, 515, 525, 535, 545 preamplifier transistors 316, 434 Current source transistor 317 Discharge transistor 320, 550, 560, 570 and 580 Sample and Hold Circuits 321, 322, 325 to 328, 423, 551, 552, 561, 562, 571, 572, 581, 582, 721, 722 Capacitor elements 331, 332, 335 to 338, 553, 554, 563, 564, 573, 574, 583, 584 selection transistor 340, 590 post-stage circuit 341, 591 Rear stage reset transistor 351, 592 post-amplifier transistor 352, 593 Post-stage selection transistor 420 Regulator 421 Low-pass filter 422 Buffer Amplifier 430 dummy pixels 431 Reset transistor 433 Amplifier Transistor 440 Switching Department 441 Inverter 442 Switching Circuit 443, 444, 711, 712 switches 500 pixel blocks 501 pixel signal generating unit 502 Sample and hold block 516, 526, 536, 546 Pre-charge transistor 517, 527, 537, 547 Connecting transistors 700 circuits 720 Differential Circuit 723 Operational Amplifier 724 Auto-zero switch 730 Comparative Department 731 Absolute Value Circuit 732 Comparator 742 Data Conversion Department 750 Area Judgment Department 751, 752 Line Buffer 753 Output Control Unit 754, 755 Rising detection unit 756 XOR (Logical Exclusive OR) Gate 757 OR (Logical OR) Gate 760 Logo Maintenance Department 12031 Imaging Department

Claims

1. A solid-state imaging element, comprising: a pixel signal generating unit which sequentially generates a first pixel signal and a second pixel signal; A first sample-and-hold circuit, which holds the first pixel signal; a second sample-and-hold circuit, which holds the second pixel signal; and A vertical scanning circuit controls the first sample-and-hold circuit and the second sample-and-hold circuit to generate a composite signal of the first pixel signal and the second pixel signal.

2. The solid-state imaging element according to claim 1, wherein The first pixel signal includes a first reset level and a first signal level, The second pixel signal includes a second reset level and a second signal level, and The vertical scanning circuit generates each of a signal obtained by adding the first reset level and the second signal level and a signal obtained by adding the first signal level and the second reset level as the synthetic signal.

3. The solid-state imaging element according to claim 1, further comprising: a third sample-and-hold circuit, which holds the second pixel signal; as well as A fourth sample-and-hold circuit holds the second pixel signal.

4. The solid-state imaging element according to claim 3, wherein The pixel signal generating section further generates a third pixel signal, and The vertical scanning circuit performs: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and causing one of the third sampling and holding circuit and the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the third sampling and holding circuit and the fourth sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and causing one of the first sampling and holding circuit and the second sampling and holding circuit to output the third pixel signal.

5. The solid-state imaging element according to claim 3, wherein The pixel signal generating section further generates a third pixel signal, and The vertical scanning circuit performs: control for causing the first sampling and holding circuit and the second sampling and holding circuit to generate a composite signal of the first pixel signal and the second pixel signal, and for causing the fourth sampling and holding circuit to output the second pixel signal; control for causing the first sampling and holding circuit, the second sampling and holding circuit, and the fourth sampling and holding circuit to hold the third pixel signal; and control for causing the second sampling and holding circuit and the third sampling and holding circuit to generate a composite signal of the second pixel signal and the third pixel signal, and for causing the fourth sampling and holding circuit to output the third pixel signal.

6. The solid-state imaging element according to claim 1, wherein The pixel signal generating unit includes a first front stage circuit and a second front stage circuit. The first front stage circuit comprises: a first transfer transistor that transfers charges from the first photoelectric conversion element to the first floating diffusion layer, and a first connection transistor connecting the first floating diffusion layer and a predetermined node, and The second front stage circuit comprises: a second transfer transistor that transfers charges from the second photoelectric conversion element to the second floating diffusion layer, and The second connection transistor connects the second floating diffusion layer and a predetermined node.

7. The solid-state imaging element according to claim 1, wherein The pixel signal generating section includes a front-stage circuit, and The preceding stage circuit includes a transfer transistor that transfers charges from a photoelectric conversion element to a floating diffusion layer.

8. The solid-state imaging element according to claim 1, further comprising: a motion determination unit configured to determine whether the subject is moving based on the synthesized signal; as well as An interface outputs the second pixel signal when the motion occurs.

9. The solid-state imaging element according to claim 1, further comprising: The column signal processing circuit outputs the second pixel signal when receiving a determination result indicating that the subject is moving from the outside.

10. A method for controlling a solid-state imaging element, the method comprising: A pixel signal generating process for sequentially generating a first pixel signal and a second pixel signal; A first sampling and holding process of holding the first pixel signal by a first sampling and holding circuit; a second sampling and holding process of holding the second pixel signal by a second sampling and holding circuit; as well as A vertical scanning process of controlling the first sample-and-hold circuit and the second sample-and-hold circuit to generate a composite signal of the first pixel signal and the second pixel signal.

11. A solid-state imaging element, comprising: a predetermined number of pixels that sequentially maintain and sequentially output a first signal level and a second signal level according to an exposure amount, generate a reset level, and sequentially output the second signal level and the reset level; a differential circuit that obtains a difference between the first signal level and the second signal level; a comparing unit, which compares the absolute value of the difference with a predetermined threshold value and outputs a comparison result; an area determination unit that determines whether each of the pixels is located in an area of ​​a moving object based on the difference and the comparison result; as well as An analog-to-digital converter sequentially converts the second signal level and the reset level into digital signals.

12. The solid-state imaging element according to claim 11, further comprising: an analog-to-digital converter that converts each of the reset level and the second signal level into a digital signal; a vertical scanning circuit that drives a predetermined number of said pixels; as well as A control circuit controls the vertical scanning circuit and the analog-to-digital converter to generate the digital signal in a cropped area including the area of ​​the moving object when any of the pixels is determined to be located in the area of ​​the moving object.

13. The solid-state imaging element according to claim 12, wherein The control circuit receives cropping area information indicating the cropping area from the outside.

14. The solid-state imaging element according to claim 11, further comprising: A control circuit changes an analog gain of the region of the moving object when any of the pixels is determined to be located in the region of the moving object.

15. The solid-state imaging element according to claim 11, wherein The reset level includes a first reset level and a second reset level, The pixel maintains the first reset level, the first signal level, the second reset level and the second signal level, and sequentially outputs the first signal level and the second signal level, and when any of the pixels is determined to be located within the area of ​​the moving object, the pixel sequentially outputs the second reset level and the second signal level.

16. A method for controlling a solid-state imaging element, the method comprising: A process of causing a predetermined number of pixels to sequentially maintain and sequentially output a first signal level and a second signal level according to an exposure amount, generate a reset level, and sequentially output the second signal level and the reset level; a differential process of obtaining a difference between the first signal level and the second signal level; A comparison process of comparing the absolute value of the difference with a predetermined threshold value and outputting a comparison result; An area determination process of determining whether each of the pixels is located within an area of ​​a moving body based on the difference and the comparison result; as well as The analog-to-digital conversion process sequentially converts the second signal level and the reset level into digital signals.

Images