Barrier layer package for organic light emitting diodes

Abstract

Sub-pixel circuits and methods of forming sub-pixel circuits useful for displays such as organic light emitting diode (OLED) displays are provided. In one example, a sub-pixel includes a substrate, an adjacent overhang structure, an anode, an OLED material, a cathode, a package stack. The package stack includes a first layer, a second layer disposed over the first layer, and a third layer. The first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each of the overhanging structures, and a third portion disposed below an underside surface of an extension of each of the overhanging structures. A gap is defined by contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed over the second layer outside the gap.

Description

Technical Field

[0001] Embodiments described herein generally relate to displays. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that can be used in displays such as organic light emitting diode (OLED) displays. Background Art

[0002] Input devices including display devices can be used in various electronic systems. An organic light emitting diode (OLED) is a light emitting diode (LED) in which the emitting electroluminescent layer is a film of organic compounds that emits light in response to an electric current. An OLED device is classified as a bottom emitting device if the emitted light passes through a transparent or translucent bottom electrode and substrate on which the panel is manufactured. An OLED device is classified as a top emitting device if the emitted light passes through a cover that is added after the device is manufactured. Currently, OLEDs are used to create display devices in many electronic devices. Display devices are expected to be reduced in size while providing higher resolution.

[0003] OLED pixel patterning is based on processes that limit panel size, pixel resolution, and substrate size. It is desirable to use photolithography to pattern pixels rather than using fine metal masks. Currently, OLED pixel patterning requires stripping of organic materials after the patterning process. When stripping organic materials, the organic materials may leave particles that can damage OLED performance. Therefore, what is needed in the art is a sub-pixel circuit and a method of forming a sub-pixel circuit that can be used for a display such as an organic OLED display. Summary of the invention

[0004] In an embodiment, a sub-pixel is provided. The sub-pixel includes a substrate, an adjacent overhang structure, an anode, an organic light emitting diode (OLED) material, a cathode disposed above the OLED material, and an encapsulation layer stack. The adjacent overhang structure defines the sub-pixel. The OLED material is disposed above the anode. The cathode is disposed above the OLED material. The encapsulation layer stack has a first layer, a second layer disposed above the first layer, and a third layer. The first layer and the second layer have a first portion disposed above the cathode, a second portion disposed above the sidewall of each overhang structure, and a third portion disposed below the lower side surface of the extension of each overhang structure. The gap is defined by the contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed above the second layer outside the gap.

[0005] In another embodiment, a device is provided. The device includes a substrate, adjacent overhang structures, an anode, an organic light emitting diode (OLED) material, a cathode, and an encapsulation layer stack. The OLED material is disposed above the anode. The cathode is disposed above the OLED material. The encapsulation layer stack has a first layer, a second layer disposed above the first layer, and a third layer. The first layer and the second layer have a first portion disposed above the cathode, a second portion disposed above the sidewall of each overhang structure, and a third portion disposed below the lower side surface of the extension of each overhang structure. The gap is defined by the contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed above the second layer outside the gap.

[0006] In an embodiment, a method of forming a sub-pixel circuit is provided. The method includes: depositing a first layer of a first material over a first organic light emitting diode (OLED) material of the sub-pixel circuit; depositing a second layer of a second material over the first layer; depositing a resist material over the sub-pixel circuit; patterning and removing a portion of the resist material; removing a first portion of the first layer and a first portion of the second layer exposed by the resist material in a well of a sub-pixel of the sub-pixel circuit; depositing a second OLED material in the well; depositing a third layer of the first material over the second OLED material in the well; depositing a fourth layer of the second material over the third layer; and depositing a fifth layer of the third material over a second portion of the first layer and over a second portion of the second layer. The first layer and the third layer of the first material may be deposited using a plasma enhanced chemical vapor deposition (PECVD) process. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope thereof, and other equivalent embodiments may be recognized.

[0008] Figure 1A is a schematic cross-sectional view of a sub-pixel circuit according to an embodiment.

[0009] Figure 1B is a schematic top cross-sectional view of a sub-pixel circuit having a dot-type architecture according to an embodiment.

[0010] Figure 1C is a schematic cross-sectional view of a sub-pixel circuit having a linear architecture according to an embodiment.

[0011] Figure 2A is a schematic cross-sectional view of an overhang structure of a sub-pixel circuit according to an embodiment.

[0012] Figure 2B is a schematic cross-sectional view of an overhang structure of a sub-pixel circuit with a first layer of an encapsulation layer stack according to an embodiment.

[0013] Figure 2C is a schematic cross-sectional view of an overhang structure of a sub-pixel circuit having a first layer and a second layer of an encapsulation layer stack according to an embodiment.

[0014] Figure 2D is a schematic cross-sectional view of an overhang structure of a sub-pixel circuit having first and second layers of an encapsulation layer stack and a resist material layer according to an embodiment.

[0015] Figure 3 is a schematic cross-sectional view of a sub-pixel circuit 300 according to an embodiment.

[0016] Figure 4A yes Figure 3 A schematic enlarged cross-sectional view of the overhang structure of the sub-pixel circuit shown.

[0017] Figure 4B yes Figure 3 and Figure 4A A schematic enlarged cross-sectional view of the overhang structure of the sub-pixel circuit is shown, but without the second and third layers.

[0018] Figure 4C yes Figure 3 , Figure 4A and Figure 4B Schematic cross-sectional view of the overhang structure of the sub-pixel circuit shown, but without the third layer.

[0019] Figure 4D is a schematic cross-sectional view of an overhang structure of a sub-pixel circuit having first and second layers of an encapsulation layer stack and a resist material layer.

[0020] Figure 5 is a flow chart of a method for forming a sub-pixel circuit according to an embodiment.

[0021] FIG. 6A to FIG. 6I is a schematic cross-sectional view of a substrate during a method of forming a sub-pixel according to an embodiment.

[0022] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0023] Embodiments described herein generally relate to displays. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that can be used in displays such as organic light emitting diode (OLED) displays.

[0024] The subpixel circuit in each of the embodiments described herein includes a plurality of subpixels, wherein each of the subpixels is defined by an adjacent overhang structure that is permanent to the subpixel circuit. Although the accompanying drawings depict two or three subpixels, each of which is defined by an adjacent overhang structure, the subpixel circuit in the embodiments described herein may include a plurality of subpixels, such as three or more subpixels. Each subpixel has an OLED material that is configured to emit white, red, green, blue, or other color light when powered on. For example, the OLED material of the first subpixel emits red light when powered on, the OLED material of the second subpixel emits green light when powered on, and the OLED material of the third subpixel emits blue light when powered on.

[0025] The overhang structure is permanent for the sub-pixel circuit and includes at least a second structure disposed above the first structure. The adjacent overhang structure of each sub-pixel of the sub-pixel circuit of the display is provided to form the sub-pixel circuit using evaporative deposition, and an overhang structure that remains in place after the sub-pixel circuit is formed is provided. Evaporative deposition is used to deposit OLED materials (including hole injection layer (HIL), hole transport layer (HTL), emission layer (EML) and electron transport layer (ETL)) and cathode. In one embodiment, the HIL layer has a greater conductivity than the HTL layer. In another embodiment, the HIL layer has a greater energy level than the HTL layer. In some cases, the layer of the encapsulation layer stack can be set by evaporative deposition. In an embodiment including one or more cover layers, the cover layer is disposed between the cathode and the encapsulation layer stack. The overhang structure and the evaporation angle set by the evaporation source define the deposition angle, that is, the overhang structure provides a shielding effect during evaporative deposition at the evaporation angle set by the evaporation source. In order to deposit at a specific angle, the evaporation source is configured to emit the deposited material at a specific angle relative to the overhang structure. The encapsulation layer stack (which may be formed of one or more layers) of each sub-pixel is disposed above the cathode, wherein the encapsulation layer stack extends under at least a portion of each of the adjacent overhang structures. The encapsulation layer stack of each sub-pixel contacts at least a portion of the sidewall of each of the adjacent overhang structures. Depending on the OLED material deposited on the sub-pixel, the encapsulation layer stack may vary in thickness, composition, and deposition method.

[0026] Figure 1A is a schematic cross-sectional view of a sub-pixel circuit 100 having an arrangement structure 101A. Figure 1A The cross-sectional view is along Figure 1Band Figure 1C The section line 1'-1' is taken.

[0027] The sub-pixel circuit 100 includes a substrate 102. In an embodiment, a metal-containing layer 104 can be patterned on the substrate 102, and the metal-containing layer 104 can be defined by an adjacent pixel definition layer (PDL) structure 126 disposed on the substrate 102. In one embodiment, the metal-containing layer 104 is pre-patterned on the substrate 102. For example, the substrate 102 is a pre-patterned indium tin oxide (ITO) glass substrate. The metal-containing layer 104 is configured to serve as an anode for each sub-pixel. The metal-containing layer 104 includes, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, a combination of the above items, or other suitable conductive materials.

[0028] In an embodiment, the PDL structure 126 may be disposed on the substrate 102. The PDL structure 126 includes an organic material, an organic material having an inorganic coating disposed thereon, or one of an inorganic material. The organic material of the PDL structure 126 includes, but is not limited to, polyimide. The inorganic material of the PDL structure 126 includes, but is not limited to, a silicon oxide (SiO2) material, a silicon nitride (Si3N4) material, a silicon oxynitride (Si2N2O) material, a magnesium fluoride (MgF2) material, or a combination of the above items. Adjacent PDL structures 126 may define wells 128 of each sub-pixel 108 and expose anodes (i.e., metal-containing layers 104) of each sub-pixel 108 of the sub-pixel circuit 100.

[0029] The sub-pixel circuit 100 has a plurality of sub-pixels 106 including at least a first sub-pixel 108a, a second sub-pixel 108b, and a third sub-pixel 108c. Although the drawings depict the first sub-pixel 108a, the second sub-pixel 108b, and the third sub-pixel 108c, the sub-pixel circuit 100 of the embodiments described herein may include three or more sub-pixels 106, such as a fourth sub-pixel and a fifth sub-pixel. Each sub-pixel 106 has an organic light emitting diode (OLED) material 112, which is configured to emit white, red, green, blue, or other color light when powered on. For example, the OLED material 112 of the first sub-pixel 108a emits red light when powered on, the OLED material of the second sub-pixel 108b emits green light when powered on, the OLED material of the third sub-pixel 108c emits blue light when powered on, and the OLED material of the fourth sub-pixel and the fifth sub-pixel emits another color of light when powered on.

[0030] In an embodiment, an overhang structure 110 may be disposed on the upper surface 103 of each of the PDL structures 126. The overhang structure 110 is permanent to the sub-pixel circuit. The overhang structure 110 further defines each sub-pixel 106 of the sub-pixel circuit 100. The overhang structure 110 includes at least a second structure 110B disposed above the first structure 110A. In one embodiment, the second structure 110B is disposed on the first structure 110A. The first structure 110A may be disposed above the upper surface 103 of the PDL structure 126. In one embodiment, the first structure 110A is disposed on the upper surface 103 of the PDL structure 126. Each overhang structure 110 includes adjacent overhang portions 109. Adjacent overhang portions 109 are defined by top extensions 109A of the second structure 110B, which extend laterally through the sidewalls 111 of the first structure 110A.

[0031] The second structure 110B includes one of a non-conductive material, an inorganic material or a metal-containing material. The first structure 110A includes a non-conductive material, an inorganic material or a metal-containing material. The non-conductive material includes, but is not limited to, an inorganic silicon-containing material. For example, the silicon-containing material includes an oxide or nitride of silicon, or a combination of the above items. The metal-containing material includes at least one of a metal or a metal alloy, such as titanium (Ti), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), copper (Cu) or a combination of the above items. The inorganic materials of the first structure 110A and the second structure 110B may include silicon nitride (Si3N4) material, silicon oxide (SiO2) material, silicon oxynitride (Si2N2O) material or a combination of the above items. The overhang structure 110 can be maintained in place, i.e., it is permanent. Therefore, during the formation of the device, the overhang structure is not peeled off, and the overhang structure does not leave organic materials that may damage the performance of the OLED. During the formation of the device, eliminating the need for the peeling procedure also increases the processing volume.

[0032] In one example, the second structure 110B includes a non-conductive inorganic material and the first structure 110A includes a conductive inorganic material or a metal-containing material. In another example, the second structure 110B includes a conductive inorganic material or a metal-containing material and the first structure 110A includes a conductive inorganic material or a metal-containing material.

[0033] The adjacent overhang portion 109 is defined by the top extension 109A of the second structure 110B. At least the bottom surface 107 of the second structure 110B is wider than the top surface 105 of the first structure 110A to form the top extension 109A of the overhang portion 109 (eg, Figure 1A10A). The second structure 110B is disposed above the top surface 105 of the first structure 110A. The top extension 109A of the second structure 110B forms an overhang 109 and allows the second structure 110B to shield the first structure 110A. The shielding of the overhang 109 provides for evaporative deposition of each of the OLED material 112 and the cathode 114. The OLED material 112 is disposed below the overhang 109. The cathode 114 is disposed above the OLED material 112 and extends below the overhang 109. In one embodiment, as Figure 2A As shown, the cathode 114 is in contact with the first portion 220 of the sidewall 111 of the first structure 110A.

[0034] The overhang structure 110 provides a shielding effect during evaporation deposition at an evaporation angle set by the evaporation source.

[0035] In one embodiment, the OLED material 112 and the cathode 114 are in contact with the sidewalls 111 of the first structure 110A of the overhang structure 110. In another embodiment, Figure 1A As shown, the cathode 114 contacts the sidewall 111 of the first structure 110A of the overhang structure 110. In one embodiment, as shown in FIG. Figure 1A As shown, the encapsulation layer stack 116 is disposed above the sidewall 111 of the first structure 110A and the bottom surface 107 of the second structure 110B. In another embodiment, the cathode 114 contacts a bus bar (not shown) outside the active area of ​​the sub-pixel circuit 100. The cathode 114 includes a conductive material, such as a metal or a metal alloy. For example, the material of the cathode 114 includes, but is not limited to, chromium, titanium, aluminum, ITO, or a combination of the above. In some embodiments, the material of the cathode 114 is different from the material of the first structure 110A and the second structure 110B.

[0036] Each sub-pixel 106 includes an encapsulation layer stack 116, which includes a first layer 116A, a second layer 116B, and a third layer 116C. The encapsulation layer stack 116 can be or can correspond to a local passivation layer. The encapsulation layer stack 116 of each sub-pixel is disposed above the cathode 114 (and the OLED material 112), wherein the encapsulation layer stack 116 extends below at least a portion of the overhang structure 110 and above at least a portion of the sidewall of each of the adjacent overhang structures 110.

[0037] In an embodiment, if Figure 1AAs shown in the sub-pixel 108a of FIG. 1 , the first layer 116A, the second layer 116B, and the third layer 116C are disposed over the sidewall 111 of the first structure 110A of the overhang structure 110, the bottom surface 107 of the second structure 110B, the sidewall 113 of the second structure 110B, and a portion of the top surface 115 of the second structure 110B. The first layer 116A and the second layer 116B have a gap 150. Each of the gaps 150 is defined by a first portion 151, a second portion 152, a third portion 153, and a first portion 151 of the second layer 116B in contact with the third portion 153 of the second layer 116B. The first portion 151 of the second layer is disposed over a portion of the first layer 116A, which is disposed over the cathode 114. In some embodiments, the first layer 116A contacts the cathode 114. The second portion 152 of the second layer 116B is disposed over a portion of the first layer 116A, which is disposed over the sidewall 111 of the first structure 110A. In some embodiments, the first layer 116A contacts the sidewall 111 of the first structure 110A. The third portion 153 of the second layer 116B is disposed below a portion of the first layer 116A that is below the lower surface 117 of the top extension 109A of the second structure 110B. In some embodiments, the first layer 116A contacts the lower surface 117 of the top extension 109A of the second structure 110B. The first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B. The gap 150 is sealed by the contact of the first portion 151 and the third portion 153. The first layer 116A has an inner surface 155. The inner surface 155 contacts the cathode 114, the sidewall 111 of the first structure 110A, and the lower surface 117 of the top extension 109A of the second structure 110B. The second layer 116B has an outer surface 156. The outer surface 156 surrounds the void space outside the second layer 116B. The void space corresponds to gap 150. In one or more embodiments, the size of gap 150 and voids is less than the height of overhang 109. In one or more embodiments, the size of gap 150 and voids is less than 1.5 μm, such as less than 0.5 μm.

[0038] In some embodiments, Figure 1AAs shown in the second subpixel 108b of the overhang structure 110, the first layer 116A, the second layer 116B, and the third layer 116C are disposed over the sidewall 111 of the first structure 110A of the overhang structure 110, the bottom surface 107 of the second structure 110B, the sidewall 113 of the second structure 110B, and a portion of the top surface 115 of the second structure 110B. The second layer 116B has a gap 150. Each of the gaps 150 is defined by a first portion 151, a second portion 152, a third portion 153, and a first portion 151 of the second layer 116B in contact with the third portion 153 of the second layer 116B. The first portion 151 of the second layer 116B is disposed over a portion of the first layer 116A, which is disposed over the cathode 114. In some embodiments, the first layer 116A contacts the cathode 114. The second portion 152 of the second layer 116B is disposed over another portion of the first layer 116A, which is disposed over the sidewall 111 of the first structure 110A. In some embodiments, the first layer 116A contacts the sidewall 111 of the first structure 110A. The third portion 153 of the second layer 116B is disposed below another portion of the first layer 116A, which is disposed below the lower surface 117 of the top extension 109A of the second structure 110B. In some embodiments, the first layer 116A contacts the lower surface 117 of the top extension 109A of the second structure 110B. The first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B. The gap 150 is sealed by the contact between the first portion 151 and the third portion 153. The first layer 116A has an inner surface 155. The inner surface 155 contacts the cathode 114, the sidewall 111 of the first structure 110A, and the lower surface 117 of the top extension 109A of the second structure 110B. The second layer 116B has an outer surface 156. The outer surface 156 surrounds the void space outside the second layer 116B. The void space corresponds to gap 150 .

[0039] In some embodiments, a portion of the top surface 115 of the second structure 110B on which the first sub-pixel 108a is disposed is separated from a portion of the top surface 115 of the second structure 110B on which the second sub-pixel 108b is disposed. Figure 1A As shown, there is a space 160 between the encapsulation layer stack 116 of the first sub-pixel 108a and the encapsulation layer stack 116 of the second sub-pixel 108b. In some embodiments, the encapsulation layer stack 116 of the first sub-pixel 108a overlaps the encapsulation layer stack 116 of the second sub-pixel 108b.

[0040] In some embodiments, Figure 1AAs shown in the third sub-pixel 108c of the overhang structure 110, the encapsulation layer stack 116 is disposed over the sidewall 111 of the first structure 110A of the overhang structure 110, the bottom surface 107 of the second structure 110B, the sidewall 113 of the second structure 110B, and a portion of the top surface 115 of the second structure 110B. The first layer 116A and the second layer 116B have a gap 150. Each of the gaps 150 is defined by a first portion 151, a second portion 152, a third portion 153, and a first portion 151 of the second layer 116B in contact with the third portion 153 of the second layer 116B. The first portion 151 of the second layer 116B is disposed over a portion of the first layer 116A, which is disposed over the cathode 114. In some embodiments, the first layer 116A contacts the cathode 114. The second portion 152 of the second layer 116B is disposed over a portion of the first layer 116A, which is disposed over the sidewall 111 of the first structure 110A. In some embodiments, the first layer 116A contacts the sidewall 111 of the first structure 110A. The third portion 153 of the second layer 116B is disposed below a portion of the first layer 116A disposed below the lower surface 117 of the top extension 109A of the second structure 110B. In some embodiments, the first layer 116A contacts the lower surface 117 of the top extension 109A of the second structure 110B. The first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B. The gap 150 is sealed by the contact of the first portion 151 and the third portion 153. The third layer 116C has an inner surface 155 and an outer surface 156. The inner surface 155 contacts the cathode 114, the sidewall 111 of the first structure 110A, and the lower surface 117 of the top extension 109A of the second structure 110B. The outer surface 156 surrounds the void space outside the third layer 116C. The void space corresponds to gap 150 .

[0041] In some embodiments, a portion of the top surface 115 of the second structure 110B on which the encapsulation layer stack 116 of the second sub-pixel 108b is disposed is separated from a portion of the top surface 115 of the second structure 110B on which the encapsulation layer stack 116 of the third sub-pixel 108c is disposed. Therefore, there is a space 160 between the encapsulation layer stack 116 of the second sub-pixel 108b and the encapsulation layer stack 116 of the third sub-pixel 108c. In some embodiments, as Figure 1A As shown, the encapsulation layer stack 116 of the second sub-pixel 108b overlaps the encapsulation layer stack 116 of the third sub-pixel 108c.

[0042] In an embodiment including one or more covering layers, the covering layer is disposed between the cathode 114 and the encapsulation layer stack 116. For example, a first covering layer and a second covering layer are disposed between the cathode 114 and the encapsulation layer stack 116. Each of the embodiments described herein may include one or more covering layers disposed between the cathode 114 and the encapsulation layer stack 116. The first covering layer may include an organic material. The second covering layer may include an inorganic material, such as lithium fluoride. The first covering layer and the second covering layer may be deposited by evaporative deposition. In another embodiment, the sub-pixel circuit 100 further includes at least one overall passivation layer 120 disposed above the overhang structure 110 and the encapsulation layer stack 116. In yet another embodiment, the sub-pixel includes an intermediate layer 118 (e.g., an intermediate passivation layer) disposed above the overhang structure 110 of each of the sub-pixels 106 and disposed between the encapsulation layer stack 116 and the overall passivation layer 120.

[0043] The arrangement structure 101A of the sub-pixel circuit 100 further includes at least one overall passivation layer 120 disposed above the overhang structure 110 and the encapsulation layer stack 116. In one embodiment, an intermediate layer 118 may be disposed between the overall passivation layer 120 and the overhang structure 110 and the encapsulation layer stack 116. The intermediate layer 118 may include an inkjet material, such as an acrylic material.

[0044] Figure 1B is a schematic top cross-sectional view of a sub-pixel circuit 100 having a dot-type architecture 101B. Figure 1C is a schematic top cross-sectional view of a sub-pixel circuit 100 having a linear architecture 101C. Figure 1B and Figure 1C Each of the top cross-sectional views is along Figure 1A The dot-type architecture 101B may include a plurality of pixel openings 124A from adjacent PDL structures 126. Figure 1A As shown, each of the pixel openings 124A is surrounded by an overhang structure 110, which defines each of the sub-pixels 106 of the dot-type architecture 101B. The line-type architecture 101C may include multiple pixel openings 124B from adjacent PDL structures 126. Figure 1A As shown, each of the pixel openings 124B is surrounded by an overhang structure 110 that defines each of the sub-pixels 106 of the linear architecture 101C.

[0045] Figure 2A1 is a schematic cross-sectional view of an overhang structure 110 of a sub-pixel circuit 100 having an encapsulation layer stack 116 including a first layer 116A, a second layer 116B, and a third layer 116C. In one embodiment, the overhang structure 110 includes a second structure 110B of a non-conductive inorganic material and a first structure 110A of a conductive inorganic material. In another embodiment, the overhang structure 110 includes a second structure 110B of a conductive inorganic material and a first structure 110A of a conductive inorganic material. In one embodiment, the cathode 114 is in contact with the first structure 110A of the overhang structure 110. In another embodiment, as Figure 2A As shown, the encapsulation layer stack 116 has gaps 150. Each of the gaps 150 is defined by a first portion 151, a second portion 152, a third portion 153, and a first portion 151 of the second layer 116B in contact with the third portion 153 of the second layer 116B. As shown, the second layer 116B prevents the material of the third layer 116C from entering the gap 150. During the formation of the encapsulation layer stack 116, the gap 150 is retained after the third layer 116C is formed. The first portion 151 of the encapsulation layer stack 116 is disposed above the cathode 114. In some embodiments, the first portion 151 is in contact with the cathode 114. The second portion 152 of the encapsulation layer stack 116 is disposed above the sidewall 111 of the first structure 110A. In some embodiments, the second structure 152 is in contact with the sidewall 111 of the first structure 110A. The third portion 153 of the encapsulation layer stack 116 is disposed below the lower side surface 117 of the top extension 109A of the second structure 110B. In some embodiments, third portion 153 contacts underside surface 117 of top extension 109A of second structure 110B. First portion 151 of package layer stack 116 contacts third portion 153 of package layer stack 116. Gap 150 is sealed by contact between first portion 151 and third portion 153.

[0046] The second structure 110B includes a lower side edge 206 and an overhang vector 208. The lower side edge 206 extends through the sidewall 111 of the first structure 110A. The overhang vector 208 can be defined by the lower side edge 206 and the PDL structure 126. In an embodiment, the OLED material 112 can be disposed over the metal-containing layer 104, over the sidewall 127 of the PDL structure 126, and over the first portion 210 of the upper surface 103 of the PDL structure 126, extending below the overhang 109 to the OLED endpoint 218. The OLED material 112 can form an OLED angle θ between the OLED vector 212 and the overhang vector 208. OLEDThe OLED vector 212 is defined by an OLED endpoint 218 extending below the second structure 110B and a lower edge 206 of the second structure 110B. In one embodiment, the OLED material 112 may include one or more of a HIL, a HTL, an EML, and an ETL.

[0047] In an embodiment, in each sub-pixel 106, the cathode 114 can be disposed over the OLED material 112, over the first portion 210 of the PDL structure 126, and over the second portion 211 of the upper surface 103 of the PDL structure 126. In some embodiments, which may be combined with other embodiments described herein, the cathode 114 is disposed on the first portion 220 of the sidewall 111 of the first structure 110A.

[0048] The encapsulation layer stack 116 is disposed over the cathode 114 (and the OLED material 112), wherein the encapsulation layer stack 116 extends at least below the second structure 110B of the overhang structure 110 and over at least a portion of the sidewalls of the overhang structure 110. Figure 1A As shown in the sub-pixels 108a, 108b and 108c of the first embodiment, the encapsulation layer stack 116 of the sub-pixel 108b and the encapsulation layer stack 116 of the third sub-pixel 108c are disposed above the cathode 114 and extend under the adjacent overhang portion 109 to contact the second portion (not shown) of the sidewall 111 of the first structure 110A. In an embodiment, as Figure 2A As shown, first layer 116A contacts sidewalls 111 of first structure 110A, bottom surface 107 of second structure 110B, sidewalls 113 of second structure 110B, and a portion of top surface 115 of second structure 110B of overhang structure 110. Package layer stack 116 further includes top surface 119 that defines an uppermost edge of package layer stack 116 between sidewalls 111 of first structure 110A.

[0049] In an embodiment, the encapsulation layer stack 116 includes a non-conductive inorganic material, such as a silicon-containing material. The silicon-containing material may include a silicon nitride (e.g., Si3N4) material, a silicon oxynitride (e.g., Si2N2O) material, a silicon oxide (e.g., SiO2) material, or a combination of the above items. In one embodiment, the encapsulation layer stack 116 of the first sub-pixel 108a includes a silicon nitride material, the encapsulation layer stack 116 of the second sub-pixel 108b includes a silicon oxynitride material, and the encapsulation layer stack 116 of the third sub-pixel 108c includes a silicon oxide material. The thickness of the encapsulation layer stack 116 may depend on the etching selectivity of the material of the encapsulation layer stack 116. The silicon-containing material may be further changed to change the optical properties of the encapsulation layer stack 116. For example, the silicon-containing material may be adjusted to increase or decrease the refractive index. The difference in refractive index may also affect the etching rate of the encapsulation layer stack 116. This allows additional etching selectivity control of the encapsulation layer stack 116. In one embodiment, the encapsulation layer stack 116 of the first sub-pixel 108a has a first refractive index, the encapsulation layer stack 116 of the second sub-pixel 108b has a second refractive index, and the encapsulation layer stack 116 of the third sub-pixel 108c has a third refractive index. In this embodiment, the first refractive index, the second refractive index, and the third refractive index are different from each other.

[0050] In one embodiment, at least one of the encapsulation layer stack 116 of the first sub-pixel 108a, the encapsulation layer stack 116 of the second sub-pixel 108b, and the encapsulation layer stack 116 of the third sub-pixel 108c may include at least two layers of silicon-containing materials. At least one of the encapsulation layer stack 116 of the first sub-pixel 108a, the encapsulation layer stack 116 of the second sub-pixel 108b, and the encapsulation layer stack 116 of the third sub-pixel 108c includes a composition of at least one of the layers of silicon-containing materials that is different from the composition of the other encapsulation layer stacks 116. In a first example, the encapsulation layer stack 116 of the first sub-pixel 108a includes an oxynitride silicon material above the silicon nitride material. The encapsulation layer stack 116 of the second sub-pixel 108b includes an oxide silicon material above the silicon nitride material. The encapsulation layer stack 116 of the third sub-pixel 108c includes a nitride silicon material above the oxide silicon material. In a second example, the encapsulation layer stack 116 of the first sub-pixel 108a includes an oxide silicon material above the oxynitride silicon material. The encapsulation layer stack 116 of the second sub-pixel 108b includes a silicon nitride material over a silicon oxynitride material. The encapsulation layer stack 116 of the third sub-pixel 108c has a silicon oxynitride material over a silicon oxide material.

[0051] The encapsulation layer stack 116 can be further changed using different deposition modes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In one example, the first sub-pixel 108a includes a silicon nitride material deposited using CVD and a silicon oxide material deposited using ALD. The second sub-pixel 108b includes a silicon nitride material deposited using CVD and a silicon oxynitride material deposited using CVD. The third sub-pixel 108c includes a silicon nitride material deposited using CVD. The encapsulation layer stack 116 can be further changed between using an inductively coupled plasma (IDP) or a conductively coupled plasma (CCP) for the deposition process.

[0052] By varying the composition, deposition method, and thickness of the encapsulation layer stack 116, the encapsulation layer stack 116 in each sub-pixel protects the deposited layers during subsequent processing and improves process yield and efficiency. Figure 1A As shown in sub-pixels 108b and 108c in FIG. 1 , variations in the thickness of encapsulation layer stack 116 further control the distance between lower edge 206 and the top surface of encapsulation layer stack 116. These distances control the amount of etching and deposition that occurs under overhang structure 110, resulting in enhanced protection of OLED material 112 during subsequent deposition and etching.

[0053] In some embodiments, first layer 116A may be between about 0.5 μm and 1.0 μm thick, second layer 116B may be between about 0.03 μm and 0.1 μm thick, and third layer 116C may be between about 0.3 μm and 0.5 μm thick. In such embodiments, the total thickness of encapsulation layer stack 116 may be about 1 μm.

[0054] In some embodiments, the first layer 116A may be formed of a silicon nitride material, a silicon oxynitride material, a combination thereof, or other materials. The first layer 116A may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0055] In some embodiments, the second layer 116B may be formed of hexamethyldisiloxane (HMDSO) or other materials. The second layer 116B may be deposited by an ALD process.

[0056] In some embodiments, the third layer 116C may be formed of a silicon nitride material, a silicon oxynitride material, a combination thereof, or other materials. The third layer 116C may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0057] During evaporative deposition of the OLED material 112, the lower edge 206 of the second structure 110B defines the location of the OLED endpoint 218. For example, the OLED material 112 is evaporated at an OLED maximum angle corresponding to the OLED vector 212, and the lower edge 206 ensures that the OLED material 112 is not deposited beyond the OLED endpoint 218. During evaporative deposition of the cathode 114, the lower edge 206 of the second structure 110B defines the location of the cathode endpoint 226. For example, the cathode 114 is evaporated at a cathode maximum angle corresponding to the cathode vector 224, and the lower edge 206 ensures that the cathode 114 is not deposited beyond the cathode endpoint 226. OLED Angle θ OLED Smaller than cathode angle θ 阴极 .

[0058] Figure 2B is a schematic cross-sectional view of the overhang structure 110 of the sub-pixel circuit 100 with the first layer 116A of the encapsulation layer stack 116. That is, Figure 2B Shown with Figure 2A The same sub-pixel circuit 100 is shown, except that the encapsulation layer stack is still being formed, and the second layer 116B is not formed on the sub-pixel circuit 100 (see Figure 2A and Figure 2C ) and the third encapsulation layer (see Figure 2A ). No further description is given of what has already been described in this article. Figure 2B As shown, when the first layer 116A is formed on the sub-pixel circuit 100, a gap 150 is also formed.

[0059] Figure 2C is a schematic cross-sectional view of the overhang structure 110 of the sub-pixel circuit 100 having the first layer 116A and the second layer 116B of the encapsulation layer stack 116. That is, Figure 2C Shown with Figure 2A The same sub-pixel circuit 100 is shown, except that the encapsulation layer stack is still being formed, and no third encapsulation layer is formed on the sub-pixel circuit 100 (see Figure 2A ). No further description of what has been described previously is given. Figure 2C As shown, during formation of the sub-pixel circuit 100, the first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B and closes the gap left by the first layer 116A. The gap 150 remains after the second layer 116B is applied.

[0060] Figure 2D is a schematic cross-sectional view of the overhang structure 110 of the sub-pixel circuit 100 having the first layer 116A and the second layer 116B of the encapsulation layer stack 116 and the resist material layer 230. That is, Figure 2D Shown with Figure 2AThe same sub-pixel circuit 100 as shown, except that the third encapsulation layer is not formed on the sub-pixel circuit 100 (see Figure 2A ), there is a resist material layer 230. During the formation of the sub-pixel circuit 100, the resist material layer 230 may be disposed on the sub-pixel circuit 100, and the resist material layer 230 may be patterned thereon. The previously described Figure 2D The resist material layer 230 is disposed over the second layer 116B. As shown, during the formation of the sub-pixel circuit 100, the first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B and closes the gap left by the first layer 116A. The gap 150 remains after the second layer 116B is applied.

[0061] The resist material can be a positive resist or a negative resist. A positive resist includes portions of a resist material that, when exposed to electromagnetic radiation, are soluble in a resist developer applied to the resist after a pattern is written to the resist using electromagnetic radiation. A negative resist includes portions of a resist that, when exposed to radiation, are insoluble in a resist developer applied to the resist after a pattern is written to the resist using electromagnetic radiation. The chemical composition of the resist material determines whether the resist is a positive resist or a negative resist. The resist material layer 230 can be patterned to form one of the pixel openings 124A of the dot-type architecture 101B or the pixel openings 124B of the line-type architecture 101C of one or more of the sub-pixels 108a, 108b, and 108c. The patterning of the resist material layer 230 can be one of a photolithography process, a digital lithography process, or a laser ablation process.

[0062] The first portion 151 of the second layer 116B in contact with the third portion 153 of the second layer 116B may prevent the resist material of the resist material layer 230 from entering the gap 150. If the resist material were to enter the gap 150, the resist material in the gap 150 may remain under the overhang 109, not be exposed to electromagnetic radiation, and may not be removed during formation of the sub-pixel circuit 100 (e.g., during an etching operation).

[0063] Figure 3300 is a schematic cross-sectional view of a sub-pixel circuit 300 according to an embodiment. The sub-pixel circuit 300 includes a substrate 302. A metal-containing layer (e.g., an anode 304) can be patterned on the substrate 302, and the metal-containing layer is defined by an adjacent anode separation structure 326A disposed on the substrate 302. In one embodiment, the anode 304 is pre-patterned on the substrate 302. For example, the substrate 302 is pre-patterned with an anode 304 of indium tin oxide (ITO). The anode 304 is configured to serve as an anode for each sub-pixel. In one embodiment, the anode 304 is a stacked layer of a first transparent conductive oxide (TCO) layer, a second metal-containing layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal-containing layer. The anode 304 includes, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, a combination of the above items, or other suitable conductive materials. The anode 304 and the anode separation structure 326A have the same thickness.

[0064] The anode separation structure 326A is disposed above the substrate 302. The anode separation structure 326A includes an organic material, an organic material on which an inorganic coating is disposed, or one of inorganic materials. In some embodiments, the anode separation structure 326A may be an electrically insulating polymer. The organic material of the anode separation structure 326A includes, but is not limited to, polyimide. The inorganic material of the anode separation structure 326A includes, but is not limited to, silicon oxide (SiO2) material, silicon nitride (Si3N4) material, silicon oxynitride (Si2N2O) material, magnesium fluoride (MgF2) material, or a combination of the above items. Adjacent anode separation structures 326A define each sub-pixel and expose the anode 304 of each sub-pixel circuit 300.

[0065] The sub-pixel circuit 300 has a plurality of sub-pixels 306 including at least a first sub-pixel 308A and a second sub-pixel 308B. Although FIG. 1 depicts a first sub-pixel 308A and a second sub-pixel 308B, the sub-pixel circuit 300 in the embodiments described herein may include two or more sub-pixels, such as a third sub-pixel and a fourth sub-pixel. Each sub-pixel has an OLED material that is configured to emit white, red, green, blue, or other color light when powered on. For example, the OLED material of the first sub-pixel 308A emits red light when powered on, the OLED material of the second sub-pixel 308B emits green light when powered on, the OLED material of the third sub-pixel emits blue light when powered on, and the OLED material of the fourth sub-pixel emits another color of light when powered on.

[0066] Each sub-pixel 306 includes adjacent overhang structures 310, wherein adjacent sub-pixels share adjacent overhang structures 310. The overhang structures 310 are permanent to the sub-pixel circuit 300. The overhang structures 310 further define each sub-pixel 306 of the sub-pixel circuit 300. Each overhang structure 310 includes adjacent overhang portions 309. Adjacent overhang portions 309 are defined by overhang extensions 309A of a second structure 310B, which extend laterally through an upper surface 305 of the first structure 310A. The first structure 310A is disposed above the anode separation structure 326A, wherein a lower surface 303A of the first structure 310A contacts an upper surface 318 of the anode separation structure 326A. The second structure 310B is disposed above the first structure 310A. The second structure 310B may be disposed on the upper surface 305 of the first structure 310A. The second structure 310B may also be disposed above the intermediate structure 310C. In some embodiments, the intermediate structure 310C is disposed above the upper surface 305 of the first structure 310A. The intermediate structure 310C may be an adhesion promoting material. The adhesion promoting material improves the adhesion between the first structure 310A and the second structure 310B. The adhesion promoting material may include a chromium (Cr) material. The intermediate structure 310C is an optional layer. The adjacent overhang portion 309 includes the first structure 310A and the second structure 310B.

[0067] In one embodiment, the overhang structure 310 includes a second structure 310B of a conductive inorganic material and a first structure 310A of a non-conductive inorganic material. The conductive material of the second structure 110B may include a gallium arsenide (GaAs) material, a copper (Cu) material, an aluminum (Al) material, an aluminum neodymium (AlNd) material, a molybdenum (Mo) material, a molybdenum tungsten (MoW) material, or a combination of the above items. The non-conductive material of the first structure 310A may include an amorphous silicon (a-Si) material, a titanium (Ti) material, a silicon nitride (Si3N4) material, a silicon oxide (SiO2) material, a silicon oxynitride (Si2N2O) material, or a combination of the above items. The overhang structure 310 can be maintained in place, i.e., it is permanent.

[0068] In one embodiment that can be combined with other embodiments described herein, the first structure 310A includes an inorganic material, for example, a silicon material such as an amorphous silicon material, and the second structure 310B includes a germanium material, a copper material, a chromium material, a gallium arsenide (GaAs) material, a group III element material, a group IV element material, a group III-V compound material, or a combination thereof. In another embodiment that can be combined with other embodiments described herein, the first structure 310A includes a germanium material, a copper material, a chromium material, a gallium arsenide (GaAs) material, a group III element material, a group IV element material, a group III-V compound semiconductor material, or a combination thereof, and the second structure 310B includes an inorganic material, for example, a silicon material such as an amorphous silicon material.

[0069] The adjacent overhang portion 309 is defined by an overhang extension 309A. At least the bottom surface 307 of the second structure 310B is wider than the upper surface 305 of the first structure 310A to form the overhang extension 309A. The overhang extension 309A of the second structure 310B forms the overhang portion 309 and allows the second structure 310B to shield the first structure 310A. The shielding of the overhang portion 309 provides evaporation deposition of the OLED material 312 and the cathode 314. The OLED material 312 may include one or more of a HIL, a HTL, an EML, and an ETL. The OLED material 312 is disposed above the anode 304 and in contact with it. The OLED material 312 is disposed below the adjacent overhang portion 309 and may be in contact with the sidewall 311 of the first structure 310A. In one embodiment, the OLED material 312 is different from the materials of the first structure 310A, the second structure 310B, and the intermediate structure 310C. The cathode 314 is disposed above the OLED material 312 and extends under the adjacent overhang portion 309. The cathode 314 may extend through an end point of the OLED material 312. The cathode 314 may contact the sidewall 311 of the first structure 310A. The overhang structure 310 and the evaporation angle set by the evaporation source define a deposition angle, that is, the overhang structure provides a shielding effect during evaporation deposition at the evaporation angle set by the evaporation source.

[0070] Cathode 314 includes a conductive material, such as a metal. For example, cathode 314 includes, but is not limited to, silver, magnesium, chromium, titanium, aluminum, ITO, or a combination thereof. In one embodiment, the material of cathode 314 is different from the material of first structure 310A, second structure 310B, and intermediate structure 310C. In some embodiments, for example, Figure 3As shown, when applied to the sub-pixel circuit 300, the OLED material 312 and the cathode 314 are disposed above the sidewall 313 of the second structure 310B of the overhang structure 310 in the pixel plane. In other embodiments, the OLED material 312 and the cathode 314 are disposed above the upper surface 315 of the second structure 310B of the overhang structure 310 in the pixel plane. In still other embodiments, the OLED material 312 and the cathode 314 terminate on the sidewall 311 of the first structure 310A, that is, they are not disposed above the sidewall 313 of the second structure 310B or the upper surface 315 of the second structure 310B in the pixel plane.

[0071] Each sub-pixel 306 includes an encapsulation layer stack 316, which includes a first layer 316A, a second layer 316B and a third layer 316C. The encapsulation layer stack 116 can be or can correspond to a local passivation layer. The encapsulation layer stack 316 of each sub-pixel is disposed above the cathode 314 (and the OLED material 312), wherein the encapsulation layer stack 316 is below at least a portion of each of the overhangs 309 and extends along the sidewalls 311 of each of the first structure 310A and the second structure 310B. The encapsulation layer stack 316 is disposed above the cathode 314 and extends at least above the sidewall 311 of the first structure 310A in the pixel plane to contact the cathode 314. In some embodiments, the encapsulation layer stack 316 extends to contact the sidewall 311 of the first structure 310A. In the example Figure 3 In the illustrated embodiment shown, packaging layer stack 316 extends to contact second structure 310B at the underside surface of overhang extension 309A, sidewall 313 of second structure 310B, and upper surface 315 of second structure 310B. Packaging layer stack 316 includes a conductive inorganic material, such as aluminum oxide (Al2O3).

[0072] The first layer 316A and the second layer 316B have a gap 350. Each of the gaps 350 is defined by a first portion 351, a second portion 352, a third portion 353, and a first portion 351 in contact with the third portion 353 of the second layer 316B. The first portion 351 of the second layer 316B is in contact with the third portion 353 of the second layer 316B. The gap 350 is sealed by the contact of the first portion 351 and the third portion 353. The first layer 316A has an inner surface 355. The inner surface 355 is in contact with the cathode 314, the side wall 311 of the first structure 310A, and the lower side surface of the overhang extension 309A of the second structure 310B. The second layer 316B has an outer surface 356. The outer surface 356 surrounds the void space outside the second layer 316B. The void space corresponds to the gap 350. In one or more embodiments, the size of the gap 350 and the void is less than the height of the overhang portion 309. In one or more embodiments, the size of the gaps 350 and voids is less than 1.5 μm, such as less than 0.5 μm.

[0073] In some embodiments, the encapsulation layer stack 316 of the first sub-pixel 308a overlaps the encapsulation layer stack 316 of the second sub-pixel 308b.

[0074] In some embodiments, first layer 316A may be between about 0.5 μm and 1.0 μm thick, second layer 316B may be between about 0.03 μm and 0.1 μm thick, and third layer 316C may be between about 0.3 μm and 0.5 μm thick. In such embodiments, the total thickness of encapsulation layer stack 316 may be about 1 μm.

[0075] In some embodiments, the first layer 316A may be formed of a silicon nitride material, a silicon oxynitride material, a combination thereof, or other materials. The first layer 316A may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0076] In some embodiments, the second layer 316B may be formed of a hexamethyldisiloxane (HMDSO) material or other materials. The second layer 316B may be deposited by an ALD process.

[0077] In some embodiments, the third layer 316C may be formed of a silicon nitride material, a silicon oxynitride material, a combination thereof, or other materials. The third layer 316C may be deposited by a PECVD process.

[0078] In an embodiment including one or more covering layers, the covering layer is disposed between the cathode 314 and the encapsulation layer stack 316. For example, a first covering layer and a second covering layer are disposed between the cathode 314 and the encapsulation layer stack 316. Each of the embodiments described herein may include one or more covering layers disposed between the cathode 314 and the encapsulation layer stack 316. The first covering layer may include an organic material. The second covering layer may include an inorganic material, such as lithium fluoride. The first covering layer and the second covering layer may be deposited by evaporative deposition. In another embodiment, the sub-pixel circuit 300 further includes at least one overall passivation layer disposed above the overhang structure 310 and the encapsulation layer stack 316. In yet another embodiment, the sub-pixel includes an intermediate passivation layer disposed above the overhang structure 310 of each of the sub-pixels 306 and disposed between the encapsulation layer stack 316 and the overall passivation layer.

[0079] Figure 4A yes Figure 3 Schematic enlarged cross-sectional view of overhang structure 310 of sub-pixel circuit 300 shown. Sub-pixel circuit 300 includes packaging layer stack 316, packaging layer stack 316 includes first layer 316A, second layer 316B and third layer 316C. The previously described features will not be further described. Figure 3 As shown, packaging layer stack 316 has gaps 350. Each of gaps 350 is defined by first portion 351, second portion 352, third portion 353, and first portion 351 of second layer 316B in contact with third portion 353 of second layer 316B. As shown, second layer 316B prevents material of third layer 316C from entering gaps 350. During formation of packaging layer stack 316, gaps 350 remain after forming third layer 316C.

[0080] Figure 4B yes Figure 3 and Figure 4A Schematic enlarged cross-sectional view of the overhang structure 310 of the sub-pixel circuit 300 shown, but without the second layer 316B (see Figure 3 and 4A ) and the third layer 316C (see Figure 3 and Figure 4A ).Right now, Figure 4B Shown with Figure 3 The same sub-pixel circuit 300 is shown, except that the encapsulation layer stack 316 is still formed, and the second layer 316B is not formed on the sub-pixel circuit 300 (see Figure 3 and Figure 4A ) and the third layer 316C (see Figure 3 and Figure 4A ). No further description is given of what has already been described in this article. Figure 4BAs shown, when the first layer 316A is formed on the sub-pixel circuit 300, a gap 350 is also formed.

[0081] Figure 4C yes Figure 3 , Figure 4A and Figure 4B Schematic cross-sectional view of the overhang structure 310 of the sub-pixel circuit 300 shown, but without the third layer 316C (see Figure 3 and Figure 4A ).Right now, Figure 4C Shown with Figure 3 The same sub-pixel circuit 300 is shown, except that the encapsulation layer stack 316 is still being formed, and no third encapsulation layer is formed on the sub-pixel circuit 300 (see Figure 3 and Figure 4A ). No further description of what has been described previously is given. Figure 4C As shown, during formation of the sub-pixel circuit 300, the first portion 351 of the second layer 316B contacts the third portion 353 of the second layer 316B and closes the gap 350 left by the first layer 316A. The gap 350 remains after the second layer 316B is applied.

[0082] Figure 4D 3 is a schematic cross-sectional view of the overhang structure 310 of the sub-pixel circuit 300 having the first layer 316A and the second layer 316B of the encapsulation layer stack 316 and the resist material layer 430. That is, Figure 4D Shown with Figure 3 The same sub-pixel circuit 300 as shown, except that the third encapsulation layer is not formed on the sub-pixel circuit 300 (see Figure 3 and Figure 4A ), there is a resist material layer 430. During the formation of the sub-pixel circuit 300, the resist material of the resist material layer 430 may be disposed on the sub-pixel circuit 300, and the resist material is patterned thereon. The previously described Figure 4D 4. A resist material layer 430 is disposed over the second layer 316B. As shown, during formation of the sub-pixel circuit 300, the first portion 351 of the second layer 316B contacts the third portion 353 of the second layer 316B and closes the gap left by the first layer 316A. The gap 350 remains after the second layer 316B is applied.

[0083] The resist material of the resist material layer 430 may be a positive resist or a negative resist. The chemical composition of the resist material determines whether the resist is a positive resist or a negative resist. The resist material of the resist material layer 430 may be patterned to form one of the pixel openings 124A of the dot-type architecture 101B or the pixel openings 124B of the line-type architecture 101C of one or more of the sub-pixels 308a and 308b. The patterning of the resist material of the resist material layer 430 may be one of a photolithography process, a digital lithography process, or a laser ablation process.

[0084] The first portion 351 of the second layer 316B in contact with the third portion 353 of the second layer 316B may prevent the resist material of the resist material layer 430 from entering the gap 350. If the resist material were to enter the gap 350, the resist material in the gap 350 may remain under the overhang portion 309, not be exposed to electromagnetic radiation, and may not be removed during formation of the sub-pixel circuit 300 (e.g., during an etching operation).

[0085] Figure 5 is a flow chart of a method 500 for forming a sub-pixel circuit 100 or 300 according to an embodiment. FIG. 6A to FIG. 6I is a schematic cross-sectional view of a substrate 102 during a method 500 for forming a subpixel circuit 100 or 300 according to an embodiment described herein. The method 500 described herein provides the ability to manufacture subpixel circuits 100 having a dot-type architecture 101B and subpixel circuits 300 having a line-type architecture 101C.

[0086] At operation 502, a first layer of a first material is deposited over a first organic light emitting diode (OLED) material of a sub-pixel circuit using a plasma enhanced chemical vapor deposition (PECVD) process. Fig. 6A As shown, a first layer 116A is deposited over the first OLED material 112 and the cathode 114, and the first layer 116A has a gap 150 below the top extension 109A of the second structure 110B. Figure 2B As shown, a first layer 116A is deposited over the OLED material 112 of the sub-pixel circuit 100. In another example, as shown in FIG. Figure 4B As shown, a first layer 316A is deposited over the sub-pixel circuit 300 .

[0087] At operation 504, a second layer of a second material is deposited over the first layer. Figure 6B As shown, the first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B and closes the entrance of the gap 150 in the second layer 116B. Figure 2CAs shown, a second layer 116B is deposited over the first layer 116A. In another example, as shown in FIG. Figure 4C As shown, a second layer 316B is deposited over the first layer 316A.

[0088] At operation 506, a resist material is deposited over the sub-pixel circuitry. Figure 6C As shown, the resist material 230 cannot enter the gap 150 because the first portion 151 of the second layer 116B contacts the third portion 153 of the second layer 116B and closes the entrance of the gap 150 in the second layer 116B. Figure 2D As shown, a resist material layer 230 is deposited over the sub-pixel circuit 100. Due to the contact between the first portion 151 of the second layer 116B and the third portion 153 of the second layer 116B, the resist material of the resist material layer 230 cannot enter the gap 150. Due to the gap 150 and the encapsulation layer stack 116, the resist material of the resist material layer 230 cannot be under the second structure 110B. In another example, as Figure 4D As shown, a resist material layer 430 is deposited over the sub-pixel circuit 300. Due to the contact between the first portion 351 of the second layer 316B and the third portion 353 of the second layer 316B, the resist material of the resist material layer 430 cannot enter the gap 350. Due to the gap 350 and the encapsulation layer stack 316, the resist material of the resist material layer 430 cannot be under the second structure 310B.

[0089] At operation 508, a portion of the resist material is patterned and removed. Fig.6D As shown, a portion of the resist material 230 may be removed over the well 128a of the sub-pixel 108a. In an example, the resist material of the resist material layer 230 or the resist material of the resist material layer 430 may be patterned to form a first sub-pixel 108a. Figure 1B The pixel opening 124A or the pixel opening 124B of the dot-type structure 101B shown in FIG. Figure 1C One of the pixel openings 124B of the linear architecture 101C shown. In an example, the patterning can be one of a photolithography, a digital lithography process, or a laser ablation process. Because the resist material of the resist material layers 230 and 430 is prevented from moving under the second structure 110B or 310B, the second structure 110B and 310B does not shield the resist material of the resist material layers 230 and 430, and the resist material of the resist material layers 230 and 430 can be patterned by exposure to ultraviolet light or other radiation.

[0090] At operation 510, a first portion of the first layer and a first portion of the second layer exposed by the resist material in a well of a sub-pixel of a sub-pixel circuit are removed. Fig. 6EAs shown, the first portion of the first layer 116A and the first portion of the second layer 116B exposed by the resist material 230 above the well 128a of the sub-pixel 108a can be removed. In addition, the cathode 114 exposed in the well 128a of the sub-pixel 108a (at Fig. 6E Remove and Fig.6D ) and the first OLED material 112 (shown in Fig. 6E Remove and Fig.6D ). The first portion of the first layer and the first portion of the second layer exposed by the resist material may be removed by a dry etching process or a wet etching process. In an example, the first portion of the first layer and the first portion of the second layer exposed by the resist material may be removed. Figure 1A A first portion of the first layer 116A over the third subpixel 108c and a first portion of the second layer 116B over the third subpixel 108c are shown. In this example, the first OLED material can be removed from the well 128c of the third subpixel 108c, and the second OLED material can be deposited in the well 128c of the third subpixel 108c. In another example, the first OLED material can be removed. Figure 3 A first portion of the first layer 316A is shown above the second subpixel 308B and a first portion of the second layer 316B is shown above the second subpixel 308B. In this example, the first OLED material can be removed from the well 328B of the second subpixel 308B and the second OLED material can be deposited in the well 328B of the second subpixel 308B.

[0091] At operation 512, a second OLED material is deposited in the well. Fig. 6F As shown, a second OLED material 612 may be deposited in well 128a. The color of the second OLED material 612 may be different from the first OLED material 112. In addition, a metal material may be deposited in well 128a to form a cathode 614. In an example, as shown in FIG. Figure 1A As shown, OLED material 112 and metal material (forming cathode 114) are deposited in well 128a of first sub-pixel 108a. In another example, as shown in FIG. Figure 3 As shown, OLED material 312 and metal material (forming cathode 314) are deposited in well 328A of first subpixel 308A.

[0092] At operation 514, a third layer of the first material is deposited over the second OLED material in the well using a PECVD process. Figure 6G As shown, a third layer 616A is deposited over the second OLED material 612 and the cathode 614. For example, Figure 2B As shown, a first layer 116A is deposited over the OLED material 112 of the sub-pixel circuit 100. In another example, as shown in FIG. Figure 4BAs shown, a first layer 316A is deposited over the sub-pixel circuit 300 .

[0093] At operation 516, a fourth layer of the second material is deposited over the third layer. Figure 6H As shown, a fourth layer 616B is deposited over the third layer 616A. Figure 2C As shown, a second layer 116B is deposited over the first layer 116A. In another example, as shown in FIG. Figure 4C As shown, a second layer 316B is deposited over the first layer 316A.

[0094] At operation 518, a fifth layer of the third material is deposited over the second portion of the first layer and over the second portion of the second layer. Fig.6I As shown, a third material layer 116C is deposited over the second portion 696A of the first layer 116A and the second portion 696B of the second layer 116B. In addition, the third material layer 116C can be deposited over the fourth layer 616B. As shown, the third material layer 116C can form a seamless coating that can serve as a passivation layer over a device including the sub-pixel circuit 100. In an example, as shown in FIG. Figure 1A and Figure 2A As shown, a third material layer 116C is deposited over a second portion of the first layer 116A and a second portion of the second layer 116B in the well of the first sub-pixel 108a. Figure 3 and Figure 4A As shown, a third material layer 316C is deposited over a second portion of the first layer 316A and a second portion of the second layer 316B in the well of the first subpixel 308A.

[0095] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. A sub-pixel, comprising: substrate; adjacent overhang structures, the adjacent overhang structures defining the sub-pixel; anode; an organic light emitting diode (OLED) material disposed above the anode; a cathode disposed above the OLED material; as well as A package layer stack having a first layer, a second layer disposed above the first layer, and a third layer, wherein: The first layer and the second layer have a first portion disposed above the cathode, a second portion disposed above a sidewall of each overhang structure, and a third portion disposed below a lower side surface of an extension of each overhang structure; a gap defined by contact of the first portion of the second layer and the third portion of the second layer; and The third layer is disposed over the second layer outside the gap.

2. The subpixel of claim 1, wherein the first layer comprises a silicon nitride (Si3N4) material, a silicon oxynitride (Si2N2O) material, or a combination thereof. 3 . The subpixel of claim 1 , wherein the second layer comprises a hexamethyldisiloxane (HMDSO) material.

4. The sub-pixel of claim 1, wherein the third layer comprises silicon nitride (Si3N4) material, silicon oxynitride (Si2N2O) material, or a combination thereof.

5. The sub-pixel of claim 1, wherein the OLED material is further disposed below the overhang structure.

6. The subpixel of claim 1, wherein one of the overhang structures comprises a first structure and a second structure overlying the first structure, wherein the second structure has an extension extending laterally through the first structure. The sub-pixel of claim 6 , wherein the first structure comprises an inorganic material or a metal-containing material. 8 . The sub-pixel of claim 6 , wherein the second structure comprises an inorganic material, a non-conductive material, or a metal-containing material.

9. A device comprising: substrate; as well as An overhang structure, wherein the overhang structure defines a plurality of sub-pixels, each sub-pixel comprising: anode; an organic light emitting diode (OLED) material disposed above the anode; a cathode disposed over the OLED material; and A package layer stack having a first layer, a second layer disposed above the first layer, and a third layer, wherein: The first layer and the second layer have a first portion disposed above the cathode, a second portion disposed above a sidewall of each overhang structure, and a third portion disposed below a lower side surface of an extension of each overhang structure; a gap defined by contact of the first portion of the second layer and the third portion of the second layer; and The third layer is disposed over the second layer outside the gap.

10. The device of claim 9, wherein the first layer comprises a silicon nitride (Si3N4) material, a silicon oxynitride (Si2N2O) material, or a combination thereof.

11. The device of claim 9, wherein the second layer comprises a hexamethyldisiloxane (HMDSO) material.

12. The device of claim 9, wherein the third layer comprises a silicon nitride (Si3N4) material, a silicon oxynitride (Si2N2O) material, or a combination thereof.

13. The apparatus of claim 9, wherein one of the overhanging structures comprises a first structure and a second structure overlying the first structure, wherein the second structure has an extension extending laterally through the first structure.

14. The device of claim 9, wherein the OLED material is further disposed beneath the overhang structure.

15. The device of claim 9, further comprising one or more pixel definition layer (PDL) structures disposed over the substrate, wherein the PDL structures define sub-pixels of the device.

16. The apparatus of claim 9, further comprising one or more anode separation structures disposed above the substrate, wherein the anode separation structures define the anode.

17. A method of forming a sub-pixel circuit, the method comprising: depositing a first layer of a first material over a first organic light emitting diode (OLED) material of the sub-pixel circuit using a plasma enhanced chemical vapor deposition (PECVD) process; depositing a second layer of a second material over the first layer; depositing a resist material over the sub-pixel circuitry; patterning and removing a portion of the resist material; removing a first portion of the first layer and a first portion of the second layer exposed by the resist material in a well of a sub-pixel of the sub-pixel circuit; depositing a second OLED material in the well; depositing a third layer of the first material over the second OLED material in the well using the PECVD process; depositing a fourth layer of the second material over the third layer; as well as A fifth layer of a third material is deposited over the second portion of the first layer and over the second portion of the second layer.

18. The method of claim 17, wherein the sub-pixel is a first sub-pixel, and the sub-pixel circuit further comprises a second sub-pixel, and the method further comprises: depositing the first OLED material in the well of the first subpixel and in a second well of the second subpixel before depositing the first layer of the first material; after patterning the resist material and before depositing the third layer of the third material, removing from the second well a first portion of the first OLED material exposed by the resist material; as well as A second OLED material is deposited in the second well after removing the first portion of the first OLED material and before depositing the third layer of the third material.

19. The method of claim 18, wherein the sub-pixel circuit further comprises a third sub-pixel, and the method further comprises: depositing the first OLED material in a third well of the third subpixel before depositing the first layer of the first material; after patterning the resist material and before depositing the third layer of the third material, removing from the third well a third portion of the first OLED material exposed by the resist material; depositing another resist material over the sub-pixel circuitry after removing the third portion of the first OLED material; patterning said another resist material prior to depositing said third layer of said third material; after patterning the further resist material and before depositing the third layer of the third material, removing from the third well a first portion of the second OLED material exposed by the resist material; as well as After removing the first portion of the second OLED material and before depositing the third layer of the third material, a third OLED material is deposited in the third well.

20. The method of claim 17, wherein: The first material includes silicon nitride (Si3N4) material, silicon oxynitride (Si2N2O) material or a combination thereof; The second material includes hexamethyldisiloxane (HMDSO) material; and The third material includes Si3N4 material, Si2N2O material or a combination thereof.

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