A timing path optimization method, electronic device and storage medium

Abstract

The present invention relates to the technical field of EDA, and in particular to a timing optimization method, an electronic device and a storage medium. The method traverses a timing path forward and backward with a target timing path as the center to obtain a loanable area, and evaluates the timing path level by level with the target timing path as the center. When evaluating the i-th level timing path, it is judged whether the i-th level timing path and each level of timing paths between the i-th level timing path and the target timing path in the loanable area meet the timing requirements of the target establishment demand time of the current level timing path. If all of them meet, the loan pulse width is obtained by reversing the clock sampling polarity of all timing units between the i-th level timing path in the loanable area and the target timing path, and is accumulated to the total pulse width borrowed by the target path. When the total pulse width meets the timing requirements of the target establishment demand time of the target path, the evaluation is stopped, thereby achieving the purpose of optimizing the timing path.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA, and in particular to a timing path optimization method, electronic equipment and storage medium. Background Art

[0002] With the continuous advancement of semiconductor technology, the high integration of chips has become a prominent feature of the development of the modern electronics industry. In this context, the number of transistors inside the chip is growing exponentially at an alarming rate, while at the same time, the size of the chip is shrinking. This dual pressure of "the number of transistors is surging and the chip size is shrinking" has a profound impact on all aspects of chip design, especially posing unprecedented challenges to the optimization of timing paths.

[0003] The timing path is the main channel for signal propagation inside the chip, and its performance directly determines the overall operating speed and power efficiency of the chip. In the design of high-performance chips, the optimization of the timing path is particularly critical because it is directly related to whether the chip can run stably at a given frequency, and it is also an important way to achieve chip performance improvement and power reduction. Therefore, how to optimize the timing path has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a method for optimizing a timing path, the method comprising the following steps:

[0005] S100, obtaining a target timing path, where the target timing path is a path that is lower than a target time margin.

[0006] S200, traversing the timing paths forward and backward with the target timing path as the center, marking the timing paths with loanable pulse widths, and obtaining loanable regions.

[0007] S300, evaluating the timing paths level by level with the target timing path as the center, when evaluating the i-th level timing path, judging whether the i-th level timing path and each level timing path between the i-th level timing path and the target timing path in the lending area meet the timing requirements of the target establishment demand time of the current level timing path when the i-th level timing path is lending pulse width, if all meet, obtaining the lending pulse width by reversing the clock sampling polarity of all timing units between the i-th level timing path and the target timing path in the lending area and accumulating it to the total pulse width borrowed by the target path, the value range of i is 1 to K, K is the total number of timing paths; when the total pulse width meets the timing requirements of the target establishment demand time of the target timing path, stopping the evaluation, marking all timing paths that lend pulse widths as timing change paths and their lent pulse widths.

[0008] S400, updating the lending area according to the timing change path and the pulse width of the lending, and obtaining the target lending area.

[0009] S500: Adjust the timing requirement of the required time of the timing change path in the target lending area.

[0010] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0011] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects:

[0013] The embodiment of the present invention provides a timing path optimization method, electronic device and storage medium, which traverses the timing path forward and backward with the target path as the center, and evaluates whether to lend according to the timing requirements of the target establishment time of the current level timing path. If it is lent, the purpose of lending pulse width is achieved by reversing the clock sampling polarity of the timing unit. It borrows the pulse width by reversing the clock sampling polarity to extend the sampling period of the target path, thereby achieving the purpose of optimizing the timing path. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of an optimization method for a chip verification system provided by an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of comparison before and after inverting the clock sampling polarity provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram showing a before-and-after comparison of a method of borrowing pulse width across stages provided in an embodiment of the present invention;

[0018] Figure 4 A comparative schematic diagram of inserting a fill register MCP is provided for an embodiment of the present invention;

[0019] Figure 5 A comparative schematic diagram of another insertion pad register MCP provided in an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of an inserted correction register provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0023] See also Figure 1 , which shows a flow chart of a timing path optimization method, the method comprising the following steps:

[0024] S100, obtaining a target timing path, where the target timing path is a path that is lower than a target time margin.

[0025] In one embodiment, the method is applied to a verification chip or to an application-specific integrated circuit (ASIC).

[0026] In one embodiment, the verification chip is a chip in a prototype verification system or a hardware simulation system. Other chip verification systems for verifying chip designs or verification chips in verification systems that meet specific stages also fall within the protection scope of the present invention.

[0027] Among them, the timing path is the transmission path of the signal from the starting point to the end point in the circuit. The starting point is the location where the data is triggered by the clock edge, and the end point is the location where the data is captured by another clock edge. Usually, the starting point is the clock pin of the input port or the trigger, and the end point is the data input pin of the output port or the trigger. There is a corresponding timing margin (slack) on each timing path. The slack value of the setup time is equal to the target setup requirement time of the timing path minus the maximum arrival time. The slack value can be positive, zero or negative. Among them, the target timing path is all timing paths that are lower than the target time margin. It should be noted that the target path includes critical paths, paths with timing violations, and other timing paths that are lower than the target time margin. Among them, the critical path refers to the single path with the worst slack, which determines the highest operating frequency and performance of the system. Among them, the path with timing violations refers to the path with negative slack. When the slack value is negative, it means that a timing violation has occurred.

[0028] S200, traversing the timing paths forward and backward with the target timing path as the center, marking the timing paths with loanable pulse widths, and obtaining loanable regions.

[0029] In one implementation, the traversal algorithm is a depth-first search (DFS) algorithm or a breadth-first search (BFS), and other algorithms for searching a timing path fall within the protection scope of the present invention.

[0030] The pulse width is the time it takes for a binary signal to switch between a high level and a low level, which determines the rise time and fall time of the signal.

[0031] In one embodiment, the step of marking includes: storing a timing path of a lendable pulse width. Other marking methods also fall within the protection scope of the present invention.

[0032] In one embodiment, S200 further includes: when the timing path satisfies any one of the following conditions, it is a timing path that cannot lend pulse width: the start point and the end point of the timing path cannot adjust the clock polarity; the timing path is a path across clock domains; and there is a user's timing exception constraint on the timing path. That is, except for the timing path that cannot lend pulse width, all other timing paths are timing paths that can lend pulse width.

[0033] The loanable area is an area formed by all timing paths of the loanable pulse widths. It should be emphasized that the loanable area is not an area formed by the timing paths of the actual loanable pulse widths, but only an area of ​​the loanable pulse widths. Whether the pulse widths are actually loaned needs to satisfy the conditions in S300. Since each sequential unit may have multiple fan-in and fan-out, there may be only one and only one timing path in the loanable area, or there may be multiple timing paths for each forward traversal level.

[0034] S300, evaluating the timing paths level by level with the target timing path as the center, when evaluating the i-th level timing path, judging whether the i-th level timing path and each level timing path between the i-th level timing path and the target timing path in the lending area meet the timing requirements of the target establishment demand time of the current level timing path when the i-th level timing path is lending pulse width, if all meet, obtaining the lending pulse width by reversing the clock sampling polarity of all timing units between the i-th level timing path and the target timing path in the lending area and accumulating it to the total pulse width borrowed by the target path, the value range of i is 1 to K, K is the total number of timing paths; when the total pulse width meets the timing requirements of the target establishment demand time of the target timing path, stopping the evaluation, marking all timing paths that lend pulse widths as timing change paths and their lent pulse widths.

[0035] It should be noted that before the total pulse width borrowed meets the timing requirements of the target establishment time of the target timing path, it is necessary to evaluate step by step, that is, to evaluate whether each level of timing path can lend the pulse width. The i-th level timing path is used to illustrate the conditions that need to be met for each level of evaluation. When evaluating the i-th level timing path, it is necessary to first determine whether the i-th level timing path meets the timing requirements of the target establishment time after the corresponding pulse width is borrowed. Even if it is satisfied, it is necessary to determine whether each level of timing path between the target timing path in the loanable area and the target timing path meets the timing requirements of the target establishment time of the current level timing path. If all are satisfied, the clock sampling polarity of all timing units between the i-th level timing path and the target timing path in the loanable area can be reversed so that the pulse width borrowed by the i-th level timing path is passed to the target timing path. The evaluation process of the i+1th level timing path is the same as that of the i-th level timing path. It should be noted that the reversal of the clock sampling polarity in the i+1th level timing path evaluation process is performed after the reversal of the i-th level timing path.

[0036] In one implementation, the timing unit is a flip-flop or a sampling register, and other registers used for sampling also fall within the protection scope of the present invention.

[0037] The target setup time refers to the time before the trigger timing unit captures data, and the data signal must be stable at the trigger input before the target setup time. It should be noted that when the target time margin is not considered, the setup time should satisfy: the arrival time is less than the setup time. When the target time margin is considered, the actual timing margin is greater than the target time margin, and the actual timing margin is equal to the difference between the target setup time and the arrival time.

[0038] In one implementation, in S300, the timing requirement of the target establishment time of the current-level timing path includes:

[0039] T slack_cur >T target_cur , where T slack_cur =T req_su_cur -T brw_cur -T arr_max_cur ;

[0040] Among them, T slack_cur is the actual time margin of the current timing path, T target_cur is the target time margin of the current timing path, T req_su_cur Establish the required time for the target of the current level timing path, T brw_cur is the pulse width provided by the current stage timing path, T arr_max_cur is the maximum arrival time of the current timing path.

[0041] Among them, T target_cur is the preset target time margin.

[0042] It should be noted that since the signal may be affected by many factors when propagating in the circuit, the arrival time (Data Arrival Time) of each timing path has a maximum and minimum value, such as the influencing factors such as power supply voltage, ambient temperature, etc.

[0043] Among them, the timing requirement of the target demand time can ensure that the timing path after lending the corresponding pulse bandwidth still meets the timing requirement. If the current timing path does not meet the timing requirement after lending the corresponding pulse bandwidth, the subsequent steps will not be executed, that is, the pulse width will not be lent by reversing the clock sampling polarity of the timing unit.

[0044] In one implementation, in S300, the timing requirements of the target establishment time of the target path include:

[0045] T slack_tar >T target_tar , where T slack_tar =T brw_total +T req_su_tar -Tarr_max_tar ;

[0046] Among them, T slack_tar is the actual time margin of the target timing path, T target_tar is the target time margin of the target timing path, T brw_total is the total pulse width borrowed by the target path, T req_su_tar Establish the required time for the target timing path, T arr_max_tar is the maximum arrival time of the target timing path.

[0047] The clock sampling polarity refers to whether the trigger edge of the clock sampling is a rising edge or a falling edge. When the trigger edge is a rising edge, the result of reversing the clock sampling polarity is that the trigger edge is a falling edge. When the trigger edge is a falling edge, the result of reversing the clock sampling polarity is that the trigger edge is a rising edge.

[0048] Among them, lending pulse width means advancing the trigger edge of the data sampling of the launch register in the current level timing path or delaying the trigger edge of the data sampling of the capture register in the current level timing path by one pulse width. When one pulse width is advanced, since the trigger time of the current sampling cycle is advanced by one pulse width, and the trigger time of the next sampling cycle remains unchanged, it is equivalent to extending the duration of the sampling cycle, that is, achieving the purpose of lending pulse width. Similarly, delaying one pulse width.

[0049] See also Figure 2 , Figure 2 2 shows a comparison diagram before and after inverting the clock sampling polarity. Figure 2 A in the figure is a schematic diagram before the clock sampling polarity is reversed, which includes the first register F1, the second register F2, the third register F3 and the fourth register F4. The timing paths include: the first timing path from F1 to F2, the second timing path from F2 to F3, and the third timing path from F3 to F4. Assuming the clock cycle is 20ns, the pulse width of the high and low levels is 10ns respectively, the T of the target timing path is slack_tar The target timing path T target_tar is 1ns. At this time, the target timing path is the timing path with timing violation. The first timing path and the third timing path are both timing paths that can lend pulse width, and the T slack_cur are both 15ns, and the T target_tarIt is also 1ns. According to S300, after the first timing path lends a pulse width of 10ns, the value of the target setup time of the first timing path minus the lend pulse width is still greater than the value of the maximum arrival time minus the time margin. That is, the timing requirement of the target setup time is still met after the lend pulse width. Therefore, by reversing the clock sampling polarity of F2 to lend the pulse width, please refer to Figure 2 B in Figure 2 B in FIG. 1 shows the schematic diagram after the clock sampling polarity is inverted. Figure 2 The circle at the clock input end of F2 in B is the sign of reverse polarity. Reversing the polarity of F2 makes it sampled at the falling edge of the clock. At this time, the sampling time of the first timing path is advanced by 10ns, and the sampling time of the second timing path is still sampled at the original rising edge. Therefore, the sampling time of the second timing path is increased by 10ns, that is, the clock sampling time of 30ns. At this time, when the timing requirement of the target establishment time of the target path is met, the evaluation is stopped and the pulse width of other paths is no longer borrowed.

[0050] It should be noted that when the timing change path is not adjacent to the target timing path, the clock sampling polarity of all timing units between the timing change path and the target timing path is reversed, so that the pulse width lent by the timing change path is transferred to the target timing path. Taking the original clock sampling as the rising edge as an example, when the timing change path that lends the pulse width is obtained, and the timing change path is not adjacent to the target timing path, the clock sampling polarity of all timing units between the timing change path and the target timing path is reversed to the falling edge, and only the sampling time of the timing change path is changed from one clock cycle to the pulse width from the rising edge to the falling edge; while the timing paths where other timing units with reversed sampling polarity are located are only changed from rising edge sampling to falling edge sampling, and the sampling cycle is still one clock cycle. Through this method, the pulse width lent by the non-adjacent timing change path is transferred to the target timing path.

[0051] To further understand the implementation of inverting the clock sampling polarity to pass the loaned pulse width to the target timing path, refer to Figure 3 , which shows a before-and-after comparison diagram of the cross-stage pulse width method, Figure 3 A in the figure shows that the pulse width of one cycle is borrowed through F3 and F4, but since the second timing path from F2 to F3 and the fourth timing path from F4 to F5 borrow the corresponding pulse width, the timing requirement of the target establishment time will not be met. At this time, the pulse width can be borrowed from the first timing path between F1 and F2 before the second timing path step by step. Please refer to Figure 3In B, if it is evaluated that the first timing path meets the timing requirement of the target establishment time after lending the corresponding pulse width, the clock sampling polarity of F2 is reversed. Similarly, if the fifth timing path between F5 and F6 also meets the timing requirement of the target establishment time after lending the corresponding pulse width, the clock sampling polarity of F5 is also reversed. At this time, if the target timing path between F3 and F4 meets the timing requirement of the target establishment time of the target timing path after superimposing the borrowed total pulse width, the evaluation is stopped. That is, the borrowed total pulse width is borrowed from the first timing path and the fifth timing path, while the second timing path and the fourth timing path do not lend the pulse width, and the purpose of reversing the clock sampling polarity of F3 and F4 is to transfer the borrowed pulse width to the target timing path.

[0052] S400, updating the lending area according to the timing change path and the pulse width of the lending, and obtaining the target lending area.

[0053] It should be noted that the timing path of the actual lending pulse width and the lent pulse width obtained in S300 can be further updated according to the result obtained in S300 to narrow the target lending area.

[0054] S500: Adjust the timing requirement of the required retention time of the timing change path in the target lending area.

[0055] The hold requirement time refers to the minimum time that the data signal must remain stable at the trigger input after the clock edge triggers the register to capture data.

[0056] Among them, the adjustment method of the required holding time includes a specified method, inserting a register or adjusting the duty cycle, and other methods for adjusting the required holding time also fall within the protection scope of the present invention.

[0057] In one implementation, S500 further includes: after S400 and before S500, it also includes: S450, when the borrowed total pulse width is M times the original sampling period of the target timing path, adjusting the sampling period of the target timing path to M times the original sampling period.

[0058] In one embodiment, S450 also includes, when the total pulse width is borrowed from the start register in the timing path, adjusting the sampling period of the start register in the target timing path to M times the original sampling period; when the total pulse width is borrowed from the capture register in the timing path, adjusting the sampling period of the capture register in the target timing path to M times the original sampling period.

[0059] In one embodiment, a method for specifying a delay multiple M of clock sampling on a target timing path is through a multi-cycle path setting command (set_multicycle_path) in a STA (Static Timing Analysis) tool or inserting a pipeline stage. Other methods for specifying a delay multiple M of clock sampling on a target timing path fall within the protection scope of the present invention.

[0060] When the sampling period of the target path is greater than one clock cycle, the data needs to span multiple clock cycles to reach the target timing unit, which means that the hold time will be extended at the same time, and the frequency reduction will cause the hold time to increase synchronously. However, for the circuit, it is necessary to increase the delay to meet the hold time. In order to solve this problem, the embodiment of the present invention provides the following solution.

[0061] In one embodiment, S500 also includes: a step of adjusting the timing requirement of the hold requirement time of the target path: when the sampling period of the target path is greater than one clock cycle, inserting a pad register (Multi-Cycle Path Register, MCPR) between two timing units connected to the target path to adjust the hold requirement time to meet the timing requirements. This method can adjust the hold requirement time to the hold requirement time triggered by a single clock cycle through the pad register. When the timing requirement of the hold requirement time is adjusted by inserting a register, it is not necessary to specify the delay multiple of the clock sampling on the target timing path.

[0062] In one embodiment, the step of obtaining the number of insertions of the pad register includes: when the original sampling period of the target path is an integer multiple of the clock period, the number of insertions of the pad register sum satisfies: sum=roundup(T brw_total / T period ), T period is the clock period, T brw_total is the total pulse width lent to the target path, and roundup() is the rounding symbol. When the original sampling period of the target path is not an integer multiple of the clock period, the insertion quantity sum of the pad register satisfies: sum=roundup(T brw_total / T period )-1. By forwarding the data of each clock cycle through the pad register, the purpose of adjusting the hold requirement time to the hold requirement time triggered by a single clock cycle is achieved, avoiding the hold requirement time violation, and at the same time avoiding the increase in energy consumption and resources and the reduction in frequency due to the increase in delay.

[0063] In one implementation, when the target path connects two sequential units that also pass through an intermediate verification chip, the pad register is inserted on the target path of the intermediate verification chip.

[0064] For ease of understanding, take the application in verification chip as an example, please refer to Figure 4 , Figure 4 A comparative schematic diagram of inserting the pad register MCP before and after adjusting the sampling polarity is shown. Figure 4 A in FIG. 1 shows a schematic diagram before the unborrowed cycle, where the target path connects the second sequential unit F2 of the first verification chip P1 and passes through the middle verification chip P2 to connect the third sequential unit F3 of the third verification chip P3 . Figure 4 B in the figure shows the schematic diagram after the clock sampling polarity is reversed by borrowing cycle. F2 reverses the clock sampling polarity, so that the clock sampling cycle of the first timing path between F1 and F2 is shortened by one pulse width, while the clock sampling cycle of the target timing path between F2 and F3 is increased by one pulse width. At this time, increasing the delay is a relatively difficult goal, and it will increase energy consumption and resources. Therefore, the pad register F5 is inserted on the target timing path, see Figure 4 C in, inserting the pad register F5 on the target timing path in P2, splitting the target path into two parts, can not only avoid the hold requirement time violation caused by frequency reduction, but also avoid the increase of energy consumption and resources due to the increase of delay. It should be noted that the clock sampling polarity of the pad register F5 can be configured as needed.

[0065] In one embodiment, when two timing units connected by the target path are adjacent, the target timing unit as a fan-in in the target path and the target verification chip in which it is located are obtained, the target port connecting the target path and the target verification chip is obtained, and the pad register MCP is inserted between the target timing unit and the target port.

[0066] For ease of understanding, take the application in verification chip as an example, please refer to Figure 5 , which shows another comparative schematic diagram of inserting the pad register MCP before and after adjusting the sampling polarity. Figure 5 A in FIG. 1 shows a schematic diagram before the unborrowed cycle, where the target path connects F2 of P1 and F3 of P2. Figure 5B in the figure shows the schematic diagram after the borrow cycle reverses the clock sampling polarity. F2 reverses the clock sampling polarity, so that the clock sampling period of the first timing path between F1 and F2 is shortened by one pulse width, while the clock sampling period of the target timing path between F2 and F3 is increased by one pulse width. At this time, the target timing path needs to meet a longer hold requirement time, and the delay needs to be increased to meet the hold requirement time. Increasing the delay is a relatively difficult goal, and it will increase energy consumption and resources. Therefore, the pad register F5 is inserted on the target timing path, see Figure 5 In C, a pad register F5 is inserted on the target timing path between the target ports of F2 and P1, splitting the target path into two parts. This not only avoids the hold requirement time violation caused by frequency reduction, but also does not increase energy consumption and resources due to increased latency.

[0067] In one embodiment, S500 further includes the step of adjusting the timing requirement of the hold time of the affected bypass timing path: when the target path has multiple starting points or end points, marking the same-level timing paths where other starting points or end points are located that are not on the timing change path as bypass timing paths; inserting a correction register (hold fixer) in the bypass timing path to adjust the hold time to meet the timing requirement. Wherein, the same-level timing paths refer to timing paths with the same fan-in.

[0068] For ease of understanding, take the application in verification chip as an example, please refer to Figure 6 , before inserting the sixth register F6, the target timing path from F2 to F3 and the timing path from F2 to F5 are timing paths of the same level. If the pulse width accounts for 50% of the total width, before F2 reverses the clock sampling polarity, the clock sampling period of the bypass timing path between F2 and F5 is one clock cycle; after F2 reverses the clock sampling polarity, the clock sampling period of the bypass timing path between F2 and F5 is shortened to half a cycle. After F2 reverses the clock sampling polarity, F5 is a capture register in the bypass timing path between F2 and F5, and the trigger edge of F5 capture sampling is advanced, resulting in the hold time failing to meet the timing requirements. Therefore, the correction register F6 is inserted into the bypass timing path, so that the data signal sampled in advance by F2 is delayed by F6 until the original clock edge of F5 is sampled again.

[0069] In one implementation, the timing requirement of the required time for maintaining the time can also be met by adjusting the duty cycle. S500 further includes: adjusting the timing requirement of the required time for maintaining the time change path in the target lending area by adjusting the duty cycle to meet:

[0070] T arr_min >T period ×D Ratio×A Ratio ;

[0071] Among them, T arr_min is the minimum arrival time of the timing change path, T period is the clock period, D Ratio is the duty cycle of the clock signal, A Ratio is the duty cycle adjustment ratio.

[0072] In summary, an embodiment of the present invention provides a method for optimizing a timing path, which obtains a target path, traverses the timing path forward and backward with the target path as the center, and evaluates whether to lend according to the timing requirements of the target establishment time of the current level timing path. If lending, the purpose of lending the pulse width is achieved by reversing the clock sampling polarity of the timing unit, thereby achieving the purpose of optimizing the timing path.

[0073] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0074] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0075] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0076] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0077] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for optimizing a timing path, characterized in that: The method comprises the following steps: S100, obtaining a target timing path, where the target timing path is a path that is lower than a target time margin; S200, traversing the timing paths forward and backward with the target timing path as the center, marking the timing paths of the pulse widths that can be lent, and obtaining a loanable area; S300, evaluating the timing paths level by level with the target timing path as the center, when evaluating the i-th level timing path, judging whether the i-th level timing path and each level timing path between the i-th level timing path and the target timing path in the lending area meet the timing requirements of the target establishment demand time of the current level timing path when the i-th level timing path is lending pulse width, if all meet, obtaining the lending pulse width by reversing the clock sampling polarity of all timing units between the i-th level timing path and the target timing path in the lending area and accumulating it to the total pulse width borrowed by the target path, i ranging from 1 to K, K being the total number of timing paths; when the total pulse width meets the timing requirements of the target establishment demand time of the target timing path, stopping the evaluation, marking all timing paths that lend pulse widths as timing change paths and their lent pulse widths; S400, updating the lending area according to the timing change path and the pulse width of the lending, to obtain a target lending area; S500: Adjust the timing requirement of the required time of the timing change path in the target lending area.

2. The method according to claim 1, characterized in that In S300, the timing requirements of the target establishment time of the current level timing path include: T slack_cur >T target_cur , where T slack_cur =T req_su_cur -T brw_cur -T arr_max_cur ; Among them, T slack_cur is the actual time margin of the current timing path, T target_cur is the target time margin of the current timing path, T req_su_cur Establish the required time for the target of the current level timing path, T brw_cur is the pulse width provided by the current stage timing path, T arr_max_cur is the maximum arrival time of the current timing path.

3. The method according to claim 1, characterized in that In S300, the timing requirements of the target establishment time of the target path include: T slack_tar >T target_tar , where T slack_tar =T brw_total +T req_su_tar -T arr_max_tar ; Among them, T slack_tar is the actual time margin of the target timing path, T target_tar is the target time margin of the target timing path, T brw_total is the total pulse width borrowed by the target path, T req_su_tar Establish the required time for the target timing path, T arr_max_tar is the maximum arrival time of the target timing path.

4. The method according to claim 1, characterized in that: After S400 and before S500 , the method further includes: S450 , when the borrowed total pulse width is M times of the original sampling period of the target timing path, adjusting the sampling period of the target timing path to M times of the original sampling period.

5. The method according to claim 1, characterized in that S450 also includes, when the total pulse width is borrowed from the start register in the timing path, adjusting the sampling period of the start register in the target timing path to M times the original sampling period; when the total pulse width is borrowed from the capture register in the timing path, adjusting the sampling period of the capture register in the target timing path to M times the original sampling period.

6. The method according to claim 1, characterized in that S500 also includes: a step of adjusting the timing requirement of the hold time requirement of the target timing path: when the sampling period of the target path is greater than one clock period, inserting a pad register between two timing units connected by the target timing path.

7. The method according to claim 6, characterized in that The step of obtaining the insertion quantity of the pad register comprises: When the original sampling period of the target path is an integer multiple of the clock period, the insertion number sum of the pad registers satisfies: sum=roundup(T brw_total / T period ), T period is the clock period, T brw_total is the total pulse width lent to the target path, and roundup() is the rounding up function; When the original sampling period of the target path is not an integer multiple of the clock period, the insertion number sum of the pad registers satisfies: sum=roundup(T brw_total / T period )-1.

8. The method according to claim 1, characterized in that S500 also includes the steps of adjusting the timing requirement of the required hold time of the affected bypass timing path: when the target path has multiple starting points or end points, marking the same-level timing paths where other starting points or end points are located that are not on the timing change path as bypass timing paths; and inserting a correction register in the bypass timing path.

9. The method according to claim 1, characterized in that: S500 further includes: adjusting the timing requirement of the hold time of the timing change path in the target lending area by adjusting the duty cycle to meet: T arr_min >T period ×D Ratio ×A Ratio ; Among them, T arr_min is the minimum arrival time of the timing change path, T period is the clock period, D Ratio is the duty cycle of the clock signal, A Ratio is the duty cycle adjustment ratio.

10. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 10.

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