Common mode correlation floating power supply circuit and chip

Abstract

The embodiment of the invention provides a common-mode correlation floating power supply circuit and a chip, and belongs to the field of analog circuits. The common-mode correlation floating power supply circuit comprises a common-mode comparator used for comparing a common-mode voltage with a low dropout regulator (LDO) voltage; and a floating power rail generation circuit configured to select a higher one of the common mode voltage and the LDO voltage to generate a floating power rail according to a comparison result of the common mode comparator. According to the embodiment of the invention, when the common-mode voltage is lower than the LDO voltage, the LDO voltage is utilized to generate the floating power supply rail, the problem that the floating power supply rail cannot work due to the fact that the common-mode voltage is too low is solved, and otherwise, the floating power supply rail associated with the common-mode voltage is realized by utilizing the common-mode voltage to generate the floating power supply rail.

Description

Technical Field

[0001] The present invention relates to the field of analog circuits, and in particular to a common-mode associated floating power supply circuit and a chip. Background Art

[0002] In applications such as high-voltage op amps, the power rails of the op amps need to float according to different input common-mode voltages. However, when the input common-mode voltage is low, if the power rail is high voltage, the MOS tube may not withstand enough voltage and cause voltage problems. The voltage of the traditional floating power rail increases with the increase of the input common-mode voltage. Therefore, when the input common-mode voltage is too low, the floating power rail generated on its basis will also have a voltage that is too low, causing the circuit to not work properly. When the input common-mode voltage is high, if the power rail is low voltage, the MOS tube may not work properly due to insufficient supply voltage.

[0003] Therefore, it is necessary to design a floating power supply circuit that can change with the input common mode voltage and can operate under a wider input common mode voltage range. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a common-mode associated floating power supply circuit and chip, which are used to at least partially solve the above technical problems.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a common-mode associated floating power supply circuit, including: a common-mode comparator, used to compare a common-mode voltage and an LDO (Low Drop-Out Regulator) voltage; and a floating power rail generating circuit, used to select a higher voltage between the common-mode voltage and the LDO voltage to generate a floating power rail according to the comparison result of the common-mode comparator.

[0006] Optionally, the common-mode comparator includes: an input circuit for connecting to and stabilizing the common-mode voltage; a signal comparison circuit, a first input end of which is connected to the output end of the input circuit, and a second input end of which is connected to the LDO voltage, for comparing the common-mode voltage and the LDO voltage, and outputting a level signal that can show the magnitude relationship between the common-mode voltage and the LDO voltage.

[0007] Optionally, the input circuit includes a common-source and common-gate current mirror formed by a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a first high-voltage P-type transistor HMP1, wherein the sources of the first PMOS tube MP1 and the second PMOS tube MP2 are connected to the common-mode voltage, the drain of the third PMOS tube MP3 is connected to the first bias current, and the drain of the first high-voltage P-type transistor HMP1 is connected to the first input end of the signal comparison circuit as the output end of the input circuit.

[0008] Optionally, the signal comparison circuit includes: a fourth PMOS tube MP4, whose source is connected to the output end of the input circuit, whose gate is connected to the LDO voltage divider associated with the LDO voltage, and whose drain is connected to the drain of the first NMOS tube MN1; the first NMOS tube MN1, whose drain is connected to the gate, and whose source is grounded; a second NMOS tube MN2, whose drain is connected to a first preset current, whose gate is connected to the gate of the first NMOS tube MN1, and whose source is grounded; a fifth PMOS tube MP5 and a third NMOS tube N3, whose gates are connected and connected to the first preset current, whose drains are connected and serve as the output end of the signal comparison circuit, whose source is connected to the LDO voltage, and whose source is grounded.

[0009] Optionally, the common-mode comparator further includes a hysteresis circuit, and the hysteresis circuit includes: a sixth PMOS tube MP6, whose gate is connected to the output end of the signal comparison circuit, whose source is connected to a preset main current, and a third resistor R3 is connected between the source and the drain; the third resistor R3, whose one end is connected to the preset main current, and whose other end is connected to a fourth resistor R4; the fourth resistor R4, whose one end is connected to the third resistor R3, and whose other end is connected to the LDO voltage divider and connected to the drain of the fifth NMOS tube MN5; the fifth NMOS tube MN5, whose drain is connected to the LDO voltage divider, whose gate is connected to the preset main current, and whose source is connected to another preset main current; and a fourth NMOS tube MN4, whose drain is connected to the gate and connected to the other preset main current, and whose source is grounded.

[0010] Optionally, the floating power rail generating circuit includes: a reference comparator CMP, whose positive input terminal is connected to the output level of the common mode comparator, whose negative input terminal is connected to the reference voltage, whose positive power supply terminal serves as the high voltage terminal of the floating power rail, whose negative power supply terminal is grounded, and whose output terminal outputs a first level signal obtained by comparing the output level of the common mode comparator with the reference voltage; a level inversion circuit, whose input terminal is connected to the first level signal, for level inverting the first level signal and outputting the inverted second level signal; a common mode voltage connection circuit, whose first input terminal is connected to the common mode voltage, whose second input terminal is connected to the second level signal, for connecting the common mode voltage to the high voltage terminal of the floating power rail in response to the second level signal being at a low level; and an LDO voltage connection circuit, whose first input terminal is connected to the LDO voltage, whose second input terminal is connected to the first level signal, for connecting the LDO voltage to the high voltage terminal of the floating power rail in response to the first level signal being at a low level.

[0011] Optionally, the floating power rail generating circuit further includes: a clamping circuit, arranged between the reference comparator CMP and the level inversion circuit, for clamping a lower limit of an output voltage of the reference comparator CMP.

[0012] Optionally, the floating power rail generating circuit further includes: a voltage difference adjustment circuit, arranged between the high voltage end and the low voltage end of the floating power rail, for determining and adjusting the voltage difference between the high voltage end and the low voltage end of the floating power rail; and / or a voltage difference stabilization circuit, arranged between the high voltage end and the low voltage end of the floating power rail, for stabilizing the voltage difference between the high voltage end and the low voltage end of the floating power rail.

[0013] Optionally, the floating power rail generation circuit further includes a discharge circuit, and the discharge circuit includes: a fourth high-voltage P-type transistor HMP4, whose source is connected to the high-voltage end of the floating power rail, whose gate is connected to the voltage-dividing signal following the common-mode voltage, and whose drain is grounded; and / or an eleventh PMOS tube MP11, whose source is connected to the high-voltage end of the floating power rail, whose gate is connected to the LDO voltage, and whose drain is grounded. Wherein, when the discharge circuit includes both the fourth high-voltage P-type transistor HMP4 and the eleventh PMOS tube MP11, the drain of the fourth high-voltage P-type transistor HMP4 is directly grounded or connected to the source of the eleventh PMOS tube MP11 to be indirectly grounded, and the source of the eleventh PMOS tube MP11 is directly connected to the high-voltage end of the floating power rail or connected to the drain of the fourth high-voltage P-type transistor HMP4 to be connected to the high-voltage end of the floating power rail.

[0014] On the other hand, an embodiment of the present invention further provides a chip, comprising any of the above common-mode associated floating power supply circuits.

[0015] Through the above technical solution, the embodiment of the present invention uses a common-mode comparator to compare the common-mode voltage and the LDO voltage, and selects the one with a higher voltage to generate a floating power rail through a floating power rail generation circuit. In this way, when the common-mode voltage is lower than the LDO voltage, the floating power rail is generated by the LDO voltage, which solves the problem that the floating power rail cannot work or the MOS tube withstands voltage due to the common-mode voltage being too low; and when the common-mode voltage is higher than the LDO voltage, the floating power rail is generated by the common-mode voltage, and a floating power rail associated with the common-mode voltage is realized, so that the floating power rail changes with the input common-mode voltage, so that the corresponding floating power circuit can work under a wider input common-mode voltage range.

[0016] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0018] Figure 1 is a structural schematic diagram of a common-mode associated floating power supply circuit according to an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of a common mode comparator in an example of an embodiment of the present invention;

[0020] Figure 3 is a schematic structural diagram of a floating power rail generating circuit according to an example of an embodiment of the present invention; and

[0021] Figure 4 It is a schematic diagram of the principle of LDO voltage division in an example of an embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 100. Common mode comparator; 200. Floating power rail generating circuit;

[0024] 110. input circuit; 120. signal comparison circuit; 130. hysteresis circuit;

[0025] 210, level inversion circuit; 220, common mode voltage access circuit; 230, LDO voltage access circuit; 240, clamping circuit; 250, voltage difference adjustment circuit; 260, voltage difference stabilization circuit; 270, discharge circuit. DETAILED DESCRIPTION

[0026] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0027] It should be noted that the “connection” and “access” involved in the embodiments of the present invention mainly refer to “electrical connection”, which is used to express the signal connection between two components, such as connection through a circuit, and the “connection” and “access” involved can be a direct electrical connection between the two components, or an indirect electrical connection through other components or circuits.

[0028] Figure 1 : is a schematic diagram of the structure of the common-mode associated floating power supply circuit of an embodiment of the present invention, wherein "common-mode associated" means being associated with the input common-mode voltage of the operational amplifier (hereinafter directly referred to as the common-mode voltage) to change with the change of the common-mode voltage. Figure 1As shown, the common-mode associated floating power supply circuit includes: a common-mode comparator 100, used for comparing the common-mode voltage and the LDO voltage; and a floating power rail generating circuit 200, used for selecting a higher voltage between the common-mode voltage and the LDO voltage to generate a floating power rail according to the comparison result of the common-mode comparator 100.

[0029] Among them, the LDO circuit is a common circuit in applications such as high-voltage operational amplifiers. It can provide a clean and stable output voltage (i.e., the LDO voltage) to ensure that the components and devices in the circuit can work normally and reduce the impact of power supply noise and fluctuations on circuit performance.

[0030] In this way, the embodiment of the present invention uses the common-mode comparator 100 to compare the common-mode voltage and the LDO voltage, and selects the higher voltage to generate the floating power rail through the floating power rail generation circuit 200. That is, when the common-mode voltage is lower than the LDO voltage, the floating power rail is generated by the LDO voltage, which solves the problem that the voltage generated by the floating power rail is too low to work when the common-mode voltage is too low, and solves the MOS tube withstand voltage problem generated when the common-mode voltage is low and the power rail is high. When the common-mode voltage is higher than the LDO voltage, the embodiment of the present invention uses the common-mode voltage to generate the floating power rail, realizes the floating power rail associated with the common-mode voltage, and further solves the problem that the voltage of the power rail is not enough or high enough under different common-mode voltages in applications such as high-voltage operational amplifiers, so that the floating power rail changes with the input common-mode voltage, and the corresponding floating power supply circuit can work under a wider input common-mode voltage range.

[0031] The common mode comparator 100 and the floating power rail generating circuit 200 can be arbitrarily designed based on the functions they implement. The following describes a preferred design example provided in the embodiment of the present invention in conjunction with the accompanying drawings.

[0032] Figure 2 1 is a schematic diagram of a common mode comparator 100 in an example of an embodiment of the present invention. Figure 2 As shown, the common-mode comparator 100 includes: an input circuit 110, which is used to access and stabilize the common-mode voltage; a signal comparison circuit 120, whose first input terminal is connected to the output terminal of the input circuit 110, and the second input terminal is connected to the LDO voltage, for comparing the common-mode voltage and the LDO voltage, and outputting a level signal that can show the magnitude relationship between the common-mode voltage and the LDO voltage.

[0033] exist Figure 1In the example of , the input circuit 110 includes a common-source common-gate current mirror formed by a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a first high-voltage P-type transistor HMP1, wherein the drains of the first PMOS tube MP1 and the second PMOS tube MP2 are connected to a common-mode voltage, the gates are connected and connected to the drain of the first PMOS tube MP1, and the drains of the two are respectively connected to the source of the third PMOS tube MP3 and the first high-voltage P-type transistor HMP1, and the drain of the third PMOS tube MP3 is connected to the first bias current I BIASI The first high-voltage P-type transistor HMP1 is connected to the first input terminal of the signal comparison circuit 120 as the output terminal of the input circuit 110, and the third PMOS transistor MP3 is connected to the gate of the first high-voltage P-type transistor HMP1 and to the drain of the third PMOS transistor MP3. Figure 2 In addition to the four transistors shown in the figure, other transistor arrangements and connection methods may be used for design, and the embodiment of the present invention is not limited to this. In addition, the "common mode voltage" of the embodiment of the present invention may be Figure 2 The voltage connected to the IN+ terminal and the IN- terminal may also be a voltage divided by, for example, the first resistor R1 and the second resistor R2.

[0034] The signal comparison circuit 120 includes: a fourth PMOS transistor MP4, whose source is connected to the output end of the input circuit, whose gate is connected to the LDO voltage LDO_GATE1 associated with the LDO voltage LDO_BIAS, and whose drain is connected to the drain of the first NMOS transistor MN1; the first NMOS transistor MN1, whose drain is connected to the gate, and whose source is grounded; a second NMOS transistor MN2, whose drain is connected to the first preset current I1, whose gate is connected to the gate of the first NMOS transistor MN1, and whose source is grounded; a fifth PMOS transistor MP5 and a third NMOS transistor N3, whose gates are connected (the middle point of the connection is marked as Net1) and connected to the first preset current I1, whose drains are connected and serve as the output end CM_H of the signal comparison circuit 120, whose source is connected to the LDO voltage, and whose source is grounded.

[0035] In a preferred embodiment, the common mode comparator 100 further includes a hysteresis circuit 130. Figure 2As shown, the hysteresis circuit includes: a sixth PMOS transistor MP6, whose gate is connected to the output end of the signal comparison circuit, whose source is connected to the preset main current I, and a third resistor R3 is connected between the source and the drain; the third resistor R3, whose one end is connected to the preset main current I and connected to the source of the sixth PMOS transistor MP6, and whose other end is connected to the drain of the sixth PMOS transistor MP6 and the fourth resistor R4; the fourth resistor R4, whose one end is connected to the third resistor R3, and whose other end is connected to the LDO voltage divider and connected to the drain of the fifth NMOS transistor MN5; the fifth NMOS transistor MN5, whose drain is connected to the LDO voltage divider, whose gate is connected to one end of the third resistor R3 connected to the preset main current I, and whose source is connected to another preset main current I; the fourth NMOS transistor MN4, whose drain is connected to the gate and connected to the source of the fifth NMOS transistor MN5, and whose source is grounded.

[0036] Accordingly, for the common mode comparator 100, refer to Figure 2 In the example, when the level of the common mode voltage of IN+ and IN- (hereinafter referred to as the common mode level) is low, the transistors MP1, MP2, MP3 and HMP1 are turned off and the first bias current I BIAS1 Therefore, transistor MN2 cannot be turned on, and the voltage at Net1 is pulled to a high level by the first preset current I1 (which is also a bias current). At this time, the output voltage CM_H is a low level. When the input common-mode level gradually increases, when the four mirror tubes can achieve normal mirroring, Net1 will be pulled down, causing CM_H to flip to a high level. The flip voltage V TH The common mode voltage for normal operation of the transistor MP2 branch is expressed as follows:

[0037] V TH =V SD，MP2 +V SD，HMP1 +V LDO_GATE1 +V SG，MP4 (1)

[0038] Among them, V SD,MP2 and V SD,HMP1 are the source-drain voltages of transistors MP2 and HMP1, V SG,MP4 is the source-gate voltage of transistor MP4. Further reference Figure 4 , the gate voltage of NMOS tube MN5 and LDO voltage (V LDO_BIAS ) differs by a gate-source voltage of a PMOS tube (V GS ), so V LDO_GATE1 With V LDO_BIAS Correlated with about a V GS Voltage, V LDO_GATE1 is the LDO output voltage V LDO_BIASSubtract a PMOS gate-source voltage and the voltage drops of R3 and R4. In addition, V TH Approximately the LDO output voltage V LDO_BIAS , thus achieving Figure 2 The common-mode comparator 100 shown performs an approximate comparison between the input common-mode voltage and the LDO voltage.

[0039] Further, Figure 2 The hysteresis circuit 130 has a hysteresis effect on the common mode comparator 100. When the output CM_H of the common mode comparator 100 is at a high level, that is, when the input common mode voltage is high, the transistor MP6 is turned off. At this time, the voltage of LDO_GATE1 is:

[0040] V LDO_GATE1 =V GS，MN4 +V GS，MN5 -I*(R3+R4) (2)

[0041] When the output CM_H of the common-mode comparator 100 is at a low level, that is, when the input common-mode voltage is low, the transistor MP6 is turned on, and the voltage of LDO_GATE1 is:

[0042] V LDO_GATE1 =V GS，MN4 +V GS,MN5 -I*R4 (3)

[0043] Therefore, the hysteresis of the common-mode comparator is I*R3.

[0044] Further, Figure 3 FIG. 2 is a schematic diagram of a floating power rail generating circuit 200 according to an example of an embodiment of the present invention. Figure 3As shown, the floating power rail generating circuit 200 includes: a reference comparator CMP, whose positive input terminal is connected to the output level of the common mode comparator, whose negative input terminal is connected to the reference voltage, whose positive power supply terminal is used as the high-voltage terminal FLOATV_H of the floating power rail, whose negative power supply terminal is grounded, and whose output terminal outputs a first level signal Net4 obtained by comparing the output level of the common mode comparator with the reference voltage; a level inversion circuit 210, whose input terminal is connected to the first level signal Net4, for level inverting the first level signal Net4, and outputting the inverted second level signal Net2; The common mode voltage access circuit 220 has a first input terminal connected to the common mode voltage and a second input terminal connected to the second level signal Net2, and is used to connect the common mode voltage to the high voltage terminal FLOATV_H of the floating power rail in response to the second level signal Net2 being a low level. The LDO voltage access circuit 230 has a first input terminal connected to the LDO voltage and a second input terminal connected to the first level signal Net4, and is used to connect the LDO voltage to the high voltage terminal FLOATV_H of the floating power rail in response to the first level signal Net4 being a low level. It is understandable that the floating power rail also has a corresponding low voltage terminal FLOATV_L, which, for example, provides a second deflection current I BIAS2 Accordingly, the floating power rail generating circuit generates a floating power rail formed by electrically connecting the high voltage terminal FLOATV_H and the low voltage terminal FLOATV_L.

[0045] It should be noted that the common-mode comparator 100 cannot be skipped and the reference comparator CMP cannot be directly used to compare the common-mode voltage and the LDO voltage. This is because the reference comparator CMP is a conventional comparator, which will break down when the common-mode voltage is high voltage. Therefore, the common-mode comparator 100 needs to be used to stabilize the common-mode voltage and perform level shifting (levelshifter) in advance.

[0046] exist Figure 3 In the example of , the level inversion circuit 210 includes a sixth NMOS transistor MN6 and a ninth PMOS transistor MP9, wherein the gates of the sixth NMOS transistor MN6 and the ninth PMOS transistor MP9 are connected and connected to the first level signal Net4 as the input end of the level inversion circuit 210, and the drains of the sixth NMOS transistor MN6 and the ninth PMOS transistor MP9 are connected and connected to the second level signal Net2 as the input end of the level inversion circuit 210. In addition, the source of the sixth NMOS transistor MN6 is connected to the low voltage end FLOATV_L of the floating power rail, and the source of the ninth PMOS transistor MP9 is connected to the high voltage end FLOATV_H of the floating power rail.

[0047] The common-mode voltage access circuit 220 includes: a sixth resistor R6 and a seventh resistor R7 respectively connected to the access terminals IN+ and IN- of the common-mode voltage, one end of the sixth resistor R6 and the seventh resistor R7 corresponding to the access terminals IN+ and IN- serving as the first input terminal of the common-mode voltage access circuit 220, and the other end being connected to output the voltage-dividing signal Net3; and a third high-voltage P-type transistor HMP3, a gate of which serves as a second input terminal to access the second level signal Net2, a source to access the voltage-dividing signal Net3, and a drain to the high-voltage terminal FLOATV_H of the floating power rail.

[0048] The LDO voltage access circuit 230 includes: a second high-voltage P-type transistor HMP2 and an eighth resistor R8, wherein the source of the second high-voltage P-type transistor HMP2 is connected to the LDO voltage as a first input terminal, the gate is connected to the first level signal Net4 as a second input terminal, and the drain is connected to the high-voltage terminal FLOATV_H of the floating power rail through the eighth resistor R8.

[0049] Furthermore, the floating power rail generating circuit 200 further includes: a clamping circuit 240 , which is arranged between the reference comparator CMP and the level inversion circuit 210 and is used to clamp the lower limit of the output voltage of the reference comparator CMP.

[0050] exist Figure 3 In the example, the clamping circuit 240 includes: a fifth resistor R5, one end of which is connected to the output end of the reference comparator CMP, and the other end is connected to the high-voltage end FLOATV_H of the floating power rail; and a seventh PMOS tube MP7 and an eighth PMOS tube MP8, the drain and gate of the eighth PMOS tube MP8 are both connected to the output end of the reference comparator CMP, the source is connected to the drain and gate of the seventh PMOS tube MP7, and the source of the seventh PMOS tube MP7 is connected to the high-voltage end FLOATV_H of the floating power rail.

[0051] Furthermore, the floating power rail generating circuit 200 also includes: a voltage difference adjustment circuit 250, which is arranged between the high voltage end FLOATV_H and the low voltage end FLOATV_L of the floating power rail, and is used to determine and adjust the voltage difference between the high voltage end FLOATV_H and the low voltage end FLOATV_L of the floating power rail; and / or a voltage difference stabilization circuit 260, which is arranged between the high voltage end FLOATV_H and the low voltage end FLOATV_L of the floating power rail, and is used to stabilize the voltage difference between the high voltage end FLOATV_H and the low voltage end FLOATV_L of the floating power rail.

[0052] exist Figure 3In the example, the voltage difference adjustment circuit 250 includes a tenth PMOS transistor MP10, an eighth NMOS transistor MN8 and a seventh NMOS transistor MN7, wherein the source of the tenth PMOS transistor MP10 is connected to the high voltage end FLOATV_H of the floating power rail, the drain is connected to the gate and connected to the drain of the eighth NMOS transistor MN8, the drain of the eighth NMOS transistor MN8 is connected to the gate, the source is connected to the drain of the seventh NMOS transistor MN7, the drain of the seventh NMOS transistor MN7 is connected to the gate, and the source is connected to the low voltage end FLOATV_L of the floating power rail. In addition, the voltage difference stabilization circuit 260 includes a first capacitor C1 connected between the high voltage end FLOATV_H and the low voltage end FLOATV_L of the floating power rail.

[0053] Further, the floating power rail generation circuit 200 further includes a discharge circuit 270, and the discharge circuit 270 includes: a fourth high-voltage P-type transistor HMP4, whose source is connected to the high-voltage end FLOATV_H of the floating power rail, whose gate is connected to the voltage-dividing signal Net3 following the common-mode voltage, and whose drain is grounded; and / or an eleventh PMOS transistor MP11, whose source is connected to the high-voltage end of the floating power rail, whose gate is connected to the LDO voltage, and whose drain is grounded. Wherein, when the discharge circuit 270 includes both the fourth high-voltage P-type transistor HMP4 and the eleventh PMOS transistor MP11, the drain of the fourth high-voltage P-type transistor HMP4 is directly grounded or connected to the source of the eleventh PMOS transistor MP11 to be indirectly grounded, and the source of the eleventh PMOS transistor MP11 is directly connected to the high-voltage end of the floating power rail or connected to the drain of the fourth high-voltage P-type transistor HMP4 to be connected to the high-voltage end of the floating power rail. Figure 3 This is only one example connection method of the fourth high-voltage P-type transistor HMP4 and the eleventh PMOS transistor MP11, which can be adjusted according to specific needs.

[0054] Accordingly, reference Figure 3 , and combined with Figure 2The floating power rail generating circuit 200 of the embodiment of the present invention uses the reference comparator CMP to compare the output voltage CM_H of the common mode comparator 100 with the reference voltage REF generated by the reference module, for example. When the common mode level of IN+ and IN- is low, that is, CM_H is at a low level, the comparator CMP outputs the first level signal Net4 as a low level, the second level signal Net2 as a high level, the transistor HMP2 is turned on, and LDO_BIAS is connected to FLOATV_H; when the common mode level is high, CM_H is at a high level, the first level signal Net4 becomes a high level, the second level signal Net2 is at a low level, and the control transistor HMP3 is turned on. At this time, the common mode level of IN+ and IN- is connected to FLOATV_H.

[0055] In this process, transistors MP7, MP8 and the fifth resistor R5 are used to clamp the lower limit of the output voltage of the reference comparator CMP to prevent the gate-source voltage of the transistor MP9 from being too large and breaking down. The voltage difference between the floating power rails FLOATV_H and FLOATV_L is the current I BIAS2 It is determined by three MOS tubes MP10, MN8, and MN7 with gate-source short circuits, and the first capacitor C1 is used to stabilize the voltage difference.

[0056] Furthermore, the fourth high-voltage P-type transistor HMP4 quickly discharges FLOATV_H when the common-mode level quickly jumps from a high level to a low level. Specifically, when the common-mode level is relatively high, the common-mode level is used to power FLOATV_H. If the common-mode level suddenly jumps to a low level at this time, the transistor HMP2 will be turned on, allowing LDO_BIAS to power FLOATV_H, but since the voltage of FLOATV_H is still maintained at a high level of the common mode, it may cause damage to the LDO. At this time, Net3 will also jump low with the common-mode level, so the transistor HMP4 will be turned on to quickly discharge the charge for FLOATV_H.

[0057] It should be noted that Figure 2 , Figure 3 Some transistors in the circuit adopt high-voltage P-type transistor HMP1 to play a voltage-withstanding function in the circuit and protect the low-voltage devices connected below.

[0058] The embodiment of the present invention further provides a chip, which integrates any of the above common-mode associated floating power supply circuits. The chip is, for example, a high-voltage operational amplifier chip, which can also integrate an LDO circuit, etc. The floating power rail generated by the common-mode associated floating power supply of the embodiment of the present invention can change with the input common-mode voltage and can operate under a wider input common-mode voltage range, thereby also improving the applicability of the high-voltage operational amplifier chip.

[0059] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0060] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A common-mode associated floating power supply circuit, characterized in that: include: A common mode comparator (100) for comparing a common mode voltage with a voltage of a low dropout linear stabilizer LDO; as well as A floating power rail generating circuit (200) is used for selecting a higher voltage between the common mode voltage and the LDO voltage to generate a floating power rail according to a comparison result of the common mode comparator (100).

2. The common-mode-linked floating power supply circuit according to claim 1, characterized in that: The common mode comparator (100) comprises: An input circuit (110), used for accessing and stabilizing the common mode voltage; A signal comparison circuit (120) has a first input end connected to the output end of the input circuit (110) and a second input end connected to the LDO voltage, and is used to compare the common mode voltage and the LDO voltage and output a level signal capable of indicating the magnitude relationship between the common mode voltage and the LDO voltage.

3. The common-mode-linked floating power supply circuit according to claim 2, characterized in that: The input circuit (110) comprises a common-source common-gate current mirror formed by a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3) and a first high-voltage P-type transistor (HMP1), wherein the sources of the first PMOS tube (MP1) and the second PMOS tube (MP2) are connected to the common-mode voltage, the drain of the third PMOS tube (MP3) is connected to the first bias current, and the drain of the first high-voltage P-type transistor (HMP1) is connected to the first input end of the signal comparison circuit (120) as the output end of the input circuit (110).

4. The common-mode associated floating power supply circuit according to claim 2, characterized in that: The signal comparison circuit (120) comprises: a fourth PMOS transistor (MP4), whose source is connected to the output end of the input circuit (110), whose gate is connected to the LDO voltage divider associated with the LDO voltage, and whose drain is connected to the drain of the first NMOS transistor (MN1); The first NMOS transistor (MN1) has a drain connected to the gate and a source connected to the ground; a second NMOS transistor (MN2), whose drain is connected to a first preset current, whose gate is connected to the gate of the first NMOS transistor (MN1), and whose source is grounded; The gates of the fifth PMOS tube (MP5) and the third NMOS tube (N3) are connected and connected to the first preset current, the drains are connected and serve as the output end of the signal comparison circuit (120), the source of the fifth PMOS tube (MP5) is connected to the LDO voltage, and the source of the third NMOS tube (N3) is grounded.

5. The common-mode-linked floating power supply circuit according to claim 4, characterized in that: The common mode comparator (100) further comprises a hysteresis circuit (130), and the hysteresis circuit (130) comprises: a sixth PMOS tube (MP6), whose gate is connected to the output end of the signal comparison circuit (120), whose source is connected to a preset main current, and whose source and drain are connected to a third resistor (R3); The third resistor (R3) has one end connected to the preset main current and the other end connected to the fourth resistor (R4); The fourth resistor (R4), one end of which is connected to the third resistor (R3), and the other end of which is connected to the LDO voltage divider and connected to the drain of the fifth NMOS tube (MN5); The fifth NMOS transistor (MN5), having a drain connected to the LDO voltage divider, a gate connected to the preset main current, and a source connected to another preset main current; and The fourth NMOS transistor (MN4) has a drain connected to the gate and connected to the other preset main current, and a source connected to the ground.

6. The common-mode-linked floating power supply circuit according to claim 1, characterized in that: The floating power rail generating circuit (200) comprises: A reference comparator (CMP), wherein the positive input terminal is connected to the output level of the common mode comparator (100), the negative input terminal is connected to the reference voltage, the positive power supply terminal serves as the high voltage terminal of the floating power supply rail, the negative power supply terminal is grounded, and the output terminal outputs a first level signal obtained by comparing the output level of the common mode comparator (100) with the reference voltage; A level inversion circuit (210), whose input terminal is connected to the first level signal, is used to perform level inversion on the first level signal and output a second level signal after inversion; a common mode voltage access circuit (220), a first input terminal of which is connected to the common mode voltage, a second input terminal of which is connected to the second level signal, and is used to connect the common mode voltage to the high voltage end of the floating power rail in response to the second level signal being at a low level; and An LDO voltage access circuit (230) has a first input terminal connected to the LDO voltage and a second input terminal connected to the first level signal, and is used to connect the LDO voltage to the high voltage end of the floating power rail in response to the first level signal being at a low level.

7. The common-mode associated floating power supply circuit according to claim 6, characterized in that: The floating power rail generating circuit (200) further comprises: The clamping circuit (240) is arranged between the reference comparator (CMP) and the level inversion circuit (210) and is used to clamp the lower limit of the output voltage of the reference comparator (CMP).

8. The common-mode-linked floating power supply circuit according to claim 6, characterized in that: The floating power rail generating circuit (200) further comprises: A voltage difference adjustment circuit (250) is arranged between the high voltage end and the low voltage end of the floating power rail, and is used to determine and adjust the voltage difference between the high voltage end and the low voltage end of the floating power rail; and / or A voltage difference stabilization circuit (260) is arranged between the high voltage end and the low voltage end of the floating power rail and is used to stabilize the voltage difference between the high voltage end and the low voltage end of the floating power rail.

9. The common-mode-linked floating power supply circuit according to claim 6, characterized in that: The floating power rail generating circuit (200) further comprises a discharge circuit (270), and the discharge circuit (270) comprises: a fourth high-voltage P-type transistor (HMP4), whose source is connected to the high-voltage end of the floating power rail, whose gate is connected to the divided voltage signal following the common-mode voltage, and whose drain is grounded; and / or an eleventh PMOS transistor (MP11), a source of which is connected to the high-voltage end of the floating power rail, a gate of which is connected to the LDO voltage, and a drain of which is grounded; Wherein, when the discharge circuit (270) includes both the fourth high-voltage P-type transistor (HMP4) and the eleventh PMOS transistor (MP11), the drain of the fourth high-voltage P-type transistor (HMP4) is directly grounded or connected to the source of the eleventh PMOS transistor (MP11) to be indirectly grounded, and the source of the eleventh PMOS transistor (MP11) is directly connected to the high-voltage end of the floating power rail or connected to the drain of the fourth high-voltage P-type transistor (HMP4) to access the high-voltage end of the floating power rail.

10. A chip, characterized in that: The common-mode associated floating power supply circuit comprises the common-mode associated floating power supply circuit as claimed in any one of claims 1 to 9.

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