Data processing method and device, medium and chip

Abstract

The invention discloses a data processing method and device, a medium and a chip. The method comprises the following steps: determining each storage position in each memory and endowing an address code; partitioning the storage position of each memory based on the suffixes of the address codes, wherein the suffixes of the address codes at the storage positions of the same partitions in the same memory are the same; determining a first type of partitions and a second type of partitions in each memory; traversing and determining an inverse transformation position corresponding to each storage position of the first type of partitions in each memory; on the basis of the prefixes and the suffixes in the address codes of the storage positions in the second-class partitions of the storages, matching the second-class partitions in the different storages to obtain a second-class partition matching relation; and determining an inverse transformation position corresponding to each storage position in the second-class partition of each memory based on the second-class partition matching relationship. According to the method, when the inverse transformation position corresponding to each storage position is determined, the number of times of repeated determination can be reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing in computing devices, and in particular to a data processing method, device, medium and chip. Background Art

[0002] In data encryption, such as Fully Homomorphic Encryption (FHE) and Zero Knowledge Proof (ZKP), number theory transformations are involved. Number theory transformations involve butterfly calculations and inverse transformations. Inverse transformations refer to reordering the data obtained after butterfly calculations. At present, butterfly calculations are often processed in parallel, so multiple memories are involved to store the data that needs to be reordered. When reordering, two data at specific locations in the memory need to be exchanged. The binary encoding of the storage addresses of the two exchanged data in the memory is in reverse order.

[0003] For example, the storage address binary code 001001 and the storage address binary code 100100 are inverse order, so the data of these two storage locations must be exchanged during the inverse transformation process, where 001001 represents the storage address 1001 of the memory numbered 00, and 100100 represents the storage address 0100 of the memory numbered 10. For another example, the storage address binary code 001000 and the storage address binary code 000100 are also inverse order, 001000 represents the storage address 1000 of the memory numbered 00, and 000100 represents the storage address 0100 of the memory numbered 00. That is, in the inverse transformation step after the parallel butterfly calculation, the two data to be exchanged may be located in different memories or in the same memory.

[0004] Since the two data to be exchanged in the inverse transformation step after the parallel butterfly calculation may be located in different memories or in the same memory, the current inverse transformation does not adopt a parallel operation method, but adopts a serial method to obtain each data to be processed one by one, and after reversing the binary code of its storage address, the data to be processed is exchanged with the data on the storage address corresponding to the reversed binary code until all the data to be processed are traversed. Among them, since it is a serial one-by-one traversal, the processing time is relatively long; and when the serial one-by-one processing is performed, the two data whose storage addresses are inverse to each other need to be read separately. For example, the two data whose storage addresses are binary codes 001001 and 100100 are inverse to each other, and only the data on any one of the addresses needs to be read and exchanged with the data on the other address. However, since it is a serial one-by-one reading, the two data will still be read separately during the traversal. Summary of the invention

[0005] The main purpose of the present application is to propose a data processing method, device, medium and chip, which aims to solve the problem that serial processing is slow during inverse transformation in current number theory transformation, and data with storage addresses in reverse order in the data to be processed need to be read separately.

[0006] To achieve the above purpose, the present application proposes a data processing method, which includes:

[0007] Determining each storage location in each memory for storing the data to be inverse transformed;

[0008] Assigning an address code to each storage location; the address code of each storage location includes at least a prefix and a suffix, the prefix being a binary code of the number of the memory where the storage location is located, and the suffix being the last two digits of the binary code of the address number of the storage location in the memory to which it corresponds;

[0009] Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix;

[0010] Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition;

[0011] Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory;

[0012] Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition;

[0013] Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

[0014] In the embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0015] The traversal determines the inverse transformation position corresponding to each storage position of the first type partition in each memory, including:

[0016] The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

[0017] In the embodiment of the present application, the inverse transformation position corresponding to each storage position in the first type partition in each memory is determined by the following method:

[0018] If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location;

[0019] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0020] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the data processing method further includes:

[0021] Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

[0022] In an embodiment of the present application, based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory, including:

[0023] Read data in parallel from the first type partition of each memory in a cycle; wherein each cycle includes two parallel reads, and in each cycle, during the first read, data on a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second read, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first read;

[0024] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0025] In the embodiment of the present application, when data is read in parallel from the first type partition of each memory in a cycle, the data is read in order of the size of the base codes of the storage locations to be inversely transformed contained in the first type partition of each memory.

[0026] In the embodiment of the present application, within the same cycle, if the storage position to be inversely transformed read for the first time and the inversely transformed position read for the second time from the same memory are the same, data exchange is not performed;

[0027] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0028] In the embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0029] The inverse transformation position corresponding to each storage position in the second type partition of each memory is determined based on the following method:

[0030] The inverse transformation position corresponding to the storage position of any partition of two matching second-category partitions is traversed and determined in order, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0031] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the data processing method further includes:

[0032] Based on the inverse transformation position corresponding to each storage position of the second type partition in each memory, the data to be inversely transformed at two storage positions are read from each memory in parallel to perform inverse transformation processing;

[0033] Among the four storage positions read from the two second-type partitions that match each other, two storage positions in one partition and two storage positions in the other partition are inversely transformed positions.

[0034] In the embodiment of the present application, when the data to be inversely transformed at two storage locations are read from each memory in parallel, the two second-category partitions that match each other are read in order of the size of the base code of each storage location in any partition.

[0035] The present application also proposes a data processing device, comprising:

[0036] A determination module, the determination module is used to determine each storage location in each memory storing the data to be inverse transformed;

[0037] A processing module, the processing module is used to assign an address code to each storage location; the address code of each storage location at least includes a prefix and a suffix, the prefix is ​​a binary code of the number of the storage location where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in the corresponding storage location;

[0038] Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix;

[0039] Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition;

[0040] Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory;

[0041] Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition;

[0042] Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

[0043] In the embodiment of the present application, the address code of each storage location also includes a base code, the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix; the processing module is also used for:

[0044] The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

[0045] In an embodiment of the present application, the processing module is configured to determine the inverse transformation position corresponding to each storage position in the first type partition in each memory by the following method:

[0046] If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location;

[0047] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0048] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the processing module is further used to:

[0049] Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

[0050] In the embodiment of the present application, the processing module is further configured as follows:

[0051] Read data in parallel from the first type partition of each memory in a cycle; wherein each cycle includes two parallel reads, and in each cycle, during the first read, data on a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second read, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first read;

[0052] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0053] In an embodiment of the present application, the processing module is further configured to: when reading data in parallel from the first type partition of each memory in a cycle, read in order of the size of the base code of the storage location to be inverse transformed contained in the first type partition of each memory.

[0054] In the embodiment of the present application, the processing module is further configured:

[0055] In the same cycle, if the storage location to be inversely transformed read for the first time and the inversely transformed location read for the second time from the same memory are the same, no data exchange is performed;

[0056] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0057] In the embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0058] The processing module is further configured to determine the inverse transformation position corresponding to each storage position in the second type partition of each memory based on the following method:

[0059] The inverse transformation position corresponding to the storage position of any partition of two matching second-category partitions is traversed and determined in order, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0060] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the processing module is further configured to:

[0061] Based on the inverse transformation position corresponding to each storage position of the second type partition in each memory, the data to be inversely transformed at two storage positions are read from each memory in parallel to perform inverse transformation processing;

[0062] Among the four storage positions read from the two second-type partitions that match each other, two storage positions in one partition and two storage positions in the other partition are inversely transformed positions.

[0063] In the embodiment of the present application, when the data to be inversely transformed at two storage locations are read from each memory in parallel, the processing module is further configured as follows:

[0064] In two second-type partitions that match each other, the base codes of the storage locations in any one partition are read in order of size.

[0065] The present application also proposes a readable storage medium, which includes instructions. When the instructions are executed on a computing device, the computing device executes any of the above methods.

[0066] The present application also proposes a chip, comprising the data processing device described in any of the above embodiments.

[0067] In an embodiment of the present application, the storage locations in each memory are partitioned, and each partition in each memory is further divided into a first type of partition and a second type of partition. For the first type of partition, the inverse transformation positions corresponding to the storage locations contained in the first type of partition in each memory are all located in the memory where the first type of partition is located. When determining the inverse transformation positions corresponding to the storage locations in the first type of partition in each memory, all the storage locations of the first type of partition in each memory can be traversed to determine. For the second type of partition, the inverse transformation positions corresponding to the partitions contained in the second type of partition in each memory are all located in the partitions of other memories, and according to the prefixes and suffixes corresponding to the partitions, the matching relationship between the second type of partitions of each memory can be determined. After determining the matching relationship between the second type of partitions of each memory, for two partitions that match each other, it is only necessary to traverse and determine the inverse transformation position corresponding to the storage location in any one of the partitions, and the other partition does not need to be traversed and determined again. The prior art is to traverse one by one to determine the inverse transformation position corresponding to each storage position. For two storage positions that are inverse transformation positions of each other, their corresponding inverse transformation positions must be determined twice in succession. In contrast, in the embodiment of the present application, repeated determination will only occur in the first type of partition, and will not occur for the second type of partition. Therefore, the data processing method in the present application can reduce the number of repeated determinations to a certain extent when determining the inverse transformation positions corresponding to each storage position, thereby providing a basis for reducing repeated determinations during subsequent inverse transformations. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0069] Figure 1 A step diagram of a data processing method in an embodiment of the present application;

[0070] Figure 2 A module diagram of a data processing device in an embodiment of the present application;

[0071] Figure 3 A module diagram of a readable storage medium in an embodiment of the present application.

[0072] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0073] The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present application, and are not intended to limit the scope of the present application in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] Those skilled in the art know that the embodiments of the present application can be implemented as a system, device, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0075] According to the implementation manner of the present application, a data processing method, device, medium and chip are proposed.

[0076] It should be understood herein that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction rather than having any limiting meaning.

[0077] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0078] Exemplary Methods

[0079] This exemplary embodiment proposes a data processing method, which is applied to the encryption field, wherein: Figure 1 As shown, in the embodiment of the present application, the data processing method includes the following steps S100-S700:

[0080] Step S100: Determine each storage location in each memory for storing data to be inversely transformed.

[0081] Assume that the sequence length of the data to be processed during the number theory transformation is 64 and the degree of parallelism is 4, that is, there are four memories to store the calculation results of the butterfly calculation in each stage of the number theory transformation. As shown in Table 1 below, assume that the four memories 0-3 in Table 1 are the memories used for the number theory transformation of the data to be processed with a sequence length of 64, where "0-3" is the number of each memory, and the sequence length of the data to be processed is 64, that is, there will be 64 butterfly calculation results in each stage of the number theory transformation, and they are stored in four memories on average, that is, each memory provides 16 storage locations, and 0-15 in a column corresponding to each memory in Table 1 is the address number of the 16 storage locations in each memory. Therefore, based on the sequence length and degree of parallelism of the data to be transformed, the various memories and storage locations required in the inverse transformation process can be determined.

[0082] Table 1

[0083] Memory 0 Memory 1 Memory 2 Memory 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15

[0084] Step S200: assigning an address code to each storage location; the address code of each storage location includes at least a prefix and a suffix, wherein the prefix is ​​a binary code of the number of the memory where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in its corresponding memory.

[0085] As shown in Table 1 above, after the memories required for inverse transformation and the storage locations in the memories are determined, address codes are assigned to the storage locations in the memories in step S200.

[0086] In the embodiment of the present application, the address code includes two parts, the first part is the binary code of each memory number, and the second part is the binary code of the address number of each storage location in the memory where it is located.

[0087] For example, memory 0 is numbered 0, and the corresponding binary code is 00;

[0088] Memory 1 is numbered 1, and the corresponding binary code is 01;

[0089] The number of memory 2 is 2, and the corresponding binary code is 10;

[0090] The number of memory 3 is 3, and the corresponding binary code is 11.

[0091] For the storage locations in the memory, each memory includes 16 storage locations from 0 to 15, and the address numbers of the 16 storage locations are 0 to 15. When the address number of the storage location is converted into a binary code, the bit of the binary code is determined by the largest address number. For example, in the embodiment of the present application, the maximum address number is 15, and its corresponding binary code is 1111, then the bit is 4, that is, 0-15 can be converted into a 4-bit binary code, as shown in the following Table 2, which shows the address codes of each storage location in the memory 0-3:

[0092] Table 2

[0093] Address Number Memory 0 Memory 1 Memory 2 Memory 3 0 000000 010000 100000 110000 1 000001 010001 100001 110001 2 000010 010010 100010 110010 3 000011 010011 100011 110011 4 000100 010100 100100 110100 5 000101 010101 100101 110101 6 000110 010110 100110 110110 7 000111 010111 100111 110111 8 001000 011000 101000 111000 9 001001 011001 101001 111001 10 001010 011010 101010 111010 11 001011 011011 101011 111011 12 001100 011100 101100 111100 13 001101 011101 101101 111101 14 001110 011110 101110 111110 15 001111 011111 101111 111111

[0094] As shown in Table 2 above, taking the address code 000100 corresponding to the storage position of address number 4 in memory 0 as an example, the first two digits 00 are the prefix of the address code corresponding to the storage position of address number 4 in memory 0, representing that the binary code of the number of the memory where the storage position is located is 00, and the last four digits 0100 represent that the binary code of the address number of the storage position in the memory where it is located is 0100, then, the last two digits 00 of 0100 are the suffix of the address code corresponding to the storage position of address number 4 in memory 0.

[0095] Step S300: partitioning the storage locations of each memory based on the suffix, and the address codes of the storage locations of the same partition in the same memory have the same suffix.

[0096] As shown in Table 2 above, for memories 0, 1, 2, and 3, the address codes of the 16 storage locations they contain are all suffixed with 00, 01, 10, and 11. Therefore, memories 0, 1, 2, and 3 can be divided into four areas according to the suffixes. The storage location with the suffix 00 is partition 0, the storage location with the suffix 01 is partition 1, the storage location with the suffix 10 is partition 2, and the storage location with the suffix 11 is partition 3. As shown in Table 3 below:

[0097] Table 3

[0098] Partition Address Number Memory 0 Memory 1 Memory 2 Memory 3 Partition 0 0 000000 010000 100000 110000 Partition 1 1 000001 010001 100001 110001 Partition 2 2 000010 010010 100010 110010 Partition 3 3 000011 010011 100011 110011 Partition 0 4 000100 010100 100100 110100 Partition 1 5 000101 010101 100101 110101 Partition 2 6 000110 010110 100110 110110 Partition 3 7 000111 010111 100111 110111 Partition 0 8 001000 011000 101000 111000 Partition 1 9 001001 011001 101001 111001 Partition 2 10 001010 011010 101010 111010 Partition 3 11 001011 011011 101011 111011 Partition 0 12 001100 011100 101100 111100 Partition 1 13 001101 011101 101101 111101 Partition 2 14 001110 011110 101110 111110 Partition 3 15 001111 011111 101111 111111

[0099] As shown in Table 3 above, memories 0-3 each include four partitions. Taking memory 0 as an example, partition 0 includes four storage locations with address numbers 0, 4, 8, and 12, and the suffixes of the address codes corresponding to the four storage locations in partition 0 are all 00; partition 1 includes four storage locations with address numbers 1, 5, 9, and 13, and the suffixes of the address codes corresponding to the four storage locations in partition 1 are all 01; partition 2 includes four storage locations with address numbers 2, 6, 10, and 14, and the suffixes of the address codes corresponding to the four storage locations in partition 2 are all 10; partition 3 includes four storage locations with address numbers 3, 7, 11, and 15, and the suffixes of the address codes corresponding to the four storage locations in partition 3 are all 11.

[0100] Step S400: Determine the first type of partition and the second type of partition in each memory, wherein the address codes of the storage locations in the first type of partition remain unchanged after being reversed, or the storage locations represented by the reversed address codes are in the same memory; the second type of partition is other partitions in the same memory except the first type of partition.

[0101] For memory 0, the four storage locations included in partition 0 have address numbers 0, 4, 8, and 12, and the corresponding address codes are 000000, 000100, 001000, and 001100, respectively. Among them, the address codes corresponding to address numbers 0 and 12 are still in reverse order, while the address codes corresponding to address numbers 4 and 8 are in reverse order, that is, the address code corresponding to address number 4 is in reverse order to the address code corresponding to address number 8, which is still located in memory 0. Similarly, the address code corresponding to address number 8 is in reverse order to the address code corresponding to address number 4, which is still located in memory 0. Therefore, partition 0 is the first type of partition in memory 0; the storage locations corresponding to the storage locations in partitions 1, 2, and 3 are all located in other memories after the address codes are reversed, and partitions 1, 2, and 3 are the second type of partitions in memory 0.

[0102] By analogy, the first type of partition in memory 1 is partition 2, and the second type of partition includes partitions 0, 1, and 3; the first type of partition in memory 2 is partition 1, and the second type of partition includes partitions 0, 2, and 3; the first type of partition in memory 3 is partition 3, and the second type of partition includes partitions 0, 1, and 2.

[0103] As shown in the following Table 4, Table 4 shows a schematic diagram of the first type of partition and the second type of partition of each memory.

[0104] Table 4

[0105]

[0106] As shown in Table 4 above, the reverse order of the address code of each storage location in the first-class partition of each memory is itself, or the storage location of the reversed code is still the same memory. Therefore, when the data in the first-class partition of each memory is reversed, the two data to be reversed that are paired and exchanged can be read from the same memory. The storage location of the code after the reverse order of the address code of each storage location in the second-class partition of each memory is located in other memories. Therefore, when the data in the second-class partition of each memory is reversed, it is necessary to read one data to be reversed from each of the two memories to exchange the positions.

[0107] Based on this, in an embodiment of the present application, the inverse transformation positions corresponding to each storage position of the first type partition in each memory can be determined first, that is, step S500: traverse and determine the inverse transformation positions corresponding to each storage position of the first type partition in each memory.

[0108] In the embodiment of the present application, the inverse transformation positions corresponding to the storage positions included in the first type of partition in each memory may be traversed and determined respectively.

[0109] For example, as shown in Table 4 above, for memory 0, the first type of partition in memory 0 includes four storage locations, and the address codes of the four storage locations are 000000, 000100, 001000, and 001100, respectively. Therefore, the four address codes can be traversed to determine the reverse address codes corresponding to the four address codes respectively.

[0110] For example, the reverse order of 000000 is 000000, that is, the reverse order is itself, which means that the reverse transformation position of the storage location with address code 000000 in memory 0 is itself;

[0111] The reverse order of 000100 is 001000, which means that the reverse order of the storage location with address code 000100 in memory 0 is the storage location with address code 001000;

[0112] The reverse order of 001000 is 000100, which means that the reverse order of the storage location with address code 001000 in memory 0 is the storage location with address code 000100;

[0113] The reverse order of 001100 is 001100, that is, the reverse order is itself, which means that the inverse transformation position of the storage position with the address code of 001100 in memory 0 is itself.

[0114] In addition, in an embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and suffix of the address code corresponding to the storage location, and the code between the prefix and suffix of each address code is the base code, that is, the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the prefix and suffix.

[0115] For example, as shown in Table 1 above, for the address code 110011, its prefix is ​​11, the base code is 00, and the suffix is ​​11.

[0116] Based on this, for the first-class partitions in each memory, the prefixes and suffixes of the address codes of the storage locations contained in the first-class partitions in each memory are the same, and the base codes are from small to large. For example, for the address codes of the four storage locations in the first-class partition of memory 0, the prefixes are all 00, the suffixes are all 00, and the base codes are 00, 01, 10, and 11 respectively.

[0117] Therefore, when traversing to determine the inverse transformation position corresponding to each storage position of the first type partition in each memory, the inverse transformation position corresponding to each storage position can be traversed to determine in order of the base codes corresponding to each storage position contained in the first type partition in each memory.

[0118] For example, the base codes corresponding to the storage positions contained in the first type of partition in memory 0 are 00, 01, 10, and 11 respectively. Then, the inverse transformation position corresponding to each storage position can be traversed and determined in the order of the storage position base codes 00, 01, 10, and 11.

[0119] For example, as shown in the following Table 5, Table 5 shows a schematic diagram of traversing the inverse transformation positions corresponding to each storage position of the first type partition in each memory in the base coding order.

[0120] Table 5

[0121]

[0122]

[0123] As shown in Table 5 above, Addr is the base code, and Addr_inv is the base code for obtaining the inverse address code. In Table 5 above, the four memories can be traversed according to Addr=00, 01, 10, 11 to determine the inverse transformation position corresponding to each storage position contained in the first type partition in each memory.

[0124] In addition, in the embodiment of the present application, if the reverse order of the address code of any storage position is itself, the storage position itself is used as its corresponding inverse transformation position;

[0125] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0126] For example, when Addr=00 in the above Table 5, memory 0 determines the inverse transformation position of the storage position with address code 00000, the reverse address code is 00000, and the corresponding Addr_inv=00, which means that the inverse transformation position corresponding to the storage position with address code 00000 in memory 0 is itself.

[0127] For another example, when Addr=01 in the above Table 5, memory 0 determines the inverse transformation position of the storage position with address code 00010, the reverse address code is 01000, and the corresponding Addr_inv=10, which means that the address code of the inverse transformation position corresponding to the storage position with address code 00010 in memory 0 is 01000.

[0128] Similarly, the inverse transformation positions corresponding to the storage positions in the first type partitions of the memory 1, 2, and 3 can be traversed and determined respectively according to the base code size order. As shown in Table 5 above, where:

[0129] For Memory 1

[0130] The reverse order of 010010 is 010010, that is, the reverse order is itself, which means that the reverse transformation position of the storage location with address code 010010 in memory 1 is itself;

[0131] The reverse order of 010110 is 011010, which means that the reverse transformation position of the storage location with address code 010110 in memory 1 is the storage location with address code 011010;

[0132] The reverse order of 011010 is 010110, which means that the reverse transformation position of the storage location with address code 011010 in memory 1 is the storage location with address code 010110;

[0133] The reverse sequence of 011110 is 011110, that is, the reverse sequence is itself, which means that the reverse transformation position of the storage position with the address code of 011110 in memory 1 is itself.

[0134] For Memory 2

[0135] The reverse order of 100001 is 100001, that is, the reverse order is itself, which means that the reverse transformation position of the storage position with the address code of 100001 in the memory 2 is itself;

[0136] The reverse order of 100101 is 101001, which means that the reverse transformation position of the storage position with address code 100101 in memory 2 is the storage position with address code 101001;

[0137] The reverse order of 101001 is 100101, which means that the reverse transformation position of the storage position with address code 101001 in memory 2 is the storage position with address code 100101;

[0138] The reverse order of 101101 is 101101, that is, the reverse order is itself, which means that the reverse transformation position of the storage position with the address code of 101101 in the memory 2 is itself.

[0139] For Memory 3

[0140] The reverse order of 110011 is 110011, that is, the reverse order is itself, which means that the reverse transformation position of the storage position with the address code of 110011 in the memory 3 is itself;

[0141] The reverse order of 110111 is 111011, which means that the reverse transformation position of the storage position with the address code 110111 in the memory 3 is the storage position with the address code 111011;

[0142] The reverse order of 111011 is 110111, which means that the inverse transformation position of the storage position with the address code 111011 in the memory 3 is the storage position with the address code 110111;

[0143] The reverse sequence of 111111 is 111111, that is, the reverse sequence is itself, which means that the reverse transformation position of the storage position with the address code of 1111111 in the memory 3 is itself.

[0144] The above describes how to determine the inverse transformation position in the first type partition of each memory. Next, how to determine the inverse transformation position corresponding to each storage position in the second type partition is described.

[0145] Step S600: Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, match the second-class partitions in different memories to obtain a matching relationship of the second-class partitions; wherein the prefix and suffix of the address code of one partition of two matching partitions are the suffix and prefix of the address code of the other partition.

[0146] As shown in Table 4 above, for memory 0, partition 1 in its second type of partition includes four storage locations, and the address codes of the four storage locations are 000001, 000101, 001001, and 001101, respectively. It can be seen that the prefixes of the four address codes in partition 1 are all 00, and the suffixes are all 01. Then, after the four address codes are reversed, the prefix of the address code must be 10, and the suffix must be 00. It can be seen from Table 5 that the prefixes of the address codes corresponding to the storage locations in partition 0 in the second type of partition of memory 2 are all 10, and the suffixes are all 00. Compare partition 1 of memory 0 with partition 0 of memory 2, as follows:

[0147] 000001 in partition 1 of memory 0 is reversed to 100000 in partition 0 of memory 2;

[0148] 000101 in partition 1 of memory 0 is reversed to 101000 in partition 0 of memory 2;

[0149] 001001 in partition 1 of memory 0 is reversed to 100100 in partition 0 of memory 2;

[0150] 001101 in partition 1 of memory 0 is reversed to 101100 in partition 0 of memory 2.

[0151] That is, the inverse transformation positions corresponding to the four storage positions in the partition 1 of the memory 0 are the four positions in the partition 0 of the memory 2, and the partition 1 of the memory 0 matches the partition 0 of the memory 2.

[0152] Similarly, it can also be determined that partition 2 of memory 0 matches partition 0 of memory 1;

[0153] Partition 3 of memory 0 matches partition 0 of memory 3;

[0154] Partition 3 of memory 1 matches partition 2 of memory 3;

[0155] Partition 1 of memory 1 matches partition 2 of memory 2.

[0156] Therefore, according to the prefix and suffix of the storage location in each partition, the second type of partition matching relationship shown in Table 6 can be obtained:

[0157] Table 6

[0158]

[0159] As shown in Table 6 above, in the same row, two partitions with the same color are two partitions that match each other, for example, in the first row, partition 2 matches partition 0, and partition 3 matches partition 1; in the second row, partition 1 matches partition 0, and partition 3 matches partition 2; in the third row, partition 3 matches partition 0, and partition 1 matches partition 2.

[0160] After obtaining the second-class partition matching relationship, the inverse transformation position corresponding to each storage location in the second-class partition of each memory device can be determined based on the second-class partition matching relationship, that is, the following step S700: based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage location in the second-class partition of each memory device is determined, wherein only the inverse transformation position corresponding to each storage location in any one of the two second-class partitions that match each other is traversed to determine.

[0161] As shown in Table 6 above, partition 2 of memory 0 matches partition 0 of memory 1. After the address codes of the four storage locations in partition 2 of memory 0 are reversed, they must be the four locations in partition 0 of memory 1. Therefore, only by traversing to determine the inverse transformation positions corresponding to the respective storage locations in partition 2 of memory 0, or only by traversing to determine the inverse transformation positions corresponding to the respective storage locations in partition 0 of memory 1, the inverse transformation positions corresponding to the respective storage locations in partition 2 of memory 0 and partition 0 of memory 1 can be determined.

[0162] Therefore, in an embodiment of the present application, when determining the inverse transformation position corresponding to each storage position in the second type partition of each memory based on the second type partition matching relationship, it is sufficient to traverse only the inverse transformation position corresponding to each storage position in any one of the two second type partitions that match each other, thereby reducing the data reading time by half.

[0163] In the embodiment of the present application, the storage locations in each memory are partitioned, and each partition in each memory is further divided into a first type of partition and a second type of partition. For the first type of partition, the inverse transformation positions corresponding to the storage locations contained in the first type of partition in each memory are all located in the memory where the first type of partition is located. When determining the inverse transformation positions corresponding to the storage locations in the first type of partition in each memory, all the storage locations of the first type of partition in each memory can be traversed and determined. For the second type of partition, the inverse transformation positions corresponding to the partitions contained in the second type of partition in each memory are all located in the partitions of other memories, and according to the prefixes and suffixes corresponding to the partitions, the matching relationship between the second type of partitions of each memory can be determined. After determining the matching relationship between the second type of partitions of each memory, for two partitions that match each other, it is only necessary to traverse and determine the inverse transformation position corresponding to the storage position in any one of the partitions, and the other partition does not need to be traversed and determined again. The prior art is to traverse one by one to determine the inverse transformation position corresponding to each storage position. For two storage positions that are inverse transformation positions of each other, their corresponding inverse transformation positions must be determined twice in succession. In contrast, in the embodiment of the present application, repeated determination will only occur in the first type of partition, and will not occur for the second type of partition. Therefore, the data processing method in the present application can reduce the number of repeated determinations to a certain extent when determining the inverse transformation positions corresponding to each storage position, thereby providing a basis for reducing repeated determinations during subsequent inverse transformations.

[0164] In the embodiment of the present application, after the inverse transformation positions corresponding to the respective storage positions in the first type of partition and the second type of partition are determined, the inverse transformation operation can be performed.

[0165] For example, in an embodiment of the present application, an inverse transformation operation may be performed on the first type of partitions first.

[0166] In the embodiment of the present application, based on the storage locations and corresponding inverse transformation locations contained in the first type of partition of each memory, the data to be inversely transformed is read in parallel from the first type of partition of each memory.

[0167] In the embodiment of the present application, when reading data from each memory in parallel, data is read in parallel from the first type partition of each memory according to a preset cycle; wherein each cycle includes two parallel readings, and in each cycle, during the first reading, data at a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second reading, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first reading;

[0168] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0169] For example, as shown in Table 4 above, the first-class partitions of memories 0-3 each include four storage locations, that is, the storage locations to be inversely transformed in the first-class partitions of memories 0-3 are all four, so each time the data is read in parallel, the data at one storage location to be inversely transformed can be read from each memory. In addition, since the inverse transformation location corresponding to each storage location in the first-class partition is itself or in the same memory, two readings are required in one cycle, and when the data is read for the first time, the data to be inversely transformed at the storage location to be inversely transformed is read from each memory, and when the data is read for the second time, the inverse transformation data at the inverse transformation location corresponding to the inverse transformation storage location read for the first time is read.

[0170] For example, as shown in Table 5, the first time, the data to be inversely transformed at the storage positions to be inversely transformed with address codes of 000000, 010010, 100001, and 110011 in the memory 0-3 are read respectively; the second time, the inverse transformation positions corresponding to the storage positions with address codes of 000000, 010010, 100001, and 110011 are read respectively, that is, the inverse transformation data at the storage positions with address codes of 000000, 010010, 100001, and 110011 in the memory 0-3 are read respectively. It should be noted that, since the inverse transformation positions corresponding to the storage positions with address codes of 000000, 010010, 100001, and 110011 are themselves, in the same memory, the data are read from the same position twice. When the inverse transformation position is not itself, the storage positions read twice are different.

[0171] In addition, in the embodiment of the present application, when data is read in parallel from the first type partition of each memory in a cycle, the data is read in order of the size of the base code of the storage location to be inversely transformed contained in the first type partition of each memory.

[0172] For example, as shown in Table 5 above, the base codes of the storage locations to be inversely transformed in the first type of partition of each memory are 00, 01, 10, and 11, respectively. Therefore, according to the order of base codes 00, 01, 10, and 11, it can be divided into four cycles to read the corresponding data to be inversely transformed from each memory in parallel.

[0173] For example, in cycle 0, when Addr=00, the base code of the storage location to be inversely transformed is 00. As can be seen from Table 5, the address code of the storage location to be inversely transformed is 000000, and the address code of the corresponding inversely transformed location is 000000. Therefore, in cycle 0, the data at the storage locations with address codes 00000 and 000000 are read from the memory twice;

[0174] Similarly, for memory 1, the base code of the storage position to be inversely transformed is 00, the address code of the storage position to be inversely transformed is 010010, and the address code of the corresponding inversely transformed position is 010010. Therefore, in cycle 0, the data at the storage positions with address codes 010010 and 010010 are read from memory 1 twice;

[0175] For memory 2, the base code of the storage position to be inversely transformed is 00, the address code of the storage position to be inversely transformed is 100001, and the address code of the corresponding inversely transformed position is 100001. Therefore, in cycle 0, the data at the storage positions with address codes 100001 and 100001 are read twice successively;

[0176] For memory 3, the base code of the storage position to be inversely transformed is 00, the address code of the storage position to be inversely transformed is 110011, and the address code of the corresponding inversely transformed position is 110011. Therefore, in cycle 0, the data at the storage positions with address codes 110011 and 110011 are read twice in succession.

[0177] The same process is repeated until all the inverse-transformed data in the storage location to be inverse-transformed corresponding to Addr=11 are read.

[0178] In addition, in the embodiment of the present application, in the same cycle, if the storage position to be inversely transformed read for the first time and the inversely transformed position read for the second time from the same memory are the same, data exchange is not performed;

[0179] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0180] For example, in cycle 0 and cycle 3, that is, when Addr = 00, 11, the storage position to be inversely transformed and its corresponding inversely transformed position in the same memory are the same storage position, that is, the two data read twice from the same memory are the same. At this time, data exchange is not performed, that is, the data at the storage position to be inversely transformed is not changed.

[0181] For another example, in cycle 1 and cycle 2, that is, when Addr=01, 10, the storage position to be inversely transformed and its corresponding inversely transformed position read successively from the same memory are not the same storage position, that is, the two data read successively from the same memory are different. At this time, the data read from Addr is replaced by the data read from Addr_inv, that is, for the same memory, the data to be inversely transformed read from the storage position to be inversely transformed for the first time is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0182] After introducing how to perform inverse transformation processing on each data of the first type partition of each memory in parallel, next, how to perform inverse transformation processing on each data of the second type partition of each memory is introduced.

[0183] As shown in Table 6 above, Table 6 shows the matching relationship between the second-type partitions of each memory. In the embodiment of the present application, the inverse transformation position corresponding to each storage position in the second-type partition of each memory can be determined based on the matching relationship between the second-type partitions of each memory.

[0184] For example, in an embodiment of the present application, the base codes of the storage positions of any partition of two matching second-category partitions are used as the order to traverse and determine the inverse transformation position corresponding to the storage position of any partition, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0185] For example, as shown in Table 6 above, partition 2 of memory 0 matches partition 0 of memory 1. The base codes of the storage locations in partition 2 of memory 0 may be used as the order to traverse and determine the inverse transformation positions corresponding to the storage locations in partition 2 of memory 0 in partition 0 of memory 1, as shown in Table 7 below:

[0186] Table 7

[0187] Memory 0 Memory 1 000010 010000 000110 011000 001010 010100 001110 011100

[0188] Partition 1 of memory 0 matches partition 0 of memory 2. The base codes of the storage locations in partition 1 of memory 0 can be used as the order to traverse and determine the inverse transformation positions corresponding to the storage locations in partition 1 of memory 0 in partition 0 of memory 2, as shown in Table 8 below:

[0189] Table 8

[0190] Memory 0 Memory 2 000001 100000 000101 101000 001001 100100 001101 101100

[0191] Partition 3 of memory 0 matches partition 0 of memory 3. The base codes of the storage locations in partition 3 of memory 0 can be used as the order to traverse and determine the inverse transformation positions corresponding to the storage locations in partition 3 of memory 0 in partition 0 of memory 3, as shown in Table 9 below:

[0192] Table 9

[0193] Memory 0 Memory 3 000011 110000 000111 111000 001011 110100 001111 111100

[0194] Partition 3 of memory 1 matches partition 2 of memory 3. The base codes of the storage locations in partition 3 of memory 1 can be used as the order to traverse and determine the inverse transformation positions corresponding to the storage locations in partition 3 of memory 1 in partition 2 of memory 3, as shown in Table 10 below:

[0195] Table 10

[0196] Memory 1 Memory 3 010011 110010 010111 110110 011011 111010 011111 111110

[0197] Partition 1 of memory 1 matches partition 2 of memory 2. The base codes of the storage locations in partition 1 of memory 1 can be used as the order to traverse and determine the corresponding inverse transformation positions of the storage locations in partition 1 of memory 1 in partition 2 of memory 2, as shown in Table 11 below:

[0198] Table 11

[0199] Memory 1 Memory 2 010001 100010 010101 101010 011001 100110 011101 101110

[0200] Partition 3 of memory 2 matches partition 1 of memory 3. The base codes of the storage locations in partition 3 of memory 2 can be used as the order to traverse and determine the inverse transformation positions corresponding to the storage locations in partition 3 of memory 2 in partition 1 of memory 3, as shown in Table 12 below:

[0201] Table 12

[0202] Memory 2 Memory 3 100011 110001 100111 111001 101011 110101 101111 111101

[0203] As shown in Tables 7-12 above, the matching relationship between the inverse transformation positions in each storage location included in the second type partition of each memory is shown.

[0204] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the data to be inversely transformed can be read in parallel from each memory based on the inverse transformation position corresponding to each storage position in the second type partition in each memory to perform inverse transformation processing;

[0205] Each time when the inverse transformation data is read in parallel from each memory, every two memories form a pair, and the two storage positions read from the two memories of the same pair are inverse transformation positions of each other, and different pairs contain different memories.

[0206] For example, as shown in Table 7 and Table 12 above, each table involves two memories, that is, a pair of memories, and the storage positions contained in the two memories in each table are inverse transformation positions of each other. Therefore, the data to be inversely transformed can be read in parallel from the storage positions in each memory according to the above Tables 7-12.

[0207] For example, in the first stage, memory 0 and memory 2 are a pair, and memory 1 and memory 3 are another pair. According to this pairing, the storage locations in partition 1 of memory 0, partition 0 of memory 2, partition 3 of memory 1, and partition 2 of memory 3 can be read.

[0208] In the second stage, memory 1 and memory 2 are the first pair, and memory 0 and memory 3 are another pair. According to this pairing, the storage locations in partition 1 of memory 1, partition 2 of memory 2, partition 3 of memory 0, and partition 0 of memory 3 can be read.

[0209] In the third stage, memory 0 and memory 1 are the first pair, and memory 2 and memory 3 are another pair. According to this pairing, the storage locations in partition 2 of memory 0, partition 0 of memory 1, partition 3 of memory 2, and partition 11 of memory 3 can be read.

[0210] Through the above three stages, all the data to be inversely transformed at the storage locations contained in the second type of partitions in all memories can be read.

[0211] In addition, it should be noted that the order of the above three stages is not limited.

[0212] In the embodiment of the present application, when the data to be inversely transformed at two storage locations are read from each memory in parallel, the two second-category partitions that match each other are read in order of the size of the base code of each storage location in any partition.

[0213] For example, taking the above three stages as an example, in the first stage, the base code is read in parallel in order of size, as shown in Table 13 below:

[0214] Table 13

[0215]

[0216]

[0217] In the second stage, the data is read in parallel in the order of base code size, as shown in Table 14 below:

[0218] Table 14

[0219] Memory 0 Memory 2 Memory 1 Memory 3 Addr = 0 010001 100010 000011 110000 Addr = 1 010101 101010 000111 111000 Addr = 2 011001 100110 001011 110100 Addr = 3 011101 101110 001111 111100

[0220] In the third stage, the data is read in parallel in the order of base code size, as shown in Table 15 below:

[0221] Table 15

[0222] Memory 0 Memory 2 Memory 1 Memory 3 Addr = 0 000010 010000 100011 110001 Addr = 1 000110 011000 100111 111001 Addr = 2 001010 010100 101011 110101 Addr = 3 001110 011100 101111 111101

[0223] Taking the first stage as an example, when Addr=0, the data at the storage location with the address code of 000001 is read from the memory 0, the data at the storage location with the address code of 100000 is read from the memory 2, the data at the storage location with the address code of 010011 is read from the memory 1, and the data at the storage location with the address code of 110010 is read from the memory 3. The data read from the memory 0 is exchanged with the data read from the memory 2, and the data read from the memory 1 is exchanged with the data read from the memory 3.

[0224] After all three stages are processed, the inverse transformation process of the second type of partitions in each memory is completed.

[0225] In the embodiment of the present application, the storage locations in each memory are partitioned, and each partition in each memory is further divided into a first type of partition and a second type of partition. For the first type of partition, the inverse transformation positions corresponding to the storage locations contained in the first type of partition in each memory are all located in the memory where the first type of partition is located. When determining the inverse transformation positions corresponding to the storage locations in the first type of partition in each memory, all the storage locations of the first type of partition in each memory can be traversed and determined. For the second type of partition, the inverse transformation positions corresponding to the partitions contained in the second type of partition in each memory are all located in the partitions of other memories, and according to the prefixes and suffixes corresponding to the partitions, the matching relationship between the second type of partitions of each memory can be determined. After determining the matching relationship between the second type of partitions of each memory, for two partitions that match each other, it is only necessary to traverse and determine the inverse transformation position corresponding to the storage position in any one of the partitions, and the other partition does not need to be traversed and determined again. The prior art is to traverse one by one to determine the inverse transformation position corresponding to each storage position. For two storage positions that are inverse transformation positions of each other, their corresponding inverse transformation positions must be determined twice in succession. In contrast, in the embodiment of the present application, repeated determination will only occur in the first type of partition, and will not occur for the second type of partition. Therefore, the data processing method in the present application can reduce the number of repeated determinations to a certain extent when determining the inverse transformation positions corresponding to each storage position, thereby providing a basis for reducing repeated determinations during subsequent inverse transformations.

[0226] Exemplary Devices

[0227] like Figure 2 As shown, the present application also proposes a data processing device 100, which includes:

[0228] A determination module 110, the determination module 110 is used to determine each storage location in each memory storing the data to be inverse transformed;

[0229] A processing module 120, the processing module 120 is used to assign an address code to each storage location; the address code of each storage location at least includes a prefix and a suffix, the prefix is ​​a binary code of the number of the storage location where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in the corresponding storage location;

[0230] Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix;

[0231] Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition;

[0232] Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory;

[0233] Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition;

[0234] Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

[0235] In the embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix; the processing module 120 is also used for:

[0236] The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

[0237] In the embodiment of the present application, the processing module 120 is configured to determine the inverse transformation position corresponding to each storage position in the first type partition in each memory by the following method:

[0238] If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location;

[0239] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0240] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the processing module 120 is further used to:

[0241] Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

[0242] In the embodiment of the present application, the processing module 120 is further configured to:

[0243] Read data in parallel from the first type partition of each memory in a cycle; wherein each cycle includes two parallel reads, and in each cycle, during the first read, data on a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second read, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first read;

[0244] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0245] In an embodiment of the present application, the processing module 120 is further configured to read data in parallel from the first type partition of each memory in a cycle, and read in order of the size of the base code of the storage location to be inverse transformed contained in the first type partition of each memory.

[0246] In the embodiment of the present application, the processing module 120 is further configured:

[0247] In the same cycle, if the storage location to be inversely transformed read for the first time and the inversely transformed location read for the second time from the same memory are the same, no data exchange is performed;

[0248] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0249] In the embodiment of the present application, the address code of each storage location also includes a base code, and the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0250] The processing module 120 is further configured to determine the inverse transformation position corresponding to each storage position in the second type partition of each memory based on the following method:

[0251] The inverse transformation position corresponding to the storage position of any partition of two matching second-category partitions is traversed and determined in order, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0252] In the embodiment of the present application, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the processing module 120 is further configured to:

[0253] Based on the inverse transformation position corresponding to each storage position of the second type partition in each memory, the data to be inversely transformed at two storage positions are read from each memory in parallel to perform inverse transformation processing;

[0254] Among the four storage positions read from the two second-type partitions that match each other, two storage positions in one partition and two storage positions in the other partition are inversely transformed positions.

[0255] In the embodiment of the present application, when the data to be inversely transformed at two storage locations are read from each memory in parallel, the processing module 120 is further configured as follows:

[0256] In two second-type partitions that match each other, the base codes of the storage locations in any one partition are read in order of size.

[0257] The specific implementation methods of each module in the data processing device 100 proposed in the embodiment of the present application refer to the various embodiments of the above-mentioned data processing method, which will not be described one by one here.

[0258] In the embodiment of the present application, the storage locations in each memory are partitioned by the processing module 120, and each partition in each memory is further divided into a first type of partition and a second type of partition. For the first type of partition, the inverse transformation positions corresponding to the storage locations contained in the first type of partition in each memory are all located in the memory where the first type of partition is located. When determining the inverse transformation positions corresponding to the storage locations in the first type of partition in each memory, all the storage locations of the first type of partition in each memory can be traversed and determined. For the second type of partition, the inverse transformation positions corresponding to the partitions contained in the second type of partition of each memory are all located in the partitions of other memories, and according to the prefixes and suffixes corresponding to the partitions, the matching relationship between the second type of partitions of each memory can be determined. After determining the matching relationship between the second type of partitions of each memory, for two partitions that match each other, it is only necessary to traverse and determine the inverse transformation position corresponding to the storage location in any one of the partitions, and the other partition does not need to be traversed and determined again. The prior art is to traverse one by one to determine the inverse transformation position corresponding to each storage position. For two storage positions that are inverse transformation positions of each other, their corresponding inverse transformation positions must be determined twice in succession. In contrast, in the embodiment of the present application, repeated determination will only occur in the first type of partition, and will not occur for the second type of partition. Therefore, the data processing method in the present application can reduce the number of repeated determinations to a certain extent when determining the inverse transformation positions corresponding to each storage position, thereby providing a basis for reducing repeated determinations during subsequent inverse transformations.

[0259] Exemplary Media

[0260] After introducing the method, medium and system of the exemplary embodiments of the present application, next, reference is made to Figure 3 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 3, the computer-readable storage medium shown is a CD 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by a processor, the steps described in the above method implementation are implemented, for example, determining each storage location in each memory for storing the data to be inversely transformed; assigning an address code to each storage location; the address code of each storage location includes at least a prefix and a suffix, the prefix being a binary code of the number of the memory where the storage location is located, and the suffix being the last two digits of the binary code of the address number of the storage location in the memory to which it corresponds; partitioning the storage location of each memory based on the suffix, and the address codes of the storage locations of the same partition in the same memory have the same suffix; determining a first-class partition and a second-class partition in each memory, and the address codes of the storage locations in the first-class partition are the same. The reverse order is itself, or the storage location represented by the address code after the reverse order is in the same memory; the second-class partition is the other partitions in the same memory except the first-class partition; traverse to determine the inverse transformation position corresponding to each storage location of the first-class partition in each memory; based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, match each second-class partition in different memories to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two matching partitions are the suffix and prefix of the address code of the other partition; based on the second-class partition matching relationship, determine the inverse transformation position corresponding to each storage location in the second-class partition of each memory, wherein only traverse to determine the inverse transformation position corresponding to each storage location in any one of the two matching second-class partitions. The specific implementation method of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0261] Exemplary Chips

[0262] After introducing the method, circuit and medium of the exemplary embodiment of the present application, next, the chip of the exemplary embodiment of the present application is introduced.

[0263] In an embodiment of the present application, a chip is provided, including the data processing device described in any of the above embodiments. Since the chip includes the data processing device described in any of the above embodiments, all the beneficial effects of the data processing device described in the above embodiments are not described in detail here.

[0264] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0265] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0266] Through the above description, the embodiments of the present application provide the following technical solutions, but are not limited thereto:

[0267] 1. A data processing method, comprising:

[0268] Determining each storage location in each memory for storing the data to be inverse transformed;

[0269] Assigning an address code to each storage location; the address code of each storage location includes at least a prefix and a suffix, the prefix being a binary code of the number of the memory where the storage location is located, and the suffix being the last two digits of the binary code of the address number of the storage location in the memory to which it corresponds;

[0270] Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix;

[0271] Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition;

[0272] Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory;

[0273] Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition;

[0274] Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

[0275] 2. In the data processing method as described in technical solution 1, the address code of each storage location also includes a base code, the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0276] The traversal determines the inverse transformation position corresponding to each storage position of the first type partition in each memory, including:

[0277] The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

[0278] 3. In the data processing method of technical solution 1 or 2, the inverse transformation position corresponding to each storage position in the first type partition in each memory is determined by the following method:

[0279] If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location;

[0280] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0281] 4. The data processing method according to any one of technical solutions 1 to 3, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the data processing method further includes:

[0282] Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

[0283] 5. The data processing method according to any one of technical solutions 1 to 4, based on each storage location and corresponding inverse transformation location contained in the first type partition of each memory, reads the data to be inversely transformed from the first type partition of each memory in parallel, comprising:

[0284] Read data in parallel from the first type partition of each memory in a cycle; wherein each cycle includes two parallel reads, and in each cycle, during the first read, data on a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second read, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first read;

[0285] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0286] 6. In the data processing method as described in any one of technical solutions 1-5, when reading data in parallel from the first type partition of each memory according to a cycle, the data is read in order of the size of the base code of the storage position to be inverse transformed contained in the first type partition of each memory.

[0287] 7. In the data processing method according to any one of technical solutions 1 to 6, in the same cycle, if the storage position to be inversely transformed read for the first time and the inversely transformed position read for the second time from the same memory are the same, no data exchange is performed;

[0288] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0289] 8. In the data processing method as described in any one of technical solutions 1 to 7, the address code of each storage location also includes a base code, the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0290] The inverse transformation position corresponding to each storage position in the second type partition of each memory is determined based on the following method:

[0291] The inverse transformation position corresponding to the storage position of any partition of two matching second-category partitions is traversed and determined in order, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0292] 9. The data processing method according to any one of technical solutions 1 to 8, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the data processing method further comprises:

[0293] Based on the inverse transformation position corresponding to each storage position of the second type partition in each memory, the data to be inversely transformed at two storage positions are read from each memory in parallel to perform inverse transformation processing;

[0294] Among the four storage positions read from the two second-type partitions that match each other, two storage positions in one partition and two storage positions in the other partition are inversely transformed positions.

[0295] 10. In the data processing method as described in any one of technical solutions 1-9, when the data to be inversely transformed in two storage locations are read from each memory in parallel, the two second-category partitions that match each other are read in the order of the size of the base code of each storage location in any partition.

[0296] 11. A data processing device, comprising:

[0297] A determination module, the determination module is used to determine each storage location in each memory storing the data to be inverse transformed;

[0298] A processing module, the processing module is used to assign an address code to each storage location; the address code of each storage location at least includes a prefix and a suffix, the prefix is ​​a binary code of the number of the storage location where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in the corresponding storage location;

[0299] Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix;

[0300] Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition;

[0301] Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory;

[0302] Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition;

[0303] Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

[0304] 12. As described in technical solution 11, the data processing device, the address code of each storage location also includes a base code, the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix; the processing module is also used to:

[0305] The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

[0306] 13. As the data processing device of technical solution 11 or 12, the processing module is configured to determine the inverse transformation position corresponding to each storage position in the first type partition in each memory by the following method:

[0307] If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location;

[0308] If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

[0309] 14. The data processing device according to any one of technical solutions 11 to 13, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the processing module is further used to:

[0310] Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

[0311] 15. The data processing device according to any one of technical solutions 11 to 14, wherein the processing module is further configured to:

[0312] Read data in parallel from the first type partition of each memory in a cycle; wherein each cycle includes two parallel reads, and in each cycle, during the first read, data on a storage position to be inversely transformed is read in parallel from the first type partition of each memory, and during the second read, data is read in parallel from the inverse transformation position corresponding to the storage position to be inversely transformed read in each memory during the first read;

[0313] This continues until all storage locations to be inversely transformed in the first type of partition of each memory are traversed.

[0314] 16. In the data processing device as described in any one of technical solutions 11-15, the processing module is also configured to: when reading data in parallel from the first type partition of each memory according to a cycle, read in order of the size of the base code of the storage position to be inverse transformed contained in the first type partition of each memory.

[0315] 17. The data processing device according to any one of technical solutions 11 to 16, wherein the processing module is further configured to:

[0316] In the same cycle, if the storage location to be inversely transformed read for the first time and the inversely transformed location read for the second time from the same memory are the same, no data exchange is performed;

[0317] If they are different, the data to be inversely transformed at the storage position to be inversely transformed is replaced by the inversely transformed data read from the inversely transformed position for the second time.

[0318] 18. The data processing device as described in any one of technical solutions 11 to 17, wherein the address code of each storage location further includes a base code, the base code of each storage location is located between the prefix and the suffix of the address code corresponding to the storage location, and the base code of each storage location is the binary code of the address number of the storage location in the memory excluding the suffix;

[0319] The processing module is further configured to determine the inverse transformation position corresponding to each storage position in the second type partition of each memory based on the following method:

[0320] The inverse transformation position corresponding to the storage position of any partition of two matching second-category partitions is traversed and determined in order, wherein the base codes of the two storage positions of the inverse transformation positions are in reverse order.

[0321] 19. According to the data processing device of any one of technical solutions 11 to 18, after determining the inverse transformation position corresponding to each storage position in the second type partition in each memory, the processing module is further configured to:

[0322] Based on the inverse transformation position corresponding to each storage position of the second type partition in each memory, the data to be inversely transformed at two storage positions are read from each memory in parallel to perform inverse transformation processing;

[0323] Among the four storage positions read from the two second-type partitions that match each other, two storage positions in one partition and two storage positions in the other partition are inversely transformed positions.

[0324] 20. According to any one of technical solutions 11 to 19, when the data to be inversely transformed in two storage locations are read from each memory in parallel, the processing module is further configured to:

[0325] In two second-type partitions that match each other, the base codes of the storage locations in any one partition are read in order of size.

[0326] 21. A readable storage medium comprising instructions, which, when executed on a computing device, enables the computing device to execute a data processing apparatus as described in any one of technical solutions 11-20.

[0327] 22. A chip, comprising a data processing device as described in any one of technical solutions 11-20.

Claims

1. A data processing method, comprising: Determining each storage location in each memory for storing the data to be inverse transformed; Assign address codes to each storage location; The address code of each storage location at least includes a prefix and a suffix, wherein the prefix is ​​a binary code of the number of the storage location where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in the corresponding storage location; Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix; Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition; Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory; Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition; Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

2. The data processing method according to claim 1, wherein the address code of each storage location further comprises a base code, the base code of each storage location is located between a prefix and a suffix of the address code corresponding to the storage location, and the base code of each storage location is a binary code of the address number of the storage location in the memory excluding the suffix; The traversal determines the inverse transformation position corresponding to each storage position of the first type partition in each memory, including: The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

3. The data processing method according to claim 2, wherein the inverse transformation position corresponding to each storage position in the first type partition in each memory is determined by the following method: If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location; If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

4. The data processing method according to claim 2, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the data processing method further comprises: Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

5. A data processing device, comprising: A determination module, the determination module is used to determine each storage location in each memory storing the data to be inverse transformed; A processing module, the processing module is used to assign an address code to each storage location; the address code of each storage location at least includes a prefix and a suffix, the prefix is ​​a binary code of the number of the storage location where the storage location is located, and the suffix is ​​the last two digits of the binary code of the address number of the storage location in the corresponding storage location; Partitioning the storage locations of each memory based on the suffix, the address codes of the storage locations of the same partition in the same memory have the same suffix; Determine a first-class partition and a second-class partition in each memory, wherein the address codes of each storage location in the first-class partition are in reverse order of themselves, or the storage locations represented by the address codes after reverse order are in the same memory; and the second-class partition is other partitions in the same memory except the first-class partition; Traversing and determining the inverse transformation position corresponding to each storage position of the first type partition in each memory; Based on the prefix and suffix in the address code of each storage location in the second-class partition of each memory, the second-class partitions in different memories are matched to obtain a second-class partition matching relationship; wherein the prefix and suffix of the address code of one of the two partitions that match each other are the suffix and prefix of the address code of the other partition; Based on the second-class partition matching relationship, the inverse transformation position corresponding to each storage position in the second-class partition of each memory is determined, wherein only the inverse transformation position corresponding to each storage position in any one of the two second-class partitions that match each other is traversed to determine.

6. The data processing device according to claim 5, wherein the address code of each storage location further comprises a base code, the base code of each storage location is located between a prefix and a suffix of the address code corresponding to the storage location, and the base code of each storage location is a binary code of the address number of the storage location in the memory excluding the suffix; the processing module is further used for: The inverse transformation position corresponding to each storage position is determined by traversing in order of the base codes corresponding to each storage position included in the first type partition in each memory.

7. The data processing device according to claim 6, wherein the processing module is configured to determine the inverse transformation position corresponding to each storage position in the first type partition in each memory by the following method: If the address code of any storage location is in reverse order to itself, then the storage location itself is used as its corresponding inverse transformation location; If the reverse order of the address code of any storage position is different from itself, the storage position corresponding to the reversed address code is used as its corresponding inverse transformation position.

8. The data processing device according to claim 6, after determining the inverse transformation position corresponding to each storage position included in the first type partition in each memory, the processing module is further used to: Based on each storage location and the corresponding inverse transformation location contained in the first type partition of each memory, the data to be inversely transformed is read in parallel from the first type partition of each memory.

9. A readable storage medium comprising instructions, which, when executed on a computing device, causes the computing device to execute the data processing apparatus according to any one of claims 5 to 8.

10. A chip, comprising the data processing device according to any one of claims 5 to 8.

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