Matrix preprocessing method and system for static analysis of semiconductor device structures

Abstract

The present application belongs to the field of matrix operations, and specifically discloses a matrix preprocessing method, system and device, the method comprising: converting the finite element mesh corresponding to the sparse matrix into a graph structure; simplifying the graph structure by using a heavy edge matching algorithm to obtain a coarsened graph structure; dividing the coarsened graph structure into multiple subgraphs by a direct partitioning algorithm; refining and enlarging each of the divided subgraphs by a vertex splitting and partition refinement algorithm to obtain multiple refined graphs; mapping the sparse matrix accordingly with reference to multiple refined graphs to obtain multiple partitioned matrices; reducing and sorting each partition matrix by a multi-layer nested decomposition paradigm algorithm to obtain a rearranged matrix of multiple partitions; the rearranged matrix of the multiple partitions is used for parallel decomposition and solution to realize the solution of the sparse matrix. Through the present application, the limitations of the existing preprocessing methods, such as large amount of calculation and difficulty in parallelization, are overcome, providing support for efficient solution of large-scale matrices.

Description

Technical Field

[0001] The present application belongs to the field of matrix operations, and more specifically, relates to a matrix preprocessing method and system suitable for static analysis of semiconductor device structures. Background Art

[0002] In the static analysis simulation process of the modern semiconductor industry in CAE, it is often necessary to solve the sparse matrix corresponding to the finite element mesh. These matrices are not only huge in size, but also have a large number of zero matrix element values. If the traditional dense matrix solution algorithm is used, the time of invalid calculation will be greatly increased. Therefore, an efficient sparse matrix solution algorithm needs to preprocess the matrix structure, that is, adjust the arrangement of non-zero elements in the matrix before solving, so as to accelerate the matrix solution more efficiently.

[0003] At present, the existing technology often performs incomplete LU (ILU) decomposition on sparse matrices for preprocessing. However, ILU decomposition preprocessing for large-scale matrices often consumes a lot of computing time and storage space, and further improvement is needed. In addition, solving the calculation after ILU decomposition preprocessing involves a large number of forward / backward substitution operations, which makes parallel computing difficult to achieve. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of this application is to provide a matrix preprocessing method, system and equipment, which is intended to solve the problems of a large amount of invalid calculation time, unnecessary consumption of storage space and difficulty in implementing parallel calculation when decomposing sparse matrices in existing finite element grids.

[0005] To achieve the above objectives, in a first aspect, the present application provides a matrix preprocessing method, wherein the matrix is ​​a sparse matrix corresponding to a finite element mesh, and the method comprises:

[0006] Convert the finite element mesh corresponding to the sparse matrix into a graph structure;

[0007] The graph structure is simplified by using a heavy edge matching algorithm to obtain a coarsened graph structure;

[0008] Dividing the coarsened graph structure into a plurality of subgraphs by a direct partitioning algorithm;

[0009] Each subgraph after division is refined and enlarged through vertex splitting and partition refinement algorithm to obtain multiple refined graphs;

[0010] Mapping the sparse matrix accordingly with reference to the multiple refined graphs to obtain multiple partitioned matrices;

[0011] Each partition matrix is ​​sorted by reducing filling through a multi-layer nested decomposition paradigm algorithm to obtain a rearranged matrix of multiple partitions; the rearranged matrices of the multiple partitions are used for parallel decomposition and solution to realize the solution of the sparse matrix.

[0012] The preprocessing of the matrix in this application includes: obtaining the corresponding partition matrix by coarsening, dividing, refining and mapping the corresponding graph structure, and then rearranging the partition matrix to concentrate the non-zero elements on the diagonal, generating different concentrated matrix blocks with similar sizes for easy subsequent calculations. Through the above operations, the structure of the sparse matrix is ​​optimized, the condition number of the matrix is ​​reduced, and the stability of the matrix solution calculation process is improved. At the same time, the arrangement of the non-zero elements of the concentrated matrix after rearrangement improves the memory access command rate, and combined with the parallel calculation after block division, the efficiency of matrix solution is improved together. The flexibility and easy parallelism of the block graph rearrangement overcome the limitations of the existing preprocessing methods that are large in calculation amount and difficult to parallelize, and provide support for the efficient solution of large-scale sparse matrices in finite element grids.

[0013] In a possible implementation, the method further includes decomposing and solving the rearrangement matrices of the multiple partitions in parallel.

[0014] In a possible implementation, converting a finite element mesh corresponding to the sparse matrix into a graph structure includes:

[0015] Each unit in the finite element mesh is converted into a vertex of the graph, and the shared faces or shared edges between the units are converted into edges in the graph to obtain the corresponding graph structure;

[0016] or

[0017] The nodes of each unit in the finite element mesh are converted into vertices of the graph, and the connections between the nodes are converted into edges in the graph to obtain the corresponding graph structure.

[0018] In a possible implementation, the graph structure is simplified by using a heavy edge matching algorithm to obtain a coarsened graph structure, including:

[0019] Accessing vertices in the graph structure in random order through a randomization algorithm, matching and merging the vertices with adjacent vertices of edges whose weights are greater than a weight threshold, and setting the weight of the merged new vertex to the sum of the weights of the two vertices before the merge;

[0020] The edges associated with the two vertices before merging are used as the edges associated with the new vertex. If any of the associated edges is connected to the two vertices before merging, the weight of this edge is set to the sum of the weights of the remaining associated edges.

[0021] Repeat the above-mentioned vertex and edge merging process to continuously reduce the number of vertices of the graph structure until the number of vertices of the obtained new graph structure reaches a preset vertex number threshold, and use the finally obtained graph structure as the coarsened graph structure.

[0022] In a possible implementation, the coarsened graph structure is divided into a plurality of subgraphs by a direct partitioning algorithm, including:

[0023] When divided into two subgraphs, the spectral bisection method is used to divide the coarsened graph structure into multiple subgraphs;

[0024] When divided into more than two subgraphs, the Kernighan-Lin algorithm is used to divide the coarsened graph structure into multiple subgraphs.

[0025] In a possible implementation, each subgraph after division is refined and enlarged by vertex splitting and partition refinement algorithm to obtain multiple refined graphs, including:

[0026] Split the vertex pairs in the subgraph and project the vertex pairs into the refined graph of the same partition;

[0027] After each projection assignment iteration, all vertices in each refined graph are checked in random order, and if a vertex is a boundary vertex, it is moved between different partitions of the refined graph so that each refined graph partition has the same weight.

[0028] In a possible implementation, the sparse matrix is ​​mapped accordingly with reference to the refinement graph to obtain multiple partitioned matrices, including:

[0029] With reference to the mapping relationship between the refinement graph and the finite element mesh, the sparse matrix corresponding to the finite element mesh is mapped so that the sparse matrix also produces a corresponding partitioning effect, thereby obtaining a matrix of multiple partitions.

[0030] In a possible implementation, each partition matrix is ​​sorted by reducing the filling through a multi-layer nested decomposition paradigm algorithm to obtain a rearrangement matrix of multiple partitions, including:

[0031] Determine a graph structure corresponding to each partition matrix; the graph structure corresponds to a refined graph before mapping;

[0032] Finding a minimum vertex cover in a graph structure corresponding to each partition matrix, wherein the minimum vertex cover is a set of vertices, and each edge in the partition matrix has at least one vertex in the minimum vertex cover;

[0033] Using the minimum vertex cover as a vertex separator, removing the vertex separator, and dividing the corresponding graph structure into two unconnected subgraphs;

[0034] Continue to search for vertex separators in unconnected subgraphs and continue to split until the number of vertices included in the split subgraph is less than a preset value;

[0035] The graph structure of the reference partition matrix is ​​sorted in the order of non-connected subgraphs, vertex separators, non-adjacent subgraphs obtained by dividing each non-adjacent subgraph, and vertex separators, so that adjacent nodes in the graph structure of the partition matrix have adjacent numbers, so that non-zero elements in the partition matrix are arranged continuously, reducing the proportion of zero elements between non-zero elements, and obtaining a corresponding rearrangement matrix.

[0036] In a second aspect, the present application provides a matrix preprocessing system, wherein the matrix is ​​a sparse matrix corresponding to a finite element mesh, and the system comprises:

[0037] The mesh acquisition conversion module is used to convert the finite element mesh corresponding to the sparse matrix into a graph structure;

[0038] A coarsening and shrinking module is used to simplify the graph structure by using a heavy edge matching algorithm to obtain a coarsened graph structure;

[0039] A partitioning module, used for partitioning the coarsened graph structure into a plurality of subgraphs by a direct partitioning algorithm;

[0040] A refinement and enlargement module is used to refine and enlarge each subgraph after division through vertex splitting and partition refinement algorithm to obtain multiple refined graphs;

[0041] A matrix rearrangement module is used to map the sparse matrix accordingly with reference to the multiple refined graphs to obtain multiple partitioned matrices; each partition matrix is ​​sorted by reducing the filling through a multi-layer nested decomposition normal form algorithm to obtain a rearranged matrix of multiple partitions; the rearranged matrices of the multiple partitions are used for parallel decomposition and solution to realize the solution of the sparse matrix.

[0042] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0043] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0044] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0045] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0046] In general, the above technical solutions conceived by the present application have at least the following beneficial effects compared with the prior art:

[0047] The present application provides a matrix preprocessing method, system and device, which obtains the corresponding partition matrix by coarsening, dividing, refining and mapping the corresponding graph structure, and then rearranges the partition matrix to concentrate the non-zero elements to the diagonal, generating different concentrated matrix blocks with similar sizes, which is convenient for subsequent calculations; then combines ILU decomposition and solution operations to optimize the structure of the sparse matrix. Through the above operations, the structure of the sparse matrix is ​​optimized, the condition number of the matrix is ​​reduced, and the stability of the matrix solution calculation process is improved. At the same time, the arrangement of the non-zero elements of the concentrated matrix after rearrangement improves the memory access command rate, and combined with the parallel calculation after block division, the efficiency of matrix solution is improved together. The flexibility and easy parallelism of the rearrangement of the block graph overcome the limitations of the existing preprocessing methods that are large in calculation amount and difficult to parallelize, and provide support for the efficient solution of large-scale sparse matrices in finite element grids. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flow chart of a matrix preprocessing method provided in an embodiment of the present application;

[0049] Figure 2 is a flow chart of another matrix preprocessing method provided in an embodiment of the present application;

[0050] Figure 3 is a schematic diagram of matrix rearrangement provided in an embodiment of the present application;

[0051] Figure 4 This is a comparison diagram of the effects before and after matrix preprocessing provided in the embodiment of the present application;

[0052] Figure 5 is a matrix preprocessing system architecture diagram provided in an embodiment of the present application;

[0053] Figure 6 It is an architectural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0056] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0057] First, the technical terms involved in the embodiments of the present application are introduced.

[0058] (1) Sparse matrix

[0059] In a matrix, if the number of elements with a value of 0 is much greater than the number of non-zero elements, and the distribution of non-zero elements is irregular, the matrix is ​​called a sparse matrix.

[0060] (2) Finite element mesh

[0061] Use finite element analysis software to build predictive computational models of real-world scenarios. When using finite element analysis software, a finite element mesh is used to divide the computer-aided design model that represents the material part that needs to be simulated into many smaller domains, which we call cells. Then a set of equations are solved on these cells. These equations approximate the required control equations through a set of polynomial functions defined on each cell. As the mesh is continuously refined, these cells become smaller and smaller, making the solution closer and closer to the real solution.

[0062] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0063] Figure 1 is a flow chart of the matrix preprocessing method provided in the embodiment of the present application; Figure 1 As shown, the following steps are included:

[0064] Step S101, converting the finite element mesh corresponding to the sparse matrix into a graph structure;

[0065] Step S102, simplifying the graph structure using a heavy edge matching algorithm to obtain a coarsened graph structure;

[0066] Step S103, dividing the coarsened graph structure into multiple subgraphs by a direct partitioning algorithm;

[0067] Step S104, refining and enlarging each of the divided subgraphs through vertex splitting and partition refinement algorithms to obtain multiple refined graphs;

[0068] Step S105, mapping the sparse matrix accordingly with reference to the multiple refined graphs to obtain multiple partitioned matrices;

[0069] Step S106, reducing and sorting each partition matrix by a multi-layer nested decomposition normal form algorithm to obtain a rearranged matrix of multiple partitions; the rearranged matrices of multiple partitions are used for parallel decomposition and solving to realize solving the sparse matrix.

[0070] It should be noted that the present application rearranges the divided matrix blocks through a multi-layer nested decomposition paradigm algorithm. By renumbering the graph nodes so that adjacent nodes in the graph have adjacent numbers, the features of the adjacent nodes are stored continuously in the main memory, thereby improving the memory access hit rate. The continuous numbering of adjacent nodes is reflected in the matrix arrangement as the continuous arrangement of non-zero elements, that is, the non-zero elements are concentrated to reduce the proportion of zero elements between non-zero elements. It can be understood that the graph here refers to the refined graph before mapping. Here, the graph corresponding to each partition matrix is ​​the partition in the previous refined graph. In the matrix rearrangement stage, it is mainly to operate on each individual partition, find the vertex separator in a single partition, divide it into smaller subgraphs, and then arrange them to achieve the rearrangement of the non-zero elements in a single partition.

[0071] The matrix preprocessing method provided in this application can greatly optimize the matrix structure, realize parallel computing, and improve the efficiency of matrix solving.

[0072] In a more specific embodiment, referring to Figure 2 , the present application provides a matrix preprocessing method based on finite element mesh, comprising the following steps:

[0073] S1. Obtain the finite element mesh generated in the CAE software.

[0074] In the process of finite element simulation in CAE software, such as using the finite element method for structural static analysis, it is usually necessary to derive and solve a linear equation system from the finite element mesh. This process usually requires iterative calculation, which will produce a large sparse matrix. This application is to preprocess the sparse matrix to improve the efficiency of matrix solving. In other embodiments, this solution can also be used for sparse matrix preprocessing in other fields, which is not limited here.

[0075] S2. Convert the finite element mesh into a graph structure to obtain the original graph.

[0076] Converting a finite element mesh into a graph structure can usually be done in two ways: 1. Dual graph, converting each unit in the finite element mesh into a vertex of the graph, and converting the shared faces or edges between units into edges in the graph; 2. Node graph, converting the nodes of each unit in the finite element mesh into vertices of the graph, and converting the connections between nodes into edges in the graph; at the same time, recording the weight information of each point and each edge to form the original graph structure. The most commonly used is the node graph, which can directly apply many graph theory algorithms using the structure of the node graph and well demonstrate the connectivity of the mesh.

[0077] S3. The vertices are merged and coarsened through the heavy edge matching scheme and the original graph is reduced to obtain a coarsened graph.

[0078] When the graph is coarsened and reduced, it is necessary to find the maximum matching edge in the graph and collapse the vertices on each matching edge together, so as to produce a coarsening and reduction effect on the graph to the greatest extent. In this process, no more than two vertices will be collapsed together, because the matching of the graph is a set of edges, in which no two edges are related to the same vertex. The vertices that are not related to any matching edge are directly copied to the reduced graph. When looking for the maximum matching edge in the graph, the scheme adopted is the heavy edge matching scheme, that is, to increase the weight of the edge. Specifically, the vertices are randomly visited in order by a randomization algorithm, and they are matched and merged with the vertices of the adjacent edges with larger weights. At the same time, the weight of the new vertex is equal to the sum of the weights of the original two vertices, and the edges associated with the original two vertices are retained as the edges associated with the new vertex. If there is an edge that is connected to the original two vertices at the same time, the weight of the edge is set to the sum of the weights of the remaining associated edges; repeat this process, continuously reduce the number of vertices in the graph, until the size of the graph reaches the preset vertex number threshold, and the reduced graph is obtained, and the coarsening stage ends.

[0079] S4. Partition the coarsened graph using a direct partitioning algorithm to obtain a partitioned subgraph.

[0080] Direct partitioning algorithms are a class of algorithms used to partition a graph or data set into multiple subsets. In the finite element meshing stage, two common partitioning algorithms are spectral bisection and Kernighan-Lin algorithm. Among them, spectral bisection is a method for partitioning a graph based on the eigenvalues ​​and eigenvectors of the graph's Laplace matrix. The basic steps are as follows:

[0081] 1. Calculate the Laplacian matrix: First calculate the Laplacian matrix of the graph :

[0082]

[0083] Where D is the degree matrix and A is the adjacency matrix of the graph;

[0084] 2. Find eigenvalues ​​and eigenvectors: Calculate the eigenvector corresponding to the second smallest eigenvalue of the Laplacian matrix, which is usually close to zero;

[0085] 3. Node partitioning: The nodes are divided into two groups according to the sign of the eigenvector. Usually, the nodes corresponding to the positive elements are one partition, and the nodes corresponding to the negative elements are another partition.

[0086] The Kernighan-Lin algorithm is an iterative bisection algorithm. Its core idea is to reduce the number of edges between two partitions by exchanging nodes. The specific steps are as follows:

[0087] 1. Initial partitioning: First, randomly divide the nodes of the graph into multiple partitions;

[0088] 2. Edge weight calculation: calculate the edge weight changes caused by each node moving to a different partition;

[0089] 3. Node exchange: select those node pairs that can minimize the number of edges between the two partitions after exchange;

[0090] 4. Iterative optimization: Repeat steps 2 and 3 until no better node pair is found or the preset number of iterations is reached.

[0091] As a further example, when the graph is divided into two subgraphs, the spectral bisection method is used to divide the coarsened graph structure into multiple subgraphs; when the graph is divided into more than two subgraphs, the Kernighan-Lin algorithm is used to divide the coarsened graph structure into multiple subgraphs.

[0092] The commonly used method is the Kernighan-Lin algorithm. The Kernighan-Lin algorithm can be used to iterate through partitioning so that each partition contains an approximate weight, thereby achieving load balancing between partitions.

[0093] S5. Refine and enlarge the divided graph through node splitting and partition refinement algorithm to obtain a refined graph.

[0094] More specifically, the refinement and enlargement stage is to refine the coarse graph after the partition, and obtain the partitioned original graph through multiple projections of the partitioned coarse graph. The method adopted is to split the vertex pairs in the above coarsened and reduced graph, and assign their vertex pairs to the same partitions in the refined graph. Since the refined graph is finer and has more degrees of freedom, it can be used to improve the partition, thereby reducing edge cuts. At this time, the projection partition can be improved by the partition refinement algorithm. The basic purpose of the partition refinement algorithm is to select vertices so that when they move from one partition to another, the generated partition has a smaller edge cut and maintains load balance.

[0095] The method used in this embodiment is a greedy refinement algorithm: for each vertex of the graph, its neighborhood is defined as the set of parts to which the vertices adjacent to the vertex belong. In the refinement stage, the vertex can be moved to any adjacent part, and the edge cuts generated after the move are calculated; then, through multiple iterations, the movement method that can produce the minimum edge cut is found. At the same time, in each iteration, all vertices are checked in random order to see if they can be moved. If the vertex is a boundary vertex, that is, it is associated with a neighboring area, it is moved between different partitions so that each partition part can have the same weight.

[0096] S6. Map and partition the matrix derived from the finite element mesh based on the partitioning diagram to obtain a partition matrix.

[0097] In the process of solving the finite element mesh, the linear equations are generated and solved by deriving the finite element mesh. This process usually requires iterative calculation and will produce a large sparse matrix. Referring to the divided finite element mesh and its corresponding graph structure, the matrix derived from the finite element mesh is mapped accordingly through coordinate mapping, Jacobian matrix and determinant calculation, so that the matrix also produces a corresponding division effect, and a matrix of multiple partitions is obtained.

[0098] S7. The partition matrix is ​​sorted by reducing the filling through the multi-layer nested decomposition paradigm to obtain the partition rearrangement matrix.

[0099] The multi-layer nested partitioning algorithm is used to decompose the matrix blocks after the calculation of the partitioning to reorder the graph. The vertex separator S of the graph corresponding to the matrix is ​​calculated by finding the minimum vertex cover. The vertex separator is a set of vertices in the original vertex set. After removal, the graph will be divided into two unconnected parts A and B. In this process, it is necessary to minimize , while satisfying:

[0100]

[0101] in, is a balance constraint parameter that controls the size difference between sets A and B. It is a non-negative number when When A and B are equal in size, When , a certain difference in the size of A and B is allowed. max(|A|,|B|): indicates the size of the set with the larger number of vertices in sets A and B. , as well as Respectively represent the total number of vertices in the corresponding set.

[0102] Then, the threads are divided into two groups, and they continue to look for separators and split the graph in A and B respectively until each thread group contains only one thread. At this time, each thread finds a vertex separator for the part of the graph it processes in turn. When the graph is small enough, it is sorted by the multiple minimum degree algorithm. Once A and B are sorted, the overall graph is sorted by sorting the rows and columns in the order of partition A first, B later, and S last, to achieve renumbering of the graph nodes so that adjacent nodes in the graph have adjacent numbers, so that the non-zero elements in the matrix block are arranged continuously, reducing the proportion of zero elements between non-zero elements, and obtaining the rearranged matrix block.

[0103] In one embodiment, referring to the attached Figure 3 , This application reduces the filling sorting of the partition matrix, and realizes a more concentrated distribution by rearranging the partitions of a matrix. Figure 3 The left picture in the middle shows the distribution of the original partition matrix, and the right picture shows the matrix distribution after the partitions are rearranged, which can be regarded as the rearranged matrix. Figure 3 It can be seen that the non-zero elements are concentrated on the diagonal. At the same time, different concentrated matrix blocks are generated with similar sizes, which is convenient for subsequent calculations.

[0104] S8. Allocate different partitions of the partition rearrangement matrix to different threads for decomposition and solution to obtain a matrix solution result.

[0105] The rearranged matrix blocks are assigned to different threads for parallel calculation. ILU decomposition is a commonly used matrix preprocessing method, but it is difficult to parallelize because each iterative calculation involves multiple forward / backward substitutions. Here, ILU decomposition is performed on the matrix blocks in a single thread, and then the conjugate gradient (CG) method is used to solve the problem. Parallel computing can be achieved to improve the solution efficiency, and ILU decomposition preprocessing can be used to further optimize the matrix preprocessing effect. In one embodiment, refer to the attached Figure 4, the matrix condition number (ConditionNumber) of three different models was calculated respectively. After preprocessing optimization, the matrix condition number has a significant decrease, which improves the matrix ill-conditioning and can improve the stability of matrix solution iteration. It should be noted that the matrix condition number is an indicator to measure the stability of the linear system solution and the reversibility of the matrix. It is defined as the product of the norm of the matrix and the norm of its inverse matrix.

[0106] It is understandable that the above matrix preprocessing method may include: steps S1 to S7, or may include steps S1 to S8. That is, the above preprocessing may refer to the operation before decomposition and solution, or may include the operation of the decomposition and solution step. Those skilled in the art may select specific steps or definitions according to actual conditions, and this application does not make further limitations on this.

[0107] Figure 5 The matrix preprocessing system architecture diagram provided in the embodiment of the present application is as follows: Figure 5 As shown, it includes: a grid acquisition conversion module, a coarsening and shrinking module, a partitioning module, a refinement and enlargement module, a matrix rearrangement module and a matrix parallel decomposition module.

[0108] Among them, the mesh acquisition conversion module is used to convert the finite element mesh corresponding to the sparse matrix into a graph structure;

[0109] A coarsening and shrinking module is used to simplify the graph structure by using a heavy edge matching algorithm to obtain a coarsened graph structure;

[0110] A partitioning module, used for partitioning the coarsened graph structure into a plurality of subgraphs by a direct partitioning algorithm;

[0111] A refinement and enlargement module is used to refine and enlarge each subgraph after division through vertex splitting and partition refinement algorithm to obtain multiple refined graphs;

[0112] A matrix rearrangement module is used to map the sparse matrix accordingly with reference to the multiple refined graphs to obtain multiple partitioned matrices; and to reduce and sort each partition matrix by a multi-layer nested decomposition paradigm algorithm to obtain a rearranged matrix of multiple partitions;

[0113] The matrix parallel decomposition module is used to decompose the rearranged matrices of the multiple partitions in parallel.

[0114] It should be understood that the above-mentioned system is used to execute the methods in the above-mentioned embodiments. The implementation principles and technical effects of the corresponding program modules in the system are similar to those described in the above-mentioned methods. The working process of the system can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0115] In addition, the matrix preprocessing system is connected to a matrix parallel solving module, and the matrix parallel solving module is used to solve the decomposed multiple rearranged matrices in parallel.

[0116] This application preprocesses the sparse matrix and performs graph partitioning, graph rearrangement, ILU decomposition and CG method iterative solution operations on the input sparse matrix, thereby optimizing the structure of the sparse matrix, reducing the condition number of the matrix, and improving the stability of the matrix solution calculation process. At the same time, the concentrated arrangement of non-zero elements of the matrix after rearrangement improves the memory access command rate, and combined with the parallel calculation after block division, the efficiency of matrix solution is improved together. The flexibility and easy parallelization of block graph rearrangement overcome the limitations of existing preprocessing methods that are large in calculation amount and difficult to parallelize, and provide support for efficient solution of large-scale matrices.

[0117] It should be noted that ILU decomposition is a preprocessing technique for solving large sparse linear equations. ILU decomposition is the decomposition of a sparse matrix to obtain a lower triangular matrix L and an upper triangular matrix U, such that A≈LU. The "incomplete" here means that some smaller values ​​will be ignored during the decomposition process to maintain the sparsity of the matrix.

[0118] Finally, this application introduces a parallel decomposition solution algorithm. Due to the graph partitioning algorithm and the graph rearrangement algorithm, the matrix is ​​divided into blocks and the load is balanced. At the same time, the elements in each matrix block are arranged continuously, so it is easy to use a multi-threaded algorithm to assign different matrix blocks to different threads for parallel solution. After the above matrix blocks are assigned to different threads, ILU decomposition and CG algorithms are used in parallel to solve them, which effectively overcomes the problem that ILU decomposition is difficult to parallelize. After different threads solve and obtain the results, they are combined to obtain the final matrix solution result.

[0119] Based on the method in the above embodiment, the embodiment of the present application provides an electronic device, such as Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other via the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the method in the above embodiment.

[0120] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0121] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0122] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0123] It is understandable that the processor in the embodiment of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0124] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0125] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0126] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0127] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A matrix preprocessing method suitable for static analysis of semiconductor device structures, characterized in that: Methods include: Use the finite element method to perform structural static analysis on semiconductor devices and determine the finite element mesh involved in the static analysis process; Converting the finite element mesh into a graph structure; wherein the nodes of each unit in the finite element mesh are converted into vertices in the graph structure, and the connections between the nodes are converted into edges in the graph structure; or converting each unit in the finite element mesh into a vertex of the graph structure, and converting the shared faces or shared edges between the units into edges in the graph structure; The graph structure is simplified by using a heavy edge matching algorithm to obtain a coarsened graph structure; Dividing the coarsened graph structure into a plurality of subgraphs by a direct partitioning algorithm so that the loads of the divided subgraphs are balanced; Each subgraph after division is refined and enlarged by vertex splitting and partition refinement algorithm to obtain multiple refined graphs; the partition refinement algorithm is used to ensure that each refined graph partition has the same weight and the load is balanced among multiple refined graphs; Referring to the multiple refinement graphs, the sparse matrix corresponding to the finite element mesh is mapped accordingly to obtain multiple partitioned matrices; Through the multi-layer nested decomposition paradigm algorithm, each partition matrix is ​​sorted by reducing filling, so that adjacent nodes in the corresponding graph structure have adjacent numbers, so that non-zero elements in the partition matrix are arranged continuously, and the proportion of zero elements between non-zero elements is reduced, and the rearrangement matrix of multiple partitions is obtained to improve the memory access hit rate; The rearranged matrices of the multiple partitions are allocated to different threads to perform parallel decomposition and solution on the finite element mesh to complete the structural static analysis of the semiconductor device.

2. The method according to claim 1, characterized in that The graph structure is simplified by using a heavy edge matching algorithm to obtain a coarsened graph structure, including: Accessing vertices in the graph structure in random order through a randomization algorithm, matching and merging the vertices with adjacent vertices of edges whose weights are greater than a weight threshold, and setting the weight of the merged new vertex to the sum of the weights of the two vertices before the merge; The edges associated with the two vertices before merging are used as the edges associated with the new vertex. If any of the associated edges is connected to the two vertices before merging, the weight of this edge is set to the sum of the weights of the remaining associated edges. Repeat the above-mentioned vertex and edge merging process to continuously reduce the number of vertices of the graph structure until the number of vertices of the obtained new graph structure reaches a preset vertex number threshold, and use the finally obtained graph structure as the coarsened graph structure.

3. The method according to claim 1, characterized in that The coarsened graph structure is divided into a plurality of subgraphs by a direct partitioning algorithm, including: When divided into two subgraphs, the spectral bisection method is used to divide the coarsened graph structure into multiple subgraphs; When divided into more than two subgraphs, the Kernighan-Lin algorithm is used to divide the coarsened graph structure into multiple subgraphs.

4. The method according to claim 1, characterized in that: Through vertex splitting and partition refinement algorithms, each subgraph after division is refined and enlarged to obtain multiple refined graphs, including: Split the vertex pairs in the subgraph and project the vertex pairs into the refined graph of the same partition; After each projection assignment iteration, all vertices in each refined graph are checked in random order, and if a vertex is a boundary vertex, it is moved between different partitions of the refined graph so that each refined graph partition has the same weight.

5. The method according to claim 1, characterized in that The sparse matrix is ​​mapped accordingly with reference to the refinement graph to obtain multiple partitioned matrices, including: With reference to the mapping relationship between the refinement graph and the finite element mesh, the sparse matrix corresponding to the finite element mesh is mapped so that the sparse matrix also produces a corresponding partitioning effect, thereby obtaining a matrix of multiple partitions.

6. The method according to claim 1, characterized in that Through the multi-layer nested decomposition paradigm algorithm, each partition matrix is ​​sorted by reducing the filling, and the rearranged matrix of multiple partitions is obtained, including: Determine a graph structure corresponding to each partition matrix; the graph structure corresponds to a refined graph before mapping; Finding a minimum vertex cover in a graph structure corresponding to each partition matrix, wherein the minimum vertex cover is a set of vertices, and each edge in the partition matrix has at least one vertex in the minimum vertex cover; Using the minimum vertex cover as a vertex separator, removing the vertex separator, and dividing the corresponding graph structure into two unconnected subgraphs; Continue to search for vertex separators in unconnected subgraphs and continue to split until the number of vertices included in the split subgraph is less than a preset value; The graph structure of the reference partition matrix is ​​sorted according to the order of non-connected subgraphs, vertex separators, non-adjacent subgraphs obtained by dividing each non-adjacent subgraph, and vertex separators, so that adjacent nodes in the graph structure of the partition matrix have adjacent numbers, and a corresponding rearrangement matrix is ​​obtained.

7. A matrix preprocessing system suitable for static analysis of semiconductor device structures, characterized in that: The system includes: A mesh acquisition conversion module is used to perform structural static analysis on semiconductor devices using a finite element method, determine the finite element mesh involved in the static analysis process, and convert the finite element mesh into a graph structure; wherein the nodes of each unit in the finite element mesh are converted into vertices in the graph structure, and the connections between the nodes are converted into edges in the graph structure; or each unit in the finite element mesh is converted into a vertex of the graph structure, and the shared faces or shared edges between the units are converted into edges in the graph structure; A coarsening and shrinking module is used to simplify the graph structure by using a heavy edge matching algorithm to obtain a coarsened graph structure; A partitioning module, used to partition the coarsened graph structure into a plurality of subgraphs by a direct partitioning algorithm, so that the loads of the divided subgraphs are balanced; A refinement and enlargement module is used to refine and enlarge each subgraph after division through vertex splitting and partition refinement algorithm to obtain multiple refined graphs; the partition refinement algorithm is used to ensure that each refined graph partition has the same weight and the load is balanced among multiple refined graphs; A matrix rearrangement module is used to map the sparse matrix corresponding to the finite element grid with reference to the multiple refined graphs to obtain multiple partitioned matrices; each partition matrix is ​​reduced and sorted by a multi-layer nested decomposition paradigm algorithm so that adjacent nodes in the corresponding graph structure have adjacent numbers, so that non-zero elements in the partition matrix are arranged continuously, and the proportion of zero elements between non-zero elements is reduced, so as to obtain a plurality of partitioned rearranged matrices to improve the memory access hit rate; the plurality of partitioned rearranged matrices are allocated to different threads to perform parallel decomposition and solution on the finite element grid to complete the structural static analysis of the semiconductor device.

8. An electronic device, characterized in that: include: at least one memory for storing a computer program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 6.

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