A skew calibration method, device, and medium for a parallel bus

Abstract

The present application discloses a skew calibration method, device and medium for a parallel bus, relating to the field of communication technologies. The method includes: receiving, by a processor, an instruction and test data from a host computer, sending the instruction to a controller, and parsing, by the controller, the instruction to output a control signal; inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal. The present application performs automatic calibration of the skew between ports by self-transmitting and self-receiving through the ports inside the chip, improves the phase margin of the clock and data, and has a simple designed circuit, low cost, is convenient for transplantation, and can meet the requirements under different scenarios.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a skew calibration method, device, and medium for a parallel bus. Background Art

[0002] In the design of electronic systems, the design of buses and clocks is crucial. As two basic technologies, parallel buses and serial buses each play an important role. A parallel bus can transmit multiple bits of data simultaneously, so it has a high transmission efficiency. However, since a parallel bus contains multiple signal lines, in order to reduce the skew between signals, equal-length internal processing is usually required during PCB routing.

[0003] In a source synchronous bus with a high signal rate, not only is it required that the delay times of the clock and data lines be the same, but also the delay times between the data lines need to be consistent. Therefore, during PCB routing, equal-length internal processing can often meet most communication requirements. However, in high-speed transmission scenarios, in addition to equal-length PCB traces, the impact of skew between ports also needs to be considered. For interfaces with a relatively high transmission rate, such as BT656, BT1120, etc., the electrical standards do not clearly specify parameters such as the amplitude, impedance, and delay time of the parallel interface transmitter and receiver. This results in engineers lacking clear equal-length trace error requirements when designing the PCB, which may in turn cause problems such as insufficient clock and data phase margins when transmitting data in these parallel buses. Summary of the Invention

[0004] To solve the above problems, this application proposes a skew calibration method for a parallel bus, including: receiving instructions and test data from a host computer through a processor, sending the instructions to a controller, and parsing the instructions through the controller to output control signals; inputting the control signals and the test data into a PAD port to perform a loopback test through the PAD port, obtaining a test result, and comparing the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0005] In one example, parsing the instructions through the controller to output control signals specifically includes: generating multiple control signals according to the instructions, where the control signals include an enable signal, a clock control signal, and a data control signal; sending the enable signal to a multiplexer to enable the multiplexer; sending the clock control signal to a clock delay device to turn on the clock delay device; sending the data control signal to a data delay device to turn on the data delay device.

[0006] In one example, inputting the control signal and the test data into the PAD port specifically includes: sending the test data to a buffer, and sending the test data to the data delay element through the buffer to obtain output data through the data delay element; obtaining an output clock through the clock delay element, and inputting the output clock and the output data into the PAD port.

[0007] In one example, performing a loopback test through the PAD port specifically includes: the PAD port includes a clock PAD port and a data PAD port; receiving the output clock through the DO end of the clock PAD port, and outputting a PAD clock through the DI segment of the clock PAD port; receiving the output data through the DO end of the data PAD port, and outputting PAD data through the DI segment of the data PAD port; sending the PAD data to a flip-flop, so that the flip-flop outputs the test result according to the rising edge of the PAD clock.

[0008] In one example, the method further includes: determining a preset data delay and a clock delay, and setting the PAD port according to the data delay and the clock delay; aligning the clock edge with the data center, and determining the test data and the multiplexed output value of the PAD port, and comparing the test data and the multiplexed output value; if the test data is equal to the multiplexed output value, reducing the value of the clock delay according to a preset value, or increasing the value of the data delay according to a preset value, and resetting the PAD port according to the reduced clock delay or the increased data delay; if the test data is not equal to the multiplexed output value, using the corresponding data delay as the skew difference of the PAD port.

[0009] In one example, the method further includes: determining a right boundary and a left boundary according to a preset clock delay, determining a selection range according to the right boundary and the left boundary, and determining a delay value within the selection range; performing skew compensation on the data port of the PAD port according to the delay value.

[0010] In one example, the right boundary is determined according to a preset clock delay, which specifically includes: determining test data of multiple ports and multiplexed output values, and comparing the test data with the multiplexed output values; if the test data and the multiplexed output values corresponding to all ports are not equal, an error message is reported to the processor; if there are one or more ports for which the test data and the multiplexed output values are equal, the delay time of the PAD port is increased according to a preset value; if there are one or more ports for which the test data and the multiplexed output values are not equal, the corresponding clock delay is used as the right boundary.

[0011] In one example, the left boundary is determined according to a preset clock delay, which specifically includes: determining test data of multiple ports and multiplexed output values, and comparing the test data with the multiplexed output values; if the test data and the multiplexed output values corresponding to all ports are not equal, an error message is reported to the processor; if there are one or more ports for which the test data and the multiplexed output values are equal, the delay time of the PAD port is decreased according to a preset value; if there are one or more ports for which the test data and the multiplexed output values are not equal, the corresponding clock delay is used as the left boundary.

[0012] On the other hand, the present application also proposes a skew calibration device for a parallel bus, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the skew calibration device for the parallel bus can execute: receiving, by the processor, an instruction and test data from a host computer, sending the instruction to a controller, and parsing the instruction through the controller to output a control signal; inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0013] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer-executable instructions, and the computer-executable instructions are configured to: receive instructions and test data from a host computer through a processor, send the instructions to a controller, and parse the instructions through the controller to output a control signal; input the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and compare the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0014] The present application performs automatic calibration of the skew between ports by self-transmitting and self-receiving through ports inside the chip, improving the phase margin of the clock and data. Moreover, the designed circuit is simple, the cost is low, it is convenient to transplant, and it can meet the needs in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0016] Figure 1 is a schematic flowchart of a skew calibration method for a parallel bus in an embodiment of the present application;

[0017] Figure 2 is a schematic structural diagram of a skew calibration system for a parallel bus in an embodiment of the present application;

[0018] Figure 3 is a schematic loopback test diagram of skew calibration in an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of a skew calibration device for a parallel bus in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with specific embodiments of the present application and the corresponding drawings. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0021] The following will describe in detail the technical solutions provided by each embodiment of the present application in conjunction with the drawings.

[0022] As Figure 1As shown in the figure, to solve the above problems, an embodiment of the present application provides a skew calibration method for a parallel bus, which is applied in a skew calibration system for a parallel bus. As Figure 2 shown, the system includes a PAD port, a delay module (Delay), a control module (Control), a CPU core (Core), and a host computer module (PC). The method includes:

[0023] S101. Receive instructions and test data from the host computer through the processor, send the instructions to the controller, and parse the instructions through the controller to output a control signal.

[0024] The PAD port is configured in a bidirectional mode. In the normal operation mode, if data needs to be output, the output enable OE is activated; if data needs to be input, the input enable IE is activated. When either enable is disabled, the subsequent signal will remain in a high-impedance state. In the normal mode, OE and IE are in an interlocked state, that is, when one enable is valid, the other is invalid. When entering the loop test mode, the output of the interconnected device is set to a high-impedance state, and for the PAD ports related to data and clock in the present application, its OE and IE will be activated simultaneously.

[0025] The delay module is responsible for receiving data from the transmit register or loop test data, delaying the data, and then transmitting it to the external PAD port. The delay time is regulated by the control module, dividing the width of 1-bit data into 254 equal parts, and setting a value between 0 and 255 through the selection register to achieve different delay times. The maximum delay is equal to the width of 1-bit data.

[0026] The control module is responsible for receiving instructions and loop test data sent by the processor core, setting the delay times of the clock delay module and the data delay module accordingly, and controlling the selection switch of the multiplexer. In addition, it is also responsible for receiving the data returned by the flip-flop D1 during the loop test.

[0027] The CPU core and the host computer module work together. The host computer first sends a loop test command through the USB interface, and then sends a manual verification or automatic verification selection command for the loop test. After receiving and parsing the instructions from the host computer, the CPU core sends data to the transmit buffer register or the control module, and at the same time receives the data fed back by the control module. Based on these feedback data, the CPU core calculates the skew values of each port and sets appropriate delay times for each data port accordingly.

[0028] In one embodiment, as Figure 3As shown, the host computer sends instructions and test data to the processor through the USB interface. After receiving these data, the processor core first parses them, and then transmits the test data PB_DATA[7:0] to the buffer TX buffer through the AHB bus. At the same time, the processor core also sends corresponding instructions to the control module.

[0029] After receiving the instructions, the control module outputs an enable signal Looptest_EN to the multiplexer MUX and sets this signal to 1. In addition, it outputs a control signal Lcontrol[8:0] to the clock delay module CLKdelay, and the value of this signal is set to 128. For each data delay module Data delay, the control signal output by the data control module is Dcontrol[8:0], and its value is set to 0, which means that the clock delay module will delay by half of the data width of 1 bit to ensure that the data is output first and then the clock is delayed, so that the clock edge is aligned with the center of the data.

[0030] S102. Input the control signal and the test data into the PAD port to perform a loopback test through the PAD port, obtain the test result, and compare the test result with the test data.

[0031] After being processed by the MUX and the delay module Data delay, the data PB_DATA[7:0] to be sent is output as out_data and sent to the PAD port. At the same time, after the reference clock PB_CLK is implemented by the clock delay CLK delay, it is output as out_clk and also sent to the PAD port.

[0032] When the output enable OE and the input enable IE of the clock PAD port are both activated at the same time, the clock signal out_clk will form a loopback inside the PAD port of CLK: input from the DO end and then output from the DI end as PAD_CLK. Similarly, inside the data PAD port, when the output enable OE and the input enable IE are both activated at the same time, the data signal out_data will also be input from the DO end and output from the DI end as PAD_data, thus forming a loopback inside the PAD port of DATA.

[0033] PAD_data then enters the input end of the flip-flop D1, and is triggered by the rising edge of PAD_CLK, and the flip-flop outputs looptest_data.

[0034] S103. If the test result is the same as the test data, it means that the skew is normal.

[0035] The looptest_data is then sent to the control module and compared with the original PB_DATA[7:0]. If the two are exactly the same, it can be shown that the skew of the port is normal in the initialization state.

[0036] In one embodiment, the skew between data ports is calibrated. The PAD ports to be tested are selected, and their input and output enables are turned on simultaneously to ensure that the inside of the PAD is in the loopback mode. Then, the data delay settings Dcontrol[7:0] of all ports are set to 0, and the clock port delay setting Lcontrol[7:0] is set to 128 to align the clock edge with the data center.

[0037] Subsequently, it is compared whether the loop test data looptest_data[7:0] of each port is equal to Mux_out[7:0]. If the two sets of data of all ports are equal, the clock port delay value Lcontrol[7:0] is gradually decreased, such as decreasing by one each time, and the comparison continues until the two sets of data of a certain port become unequal.

[0038] When an unequal situation is found, record the port number of the current comparison failure and its Dcontrol[7:0] value, denoted as Dcontrol_x_fail, and at the same time record the current clock port delay value Lcontrol[7:0], denoted as Lcontrol_fail.

[0039] For other ports with successful comparisons, keep their Lcontrol values unchanged, but gradually increase their Dcontrol[7:0] values, such as increasing by one each time, and continue the comparison. If looptest_data[7:0] is equal to Mux_out[7:0], continue to increase the Dcontrol[7:0] value; if a new port fails the comparison, record the port number and its Dcontrol[7:0] value. This process continues until all ports fail the comparison, at which point the skew calibration between data ports is completed.

[0040] Finally, the data delay value Dcontrol_x_fail of each port reflects the skew difference between data ports.

[0041] In one embodiment, before calibrating the skew between the clock port and the data port, confirm the right boundary and the left boundary of the clock delay.

[0042] First, configure the data delay values Dcontrol[7:0] of each data port as the data skew calibration value Dcontrol_x_fail, and initialize the clock port delay value Lcontrol[7:0] to 128. Subsequently, compare whether looptest_data[7:0] of each port is equal to Mux_out[7:0]. If they are not equal, report an error to the processor core; if they are equal, increment the value of Lcontrol[7:0] by one each time. After each increment, perform the comparison again. When looptest_data[7:0] of a certain port is not equal to Mux_out[7:0], record the current value of Lcontrol[7:0] as Lcontrol_right, which is determined as the right boundary of the clock delay.

[0043] The process for determining the left boundary is similar to that of the right boundary, but in the opposite direction. Similarly, configure the data delay values Dcontrol[7:0] of each data port as Dcontrol_x_fail, and initialize the clock port delay value Lcontrol[7:0] to 128. Compare whether looptest_data[7:0] of each port is equal to Mux_out[7:0]. If they are not equal, report an error; if they are equal, decrement the value of Lcontrol[7:0] by one each time. After each decrement, perform the comparison again. When looptest_data[7:0] of a certain port is not equal to Mux_out[7:0], it should be noted that here, record it as Lcontrol_left as the left boundary of the clock delay.

[0044] Through the above process, the left and right boundaries of the clock delay can be determined.

[0045] In one embodiment, according to the left and right boundary values of the clock port delay obtained from the test, select a moderate delay value within this range for setting. At the same time, the data delay value Dcontrol_x_fail of each data port actually performs skew compensation on the data port. Such compensation enables a large phase margin between the data port and the clock port, thereby improving the integrity of the transmitted signal.

[0046] As Figure 4 shown, the embodiment of the present application also provides a skew calibration device for a parallel bus, including:

[0047] At least one processor; and,

[0048] A memory communicatively connected to at least one processor; wherein,

[0049] The memory stores instructions executable by at least one processor. The instructions are executed by at least one processor to enable a skew calibration device of a parallel bus to perform:

[0050] Receive instructions and test data from a host computer through a processor, send the instructions to a controller, and parse the instructions through the controller to output a control signal;

[0051] Input the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and compare the test result with the test data;

[0052] If the test result is the same as the test data, it indicates that the skew is normal.

[0053] An embodiment of the present application also provides a non-volatile computer storage medium storing computer-executable instructions, and the computer-executable instructions are set as:

[0054] Receive instructions and test data from a host computer through a processor, send the instructions to a controller, and parse the instructions through the controller to output a control signal;

[0055] Input the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and compare the test result with the test data;

[0056] If the test result is the same as the test data, it indicates that the skew is normal.

[0057] In the 1990s, it was obvious to distinguish whether an improvement to a technology was a hardware improvement (e.g., improvement to the circuit structure of diodes, transistors, switches, etc.) or a software improvement (improvement to the method flow). However, with the development of technology, many improvements to method flows today can be regarded as direct improvements to the hardware circuit structure. Almost all designers obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented with a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. The designer can program by himself to "integrate" a digital system on a PLD without asking the chip manufacturer to design and manufacture a dedicated integrated circuit chip. Moreover, today, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a hardware description language (HDL), and there is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be aware that by simply performing logical programming on the method flow with the above-mentioned several hardware description languages and programming it into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.

[0058] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to logically program the method steps to enable the controller to be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, and embedded microcontrollers to achieve the same function. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or the structures within the hardware component.

[0059] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0060] For the convenience of description, when describing the above devices, they are described separately as various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0061] Each embodiment in this application is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0062] The device, medium, and method provided by the embodiments of the present application correspond one by one. Therefore, the device and the medium also have beneficial technical effects similar to those of their corresponding methods. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the device and the medium will not be elaborated here.

[0063] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0064] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0065] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0066] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0067] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and a memory.

[0068] The memory may include non-permanent memory in the form of computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0069] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM (compact disc read-only memory), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0070] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0071] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A method for skew calibration of a parallel bus, characterized in that: include: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal; Determine a right boundary and a left boundary according to a preset clock delay, determine a selection range according to the right boundary and the left boundary, and determine a delay value in the selection range; The data port of the PAD port is skew compensated according to the delay value.

2. The method according to claim 1, characterized in that: The controller analyzes the instruction to output a control signal, which specifically includes: Produce a plurality of control signals according to the instructions, wherein the control signals include an enable signal, a clock control signal, and a data control signal; Sending the enable signal to the multiplexer to enable the multiplexer; Sending the clock control signal to the clock delay device to enable the clock delay device to start; The data control signal is sent to the data delayer to enable the data delayer to be turned on.

3. The method according to claim 2, characterized in that Inputting the control signal and the test data into the PAD port specifically includes: Sending the test data to a buffer, and sending the test data to the data delayer through the buffer to obtain output data through the data delayer; An output clock is obtained through the clock delay device, and the output clock and the output data are input to the PAD port.

4. The method according to claim 3, characterized in that Perform a loopback test through the PAD port, specifically including: The PAD port includes a clock PAD port and a data PAD port; Receive the output clock through the DO end of the clock PAD port, and output the PAD clock through the DI segment of the clock PAD port; Receive the output data through the DO terminal of the data PAD port, and output the PAD data through the DI segment of the data PAD port; The PAD data is sent to a trigger, so that the trigger outputs the test result according to a rising edge of the PAD clock.

5. The method according to claim 1, characterized in that The method further comprises: Determine a preset data delay and a clock delay, and set the PAD port according to the data delay and the clock delay; Aligning a clock edge with a data center, determining test data and a multiplexed output value of the PAD port, and comparing the test data with the multiplexed output value; If the test data is equal to the multiplexed output value, the value of the clock delay is reduced according to a preset value, or the value of the data delay is increased according to a preset value, and the PAD port is reset according to the reduced clock delay or the increased data delay; If the test data is not equal to the multiplexed output value, the corresponding data delay is used as the skew difference of the PAD port.

6. The method according to claim 1, characterized in that The right boundary is determined according to the preset clock delay, including: determining test data and multiplexed output values ​​for a plurality of ports, and comparing the test data with the multiplexed output values; If the test data corresponding to all ports are not equal to the multiplexed output values, reporting error information to the processor; If the test data corresponding to one or more ports are equal to the multiplexed output value, the delay time of the PAD port is increased according to a preset value; If the test data and the multiplexed output value corresponding to one or more ports are not equal, the corresponding clock delay is used as the right boundary.

7. The method according to claim 1, characterized in that The left boundary is determined according to the preset clock delay, including: determining test data and multiplexed output values ​​for a plurality of ports, and comparing the test data with the multiplexed output values; If the test data corresponding to all ports are not equal to the multiplexed output values, reporting error information to the processor; If the test data corresponding to one or more ports are equal to the multiplexed output value, the delay time of the PAD port is reduced according to a preset value; If the test data and the multiplexed output value corresponding to one or more ports are not equal, the corresponding clock delay is used as the left boundary.

8. A skew calibration device for a parallel bus, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the skew calibration device for a parallel bus to perform: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal; Determine a right boundary and a left boundary according to a preset clock delay, determine a selection range according to the right boundary and the left boundary, and determine a delay value in the selection range; The data port of the PAD port is skew compensated according to the delay value.

9. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal; Determine a right boundary and a left boundary according to a preset clock delay, determine a selection range according to the right boundary and the left boundary, and determine a delay value in the selection range; The data port of the PAD port is skew compensated according to the delay value.

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