A cholesteric liquid crystal display driving architecture and its driving method

By introducing a variety of PMOS and NMOS tubes and diodes into the cholesteric liquid crystal display driver architecture, and realizing power supply switching of the common ACVcom electrode signal through control signals, the problem of high span voltage requirements in the prior art has been solved, and a wider span voltage range and higher compatibility are achieved.

CN119559912BActive Publication Date: 2025-06-10ANHUI YUTU TECH CO LTD
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202411880073.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-12-19
Publication Date
2025-06-10
Estimated Expiration
2044-12-19

AI Technical Summary

Technical Problem

The existing cholesteric LCD display driver architecture requires high transducer pressure, resulting in very few source ICs supported and limited compatibility.

Method used

A cholesteric liquid crystal display driving architecture is proposed, including a variety of PMOS and NMOS tubes and diodes. By generating and controlling multiple control signals, the power supply switching of the common ACVcom electrode signal and the combination of synchronization with the source driving signal is realized, ensuring that the display screen enters the P state to enter the refresh scanning stage.

Benefits of technology

The cross-pressure range of cholesteric LCD display has been expanded and the compatibility of the display has been improved.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119559912B_ABST
    Figure CN119559912B_ABST
Patent Text Reader

Abstract

The present invention discloses a driving architecture for a cholesteric liquid crystal display screen and a driving method thereof, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode, and a second diode. The source of the first PMOS transistor is connected to the positive voltage of the power supply. The drain of the first PMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the first PMOS transistor is connected to a first control signal for controlling the connection of the positive voltage of the power supply. The source of the first NMOS transistor is connected to the negative voltage of the power supply. The drain of the first NMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the first NMOS transistor is connected to a second control signal for controlling the connection of the negative voltage of the power supply. The source of the second PMOS transistor is grounded, and the drain of the second PMOS transistor is electrically connected to the negative electrode of the first diode. The driving architecture for the cholesteric liquid crystal display screen and the driving method thereof in this application expand the cross-voltage range of the cholesteric liquid crystal display screen and improve the compatibility of the cholesteric liquid crystal display screen.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to the technical field of display screen driving, and particularly to a driving architecture and a driving method for a cholesteric liquid crystal display screen. Background Art

[0002] Figure 1 The conventional cholesteric LCD single-pixel driving architecture mainly consists of a source line, a gate line, a com, a TFT, and a pixel electrode. Among them, the source line is used to send data to the drain of the TFT, the gate line controls the gate of the TFT to control the on or off of the TFT, the pixel electrode is connected to the source of the TFT, and is used to receive and save the data signal and form an electric field with the com electrode to control the deflection of the liquid crystal. The driving timing is as Figure 2 shown. Since the com is DC, the applied voltage generated is relatively small, only aV. Existing cholesteric liquid crystal products have very few supported source ICs due to the need for a relatively high cross-voltage, resulting in limited compatibility of the liquid crystal active driving scheme. Summary of the Invention

[0003] To solve the technical problems existing in the background art, the present invention proposes a driving architecture and a driving method for a cholesteric liquid crystal display screen.

[0004] A driving architecture for a cholesteric liquid crystal display screen proposed by the present invention includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode, and a second diode. The source of the first PMOS transistor is connected to the positive voltage of the power supply. The drain of the first PMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the first PMOS transistor is connected to a first control signal for controlling the connection of the positive voltage of the power supply. The source of the first NMOS transistor is connected to the negative voltage of the power supply. The drain of the first NMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the first NMOS transistor is connected to a second control signal for controlling the connection of the negative voltage of the power supply. The source of the second PMOS transistor is grounded. The drain of the second PMOS transistor is electrically connected to the negative electrode of the first diode. The positive electrode of the first diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the second PMOS transistor is connected to a third control signal for controlling the grounding of the common terminal ACVcom. The drain of the second NMOS transistor is grounded. The source of the second NMOS transistor is electrically connected to the positive electrode of the second diode. The negative electrode of the second diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen. The gate of the second NMOS transistor is connected to a fourth control signal for controlling the grounding of the common terminal ACVcom.

[0005] Preferably, the absolute value of the negative power supply voltage is equal to that of the positive power supply voltage.

[0006] Preferably, it further includes a source driving signal for controlling the cholesteric liquid crystal display screen accessed through a source driver.

[0007] A driving method for a driving architecture of a cholesteric liquid crystal display screen proposed by the present invention is applied to the driving architecture of the cholesteric liquid crystal display screen as described in any one of the above, and the method includes:

[0008] Obtain the common electrode signal preset at the common terminal ACVcom and the preset source driving signal;

[0009] Generate a first control signal, a second control signal, a third control signal, and a fourth control signal according to the voltage change corresponding to the common electrode signal;

[0010] Power on the cholesteric liquid crystal display screen, perform power supply switching corresponding to the common electrode signal on the common terminal ACVcom according to the first control signal, the second control signal, the third control signal, and the fourth control signal, and synchronously combine the preset source driving signal to enable the cholesteric liquid crystal display screen to enter the P state and enter the refresh scanning stage.

[0011] Preferably, the voltage change corresponding to the common electrode signal is specifically converted from grounding to accessing a positive voltage. The generating of the first control signal, the second control signal, the third control signal, and the fourth control signal according to the voltage change corresponding to the common electrode signal is specifically that the first control signal is converted from grounding to high level, the second control signal remains low level, the third control signal remains grounded, and the fourth control signal remains low level.

[0012] Preferably, the voltage change corresponding to the common electrode signal is specifically converted from accessing a positive voltage to grounding. The generating of the first control signal, the second control signal, the third control signal, and the fourth control signal according to the voltage change corresponding to the common electrode signal is specifically that the first control signal is converted from high level to grounding, the second control signal remains low level, the third control signal is converted from grounding to high level, and the fourth control signal remains low level.

[0013] Preferably, the voltage change corresponding to the common electrode signal is specifically converted from grounding to accessing a negative voltage. The generating of the first control signal, the second control signal, the third control signal, and the fourth control signal according to the voltage change corresponding to the common electrode signal is specifically that the first control signal remains grounded, the second control signal is converted from low level to grounding, the third control signal is converted from high level to grounding, and the fourth control signal remains low level.

[0014] Preferably, the voltage change corresponding to the common electrode signal is specifically a conversion from an applied negative voltage to ground. Generating the first control signal, the second control signal, the third control signal, and the fourth control signal according to the voltage change corresponding to the common electrode signal is specifically that the first control signal remains grounded, the second control signal is converted from ground to low level, the third control signal remains grounded, and the fourth control signal is converted from low level to high level.

[0015] Preferably, before the cholesteric liquid crystal display screen enters the p state, the voltage polarities of the common electrode signal and the source drive signal at the same moment are opposite.

[0016] In the present invention, for the proposed cholesteric liquid crystal display screen driving architecture and its driving method, a preset common electrode signal of the common terminal ACVcom and a preset source drive signal are obtained; first control signal, second control signal, third control signal, and fourth control signal are generated according to the voltage change corresponding to the common electrode signal; power is supplied to the cholesteric liquid crystal display screen, and power supply switching corresponding to the common electrode signal is performed on the common terminal ACVcom according to the first control signal, the second control signal, the third control signal, and the fourth control signal, and synchronously combined with the preset source drive signal to enable the cholesteric liquid crystal display screen to enter the P state and enter the refresh scanning stage. The cross-voltage range of the cholesteric liquid crystal display screen is expanded, and the compatibility of the cholesteric liquid crystal display screen is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the driving architecture of a cholesteric liquid crystal display screen in the prior art;

[0018] Figure 2 Schematic diagram of the driving timing of a cholesteric liquid crystal display screen in the prior art;

[0019] Figure 3 Schematic diagram of the driving timing of a cholesteric liquid crystal display screen proposed by the present invention;

[0020] Figure 4 Schematic diagram of the electric field structure of the common terminal Acvcom of a cholesteric liquid crystal display screen driving architecture proposed by the present invention;

[0021] Figure 5 Schematic diagram of the positive and negative voltage switching structure of the common terminal Acvcom of a cholesteric liquid crystal display screen driving architecture proposed by the present invention;

[0022] Figure 6 Schematic diagram of the grounding structure of the common terminal Acvcom of a cholesteric liquid crystal display screen driving architecture proposed by the present invention;

[0023] Figure 7 Schematic diagram of the driving timing structure of the driving method of a cholesteric liquid crystal display screen driving architecture proposed by the present invention.

[0024] Legend: 1. Common line; 2. Gate line; 3. TFT transistor; 4. Source line; 5. Pixel unit. Detailed implementation

[0025] Refer to Figures 1-7 , a cholesteric liquid crystal display driving architecture proposed by the present invention includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode, and a second diode. The source electrode of the first PMOS transistor is connected to the positive voltage of the power supply. The drain electrode of the first PMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display. The gate electrode of the first PMOS transistor is connected to a first control signal for controlling the connection of the positive voltage of the power supply. The source electrode of the first NMOS transistor is connected to the negative voltage of the power supply. The drain electrode of the first NMOS transistor is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display. The gate electrode of the first NMOS transistor is connected to a second control signal for controlling the connection of the negative voltage of the power supply. The source electrode of the second PMOS transistor is grounded. The drain electrode of the second PMOS transistor is electrically connected to the negative electrode of the first diode. The positive electrode of the first diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display. The gate electrode of the second PMOS transistor is connected to a third control signal for controlling the grounding of the common terminal ACVcom. The drain electrode of the second NMOS transistor is grounded. The source electrode of the second NMOS transistor is electrically connected to the positive electrode of the second diode. The negative electrode of the second diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display. The gate electrode of the second NMOS transistor is connected to a fourth control signal for controlling the grounding of the common terminal ACVcom.

[0026] Specifically, the absolute values of the negative voltage of the power supply and the positive voltage of the power supply are equal.

[0027] Specifically, it further includes a source driver for accessing a source driving signal for controlling the cholesteric liquid crystal display.

[0028] Figure 4 is the electric field direction during driving, and can provide alternating voltages with equal amplitudes between the two substrates of the LCD.

[0029] Refer to Figures 1-7 , a driving method for a cholesteric liquid crystal display driving architecture proposed by the present invention is applied to the cholesteric liquid crystal display driving architecture as described in any one of the above. The method includes:

[0030] Obtain the preset common electrode signal of the common terminal ACVcom and the preset source driving signal;

[0031] Generate a first control signal, a second control signal, a third control signal, and a fourth control signal according to the voltage change corresponding to the common electrode signal;

[0032] Power on the cholesteric liquid crystal display screen, perform power supply switching corresponding to the common electrode signal on the common terminal ACVcom according to the first control signal, the second control signal, the third control signal, and the fourth control signal, and synchronously combine the preset source drive signal to enable the cholesteric liquid crystal display screen to enter the P state to enter the refresh scanning stage.

[0033] In this embodiment, when the voltage change corresponding to the common electrode signal is specifically changed from grounding to accessing a positive voltage, the first control signal changes from grounding to high level, the second control signal remains low level, the third control signal remains grounded, and the fourth control signal remains low level.

[0034] In this embodiment, when the voltage change corresponding to the common electrode signal is specifically changed from accessing a positive voltage to grounding, the first control signal changes from high level to grounding, the second control signal remains low level, the third control signal changes from grounding to high level, and the fourth control signal remains low level.

[0035] In this embodiment, when the voltage change corresponding to the common electrode signal is specifically changed from grounding to accessing a negative voltage, the first control signal remains grounded, the second control signal changes from low level to grounding, the third control signal changes from high level to grounding, and the fourth control signal remains low level.

[0036] In this embodiment, when the voltage change corresponding to the common electrode signal is specifically changed from accessing a negative voltage to grounding, the first control signal remains grounded, the second control signal changes from grounding to low level, the third control signal remains grounded, and the fourth control signal changes from low level to high level.

[0037] Specifically, before the cholesteric liquid crystal display screen enters the p state, the voltage polarities of the common electrode signal and the source drive signal at the same moment are opposite.

[0038] In the specific working process of the driving architecture and driving method of the cholesteric liquid crystal display screen in this embodiment, when Acvcom is a positive voltage, at this time the first control signal is grounded, the second control signal is at low level Low, the third control signal is at high level High, and the fourth control signal is Low; before Acvcom turns to negative voltage, first connect to ground for discharging, at this time the first control signal is at high level High, the second control signal is at low level Low, the third control signal is at high level High, and the fourth control signal is Low; then Acvcom turns to negative voltage, at this time the first control signal is grounded, the second control signal is grounded, the third control signal is grounded, and the fourth control signal is Low; finally, Acvcom discharges to ground, at this time the first control signal is grounded, the second control signal is at low level Low, the third control signal is grounded, and the fourth control signal is High; after the discharge ends, Acvcom will remain in the grounded state until the next picture is refreshed.

[0039] As described above, it is only the preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and all should be covered within the protection scope of the present invention.

Claims

1. A cholesteric liquid crystal display screen driving architecture, characterized in that: It includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first diode, and a second diode. The source of the first PMOS tube is connected to the forward voltage of the power supply. The drain of the first PMOS tube is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display. The gate of the first PMOS tube is connected to a first control signal for controlling the forward voltage of the power supply to be turned on. The source of the first NMOS tube is connected to the negative voltage of the power supply, the drain of the first NMOS tube is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen, and the gate of the first NMOS tube is connected to the second control signal for controlling the negative voltage of the power supply to be turned on; the source of the second PMOS tube is grounded, the drain of the second PMOS tube is electrically connected to the cathode of the first diode, the anode of the first diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen, and the gate of the second PMOS tube is connected to the third control signal for controlling the grounding of the common terminal ACVcom; the drain of the second NMOS tube is grounded, the source of the second NMOS tube is electrically connected to the anode of the second diode, and the cathode of the second diode is electrically connected to the common terminal ACVcom of the cholesteric liquid crystal display screen; the gate of the second NMOS tube is connected to the fourth control signal for controlling the grounding of the common terminal ACVcom.

2. The cholesteric liquid crystal display driving architecture according to claim 1, characterized in that: The absolute value of the negative voltage of the power supply is equal to the absolute value of the positive voltage of the power supply.

3. The cholesteric liquid crystal display driving architecture according to claim 2, characterized in that: The method also includes accessing a source driving signal for controlling a cholesteric liquid crystal display screen through a source driver.

4. A driving method of a cholesteric liquid crystal display screen driving architecture, characterized in that: Applied to the cholesteric liquid crystal display driving architecture according to any one of claims 1 to 3, the method comprises: Obtaining a common electrode signal and a preset source driving signal preset at the common terminal ACVcom; Generate a first control signal, a second control signal, a third control signal, and a fourth control signal according to a voltage change corresponding to the common electrode signal; The cholesteric liquid crystal display is powered on, and the power supply corresponding to the common electrode signal is switched on the common terminal ACVcom according to the first control signal, the second control signal, the third control signal, and the fourth control signal, and the preset source drive signal is synchronously combined to enable the cholesteric liquid crystal display to enter the P state to enter the refresh scanning stage.

5. The driving method of the cholesteric liquid crystal display driving architecture according to claim 4, characterized in that: The voltage change corresponding to the common electrode signal is specifically converted from grounding to accessing a forward voltage. The first control signal, the second control signal, the third control signal, and the fourth control signal are generated according to the voltage change corresponding to the common electrode signal. Specifically, the first control signal is converted from grounding to a high level, the second control signal remains at a low level, the third control signal remains grounded, and the fourth control signal remains at a low level.

6. The driving method of the cholesteric liquid crystal display driving architecture according to claim 4, characterized in that: The voltage change corresponding to the common electrode signal is specifically converted from the connected forward voltage to the ground. The first control signal, the second control signal, the third control signal, and the fourth control signal are generated according to the voltage change corresponding to the common electrode signal. Specifically, the first control signal is converted from a high level to the ground, the second control signal remains at a low level, the third control signal is converted from the ground to a high level, and the fourth control signal remains at a low level.

7. The driving method of the cholesteric liquid crystal display driving architecture according to claim 4, characterized in that: The voltage change corresponding to the common electrode signal is specifically converted from grounding to connecting to a negative voltage. According to the voltage change corresponding to the common electrode signal, a first control signal, a second control signal, a third control signal, and a fourth control signal are generated. Specifically, the first control signal remains grounded, the second control signal is converted from a low level to grounding, the third control signal is converted from a high level to grounding, and the fourth control signal remains at a low level.

8. The driving method of the cholesteric liquid crystal display driving architecture according to claim 4, characterized in that: The voltage change corresponding to the common electrode signal is specifically converted from the connected negative voltage to the ground. According to the voltage change corresponding to the common electrode signal, the first control signal, the second control signal, the third control signal, and the fourth control signal are generated. Specifically, the first control signal remains grounded, the second control signal is converted from ground to a low level, the third control signal remains grounded, and the fourth control signal is converted from a low level to a high level.

9. The driving method of the cholesteric liquid crystal display driving architecture according to claim 4, characterized in that: Before the cholesteric liquid crystal display screen enters the p-state, the common electrode signal and the source driving signal voltage have opposite polarities at the same time.

Citation Information

Patent Citations

  • LCD panel of thin-film transistor

    CN101441374A

  • Multi-voltage generation circuit and liquid crystal display device

    CN106057158A