A timing control method and circuit for FPGA BRAM read-write conflict

Abstract

The application provides a timing control method and circuit for FPGA BRAM read-write conflict. When read-write conflict occurs, two timing circuits are used to generate working timing. An initial clock acts on the first timing circuit, and the first timing circuit generates read operation timing. After the read operation of the first timing circuit is completed, the second timing circuit is controlled to generate write operation timing, so that one timing path is used to control read and write, competition caused by read-write conflict is avoided, and the memory access efficiency of the BRAM is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of timing control, in particular to a timing control method and circuit for FPGA BRAM read-write conflict. BACKGROUND

[0002] Field-Programmable Gate Array (FPGA) is a kind of general programmable logic device, which has the characteristics of high flexibility and high parallelism, and usually includes Configurable Logic Block (CLB), Configurable Routing (CR), Input Output Block (IOB) and other IP resources, such as Block RAM (BRAM) and Digital Signal Processing (DSP), etc., which provides users with system programmable or reconfigurable ability.

[0003] BRAM, as the main block storage resource in FPGA, is mainly composed of Static Random Access Memory (SRAM) inside, which not only provides a large amount of storage space for FPGA, but also has the advantages of flexible storage mode, high compatibility and no need for periodic refresh, etc., providing internal assistance for the high flexibility of FPGA. FPGA BRAM has single-port and double-port working structure, and in the working process, there is a situation that needs to read and write the same storage address in the same cycle, which causes read-write conflict. According to the needs, it is decided whether to read out the old data already stored in this storage address before writing new data, or directly read the new data to be written, which causes conflict.

[0004] BRAM read-write conflict generally includes three cases: first, in BRAM double-port working mode, the same storage address needs to be read and written in the same cycle, such as A port writing operation and B port reading operation, which corresponds to the read-write conflict (mix_old_data) configuration bit in the configuration judgment circuit module; second, in BRAM single-port working mode, reading and writing cannot be performed at the same time, so it is necessary to decide whether to read out the data already stored in the address before writing, which corresponds to the read old data (read_old_data) configuration bit in the configuration judgment circuit module; third, when the read enable (read_enable) configuration bit in the configuration judgment circuit module is valid, there may be a situation of reading and writing at the same time. If the three read-write conflict situations are controlled by using a timing path, it is difficult to avoid the competition caused by read-write conflict, thereby limiting the memory efficiency of BRAM. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to avoid BRAM read-write conflicts and improve BRAM development efficiency. A timing control method and circuit for FPGA BRAM read-write conflicts are proposed.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A timing control method for read / write conflicts in FPGA BRAM is provided. When a read / write conflict exists, two timing circuits are used to generate the working timing: a first timing circuit and a second timing circuit. The FPGA initial clock is applied to the first timing circuit, which generates the read operation timing. After the read operation is completed in the first timing circuit, the second timing circuit is controlled to generate the write operation timing.

[0008] When there is no read / write conflict, the first sequential circuit completes the corresponding read or write operation.

[0009] After the first sequential circuit completes the read operation, the method to control the second sequential circuit to generate the write operation timing is to track the read operation duration of the first sequential circuit, and after the read operation tracking is completed, give a tracking completion trigger signal, and send the trigger signal to the second sequential circuit to make the second sequential circuit generate a working clock signal to start working.

[0010] The method for tracking the read operation duration of the first timing circuit is as follows: a tracking circuit is used to simulate and track the read and write duration of the corresponding memory address unit of the BRAM static random access memory array. The first working clock signal generated by the first timing circuit is input to the tracking circuit. After the tracking circuit completes the tracking, it gives a trigger signal and sends the trigger signal to the second timing circuit as the second working clock signal for the second timing circuit to start working.

[0011] The structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit;

[0012] The row decoding circuit is used to determine which row of cells in the storage array of the selected static random access memory is operating, and at the same time provides a signal to track the operating time of the cells in that row.

[0013] The row simulation tracking circuit uses n pairs of NMOS transistors to simulate the turn-on time of n cells in a row of the static random access memory array. The gates of the n pairs of NMOS transistors are connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal after the row decoding circuit determines which row of cells is working. The source and drain of the n pairs of NMOS transistors are connected to the ground signal. After the n pairs of NMOS transistors have finished charging, a row tracking completion feedback signal is given.

[0014] The column simulation tracking circuit uses m NMOS transistors to simulate the read and write operation time of a column of m cells in the storage array of static random access memory. The column tracking start signal is input to the source terminals of the m NMOS transistors respectively, and the gate and drain terminals of the m NMOS transistors are connected to the ground signal.

[0015] The column tracking start signal is triggered by the row tracking completion feedback signal.

[0016] The column tracking start signal completes tracking after charging m NMOS transistors, and provides a pull-down trigger signal.

[0017] Furthermore, it also includes a delay circuit, which delays the trigger signal when the second timing circuit starts writing after the first timing circuit has finished reading, so as to satisfy the timing control of the first timing circuit module to complete the timing of the read operation before entering the timing control of the write operation of the second timing circuit module.

[0018] Furthermore, when the FPGA initial clock is applied to the first timing circuit, it needs to be combined with the BRAM enable signal and the power-on reset signal to generate the first working clock signal.

[0019] The clock signal of the second sequential circuit is given by the trigger signal of the tracking circuit. The BRAM enable signal of the second sequential circuit is generated by combinational logic from the read-write conflict configuration bit, the read old number configuration bit, the read enable configuration bit, and the write configuration bit. The power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit. The second sequential circuit performs logical combination of the clock signal, the BRAM enable signal, and the power-on clear signal to generate the second working clock signal.

[0020] Furthermore, after the clock signals of the first and second sequential circuits, a pulse width control circuit is used to control the pulse width length of the clock signals when they are at a high level. The first clock signal generated by the first sequential circuit is processed by the first pulse width control circuit to form a first global clock signal. The first global clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a first trigger signal is given, the first trigger signal is input to the first pulse width control circuit to pull down the high level of the first global clock signal. The second clock signal generated by the second sequential circuit is processed by the second pulse width control circuit to form a second global clock signal. The second global clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a second trigger signal is given, the second trigger signal is input to the second pulse width control circuit to pull down the high level of the second global clock signal. The first trigger signal is also input to the delay circuit and then input to the second sequential circuit after delay.

[0021] Furthermore, the pulse width control circuit module structure includes a third inverter 3, a first inverter 1 with a low-level hold, and a second inverter 2 with a high-level hold. The output terminals of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output terminal of the third inverter 3 is a global working clock signal. The working clock signal is input to the second inverter 2, and the falling edge trigger signal is input to the first inverter 1.

[0022] Furthermore, the first inverter 1 with a low-level hold includes a fourth inverter 10 composed of a first NMOS transistor 11 and a first PMOS transistor 12, a second NMOS transistor 13 and a fifth inverter 14. The source terminal of the first NMOS transistor 11 is connected to the drain terminal of the second NMOS transistor 13, the source terminal of the second NMOS transistor 13 is grounded, and the output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS transistor 13. The output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global operating clock signal.

[0023] The second inverter 2 with a high-level hold includes a sixth inverter 20, a second PMOS transistor 23, and a seventh inverter 24, which are composed of a third NMOS transistor 21 and a third PMOS transistor 22. The source of the third PMOS transistor 22 is connected to the drain of the second PMOS transistor 23, and the source of the second PMOS transistor 23 is connected to the power supply. The output of the sixth inverter 20 is connected to the gate of the second PMOS transistor 23 after being connected to the seventh inverter 24. The output of the sixth inverter 20 is connected to the output of the fourth inverter 10 and then input to the third inverter 3 to form a global operating clock signal.

[0024] The present invention also provides a timing control circuit for FPGA BRAM read / write conflicts and a timing control method for FPGA BRAM read / write conflicts, comprising a first timing circuit module, a second timing circuit module, a delay circuit module, a configuration judgment circuit module, and a tracking circuit module;

[0025] The first timing circuit module forms a first working clock signal that enables the BRAM to start working by combining the rising edge of the original clock signal with the BRAM working enable signal and the power-on clear signal signal in combination with the combinational logic switches;

[0026] The configuration judgment circuit module is used to determine which type of conflicting configuration bit it is, and together with the write configuration bit, it passes through a combinational logic switch to form the working enable signal of the second timing circuit module;

[0027] The tracking circuit module is used to simulate and track the read and write duration of the corresponding memory address unit of the static random access memory array of the BRAM. The first working clock signal generated by the first timing circuit module is input to the tracking circuit to start simulating and tracking the read and write duration of the corresponding memory address unit of the static random access memory array. After the tracking is completed, a trigger signal is given. The trigger signal is input to the delay circuit as the clock signal of the second timing circuit.

[0028] The second sequential circuit module is used to form a second working clock signal that enables the BRAM to start working when the clock signal rises and the BRAM working enable signal and the power-on clear signal are combined with the combinational logic switches. The power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit.

[0029] The delay circuit is used to delay the trigger signal for a certain period of time before inputting the clock signal of the second timing circuit.

[0030] Furthermore, the operating clock signals of the first timing circuit module and the second timing circuit module are each passed through a pulse width control circuit to control the pulse width length of the operating clock signal at the high level. The first operating clock signal generated by the first timing circuit module, after passing through the first pulse width control circuit, forms a first global operating clock signal. The first global operating clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a first trigger signal is given, the first trigger signal is input to the first pulse width control circuit to pull down the high level of the first global operating clock. The second operating clock signal generated by the second timing circuit module, after passing through the second pulse width control circuit, forms a second global operating clock signal. The second global operating clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a second trigger signal is given, the second trigger signal is input to the second pulse width control circuit to pull down the high level of the second global operating clock signal. The first trigger signal is also input to the delay circuit and, after delay, is input to the second timing circuit.

[0031] By adopting the above technical solution, the present invention has the following beneficial effects:

[0032] This invention provides a timing control method and circuit for FPGA BRAM read / write conflicts. When a read / write conflict occurs, two timing circuits are used to generate the working timing. The initial clock is applied to the first timing circuit, which generates the read operation timing. After the read operation is completed by the first timing circuit, the second timing circuit is controlled to generate the write operation timing. This achieves the goal of using a single timing path to control read and write operations, avoiding contention caused by read / write conflicts, and improving the memory access efficiency of the BRAM. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the timing circuit control structure of the present invention;

[0034] Figure 2 A schematic diagram showing the pulse width for reading and writing completed within one cycle of the original clock.

[0035] Figure 3 This is a schematic diagram of the tracking circuit structure;

[0036] Figure 4 This is a schematic diagram of an SRAM storage array;

[0037] Figure 5 This is a schematic diagram of the structure of a cell in an SRAM memory array.

[0038] Figure 6 Schematic diagram of the line tracking circuit;

[0039] Figure 7 This is a schematic diagram of the column tracking circuit structure;

[0040] Figure 8 A schematic diagram of adding a pulse width control circuit after a timing circuit;

[0041] Figure 9 This is a schematic diagram of the timing control circuit module circuit structure;

[0042] Figure 10 This is a schematic diagram of the timing control circuit module;

[0043] Figure 11 This is a schematic diagram of the timing control circuit structure of the present invention;

[0044] Figure 12 This is a schematic diagram illustrating the operation of the row tracking start signal and the column tracking start signal. Detailed Implementation

[0045] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Figures 1 to 12This illustration shows a specific embodiment of a timing control method for FPGA BRAM read / write conflicts according to the present invention. When a read / write conflict exists, two timing circuits are used to generate the working timing sequence: a first timing circuit and a second timing circuit. The FPGA initial clock is applied to the first timing circuit, which generates the read operation timing sequence. After the read operation is completed by the first timing circuit, the second timing circuit is controlled to generate the write operation timing sequence. When there is no read / write conflict, the first timing circuit completes the corresponding read or write operation. By using two timing circuits, after the first timing circuit completes the read operation, the second timing circuit is then controlled to perform the write operation, achieving the goal of using a single timing path to control read and write operations, avoiding contention caused by read / write conflicts, and improving the memory access efficiency of the BRAM. In this embodiment, when the FPGA initial clock is applied to the first timing circuit, it needs to be logically combined with the BRAM enable signal (men) and the power-on reset signal (por_reset) to generate the first working clock signal (clk1). The clock signal of the second timing circuit is given by the trigger signal of the tracking circuit, as shown in Table 1. The BRAM enable signal (men) of the second timing circuit is generated by combinational logic of the read-write conflict configuration bit (mix_old_data), the read old data configuration bit (read_old_data), the read enable configuration bit (read_enable), and the write configuration bit (wen). Whenever there is a conflict bit, and the write configuration bit is 1, the timing path generated by the second timing circuit needs to be selected. The power-on reset signal (por_reset) of the second timing circuit is connected to the power-on reset signal of the first timing circuit. The second timing circuit logically combines the clock signal, the BRAM enable signal (men), and the power-on reset signal (por_reset) to generate the working clock signal, as shown in Table 1. Figure 2 As shown, within one cycle of the original clock (clk), the read enable signal (read) is given first, and the write configuration bit enable signal (wen) is given after reading. WL is the SRAM word line signal. The first pulse is the pulse width of the read, the second pulse is the pulse width of the write, and the width between the two pulses is the width of the delay module.

[0047] Table 1 Selection of the first and second sequential circuits under read / write conflicts.

[0048]

[0049] In this embodiment, as Figure 1As shown, after the first sequential circuit completes a read operation, the method for controlling the second sequential circuit to generate a write operation timing sequence is to track the read operation duration of the first sequential circuit. After the read operation tracking is completed, a first trigger signal (Rstb1) is given, and this first trigger signal is sent to the second sequential circuit, causing the second sequential circuit to generate a working clock signal to start working. The method for tracking the read operation duration of the first sequential circuit is as follows: a tracking circuit is used to simulate and track the read and write durations of the corresponding memory address cells of the BRAM SRAM memory array. The working clock signal generated by the first sequential circuit is input to the tracking circuit. After the tracking circuit completes the tracking, it gives a first trigger signal, which is then sent to the second sequential circuit. By simulating and tracking the read and write durations of the SRAM memory cells, the duration of the read operation of the SRAM memory cell can be determined, and a trigger signal is given after the tracking is completed, causing the second sequential circuit to start working and perform a write operation.

[0050] In this embodiment, as Figure 3 As shown, the structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit;

[0051] The row decoding circuit is used to determine which row of cells in the static random access memory (SRAM) array is operating, and to provide a signal to track the operating time of the cells in that row.

[0052] like Figure 4 As shown, the SRAM memory array has m rows and n columns; Figure 5 and Figure 6 As shown, the row analog tracking circuit uses n pairs of NMOS transistors to simulate the turn-on time of n cells in a row of the word line (WL) in the SRAM memory array. The gates of the n pairs of NMOS transistors are connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal after the row decoding circuit determines which row of cells is working. The sources and drains of the n pairs, i.e., 2n NMOS transistors, are all connected to the ground signal. After the n pairs of NMOS transistors have finished charging, a row tracking completion feedback signal is given to trigger the column tracking start signal.

[0053] like Figure 7 The column simulation tracking circuit shown uses m NMOS transistors to simulate the read / write operation time of a column of m cells in an SRAM memory array. The column tracking start signal is input to the source terminals of the m NMOS transistors respectively, and the gates and drains of the m NMOS transistors are connected to the ground signal. The column tracking start signal is triggered by the row tracking completion feedback signal. The column tracking start signal is given after the tracking is completed by charging the m NMOS transistors and a pull-down level trigger signal is given.

[0054] In this embodiment, it is necessary to pre-calculate the number of rows m and columns n of the SRAM storage array in the BRAM before tracking, such as... Figure 4 As shown, the number of NMOS transistors used in the tracking circuit can be determined based on the number of rows m and the number of columns n. Figure 3 In the process, the timing circuit module generates the rising edge of the working clock (clk1). When the rising edge of the working clock (clk1) arrives, the row decoding circuit determines which row of the SRAM memory array in the BRAM needs to be selected to operate. On one hand, it provides a word line (WL) to enable the cell in the selected row of the SRAM. On the other hand, the row decoding circuit simultaneously provides a row tracking signal TKWL1 to start the row analog tracking circuit, which is used to simulate the operating duration of the word line. Therefore, the row analog tracking circuit is also called the WL tracking circuit. Figure 12 As shown, the row decoding circuit uses a commonly used row decoding circuit, which generates m rows of word line WL signals by encoding x bits of row address, where the relationship between x and m is... While the row decoding circuit encodes the x-bit row address to generate the m-row word line WL signal, it triggers the row tracking start signal TKWL1 to start row tracking simulation, so that row tracking simulation begins at the same time the word line WL opens a row of cells in the SRAM memory array.

[0055] In this embodiment, as Figure 5 The diagram shows the structure of a cell in an SRAM memory array. When the word line is high, a pair of NMOS transistors, PGL0 and PGR0, are turned on in one cell. To simulate the time it takes for all NMOS transistors in a row to be turned on by the word line, and considering that there are n cells in a row as previously counted, the row simulation tracking circuit is as follows: Figure 6 The diagram illustrates the use of n pairs of NMOS transistors to simulate the turn-on time of n cells on a single word line. The gates of each pair of NMOS transistors are connected to the row tracking start signal TKWL1, and the sources and drains of all n pairs (2n NMOS transistors) are connected to the ground signal Tielow. When the row tracking start signal is high, the n pairs of NMOS transistors begin charging; completion of charging indicates the simulation of the turn-on time of each cell is complete. In this embodiment, Figure 6 In the Bank of China's tracking analog circuit, grounding the source and drain of the NMOS transistor is a method of simulating the cell wiring in an SRAM memory array. In this embodiment, the capacitance between the source and gate is used to simulate the parasitic capacitance at the BL bit line in the cell; it has no functional purpose, only a charging and discharging function. For example... Figure 12As shown, after the row tracking simulation is completed, the row tracking completion feedback signal TKWLFB1 is given to trigger the column tracking start signal TKBL1. The column tracking start signal starts to simulate tracking the bit line (BL) in the SRAM memory array. Therefore, the column tracking circuit is also called the BL tracking circuit. Figure 12 The feedback signal TKWLFB1, indicating the completion of row tracking, is given by passing through two inverters to trigger the column tracking start signal TKBL1. The use of two inverters is to enhance the driving force.

[0056] Figure 4 In this circuit, each bit line is input from the source terminal of the NMOS transistor PGL0, so the column analog tracking circuit is as follows: Figure 7 The diagram illustrates the simulation of read / write operation time for the PGL0 NMOS transistor in a column of m cells (m rows, m cells) of an SRAM memory array, using m NMOS transistors. Figure 4 The BL and BLN bits carry a pair of opposite data, which arrive simultaneously and are time-consistent. Therefore, it is not necessary to simulate BLN for PGR0. When the SRAM is working, after the row decoding circuit selects to open all cells in a word line of a certain row, the column decoding circuit simultaneously opens the corresponding bit lines according to the number of bits of data to be written. Therefore, the read / write time of multiple columns is consistent with that of a single column, so it can be simulated using m NMOS transistors in a column. The column tracking start signal TKBL1 is input to the source of the m NMOS transistors, and the gate and drain are connected to the ground signal Tielow. The reason for this design is that in this embodiment, the m NMOS transistors only use the capacitance between the source and gate to simulate the parasitic capacitance at the BL bit line in the cell. They have no functional role, only charging and discharging. The connection of the gate to the ground signal Tielow keeps the NMOS transistor in a non-conducting state. Secondly, from Figure 5As shown in the cell diagram, the values ​​of points Q and QB are always 0 and 1 respectively. Therefore, the drain of one of the PGL0 and PGR0 NMOS transistors is always connected to 0. Since the cell is symmetrical, the PGL0 and PGR0 NMOS transistors operate simultaneously. Therefore, simulating the cell's operation time only requires simulating one side of the NMOS transistors. Thus, in the column tracking circuit, the drain of the NMOS transistor is also connected to the ground signal tielow. In the SRAM memory array, the BL bit line connects to the source of the NMOS transistors. Therefore, in this embodiment, the column tracking start signal TKBL1 connects to the sources of m NMOS transistors. Furthermore, since the BRAM operates by only turning on one row of the SRAM memory array at a time, only one of the m PGL0 NMOS transistors on the BL bit line will be turned on, while the gates of the other m-1 PGL0 NMOS transistors will be turned off with a low voltage. In this embodiment, since the number of rows m of cells in the SRAM is a large value of hundreds during the design, and given that hundreds of NMOS transistors are used in the same way, the time required for one NMOS transistor to conduct its gate is very close to the time required for charging using the source-gate capacitor when one NMOS transistor's gate is not conducting. Therefore, m NMOS transistors with their gates connected to tielow are used to simulate m rows of cells. The column tracking start signal completes tracking after charging the m NMOS transistors. After the column simulation tracking is completed, a trigger signal (Rstb1) is given to pull down the high-level global clock signal (clkint1) when tracking is complete. When the trigger signal (Rstb1) is low, the global clock signal (clkint1) is pulled down to low, thus completing the pulse width control.

[0057] from Figure 3 It can also be seen that BRAM is completely symmetrical. Before using BRAM, it is necessary to configure whether to use single-port or dual-port. In the case of single-port, the tracking circuit on the corresponding side of the port can be used for tracking. WL, BL and global clock signal (clkint1) can be used, or WR, BR and global clock signal (clkint2) can be used. If dual-port is configured, the tracking circuits on both sides need to be used to track the ports on each side respectively.

[0058] In this embodiment, as Figure 1 As shown, in order to prevent the read operation from being incomplete when the trigger signal generated by the tracking circuit enters the second timing circuit, a delay circuit is also used. This delays the first trigger signal when the first timing circuit gives the first trigger signal to start writing after the first timing circuit has finished reading, so as to satisfy the timing control of the first timing circuit module to ensure that the timing of the read operation is fully completed before the timing control of the write operation of the second timing circuit module is entered.

[0059] In this embodiment, after the clock signals of the first and second timing circuits, a pulse width control circuit is also applied, such as... Figure 8 , Figure 9 and Figure 10 As shown, the pulse width length of the working clock signal at a high level is controlled. The first working clock signal (clk1) generated by the first timing circuit is processed by the first pulse width control circuit to form the first global working clock signal (clkint1). The first global working clock signal (clkint1) is input to the tracking circuit. When the simulated tracking of the read / write duration of the corresponding memory address cell of the BRAM SRAM memory array is completed and a trigger signal (Rstb1) is given, the trigger signal (Rstb1) is input to the first pulse width control circuit to pull down the high level of the global working clock (clkint1). The second timing circuit... The generated second working clock signal (clk2) is processed by the second pulse width control circuit to form the second global working clock signal (clkint2). The second global working clock signal (clkint2) is input to the tracking circuit. When the simulation tracking of the read / write duration of the corresponding memory address cell in the BRAM SRAM memory array is completed and the second trigger signal (Rstb2) is given, the second trigger signal (Rstb2) is input to the second pulse width control circuit to pull down the high level of the global working clock (clkint2). The first trigger signal (Rstb1) is also input to the delay circuit and, after delay, is input to the second timing circuit. The first timing circuit and the first pulse width control circuit are referred to as the first timing control circuit, and the second timing circuit and the second pulse width control circuit are referred to as the second timing control circuit.

[0060] In this embodiment, as Figure 8 As shown, the pulse width control circuit module structure includes a third inverter 3, a first inverter 1 with a low-level hold, and a second inverter 2 with a high-level hold. The output terminals of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output terminal of the third inverter 3 is a global working clock signal (clk1). The working clock signal (clk1) is input to the second inverter 2, and the falling edge trigger signal is input to the first inverter 1.

[0061] The first inverter 1 with a low-level hold includes a fourth inverter 10 composed of a first NMOS transistor 11 and a first PMOS transistor 12, a second NMOS transistor 13, and a fifth inverter 14. The source terminal of the first NMOS transistor 11 is connected to the drain terminal of the second NMOS transistor 13, and the source terminal of the second NMOS transistor 13 is grounded. The output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS transistor 13. The output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global operating clock signal (clkint1).

[0062] The second inverter 2 with a high-level hold includes a sixth inverter 20, a second PMOS transistor 23, and a seventh inverter 24, which are composed of a third NMOS transistor 21 and a third PMOS transistor 22. The source of the third PMOS transistor 22 is connected to the drain of the second PMOS transistor 23, and the source of the second PMOS transistor 23 is connected to the power supply. The output of the sixth inverter 20 is connected to the gate of the second PMOS transistor 23 after being connected to the seventh inverter 24. The output of the sixth inverter 20 is connected to the output of the fourth inverter 10 and then input to the third inverter 3 to form a global operating clock signal (clkint1).

[0063] By using a pulse width control (PWM) circuit module, the length of the high level of the global operating clock signal (clkint1) can be controlled. The specific working principle is as follows: when clk1 is high, it is converted to a low level by the sixth inverter 20. Figure 8 As can be seen, clkintb1 is currently at a low level. Therefore, the low-level output signal (clkintb1) of the sixth inverter 20 becomes a high level after passing through the seventh inverter 24, turning off the second PMOS transistor 23. Meanwhile, in the first inverter 1 with a low-level sustainer, the low-level signal (clkintb1) is input to the fifth inverter 14 and becomes a high level, turning on the second NMOS transistor 13. Since the source of the second NMOS transistor 13 is grounded, the output signal (clkintb1) of the sixth inverter 20 remains at a low level. This low-level signal (clkintb1), after passing through the inverter, becomes the global clock signal (clkint1), which remains at a high level.

[0064] This invention also provides a timing control circuit for FPGA BRAM read / write conflicts, using the timing control method for FPGA BRAM read / write conflicts described above, such as... Figure 1 As shown, it includes a first timing circuit module, a second timing circuit module, a delay circuit module, a configuration judgment circuit module, and a tracking circuit module;

[0065] The first timing circuit module forms a first working clock signal (clk1) that enables the BRAM to start working by combining the rising edge of the original clock signal (clk) with the BRAM working enable signal (men) and the power-on reset signal (por_reset) under the combination of combinational logic switches.

[0066] The configuration judgment circuit module is used to determine which type of conflicting configuration bit it is, and together with the write configuration bit, it forms the working enable signal (men) of the second timing circuit module through combinational logic switches. In this embodiment, the conflicting configuration bits include the read-write conflicting configuration bit (mix_old_data), the read old data configuration bit (read_old_data), the read enable configuration bit (read_enable), and the write configuration bit (wen), which are generated after combinational logic. When using the second timing circuit, the write configuration bit (wen) is 1.

[0067] The tracking circuit module is used to simulate and track the read and write duration of the corresponding memory address unit of the SRAM memory array of the BRAM. The first working clock signal (clk1) generated by the first timing circuit module is input to the tracking circuit to start simulating and tracking the read and write duration of the corresponding memory address unit of the SRAM memory array. After the tracking is completed, a first trigger signal (Rstb1) is given. The first trigger signal (Rstb1) is input to the delay circuit as the clock signal (clk) of the second timing circuit.

[0068] The second sequential circuit module is used to form a second working clock signal (clk2) that enables the BRAM to start working when the rising edge of the clock signal (clk) is combined with the BRAM working enable signal (men) and the power-on reset signal (por_reset) under the combination of combinational logic switches. The power-on reset signal (por_reset) of the second sequential circuit is connected to the power-on reset signal (por_reset) of the first sequential circuit.

[0069] The delay circuit is used to input the clock signal of the second timing circuit after delaying the trigger signal (Rstb1) by a certain amount.

[0070] like Figure 11As shown, the operating clock signals of the first and second timing circuit modules also pass through a pulse width control circuit to control the pulse width length of the operating clock signal at the high level. The first operating clock signal (clk1) generated by the first timing circuit module, after passing through the first pulse width control circuit, forms the first global operating clock signal (clkint1). The first global operating clock signal (clkint1) is input to the tracking circuit. When the simulation tracking of the read / write duration of the corresponding memory address cell of the BRAM SRAM memory array is completed and the first trigger signal (Rstb1) is given, the first trigger signal (Rstb1) is input to the first pulse width control circuit to convert the first global operating clock signal... The high level of (clkint1) is pulled down, and the second working clock signal (clk2) generated by the second timing circuit module is processed by the second pulse width control circuit to form the second global working clock signal (clkint2). The second global working clock signal (clkint2) is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding storage address cell of the BRAM storage array is completed and the second trigger signal (Rstb2) is given, the second trigger signal (Rstb2) is input to the second pulse width control circuit to pull down the high level of the second global working clock signal (clkint2). The first trigger signal (Rstb1) is also input to the delay circuit and then input to the second timing circuit after the delay.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timing control method for FPGA BRAM read / write conflicts, characterized in that, When read / write conflicts exist, two timing circuits are used to generate the working timing sequence: a first timing circuit and a second timing circuit. The FPGA initial clock is applied to the first timing circuit, which generates the read operation timing sequence. After the read operation is completed in the first timing circuit, the second timing circuit is controlled to generate the write operation timing sequence. When there is no read / write conflict, the first sequential circuit completes the corresponding read or write operation. After the first sequential circuit completes the read operation, the method to control the second sequential circuit to generate the write operation timing is to track the read operation duration of the first sequential circuit, and after the read operation tracking is completed, give a tracking completion trigger signal, and send the trigger signal to the second sequential circuit to make the second sequential circuit generate a working clock signal to start working. The method for tracking the read operation duration of the first timing circuit is as follows: a tracking circuit is used to simulate and track the read and write duration of the corresponding memory address unit of the BRAM static random access memory array. The first working clock signal generated by the first timing circuit is input to the tracking circuit. After the tracking circuit completes the tracking, it gives a trigger signal and sends the trigger signal to the second timing circuit as the second working clock signal for the second timing circuit to start working. The structure of the tracking circuit includes a row decoding circuit, a row analog tracking circuit, and a column analog tracking circuit; The row decoding circuit is used to determine which row of cells in the storage array of the selected static random access memory is operating, and at the same time provides a signal to track the operating time of the cells in that row. The row simulation tracking circuit uses n pairs of NMOS transistors to simulate the turn-on time of n cells in a row of the static random access memory array. The gates of the n pairs of NMOS transistors are connected to the row tracking start signal. The row tracking start signal is generated by the global working clock signal after the row decoding circuit determines which row of cells is working. The source and drain of the n pairs of NMOS transistors are connected to the ground signal. After the n pairs of NMOS transistors have finished charging, a row tracking completion feedback signal is given. The column simulation tracking circuit uses m NMOS transistors to simulate the read and write operation time of a column of m cells in the storage array of static random access memory. The column tracking start signal is input to the source terminals of the m NMOS transistors respectively, and the gate and drain terminals of the m NMOS transistors are connected to the ground signal. The column tracking start signal is triggered by the row tracking completion feedback signal. The column tracking start signal completes tracking after charging m NMOS transistors, and provides a pull-down trigger signal.

2. The method according to claim 1, characterized in that, It also includes a delay circuit, which delays the trigger signal when the second timing circuit starts writing after the first timing circuit finishes reading, so as to satisfy the timing control of the first timing circuit module to complete the timing of the read operation before entering the timing control of the second timing circuit module for the write operation.

3. The method according to claim 2, characterized in that, When the FPGA initial clock is applied to the first timing circuit, it needs to be combined with the BRAM enable signal and the power-on reset signal to generate the first working clock signal. The clock signal of the second sequential circuit is given by the trigger signal of the tracking circuit. The BRAM enable signal of the second sequential circuit is generated by combinational logic from the read-write conflict configuration bit, the read old number configuration bit, the read enable configuration bit, and the write configuration bit. The power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit. The second sequential circuit performs logical combination of the clock signal, the BRAM enable signal, and the power-on clear signal to generate the second working clock signal.

4. The method according to claim 3, characterized in that, After the clock signals of the first and second sequential circuits, a pulse width control circuit is used to control the pulse width length of the clock signals at the high level. The first clock signal generated by the first sequential circuit is processed by the first pulse width control circuit to form a first global clock signal. The first global clock signal is input to the tracking circuit. When the simulation tracking of the read / write duration of the corresponding memory address cell of the BRAM static random access memory array is completed and a first trigger signal is given, the first trigger signal is input to the first pulse width control circuit to pull down the high level of the first global clock signal. The second clock signal generated by the second sequential circuit is processed by the second pulse width control circuit to form a second global clock signal. The second global clock signal is input to the tracking circuit. When the simulation tracking of the read / write duration of the corresponding memory address cell of the BRAM static random access memory array is completed and a second trigger signal is given, the second trigger signal is input to the second pulse width control circuit to pull down the high level of the second global clock signal. The first trigger signal is also input to the delay circuit and then input to the second sequential circuit after delay.

5. The method according to claim 4, characterized in that, The pulse width control circuit module structure includes a third inverter (3), a first inverter (1) with a low-level hold, and a second inverter (2) with a high-level hold. The output terminals of the first inverter (1) and the second inverter (2) are connected to the third inverter (3). The output terminal of the third inverter (3) is the global working clock signal. The working clock signal is input to the second inverter (2), and the falling edge trigger signal is input to the first inverter (1).

6. The method according to claim 5, characterized in that, The first inverter (1) with a low-level hold includes a fourth inverter (10) composed of a first NMOS transistor (11) and a first PMOS transistor (12), a second NMOS transistor (13) and a fifth inverter (14). The source of the first NMOS transistor (11) is connected to the drain of the second NMOS transistor (13), the source of the second NMOS transistor (13) is grounded, and the output of the fourth inverter (10) is connected to the gate of the second NMOS transistor (13) after being connected to the fifth inverter (14). The output of the fourth inverter (10) is connected to the output of the second inverter (2) and then input to the third inverter (3) to form a global working clock signal. The second inverter (2) with a high-level hold includes a sixth inverter (20) composed of a third NMOS transistor (21) and a third PMOS transistor (22), a second PMOS transistor (23) and a seventh inverter (24). The source of the third PMOS transistor (22) is connected to the drain of the second PMOS transistor (23), the source of the second PMOS transistor (23) is connected to the power supply, and the output of the sixth inverter (20) is connected to the gate of the second PMOS transistor (23) after being connected to the seventh inverter (24). The output of the sixth inverter (20) is connected to the output of the fourth inverter (10) and then input to the third inverter (3) to form a global working clock signal.

7. A timing control circuit for FPGA BRAM read / write conflicts, using the timing control method for FPGA BRAM read / write conflicts as described in any one of claims 1 to 6, characterized in that, It includes a first timing circuit module, a second timing circuit module, a delay circuit module, a configuration judgment circuit module, and a tracking circuit module; The first timing circuit module forms a first working clock signal that enables the BRAM to start working by combining the rising edge of the original clock signal with the BRAM working enable signal and the power-on clear signal in combinational logic switches. The configuration judgment circuit module is used to determine which type of conflicting configuration bit it is, and together with the write configuration bit, it passes through a combinational logic switch to form the working enable signal of the second timing circuit module; The tracking circuit module is used to simulate and track the read and write duration of the corresponding memory address unit of the static random access memory array of the BRAM. The first working clock signal generated by the first timing circuit module is input to the tracking circuit to start simulating and tracking the read and write duration of the corresponding memory address unit of the static random access memory array. After the tracking is completed, a trigger signal is given. The trigger signal is input to the delay circuit as the clock signal of the second timing circuit. The second sequential circuit module is used to form a second working clock signal that enables the BRAM to start working when the clock signal rises and the BRAM working enable signal and the power-on clear signal are combined with the combinational logic switches. The power-on clear signal of the second sequential circuit is connected to the power-on clear signal of the first sequential circuit. The delay circuit is used to delay the trigger signal for a certain period of time before inputting the clock signal of the second timing circuit.

8. The timing control circuit according to claim 7, characterized in that, The operating clock signals of the first and second timing circuit modules are also passed through a pulse width control circuit to control the pulse width length of the operating clock signal at the high level. The first operating clock signal generated by the first timing circuit module is processed by the first pulse width control circuit to form a first global operating clock signal. The first global operating clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a first trigger signal is given, the first trigger signal is input to the first pulse width control circuit to pull down the high level of the first global operating clock. The second operating clock signal generated by the second timing circuit module is processed by the second pulse width control circuit to form a second global operating clock signal. The second global operating clock signal is input to the tracking circuit. When the reading and writing duration simulation tracking of the corresponding memory address unit of the BRAM static random access memory array is completed and a second trigger signal is given, the second trigger signal is input to the second pulse width control circuit to pull down the high level of the second global operating clock signal. The first trigger signal is also input to the delay circuit and then input to the second timing circuit after delay.

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