A design method for high-yield magnetic random access memory system under irradiation conditions

Abstract

The present invention discloses a method for designing a magnetic random access memory system with high yield under irradiation conditions. The method is based on a 2T-2M self-reference structure, combined with a Hamming code-based error detection and correction circuit and a built-in self-test-self-repair system, to detect and repair soft and hard errors, suppress the occurrence of soft and hard errors under irradiation conditions, and effectively improve the yield of the memory. The built-in self-test-self-repair system includes a built-in self-test circuit with a fault diagnosis function and a built-in redundant self-repair circuit, and the sequential logic unit in the system calls a sequential logic standard unit library designed using a dual-mode redundant radiation-resistant reinforcement method.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a design method for a magnetic random access memory system with high yield under irradiation conditions. Background Art

[0002] With the rapid development of electronic technology, the application scope of integrated circuits has been continuously expanded, covering not only conventional environments, but also extreme conditions such as high pressure, high temperature, toxic or corrosive gases, and special scenarios such as strong radiation. In most harsh environments, the reliable operation of electronic products can be ensured by optimizing packaging technology. However, in a radiation environment, integrated circuits are susceptible to the effects of high-energy photons and particles, resulting in ionization and collision, which can cause irreversible damage to packaged semiconductor devices. At this time, traditional packaging and shielding often have limited effects, and may even aggravate the damage of radiation to the circuit due to secondary reactions caused in the packaging materials. Therefore, radiation-resistant technology for radiation environments has become a key research direction for improving the yield of integrated circuits. With the rapid development of the aerospace and nuclear industries, especially the booming growth of the satellite industry, higher requirements are placed on the radiation-resistant design of memory. Although the design of radiation-resistant logic circuits is relatively mature, the radiation-resistant design of memory is still a weak link in current technology. Memory faces multiple challenges in the development of radiation-resistant electronic products. The action of high-energy particles can cause soft and hard errors: on the one hand, soft errors such as single-particle upset and single-particle functional interruption will temporarily change the value of stored data, causing the potential of sensitive nodes to flip; on the other hand, hard errors such as single-particle burnout and single-particle gate penetration will cause permanent damage to the circuit and cannot be recovered. Therefore, a system-level yield improvement solution is needed to effectively deal with the challenges of soft and hard errors brought by the radiation environment.

[0003] As the core storage element of MRAM, the magnetic tunnel junction uses the electron spin characteristics to store data instead of the traditional charge storage method. Therefore, there is no known direct interaction mechanism between it and ionizing radiation, and it exhibits high radiation tolerance. However, the peripheral circuits of MRAM (such as read and write circuits) are usually composed of traditional CMOS transistors. Therefore, MRAM may still be affected by radiation or high-energy particles, but its failure rate is relatively reduced. It is worth noting that MRAM also has some unique transient failure sources, such as random switching of MTJ, thermal fluctuations and read interference, which make its transient failure problem more significant than traditional CMOS-based circuits. Therefore, in order to improve the overall yield of the system in a radiation environment, it is urgent to carry out radiation hardening (RH) optimization design at the system level. Through the collaborative work of various circuits, the impact of soft errors and hard errors can be effectively alleviated, and the radiation resistance and yield of the system can be enhanced. Summary of the invention

[0004] The present invention aims to provide a radiation-resistant system-level design method for magnetic random access memory, detect and repair soft errors and hard errors caused by radiation, so as to improve the reliability of MRAM in a radiation environment.

[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0006] A high-yield magnetic random access memory system method under irradiation conditions. The embedded magnetic random access memory (Magnetoresistive Random Access Memory, MRAM) is based on a 2T-2M self-reference structure, which realizes on-chip fault detection and repair under irradiation environment, thereby improving chip yield. A system-level design scheme is proposed to improve the yield under irradiation environment. Combined with the error checking and correction based on BCH code, the error checking and correction based on BCH code is realized. The ECC circuit and the BISTR system are used to detect and repair soft and hard errors. The BISTR system includes a BIST circuit and a BISR circuit with fault diagnosis function. The sequential logic unit in the system adopts a dual-mode redundant radiation-resistant reinforcement method and is replaced by a sequential logic standard unit in a dual-mode redundant radiation-resistant standard unit library. The ECC circuit works in conjunction with the BIST system to minimize soft and hard errors in the radiation environment and improve the MRAM yield.

[0007] The 2T-2M self-reference structure is composed of two groups of magnetic tunnel junctions (MTJ) and NMOS gate tubes connected in series, that is, two groups of 1T-1M storage units, in which the states of the two magnetic tunnel junctions are completely opposite; a word line (WL) controls the gates of the two groups of gate tubes at the same time, and realizes data storage through the opposite voltages of two groups of bit lines (BL) and source lines (SL); the structure uses two MTJs to store one bit unit data, and two combination states (parallel state-antiparallel state and antiparallel state-parallel state) represent data "0" and "1" respectively;

[0008] The error detection and correction ECC circuit adopts the encoding method of Hamming code, which can realize 1-bit correction and 2-bit error detection for 8-bit. Its specification is (13, 8) Hamming code, in which the data bit is 8-bit, the check bit is 5-bit, and the total codeword is 13-bit. The ECC error correction algorithm is implemented by combining the encoding module (EHC_13_8_Encoder) and the decoding module (EHC_13_8_Decoder) with the MRAM peripheral circuit. The output error correction flag bit UE and the error flag bit ERRF are combined to indicate whether an error occurs in the data bit and whether the error is corrected.

[0009] In the built-in self-test (BIST) circuit, the core module includes a controller (CTRL), a test pattern generator (TPG) and a fault location indicator (FSI); wherein the CTRL is responsible for controlling the test module; the TPG generates test data and addresses based on the test algorithm in the test mode; after the TPG generates the test vector, the FSI compares and analyzes the read data of the memory to confirm whether a fault occurs; there is also a group of multiplexers BIST_MUX in the BIST, which switches between the BIST test mode and the normal operation mode under the control of the BIST_EN signal; when performing the BIST test, the multiplexer sends the test vector generated by the TPG to the MRAM Macro to form a test loop; in the normal mode, the multiplexer directly inputs the external read and write control signal into the MRAM Macro for read and write operations;

[0010] The built-in redundant self-repair circuit, i.e., the column redundant replacement circuit, is mainly composed of two parts; first, the bit line mapping module of the storage array and the self-reference column. In the actual physical layout, the storage cells of two adjacent columns constitute a 2T-2M unit and store 1-bit data. Therefore, when performing column redundant replacement, the two columns must be replaced at the same time; the bit line mapping module of the storage array and the self-reference array has the same structure, both of which are composed of 7 2-to-1 MUXs, and the configuration signal CFG[8:14] is used as the address selection end to map the bit line connection relationship of the array; second, the source line mapping module of the storage array and the self-reference array has the same structure as the bit line mapping module, but it is composed of 8 2-to-1 MUXs, and is controlled by the configuration signal CFG[0:7] to map the source line connection relationship of the array.

[0011] Furthermore, an error detection and correction ECC circuit based on Hamming code is adopted. This design can realize one-correction-two-check, thereby effectively correcting temporary soft errors caused by irradiation; the error detection and correction ECC circuit is based on an MRAM array with a reconfigurable bit width of 8-bit / 16-bit / 24-bit / 32-bit, and can independently control the reading and writing of each byte of data and the encoding and decoding of the ECC circuit through control signals, thereby reducing power consumption and maximizing the ECC error correction capability when storing small data bit widths; in the encoding module, DIN[7:0] is the input 8-bit data, Bypass is the ECC bypass signal (when Bypass=1, ECC encoding and decoding operations are not performed, and the storage unit corresponding to the ECC check bit is not read or written), and DOUT[12:0] is the encoded 13-bit codeword (8-bit data and 5-bit check code) transmitted to the write driver module of the array for writing. In the decoding module, DIN[12:0] is the 13-bit codeword read by the sensitive amplifier from the storage array, Bypass is the ECC bypass signal, DOUT[7:0] is the data after error correction, ERRF is the error flag, marking whether the codeword is detected to be illegal, and UE is the error correction flag, marking whether the codeword is corrected.

[0012] Furthermore, the built-in self-test (BIST) circuit works in conjunction with the error detection and correction (ECC) circuit to detect hard errors that cannot be repaired by the ECC circuit by means of timed activation, and to diagnose the type and address of faulty cells in the array. Since the main source of failure in CMOS circuits is transient failure caused by radiation effects or high-energy ionized particles, detection of array failures is particularly important. The BIST circuit has a built-in March C+ test algorithm lookup table that can test all types of failures in the memory, such as fixed failures, coupling failures, and conversion failures. When performing a BIST test, the multiplexer sends the test vectors generated by the TPG to the MRAM Macro to form a test loop. In normal mode, the multiplexer directly inputs external read and write control signals into the MRAM Macro for read and write operations, realizing switching between test mode and normal mode.

[0013] Furthermore, the specific steps of replacing the sequential logic unit in the built-in self-test BIST circuit with the sequential logic standard unit in the dual-mode redundant radiation-resistant standard unit library are as follows: the sequential logic unit of the built-in self-test BIST circuit is reinforced against radiation by adopting dual-mode redundant method, that is, the transmission gate and the inverter are combined together to form a vertically stacked transistor structure; two radiation-resistant inverters are added to the reinforced structure to generate a clock signal that is in phase with the clock signal and its inverted signal but is independent of each other, so as to prevent charge sharing after the single clock signal is affected by radiation.

[0014] Furthermore, the sequential logic standard cell library in the built-in self-test (BIST) circuit filters out glitches during signal transmission, can resist interference from single particle effects in an irradiated environment, and ensure the reliability of the BIST as a self-detection circuit itself; compared with the traditional three-mode redundancy method, the dual-mode redundancy anti-irradiation reinforcement method does not need to replicate the circuit module to be reinforced three times, nor does it need to add a voting circuit, which can save more area and power consumption, while avoiding additional failures caused by unprocessable soft errors in the voting circuit, further improving circuit reliability; in a specific implementation, for NMOS and PMOS tubes with the same input and output in the same logic, the output ends remain connected unchanged, and their gate input ends are separated and connected to corresponding tubes in another logic respectively, and the clock signals are connected to the same-phase and independent signals respectively, and after cross-connection, the sequential logic unit reinforced with dual-mode redundancy is finally obtained.

[0015] Furthermore, the built-in redundant self-repairing BISR circuit can repair multiple faults or permanent hard errors detected by the BIST circuit that are caused by the radiation environment and cannot be resolved by the ECC circuit; the specific working process of the circuit is as follows:

[0016] When the fault in the array can be repaired by ECC, the column redundancy replacement circuit will not be started. At this time, the configuration signal CFG[8:14]=7'b0, so that the input data is normally stored in the 16 columns originally corresponding to the write operation; when the fault in the array exceeds the error correction capability of ECC, CFG[8:14] is no longer 7'b0, and the CGF signal corresponding to the column before the fault column becomes 1, and the data originally input to a group of two faulty columns is input to the previous group of data columns, and the data of the previous group is also sent to the previous group of data columns corresponding to itself, until the first group of data is input to the redundant column, completing the column repair; similarly, the source line mapping module structure of the storage array and the self-reference array is also the same, but it is composed of 8 2-to-1 MUXs and is controlled by the configuration signal CFG[0:7]; when no column redundancy replacement is performed, CFG[0:7]=8'b111111111; when column redundancy replacement is performed, the CGF signal corresponding to the replaced column in CFG[0:7] becomes 0. The data originally input into a set of faulty columns is input into the previous set of data columns, and the data is input into the previous column in this direction until the first set of data in the array is input into the redundant column, completing the column repair.

[0017] The method for designing a magnetic random access memory system with high yield under irradiation conditions of the present invention has the following advantages:

[0018] (1) The system-level radiation-resistant reinforcement design studied in this invention proposes to combine the error detection and correction circuit with the built-in self-detection-self-repair system to work together, and regularly start the BISTR system to detect and repair faults that the ECC circuit cannot correct, thereby effectively suppressing soft errors and hard errors caused by the radiation environment. After the embedded MRAM memory chip is manufactured, it can complete fault testing and fault repair on the chip itself, thereby improving the chip yield.

[0019] (2) The sequential logic unit of the built-in self-test circuit studied in the present invention adopts dual-mode redundancy to carry out radiation-resistant reinforcement, which can filter out burrs during signal transmission, resist single-particle effects, and ensure the reliability of BIST as a self-test circuit itself. The traditional three-mode redundancy design replicates the unit module that needs to be reinforced three times and adds a voting circuit, resulting in an increase of more than two times in area and power consumption. The dual-mode redundancy design avoids soft errors that cannot be handled in the voting circuit by removing the voting structure, effectively saving area and power consumption while further reducing the probability of soft errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is based on a self-referencing array of 2T-2M bit cells;

[0021] Figure 2 It is a schematic diagram of the layout of an ECC-compatible reconfigurable bit width array provided by the implementation of the present invention;

[0022] Figure 3 It is a circuit implementation structure diagram of the Hamming code-based error detection and correction algorithm provided by the present invention;

[0023] Figure 4 It is a block diagram of the radiation-resistant systematic design structure provided by the present invention;

[0024] Figure 5 It is a structural diagram of the D flip-flop circuit modified by the dual-mode redundancy reinforcement method provided by the implementation of the present invention;

[0025] Figure 6 It is a structural diagram of a D flip-flop reinforced with dual-mode redundancy provided by the present invention;

[0026] Figure 7 It is a comparison chart of the double-mode redundancy reinforcement method provided by the present invention and the traditional triple-mode redundancy method in terms of trigger layout area benefits;

[0027] Figure 8 It is a schematic diagram of a column redundancy replacement circuit provided by an embodiment of the present invention;

[0028] Fig. 9 It is a schematic diagram of the working process of the built-in self-repair system provided by the implementation of the present invention;

[0029] Fig.10 It is a waveform diagram of the simulation function of the built-in self-test-self-repair system when the memory provided by the present invention is fault-free;

[0030] Fig.11 It is a fault repair waveform diagram of a built-in self-test-self-repair system when a memory fails provided by the present invention. DETAILED DESCRIPTION

[0031] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a method for designing a magnetic random access memory system with high yield under irradiation conditions of the present invention in conjunction with the accompanying drawings.

[0032] The high-yield magnetic random access memory system under irradiation conditions described in the present invention is based on a 2T-2M self-reference structure, combined with a Hamming code-based error detection and correction (Error Checking and Correction, ECC) circuit and a built-in self-test-self-repair (Build-In-Self-Test-Repair, BISTR) system to detect and repair soft and hard errors; the BISTR system includes a built-in self-test (Build-In-Self-Test, BIST) circuit with fault diagnosis function and a built-in redundant self-repair (Build-In-Self-Repair, BISR) circuit, and the sequential logic unit in the system uses a sequential logic standard unit library designed by a dual-mode redundant radiation-resistant reinforcement method. The 2T-2M bit cell structure consists of two groups of serially connected magnetic tunnel junctions (Magnetic Tunnel Junction, MTJ) and NMOS gating tubes ( Figure 1 ). The error detection and correction circuit specification is (13, 8) Hamming code, where the data bit is 8-bit, the check bit is 5-bit, and the total codeword is 13-bit. The implementation of the ECC error correction algorithm includes an encoding module (EHC_13_8_Encoder) and a decoding module (EHC_13_8_Decoder). DIN[7:0] is the input 8-bit data, Bypass is the ECC bypass signal, DOUT[7:0] is the data after error correction, ERRF is the error flag, and UE is the error correction flag ( Figure 2 The built-in self-detection circuit core for fault diagnosis consists of three blocks: controller (CTRL), test pattern generator (TPG) and fault location indicator (FSI), and a set of multiplexers BIST_MUX ( Figure 3). A dual-mode redundant radiation-resistant standard cell library is provided for the sequential logic unit of the BIST circuit. The transmission gate of the sequential circuit is combined with an inverter to reinforce the standard cell. At the same time, an inverter is added to generate an independent inverted clock signal, which is finally realized through the cross-connection between different logics. The built-in redundant self-repair circuit for fault repair is designed based on the column redundant replacement circuit and mainly consists of two parts; the first is the bit line mapping module of the storage array and the self-reference column, which is composed of 7 2-to-1 MUXs, and uses the configuration signal CFG[8:14] as the address selection end to map the bit line connection relationship of the array; the second is the source line mapping module of the storage array and the self-reference array. Its structure is the same as the bit line mapping module, but it is composed of 8 2-to-1 MUXs, which is controlled by the configuration signal CFG[0:7] to map the source line connection relationship of the array ( Figure 7 ).

[0033] At present, the mainstream storage structure in MRAM is 1T-1M structure or 2T-2M structure, which corresponds to the global reference array and self-reference array in the array respectively. Figure 1 As shown. The 1T-1M structure uses one storage unit to store 1-bit data, and the 2T-2M uses two storage units to store opposite data to store 1-bit data. In terms of cell structure, 1T-1M has twice the storage density of 2T-2M, so 1T-1M MRAM usually has a larger storage capacity, and the 2T-2M self-reference structure has twice the read margin of the 1T-1M structure, with faster memory access speed and read yield. However, during the write operation of the 2T-2M MRAM, since the self-reference structure needs to perform symmetrical writing each time, its write power consumption is twice that of the 1T-1M structure, so it needs to be weighed according to the application scenario in the design. The present invention takes the yield under irradiation conditions as a priority indicator, and selects a 2T-2M structure to form an MRAM self-reference array.

[0034] The maximum bit width corresponding to each address in the reconfigurable bit width array proposed by the present invention is 32-bit. According to the control signal BEN[3:0], each 8-bit (1 Byte) data can be read and written independently and ECC encoding / decoding control can be performed to store data of four different bit widths: 8-bit / 16-bit / 24-bit / 32-bit. Figure 2As shown in the figure, the entire MRAM array has 256 rows × 416 columns, which are divided into data array and ECC array. The data array size is 256 rows × 256 columns, storing 32Kb of data in total. The data storage method in the data array is as follows (taking the first row Row 0 as an example): Each row stores 4 32-bit wide data (Data0, Data1, Data2 and Data3), and each 32-bit data occupies 64 columns. Data0 can be divided into 4 8-bit (Data0[0], Data0[1], Data0[2] and Data0[3]), and the reading and writing of each 8-bit data is controlled by the byte enable signal BEN[3:0]. Finally, each bit of data in Data[0] is stored by a 2T-2M storage unit, so it occupies two adjacent rows. The size of the ECC check array is 256 rows × 160 columns, storing the check bits generated by the ECC module encoding in the data array, with a capacity of 20Kb. The storage method of the check array is as follows (taking the first row Row 0 as an example): the check codes with the same address as the data array are stored from the 257th column to the 416th column, and each row stores 4 20-bit check data (ECC0, ECC1, ECC2 and ECC3). Each 20-bit check data is further divided into 4 5-bit check bits for Data0, Data1, Data2 and Data3 for ECC error correction. Similarly, the reading and writing of ECC0[0], ECC 0[1], ECC 0[2] and ECC 0[3] are also controlled by the byte enable signal BEN[3:0]. When the corresponding 8-bit data is not read or written, the ECC data will not be read or written to avoid additional power consumption.

[0035] like Figure 3 The figure shows the circuit implementation diagram of the error detection and correction algorithm based on Hamming code. The error correction flag UE and the error flag ERRF are combined to indicate whether an error occurs in the data bit and whether the error is corrected. When ERRF and UE are both 0, it means that the ECC check bit codeword is legal and the corresponding data bit has no error. When ERRF is 1 and UE is 0, it means that the ECC module detects an error in the data bit and corrects the error in the data bit. At this time, the output data is correct. When ERRF and UE are both 1, it means that the ECC module detects an error in the data, but the number of error bits is too large and exceeds its correction capability, and the output data is incorrect.

[0036] like Figure 4The figure shows a block diagram of the high-yield system design under irradiation conditions of the present invention, in which the ECC circuit continues to work in the MRAM Macro with redundant columns inserted in advance, and spontaneously detects and corrects soft errors caused by irradiation. When the periodic signal BIST_EN signal is 1, the BIST circuit starts to work, detects multi-bit soft errors and permanent hard errors that cannot be corrected by ECC, and performs on-chip repair through the column redundancy replacement circuit to improve the overall yield.

[0037] For the built-in self-test circuit, when performing BIST testing, the multiplexer sends the test vector generated by TPG to the MRAM Macro to form a test loop; in normal mode (i.e., BISTR does not work, ECC works), the multiplexer directly inputs the external read and write control signals into the MRAM Macro for read and write operations.

[0038] In BIST test mode, the specific working process of the controller is as follows: The BIST state control TEST_MODE input remains at 1, and the state transition will automatically proceed in the default order. By setting TEST_MODE to 0, CTRL will enter the idle state (also known as the reset state). The reset (BIST_RST) signal also drives CTRL into the idle state. Starting from the idle state, CTRL enters the read table (LUT_Out) state after starting the test and extracts the first test command from the lookup table. Then CTRL enters the send (Send_TPG) state, generates an enable signal (TPG_En) and sends a test command (March_Cmd) to enable TPG to generate test vectors. When TPG executes the test command, TPG returns a busy (TPG_Busy) signal to CTRL, and then CTRL returns to the idle state. When TPG completes the test command, the TPG_Busy signal is pulled low, and CTRL enters the LUT_Out state again to obtain the next test command. This process will be repeated until the test command in the lookup table is completed. In the LUT_Out state, if all commands have been executed, the lookup table will give a LUT_End signal, causing CTRL to enter the Finish state and send a BIST_DONE signal.

[0039] The specific workflow of using the test pattern generator to generate test vectors is as follows: After resetting TPG, the idle state is the default state. When the BIST controller enables TPG (TPG_En=1), TPG will first initialize its address register, byte enable register and operation register. Then it enters the instruction decoding state (Cmd_Dec) and passes the instruction in March_Cmd to the three counters. The address register will determine whether the address is increased or decreased by one after the execution is completed according to the value of U / D in the instruction. Since the array in MRAM is designed as a variable bit width (8 / 16 / 24 / 32-bit), each 8-bit data must be tested when performing BIST operations. The byte register records the traversal of the 4 bytes of 32-bit data corresponding to each address. The operation register is used to track the MRAM read / write operations that need to be performed on the current address. For example, for read 0-write 1-read 1 operations, the value in the operation register is 00-11-01. Each operation value is applied in turn to select the current operation of the MRAM being tested. When TPG enters the execution phase (Execute), according to the values ​​in the three registers, TPG will output the corresponding CEN, BEN, WEN, ADDR and DIN read and write waveforms into the MRAM Macro. At the same time, in the execution phase, TPG will send the expected output (Expect) to the fault location indicator for fault detection after each read operation. If FSI detects a fault, TPG will receive a detection exception signal (BIST_Fail). TPG will then enter the pause state (Pause) until FSI completes fault location and analysis, the BIST_Fail signal is pulled low, and TPG continues to execute and continue to execute unfinished operations.

[0040] The fault location indicator receives the expected output (Expect) of the memory, the current test address and the current test byte (BEN) from the TPG, and receives the read result DOUT from the memory. After the memory outputs the data, the FSI performs bit-by-bit XOR with DOUT and Expect to compare whether there is an error in the result. When it is detected that the expected output does not match the read data, a memory fault occurs, the FSI pulls up the BIST_FAIL signal, and the TPG enters the pause state. The FSI then prints the fault details serially to the fault information terminal (FAULT_INFO).

[0041] like Figure 5 and Figure 6 As shown in FIG. 1 , the dual-mode redundancy reinforcement method provided by the present invention is applied to the D flip-flop circuit. In order to facilitate the subsequent dual-mode redundancy design, the D flip-flop circuit is first modified, such as Figure 5As shown in the figure. Since the transmission gate structure will increase the design difficulty in dual-mode redundancy and is not conducive to cross-connection, the transmission gate and the inverter are combined together to form a vertically stacked four-transistor structure, and the two middle transistors are used to control the data transmission. The circuit after the transformation has only one transmission gate instead of the previous four transmission gates, which is conducive to the design of dual-mode redundancy cross-connection. The D flip-flop structure after dual-mode redundancy reinforcement is shown in the figure. Figure 6 As shown in the figure, since a clock signal is added to the sequential logic unit, if all parts of the sequential logic unit share a clock signal, when the clock signal is affected by radiation, it will cause the potential of multiple transistors connected to the clock signal to change at the same time. In order to prevent this phenomenon, in addition to the two modified D flip-flops, our reinforced structure also adds two radiation-resistant inverters to generate clock signals that are in phase with CK and CKb but independent of each other, to prevent charge sharing after a single clock signal is affected by radiation. Among them, CK, CK1, CK_1 and CK1_1 signals are positive clock signals with the same phase, and CKb and CK1b are inverse clock signals with the same phase. For NMOS and PMOS tubes with the same input and output in the same logic, the output ends remain connected unchanged, and their gate input ends are separated and connected to the corresponding tubes in another logic respectively. The clock signals are connected to the same-phase and independent signals respectively. After cross-connection, the dual-mode redundant reinforced D flip-flop unit is finally obtained.

[0042] The layout area of ​​the same trigger circuit reinforced by triple-mode redundancy and dual-mode redundancy is 9.43μm 2 and 6.45 μm 2 , the dual-mode redundant layout area is reduced by 31.6%. Figure 7 As shown. For the trigger circuit, under the condition of TT process angle 25°C, the power consumption of the dual-mode redundancy reinforcement method is reduced by 30.2% compared with the traditional three-mode redundancy, and the trigger delay time is reduced from 61.0ps to 49.1ps, a decrease of 19.5%. In addition, the radiation resistance performance of the dual-mode redundancy standard unit is verified to verify the critical flip charge. The simulation shows that among all the standard units, the trigger circuit has the lowest critical flip charge. For the trigger circuit that has not been reinforced by radiation, a charge injection of 50fC can cause a potential flip, while the standard units reinforced by three-mode redundancy and dual-mode redundancy can reach a critical flip charge of 3pC, which meets the application conditions of high earth orbit. Therefore, the dual-mode redundancy reinforcement method greatly reduces the layout area, power consumption and delay time of the standard unit while ensuring the radiation resistance performance.

[0043] like Figure 8The figure shows a column repair redundant replacement circuit proposed for a 2T-2M self-referenced MRAM array, which can replace the column where the failed 2T-2M unit in the array is located with a redundant column, thereby improving the memory yield. When the fault in the array can be repaired by ECC, column redundancy replacement is not performed. At this time, CFG[8:14]=7'b0, so that the input data is stored in the original corresponding 16 columns during the write operation; when the fault in the array exceeds the error correction capability of ECC (taking the replacement of column 2 and column 3 as an example), CFG[8:14]=7'b1000000, the data originally input to column 2 and column 3 is input to column 0 and column 1, and the data in column 0 and column 1 is input to the redundant column, completing the column repair; similarly, the source line mapping module structure of the storage array and the self-reference array is also the same, but it is composed of 8 2-to-1 MUXs and is controlled by the configuration signal CFG[0:7]; when column redundancy replacement is not performed, CFG[0:7]=8'b11111111; when column redundancy replacement is performed (taking column 3 being replaced as an example), CFG[0:7]=8'b001111111.

[0044] like Fig. 9 The figure shows the workflow of the built-in self-repair system for fault repair proposed based on the column repair redundant replacement circuit. Each time the memory test is performed, the BISR will follow the BIST to perform the test, analysis and repair operations. After the BIST_EN signal is pulled high, the BISR will replace the redundant columns in the array with the data columns by configuring the word line and bit line mapping module, and the BIST will perform the redundant column fault test. The BIST operation in this round of test is the same as the normal test process, but the BISR will determine whether the redundant column has a fault through the fault information output by the BIST. Once a fault is found, the BISR will mark the defective redundant column as a fault column and will not be used for column repair. After completing the redundant column test, the BISR will clear the word line and bit line mapping module configuration signal and start the fault test on the data array. If a fault is found (BIST_FAIL is pulled high), the BISR will read the fault information FAULT_INFO, and after completing the reading, the test suspension signal BIST_HOLD_L will be pulled low (low level is valid). After completing the redundancy repair analysis, the BISR module will save the repair data to the non-volatile redundant information area (NVR), then re-pull BIST_HOLD_L and continue the memory test until it is completed. After completing the test and redundancy repair analysis, the BISR will read out the repair information stored in the NVR area in sequence after each power-on, and configure it to the registers on each word line mapping and bit line mapping in the array to complete the column redundancy repair, and then the MRAM memory will start to work normally.

[0045] like Fig.10The figure shows the simulation waveform of the whole process of self-test and repair when the memory is fault-free. At time 0, the BIST_EN signal is pulled high and maintained to start the test process. Then the test vector generation module in the BIST generates read and write test vectors for the memory (WEB, ADDR[9:0] and DIN[51:0] signals in the figure). Since the MRAM output data DOUT[51:0] is always the same as the expected result during the test, no faulty unit is detected and BIST_FAIL is always 0. REPAIR_INFO is the BISR redundant repair information. Since no fault occurs, redundant replacement is not required, so FAULT_INFO[15:0] remains 0. After 147.85ms of test time, the entire system completes the test and finally pulls BIST_DONE high to indicate that the test is complete.

[0046] like Fig.11 As shown, when a fault occurs in the memory, BIST will diagnose the fault information, and BISR will analyze the fault and provide repair information to store in NVR BANK. The expected output of the memory is 32'h0000_0000, while the actual output is 32'h0000_0800. Since in the actual physical layout of the MRAM array, the 32-bit data is divided into 4 8-bits, and there is a column of redundant repair for each 8-bit. The output error bit is at the 11th bit in the 32-bit data, that is, the 3rd bit in the second 8-bit data. In the BISR, the replacement of each column of redundancy is recorded using 4-bit data, so the repair information is 4'b1011. The highest bit in the 4-bit repair data is 1, indicating that column redundant replacement is required to repair the fault, and 3'b011 means that the 3rd bit is replaced by column. Since there are no faulty cells in the remaining three bytes, the redundant repair information is 4'b0000, that is, REPAIR_INFO[15:0] = 16'h00b0. The simulation results show that the built-in self-test-self-repair system can complete the memory fault test and repair functions, and can effectively deal with multi-bit soft errors and hard errors caused by radiation.

[0047] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A method for designing a magnetic random access memory system with high yield under irradiation conditions, characterized in that: The following steps are involved: The embedded magnetic random access memory (MRAM) is based on a 2T-2M self-referencing structure, which can detect and repair faults on-chip under irradiation conditions. The error detection and correction (ECC) circuit is used to detect and correct soft errors in the MRAM storage array. A built-in self-test-self-repair BISTR system is used to detect and repair permanent hard errors caused by particle impacts; the built-in self-test-self-repair BISTR system includes a built-in self-test BIST circuit with a fault diagnosis function and a built-in redundant self-repair BISR circuit for repairing the detected faults; the sequential logic cells in the built-in self-test BIST circuit are replaced with sequential logic standard cells in a dual-mode redundant radiation-resistant standard cell library; the error detection and correction ECC circuit works in conjunction with the built-in self-test-self-repair BISTR system to suppress soft and hard errors in an irradiated environment; The 2T-2M self-reference structure is composed of two 1T-1M storage cells with completely opposite magnetic tunnel junction MTJ states, namely, two groups of MTJ and NMOS gating tubes connected in series; the gates of the two groups of gating tubes are connected to the word line WL, and the bit line BL voltage and source line SL voltage of the two groups of 1T-1M storage cells are opposite in magnitude; the 2T-2M self-reference structure uses two MTJs to complete the storage of one bit unit data, and the two combinations of parallel state and anti-parallel state and anti-parallel state and parallel state represent data "0" and "1" respectively; The error detection and correction ECC circuit adopts the encoding method of Hamming code to achieve 1-bit correction and 2-bit error detection for 8-bit; the Hamming code specification used has 8-bit data bits and 5-bit check bits, a total of 13-bit code words; the ECC error correction algorithm is implemented by combining the encoding module and the decoding module with the MRAM peripheral circuit, and the output error correction flag bit UE and the error flag bit ERRF are combined to indicate whether an error occurs in the data bit and whether the error is corrected; The built-in self-test BIST circuit is composed of three modules: a controller CTRL, a test pattern generator TPG and a fault location indicator FSI; the controller CTRL is used for control; the test pattern generator TPG generates test data and addresses based on a test algorithm in a test mode; After the test pattern generator TPG generates the test data and address, the fault location indicator FSI compares and analyzes the read data of the memory to confirm whether a fault occurs; there is also a group of multiplexers BIST_MUX in the built-in self-test BIST circuit, which switches between the BIST test mode and the normal operation mode under the control of the BIST_EN signal; The sequential logic standard cell in the dual-mode redundant radiation-resistant standard cell library is used to replace the sequential logic cell in the built-in self-test (BIST) circuit. The specific steps are as follows: the sequential logic cell of the built-in self-test (BIST) circuit is reinforced against radiation by using a dual-mode redundant method, that is, a transmission gate and an inverter are combined together to form a vertically stacked transistor structure; two radiation-resistant inverters are added to the reinforced structure to generate a clock signal that is in phase with the clock signal and its inverted signal but is independent of each other, so as to prevent charge sharing from occurring after a single clock signal is affected by radiation; The built-in redundant self-repair BISR circuit is composed of two parts; first, the bit line mapping module of the storage array and the self-reference array. In the actual physical layout, the storage cells of two adjacent columns constitute a 2T-2M unit and store 1-bit data. Therefore, when performing column redundancy replacement, the two columns must be replaced at the same time; the bit line mapping module of the storage array and the self-reference array has the same structure, and both are composed of 7 2-to-1 MUXs, and the configuration signal CFG[8:14] is used as the address selection end to map the bit line connection relationship of the array; second, the source line mapping module of the storage array and the self-reference array has the same structure as the bit line mapping module, but it is composed of 8 2-to-1 MUXs, and is controlled by the configuration signal CFG[0:7] to map the source line connection relationship of the array.

2. The method for designing a magnetic random access memory system with high yield under irradiation conditions according to claim 1, characterized in that: The error detection and correction ECC circuit is based on an MRAM array with a reconfigurable bit width of 8-bit / 16-bit / 24-bit / 32-bit. The read and write of each byte of data and the encoding and decoding of the error detection and correction ECC circuit are independently controlled by control signals, so as to reduce power consumption and maximize the ECC error correction capability when storing small data bit widths. In the encoding module, DIN[7:0] is the input 8-bit data, Bypass is the ECC bypass signal, when Bypass=1, ECC encoding and decoding operations are not performed, and the storage unit corresponding to the ECC check bit is not read or written. DOUT[12:0] is the encoded 13-bit codeword, which is transmitted to the write driver module of the array for writing. In the decoding module, DIN[12:0] is the 13-bit codeword read from the storage array by the sense amplifier, Bypass is the ECC bypass signal, DOUT[7:0] is the data after error correction, ERRF is the error flag bit, marking whether the codeword is detected to be illegal, and UE is the error correction flag bit, marking whether the codeword is corrected.

3. A magnetic random access memory system design with high yield under irradiation conditions according to claim 2, characterized in that: The built-in self-test (BIST) circuit works in conjunction with the error detection and correction (ECC) circuit, and is periodically turned on to detect hard errors that the error detection and correction (ECC) circuit cannot correct. It can also diagnose the type and address of faulty cells in the array. The built-in self-test (BIST) circuit has a built-in March C+ test algorithm lookup table, which can test all types of faults in the memory, including fixed faults, coupling faults, and conversion faults. When performing a BIST test, the multiplexer sends the test data and addresses generated by the TPG to the MRAM Macro composed of the MRAM storage array and peripheral circuits to form a test loop. In normal mode, the multiplexer directly inputs the external read and write control signals into the MRAM Macro for read and write operations.

4. The method for designing a magnetic random access memory system with high yield under irradiation conditions according to claim 1, characterized in that: The sequential logic standard cell library in the built-in self-test (BIST) circuit filters out glitches during signal transmission, resists single particle effects caused by radiation, and ensures that the built-in self-test (BIST) circuit is not interfered by radiation. For NMOS and PMOS tubes with the same input and output in the same logic, the output ends remain connected, and the gate input ends of the NMOS and PMOS tubes are separated and connected to the corresponding tubes in another logic respectively. The clock signals are connected to the same-phase and independent signals respectively, and after cross-connection, a sequential logic unit reinforced with dual-mode redundancy is finally obtained.

5. The method for designing a magnetic random access memory system with high yield under irradiation conditions according to claim 3, characterized in that: The built-in redundant self-repairing BISR circuit is used to repair multiple faults or permanent hard errors detected by the BIST circuit that cannot be resolved by the ECC circuit due to the irradiation environment; the specific working process of the circuit is as follows: When the fault in the array can be repaired by ECC, no column redundancy replacement is performed. At this time, CFG[8:14]=7'b0, so that the input data is stored in the original 16 columns during the write operation; when the fault in the array exceeds the error correction capability of ECC, CFG[8:14] is no longer 7'b0, and the CGF signal corresponding to the column before the fault column becomes 1, and the data originally input to a group of two fault columns is input to the previous group of data columns, and the data of the previous group is also sent to the previous group of data columns corresponding to itself, until the first group of data is input to the redundant column , the column repair is completed; the source line mapping module structure of the storage array is the same as that of the self-reference array, but it is composed of 8 2-to-1 MUXs and is controlled by the configuration signal CFG[0:7]; when no column redundant replacement is performed, CFG[0:7]=8'b111111111; when column redundant replacement is performed, the CGF signal corresponding to the replaced column in CFG[0:7] becomes 0, and the data originally input into a group of faulty columns is input into the previous group of data columns. In this direction, the data is input into the previous column until the first group of data in the array is input into the redundant column, and the column repair is completed.

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