Method of forming semiconductor device

Abstract

A method of forming a semiconductor device. The method includes forming a high dielectric constant gate dielectric layer over a channel region of a substrate; depositing a work function metal layer on the high dielectric constant gate dielectric layer; forming a titanium nitride cover body above the work function metal layer, wherein the titanium nitride cover body comprises one or more oxygenation areas; depositing a silicon cover layer on the titanium nitride cover body; depositing a conductive bonding layer on the silicon cover layer; and depositing a gate filling metal layer above the conductive bonding layer to form a gate structure.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device that can provide a titanium nitride cap with an oxygen-filled region. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design of integrated circuits (ICs) have created generations of integrated circuits, each with smaller and more complex circuits than the previous generation. Over the course of integrated circuit evolution, functional density (e.g., the number of interconnected devices per unit chip area) has generally increased, accompanied by a reduction in geometry (i.e., the size and / or dimensions of integrated circuit components and / or the spacing between these integrated circuit components). In general, downsizing is limited only by the ability to lithographically define integrated circuit components with ever-decreasing geometries.

[0003] As component sizes continue to decrease, improved channel mobility (i.e., carrier mobility in the channel) becomes increasingly important in integrated circuit components such as memory or logic elements. Memory components such as static random-access memory (SRAM) continue to shrink to smaller technology nodes (e.g., <10nm). At these sizes, SRAM mobility and the on-current of the memory cell may be lower than expected. As a result, the minimum supply voltage Vmin (i.e., minimum operating voltage) increases, thereby reducing power efficiency. Since the channel size is limited by the technology node, the gate structure, especially the gate interface with the channel, is an area of ​​development that can improve the channel mobility.

[0004] Thus, while existing methods of forming gate structures are generally adequate for their intended purposes, they are not completely satisfactory in every aspect. Summary of the invention

[0005] Some embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; forming a titanium nitride (TiN) cap above the work function metal layer, wherein the TiN cap includes one or more oxygenated regions; depositing a silicon cap layer on the TiN cap; depositing a conductive adhesion layer on the silicon cap layer; and depositing a gate fill metal layer on the conductive adhesion layer to form a gate structure.

[0006] Some embodiments of the present disclosure further provide a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; depositing a first titanium nitride cap layer above the work function metal layer; performing an oxygen treatment on the first titanium nitride cap layer; depositing a second titanium nitride cap layer above the first titanium nitride cap layer to form a titanium nitride cap body; depositing a silicon cap layer on the titanium nitride cap body; depositing a conductive adhesion layer on the silicon cap layer; and depositing a gate fill metal layer above the conductive adhesion layer to form a gate structure.

[0007] Some embodiments of the present disclosure further provide a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; depositing a bottom titanium nitride capping layer above the work function metal layer; performing an oxygen treatment on the bottom titanium nitride capping layer; depositing one or more middle titanium nitride capping layers on the bottom titanium nitride capping layer; performing an oxygen treatment on the one or more middle titanium nitride capping layers; depositing a top titanium nitride capping layer on the one or more middle titanium nitride capping layers to form a titanium nitride cap; depositing a silicon capping layer on the titanium nitride cap; depositing a conductive adhesion layer on the silicon capping layer; and depositing a gate fill metal layer on the conductive adhesion layer to form a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description in conjunction with the accompanying drawings will provide a better understanding of the embodiments of the present invention. It should be emphasized that, according to standard industry practice, many features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A cross-sectional schematic diagram of a gate structure above a channel region according to an embodiment of the present disclosure is shown.

[0010] Figure 2 Shows Figure 1 An enlarged cross-sectional schematic diagram of a portion of a gate structure is shown.

[0011] Figure 3 A flowchart of part or all of a method for a semiconductor device having a gate structure formed above a channel region according to an embodiment of the present disclosure.

[0012] Figure 4 is a flow chart of different methods of forming a titanium nitride (TiN) cap according to an embodiment of the present disclosure.

[0013] Figure 5A A titanium nitride (TiN) cap having an oxygenated region is shown, and Figure 5B Shows Figure 5A Oxygen distribution in the titanium nitride (TiN) cover.

[0014] Fig. 6A A titanium nitride (TiN) cap having multiple oxygenated regions is shown. Figure 6B Shows Fig. 6A Oxygen distribution in the titanium nitride (TiN) cover.

[0015] The reference numerals are described as follows:

[0016] 100: Gate structure (gate stack)

[0017] 102: Channel area

[0018] 104: Isolation Structure

[0019] 110: Interface layer

[0020] 112: Gate dielectric layer

[0021] 114: Work function metal layer

[0022] 115: Oxygenated Area

[0023] 116: Titanium nitride cover

[0024] 116a: first titanium nitride capping layer

[0025] 116b: Second titanium nitride capping layer

[0026] 116m: Intermediate titanium nitride cap layer

[0027] 118: Silicon cap layer

[0028] 120: Conductive adhesive layer

[0029] 205: Oxygen Atom

[0030] 300: Methods

[0031] 302, 304, 306, 308, 310, 311, 312, 313, 314, 315, 316, 318, 320, 322, 324, 326, 328, 330: Steps DETAILED DESCRIPTION

[0032] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the following description mentions that a first component is formed on or located on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present invention may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0033] In addition, spatially relative terms such as "under," "below," "lower," "above," "upper," and other similar terms may be used herein to describe the relationship between an element or component as shown in the figure and other elements or components. Such spatially relative terms include not only the orientation shown in the figure, but also different orientations of the device in use or operation. The device can be rotated arbitrarily (e.g., rotated 90 degrees or to other orientations), and the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

[0034] Furthermore, when the term "about," "approximately," "substantially," or similar terms are used to describe a number or a range of values, unless otherwise specified, as will be appreciated by those skilled in the art, such terms are intended to encompass values ​​within a reasonable range of the described value, such as within a range of ±10% of the described value. For example, the term "about 5 nanometers" may encompass a size range from 4.5 nanometers to 5.5 nanometers. And when comparing the size or size of one component to another, terms such as "substantially the same," "substantially the same," "similar in size," and the like may be understood to refer to components being compared within + / -10%, or other values ​​within a range that would be understood by those skilled in the art. In addition, the disclosed sizes of different components may implicitly disclose the size ratios between the different components.

[0035] The present disclosure relates to forming a semiconductor device with improved channel mobility to obtain a higher memory cell on-current and a reduced minimum power supply voltage Vmin. Specifically, these improvements are achieved by one or more vacuum breaks (or oxygen treatments) during the gate formation process. The vacuum break (or oxygen treatment) is performed to supply oxygen to a portion of the gate. The oxygen atoms in these oxygenated portions are then diffused into the high-k gate dielectric layer of the gate during a post-gate annealing process. Before the post-gate annealing, a silicon cap layer is formed over the oxygenated portions. The silicon cap layer can prevent oxygen atoms from further diffusing into the high-k gate dielectric layer. In this way, the amount of diffusible oxygen is controlled only by the oxygenated region. By controlling the oxygen content and further oxidizing the high-k gate dielectric layer through the oxygenated portions, the channel mobility can be improved to improve device performance.

[0036] To illustrate various aspects of the present disclosure, a method of forming a semiconductor device is discussed below. The embodiments shown in the present disclosure are implemented by a gate-all-around (GAA) device field effect transistor (FET), but the present disclosure is not limited to this. GAA FETs refer to transistors having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as vertically stacked all-around gate horizontal nanowire or nanosheet MOSFET elements. It should be understood by those of ordinary skill in the art that they can use the present disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or achieve the same advantages as the embodiments presented herein.

[0037] Figure 1 FIG. 1 is a schematic cross-sectional view of a gate structure 100 (or gate stack 100) above a channel region 102 according to an embodiment of the present disclosure. The gate structure 100 extends longitudinally along the x-direction and includes several different layers (e.g., an interface layer 110, a gate dielectric layer 112, etc.). These layers will be referred to as Figure 2 and Figure 3The channel region 102 is a portion of an active region formed above a substrate (not shown), wherein the active region extends longitudinally along the y direction (the direction into and out of the paper). In the present embodiment, the channel region 102 includes a bottom fin portion and a semiconductor channel stack above the bottom fin portion. Each semiconductor channel is separated and surrounded by a gate structure 100. The active region including the channel region 102 may be surrounded by an isolation structure 104 and separated from other active regions. The isolation structure 104 covers the top surface of the substrate and surrounds the sidewall portion of the active region. As shown, the isolation structure 104 surrounds the side of the bottom fin portion of the channel region 102. The bottom fin portion protrudes from the substrate to above the top surface of the isolation structure 104. The substrate and the active region include semiconductor materials, such as silicon, germanium, silicon carbide, silicon germanium, or other materials. The isolation structure 104 may be a shallow trench isolation (STI) structure having a dielectric material such as silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials.

[0038] Still refer to Figure 1Although not shown in this schematic diagram, the source / drain components of the active region are disposed along the y direction adjacent to the channel region 102. The source / drain components, the channel region 102 and the gate structure 100 together form a transistor element as part of a semiconductor device. The semiconductor device can be an integrated circuit (IC) chip, a system on chip (SoC), or a portion of the foregoing chips, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), fin field effect transistors (FinFETs), nanosheet field effect transistors (nanosheet FETs), nanowire field effect transistors (nanowire FETs), other types of multi-gate field effect transistors (multi-gate FETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (bipolar junction transistors; BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable devices, or combinations of the foregoing devices. In some embodiments, the device is implemented in a non-volatile memory, such as a non-volatile random access memory (NVRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), an electrically programmable read-only memory (EPROM), other suitable memory types, or a combination of the foregoing memories. In this embodiment, the source / drain features, channel region 102, and gate structure 100 are transistor portions for a static random access memory (SRAM) device.

[0039] Figure 2 Shows Figure 1 An enlarged cross-sectional view of a portion of the gate structure 100 is shown. Figure 2 1 shows a portion of a gate structure 100 formed over a semiconductor channel. Note that Figure 2 The various layers shown are not only formed over one semiconductor channel, they are also formed over the bottom fin portion of the channel region 102 and vertically surround the stack of such semiconductor channels (see Figure 1 ).

[0040] Reference Figure 2The gate structure 100 includes an interface layer 110 on a surface of a channel region 102 (e.g., a semiconductor channel), a gate dielectric layer 112 on the interface layer 110, a work function metal layer 114 on the gate dielectric layer 112, a titanium nitride (TiN) cap 116 on the work function metal layer 114, a silicon cap layer 118 on the titanium nitride (TiN) cap 116, and a conductive glue layer 120 on the silicon cap layer 118. Although not shown, a gate fill metal layer may be formed on the conductive glue layer 120 to complete the gate structure 100. In the illustrated embodiment, the titanium nitride (TiN) cap 116 includes a first titanium nitride (TiN) cap layer 116a on the work function metal layer 114, a second titanium nitride (TiN) cap layer 116b on the first titanium nitride (TiN) cap layer 116a, and an oxygenated region 115 between the first titanium nitride (TiN) cap layer 116a and the second titanium nitride (TiN) cap layer 116b. The present disclosure contemplates that the oxygen atoms 205 in the oxygenated region 115 will diffuse into the gate dielectric layer 112, and the silicon cap layer 118 will act as a barrier layer to prevent the external oxygen atoms 205 from diffusing into the titanium nitride (TiN) cap layer 116. Figure 3 The method 300 is further described in detail with reference to the gate structure 100 and the oxygen diffusion mechanism.

[0041] Figure 3 FIG. 1 is a flowchart of a portion or all of a method 300 for a semiconductor device according to an embodiment of the present disclosure. The semiconductor device has a gate structure 100 formed above a channel region 102 . Figure 3 Method 300 is referenced Figure 1 , Figure 2 Provide relevant description.

[0042] In step 302, method 300 forms a gate dielectric layer 112 above a channel region 102 of a substrate. The gate dielectric layer 112 is a high dielectric constant gate dielectric layer and includes a high dielectric constant dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). The gate dielectric layer 112 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), sintered titanium oxide (SrTiO3), aluminum oxide (AlO2), tantalum oxide (TaO), other suitable metal oxides, or combinations of the foregoing materials. The gate dielectric layer 112 may be deposited by any suitable deposition technique, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). As part of step 302 or prior to step 302, method 300 may form an interface layer 110 (e.g., a silicon oxide layer) above the channel region 102. Then, a gate dielectric layer 112 is deposited over the interface layer 110. The interface layer 110 may serve as a buffer layer to improve the bonding between the gate dielectric layer 112 and the semiconductor surface of the channel region 102. The interface layer 110 may be formed by chemical oxidation, thermal oxidation, ALD, and / or other suitable methods.

[0043] In step 304 of method 300, a sacrificial capping layer (not shown) may be deposited over the gate dielectric layer 112 by any suitable deposition technique. The sacrificial capping layer may include a titanium nitride layer and a silicon capping layer over the titanium nitride layer. In step 306 of method 300, an annealing process (also referred to as post-capping annealing) is performed on the sacrificial capping layer and the gate dielectric layer 112. The annealing process may increase the density of the gate dielectric layer 112, reduce defects in the gate dielectric layer 112, and improve the quality of the gate dielectric layer 112. The sacrificial capping layer provides filling and protection for the gate dielectric layer 112 during the annealing. In step 308 of method 300, the sacrificial capping layer is removed to expose the gate dielectric layer 112. The sacrificial capping layer may be removed by any suitable technique (e.g., wet etching).

[0044] In step 310, after removing the sacrificial capping layer, the method 300 deposits a work function metal layer 114 over the gate dielectric layer 112. The work function metal layer 114 includes a conductive layer of a metal or metal alloy having a suitable work function to enhance the device performance of a corresponding transistor device (e.g., nFET or pFET). The work function metal layer 114 may include a metal selected from, but not limited to, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), tungsten aluminide (WAl), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or a combination thereof; and may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes. For a pFET in the first transistor region and an nFET in the second transistor region, the composition of the work function metal layer 114 is different, which is referred to as a p-type work function metal and an n-type work function metal, respectively. Specifically, the n-type work function metal is a metal having a first work function, which reduces the critical voltage of the associated nFET. The n-type work function metal is close to the silicon conduction band energy (Ec) or a lower work function, which is more likely to cause electron escape. For example, the n-type work function metal has a work function of about 4.2 eV or less. The p-type work function metal is a metal having a second work function, which reduces the critical voltage of the associated pFET. The p-type work function metal is close to the silicon valence band energy (Ev) or a higher work function, presenting a stronger electron bonding energy with the nucleus. For example, the p-type work function metal has a work function of about 5.2 eV or higher. In some embodiments, the n-type work function metal includes tantalum (Ta). In some other embodiments, the n-type work function metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination of the foregoing. In some other embodiments, the n-type metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination of the foregoing. In some embodiments, the p-type work function metal includes titanium nitride (TiN) or tantalum nitride (TaN). In some other embodiments, the p-type metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), ruthenium (Ru), platinum (Pt), or a combination thereof. The n-type work function metal or the p-type work function metal may include various metal-based films as a stack to optimize device performance and process compatibility.

[0045] In some embodiments, for illustration, a patterning process is performed to selectively deposit the work function metal layer 114. For example, a p-type work function metal is conformally deposited on the transistor regions of the n-type element and the p-type element, and then the p-type work function metal in the n-type transistor region is removed by a photolithography and etching process, and then the n-type work function metal is deposited.

[0046] In step 322 of method 300, a titanium nitride (TiN) cap 116 is formed over the work function metal layer 114. The TiN cap 116 includes one or more oxygenated regions 115. The TiN cap 116 may be formed according to Figure 4 The method shown is formed. Figure 4 Step 322 is further decomposed into multiple steps.

[0047] Now refer to Figure 4 In the first embodiment, step 322 includes performing steps 311, 313, and 315. In step 311, step 322 is to deposit a first TiN capping layer 116a on the work function metal layer 114. In this embodiment, the first TiN capping layer 116a is deposited via PVD in a PVD chamber. Note that the work function metal layer 114 can be deposited in the same PVD chamber so that the work function metal layer 114 and the first TiN capping layer 116a are deposited in a sequential manner. The PVD chamber is vacuum sealed to reduce contamination by particles and other substances. In step 313, step 322 is to perform an oxygen treatment on the first TiN capping layer 116a. In one embodiment, the oxygen treatment includes removing the workpiece having the first TiN capping layer 116a from the PVD chamber and exposing the first TiN capping layer 116a to an environment outside the PVD chamber. In one embodiment, the above environment is air at room temperature, and the first TiN capping layer 116a is exposed to this environment for at least 3 hours. In another embodiment, the above environment is air with a temperature greater than 30° C. and less than 40° C., and the first TiN capping layer 116a is exposed to the environment for less than 2 hours. In any case, the first TiN capping layer is exposed to the environment outside a vacuum chamber for a period of time, and the vacuum is broken so that the top surface of the first TiN capping layer 116a absorbs oxygen and reacts with oxygen, thereby forming an oxygen-filled region 115. The oxygen-filled region 115 is used to increase the oxygen content in the gate dielectric layer 112 in subsequent operation steps, thereby enhancing and passivating the oxygen vacancies of the high-k dielectric.

[0048] In order to promote and control the oxygen absorption levels in the oxygenated region 115, according to the present disclosure, a cleaning process may be performed on the top surface of the first TiN capping layer 116a before performing an oxygen treatment to enhance oxygen absorption. The aforementioned cleaning process may include a wet cleaning process. For example, the wet cleaning process may include a standard cleaning solution, such as a solution including ammonia, hydrogen peroxide and water, or a solution including a sulfur peroxide mixture, to clean the top surface of the first TiN capping layer 116a. Furthermore, referring to step 311, according to the present disclosure, the first TiN capping layer 116a may be formed to have a rough top surface. The rough surface may improve oxygen absorption and fill vacancies during the oxygen treatment. This rough surface may be formed by depositing a lower portion of the first TiN capping layer 116a at a first deposition rate and an upper portion of the first TiN capping layer 116a at a second deposition rate, and the second deposition rate is greater than the first deposition rate.

[0049] After the oxygen treatment, in step 315, step 322 is to deposit a second TiN capping layer 116b on the first TiN capping layer 116a. In this step, the workpiece is placed back into a vacuum sealed environment, such as a PVD chamber. Then, the second TiN capping layer 116b is deposited on the oxygenated first TiN capping layer 116a. The aforementioned first TiN capping layer 116a, the oxygenated region 115, and the second TiN capping layer 116b together form a TiN capping body 116. In other words, the TiN capping body 116 includes an oxygenated region 115 located between a top region and a bottom region, and the oxygenated region 115 has a higher oxygen concentration than the top region and the bottom region.

[0050] In the second embodiment, the TiN cap 116 may be formed to have a plurality of oxygenated regions 115. In this case, step 322 performs steps 312, 314, 316, 318, and 320. In step 312, step 322 is to deposit a bottom TiN cap layer (i.e., a first TiN cap layer 116a) above the work function metal layer 114. This step is similar to step 311 described above. In step 314, step 322 is to perform an oxygen treatment on the bottom TiN cap layer. This step is similar to step 313 described above. In step 316, step 322 is to deposit one or more intermediate TiN cap layers 116m (see Fig. 6A). In step 318, step 322 performs an oxygen treatment on one or more intermediate titanium nitride (TiN) capping layers 116m. Note that step 316 and step 318 can be an iterative process, depending on the number of intermediate TiN capping layers 116m formed. In one embodiment, each deposited intermediate TiN capping layer 116m is oxygen treated. In step 320, step 322 is to deposit a top TiN capping layer (i.e., a second TiN capping layer 116b) on top of one or more intermediate TiN capping layers 116m to form a TiN capping body 116. In this way, the formed TiN capping body 116 includes a plurality of oxygenated regions 115 formed between non-oxygenated regions, wherein these oxygenated regions have a higher oxygen concentration than the non-oxygenated regions. Having a plurality of oxygenated regions 115 can improve oxygen control when oxygen atoms are diffused into the gate dielectric layer 112 in subsequent processing steps. The plurality of oxygenated regions 115 can also be adjusted to have different oxygen concentration levels.

[0051] Figure 5A A TiN cap 116 having an oxygenated region 115 is shown. Figure 5B Shows Figure 5A The oxygen distribution of the TiN cap 116 in FIG. Figure 5B As shown, the oxygen concentration of the oxygenated area 115 is greater than that of the non-oxygenated area. The change in oxygen concentration can be gradual at different areas of the TiN cap 116. Note that in the non-oxygenated area, there may still be a non-zero oxygen concentration. In any case, the middle area of ​​the TiN cap 116 has a greater oxygen concentration than the bottom area and the top area.

[0052] Fig. 6A A TiN cap 116 having a plurality of oxygenated regions 115 is shown. Figure 6B Shows Fig. 6A The oxygen distribution of the TiN cap 116 in FIG. Figure 6B As shown, the oxygen concentration of the oxygenated area 115 is greater than the oxygen concentration of the non-oxygenated area. The change in oxygen concentration can be gradually changed in different areas of the TiN cover 116. It is noted that in the non-oxygenated area, there may still be a non-zero oxygen concentration. As shown in the figure, there may be multiple oxygen concentration peaks corresponding to different oxygenated areas 115 between the bottom area and the top area of ​​the TiN cover 116. Figure 6B A uniform oxygen concentration is shown for each oxygenated region 115. However, in some embodiments, the oxygen concentration may not be uniform. For example, the top oxygenated region 115 may have a higher oxygen concentration than the bottom oxygenated region 115. One way to change the oxygen concentration of the different oxygenated regions 115 is by changing the oxygen treatment parameters of the middle TiN cap layer 116m (i.e., changing the vacuum break time, temperature, etc.).

[0053] Now refer to Figure 3 After forming the TiN cap 116, the method 300 deposits a silicon cap layer 118 (see FIG. 1 ) on the TiN cap 116 in step 324. Figure 2 ). The silicon capping layer 118 may be deposited by a suitable technique, such as CVD or PVD. The silicon capping layer 118 serves as a protective layer to prevent further oxidation into the TiN capping layer 116 during subsequent processing. In step 326, the method 300 deposits a conductive glue layer 120 (see FIG. 1 ) on the silicon capping layer 118 by a suitable technique, such as PVD or CVD. Figure 2 ). The conductive adhesion layer 120 may include titanium nitride and may serve as a seed layer for better surface contact with subsequent metal fill. In step 328, the method 300 deposits a gate fill metal layer (not shown) over the conductive adhesion layer 120 to complete the gate structure 100. CVD, PVD, or other suitable processes may be used to deposit the gate fill metal layer. The gate fill metal layer may include metals such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials.

[0054] Reference Figure 3 In step 330, the method 300 performs a post-gate annealing process on the workpiece. The post-gate annealing process refers to any annealing step that may be performed after forming the gate structure 100. Figure 2 As shown by the arrows in , the gate post annealing process diffuses oxygen atoms 205 in the TiN cap 116 into the gate dielectric layer 112, while the silicon cap layer 118 prevents the oxygen atoms 205 from diffusing into the TiN cap layer 116. In this way, the oxygen level is controlled by changing the oxygen concentration in the oxygenated region 115, rather than oxygen in a portion of the oxygenated region 115 being filtered out. Note that the silicon cap layer 118 prevents the diffusion of extraneous oxygen not only during the annealing process, but also after the annealing process, such as during subsequent processes and in-situ operation of the final device. In one embodiment, the gate post annealing process is a thermal annealing treatment of the gate electrode. In this embodiment, the annealing temperature range is between 800°C and 1000°C. In another embodiment, the gate post annealing process is a dedicated thermal treatment for driving the oxygen atoms 205. In another embodiment, the gate post annealing process can be a thermal treatment for other parts of the semiconductor device, and the oxygen atoms 205 can be driven in as a secondary effect.

[0055] During the initial formation of the gate dielectric layer 112, the high dielectric constant material in the gate dielectric layer 112 may not be fully saturated with oxygen due to process window considerations. By driving oxygen atoms 205 into the gate dielectric layer 112 using the oxygenated region 115, the gate dielectric layer 112 can be tuned to obtain better performance. However, the gate dielectric layer 112 is a sensitive layer that requires precise adjustment. Introducing too many oxygen atoms 205 may over-oxidize the gate dielectric layer 112 and cause defects. Accordingly, the silicon cap layer 118 prevents any foreign oxygen atoms 205 from reaching the gate dielectric layer 112. In this way, the exact amount of oxygen diffusion can be controlled by the oxygenated region 115, regardless of the situation where the oxygen atoms 205 exceed the silicon cap layer 118.

[0056] Although not limiting, the present disclosure provides many advantages when forming a semiconductor gate structure. One exemplary advantage is controlling the oxygen content between two titanium nitride cap layers. The oxygen content can be adjusted by oxygen treatment, which may include vacuum breaking when forming the titanium nitride cap. The oxygen treatment produces oxygenated regions, which can then be used to drive oxygen atoms into the gate dielectric layer. Studies have found that driving in these oxygen atoms can increase the mobility gain by more than 15%, which may result in an 8% increase in the memory cell turn-on current and a reduction in the minimum supply voltage Vmin by 20mV to 30mV. Another exemplary advantage is the use of a silicon cap layer to prevent foreign oxygen atoms from diffusing into the gate dielectric layer. Another exemplary advantage is the introduction of oxygen atoms as a secondary effect when performing a post-gate annealing step on different portions of the semiconductor device.

[0057] One aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; forming a titanium nitride cap above the work function metal layer, wherein the titanium nitride cap includes one or more oxygenated regions; depositing a silicon cap layer on the TiN cap; depositing a conductive adhesion layer on the silicon cap layer; and depositing a gate fill metal layer above the conductive adhesion layer to form a gate structure.

[0058] In one embodiment, the method further comprises performing an annealing process on the gate structure so that oxygen atoms in the titanium nitride cap diffuse into the high-k gate dielectric layer. In another embodiment, during and after the annealing process, the silicon cap layer prevents oxygen atoms from diffusing into the titanium nitride cap.

[0059] In one embodiment, the formation of the titanium nitride cap includes depositing a first titanium nitride cap layer on the work function metal layer; performing an oxygen treatment on the first titanium nitride cap layer; and depositing a second titanium nitride cap layer on the first titanium nitride cap layer.

[0060] In yet another embodiment, the first titanium nitride capping layer is deposited in a vacuum-sealed physical vapor deposition (PVD) chamber, wherein the oxygen treatment comprises removing a workpiece having the first titanium nitride capping layer from the PVD chamber; and exposing the first titanium nitride capping layer to an environment outside the PVD chamber.

[0061] In another embodiment, the environment is air at room temperature, and the first titanium nitride cap layer is exposed to the environment for at least 3 hours. In another embodiment, the environment is air at a temperature greater than 30° C., and the first titanium nitride cap layer is exposed to the environment for less than 2 hours.

[0062] In yet another embodiment, after the exposure, the workpiece is placed back into the PVD chamber, and the second titanium nitride capping layer is deposited over the first titanium nitride capping layer in the PVD chamber.

[0063] In another embodiment, the first titanium nitride capping layer is deposited so that a top surface of the first titanium nitride capping layer has a rough surface. In yet another embodiment, a lower portion of the first titanium nitride capping layer is deposited at a first deposition rate, and an upper portion of the first titanium nitride capping layer is deposited at a second deposition rate to form the rough surface, and the second deposition rate is greater than the first deposition rate.

[0064] Another aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; depositing a first titanium nitride cap layer above the work function metal layer; performing an oxygen treatment on the first titanium nitride cap layer; depositing a second titanium nitride cap layer above the first titanium nitride cap layer to form a titanium nitride cap body; depositing a silicon cap layer on the titanium nitride cap body; depositing a conductive adhesion layer on the silicon cap layer; and depositing a gate fill metal layer above the conductive adhesion layer to form a gate structure.

[0065] In one embodiment, before depositing the aforementioned work function metal layer, the method further includes depositing a sacrificial capping layer above the aforementioned high dielectric constant gate dielectric layer; performing a first annealing process on the aforementioned sacrificial capping layer and the aforementioned high dielectric constant gate dielectric layer; and removing the aforementioned sacrificial capping layer. After depositing the aforementioned gate fill metal layer, the method further includes performing a second annealing process on the aforementioned gate structure so that the oxygen atoms in the aforementioned titanium nitride capping body diffuse into the aforementioned high dielectric constant gate dielectric layer. In another embodiment, before depositing the aforementioned second titanium nitride capping layer, the method further includes depositing an intermediate titanium nitride capping layer (middle TiN capping layer) above the aforementioned first titanium nitride capping layer. The aforementioned intermediate titanium nitride capping layer is subjected to an oxygen treatment. The aforementioned second titanium nitride capping layer is deposited above the aforementioned intermediate titanium nitride capping layer.

[0066] In one embodiment, the TiN cap has an oxygenated region between a top region and a bottom region, the oxygenated region having a higher oxygen concentration than the top region and the bottom region. In one embodiment, the oxygen treatment includes exposing the first titanium nitride cap layer to an environment outside a vacuum chamber. In one embodiment, before the oxygen treatment, the method further includes performing a cleaning process on a top surface of the first titanium nitride cap layer.

[0067] Another aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a high-k gate dielectric layer above a channel region of a substrate; depositing a work function metal layer above the high-k gate dielectric layer; depositing a bottom titanium nitride capping layer above the work function metal layer; subjecting the bottom titanium nitride capping layer to an oxygen treatment; depositing one or more middle titanium nitride capping layers on the bottom titanium nitride capping layer; subjecting the one or more middle titanium nitride capping layers to an oxygen treatment; depositing a top titanium nitride capping layer above the one or more middle titanium nitride capping layers to form a titanium nitride cap; depositing a silicon capping layer on the titanium nitride cap; depositing a conductive adhesion layer on the silicon capping layer; and depositing a gate fill metal layer above the conductive adhesion layer to form a gate structure.

[0068] In one embodiment, each deposited intermediate titanium nitride cap layer is subjected to an oxygen treatment. In one embodiment, the titanium nitride cap comprises a plurality of oxygenated regions interposed between non-oxygenated regions, wherein the oxygenated regions have a higher oxygen concentration than the non-oxygenated regions.

[0069] In one embodiment, the method further comprises performing an annealing process on the gate structure so that oxygen atoms in the titanium nitride cap diffuse into the high-k gate dielectric layer.

[0070] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the appended claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a high-k gate dielectric layer over a channel region of a substrate; Depositing a work function metal layer over the high dielectric constant gate dielectric layer; forming a titanium nitride cap over the work function metal layer, wherein the titanium nitride cap includes one or more oxygen-filled regions; Depositing a silicon cap layer on the titanium nitride cap; depositing a conductive adhesion layer on the silicon cap layer; as well as A gate filling metal layer is deposited on the conductive adhesive layer to form a gate structure.

2. The method of claim 1, further comprising: An annealing process is performed on the gate structure to diffuse oxygen atoms in the titanium nitride cap into the high-k gate dielectric layer.

3. The method of claim 1, wherein forming the titanium nitride cap comprises: Depositing a first titanium nitride capping layer on the work function metal layer; performing an oxygen treatment on the first titanium nitride cap layer; as well as A second titanium nitride capping layer is deposited on the first titanium nitride capping layer.

4. The method of claim 3, wherein the first titanium nitride capping layer is deposited in a vacuum sealed physical vapor deposition chamber, wherein the oxygen treatment comprises: removing a workpiece having the first titanium nitride capping layer from the physical vapor deposition chamber; as well as The first titanium nitride capping layer is exposed to an environment outside the physical vapor deposition chamber. 5 . The method of claim 4 , wherein the first titanium nitride capping layer is deposited such that a top surface of the first titanium nitride capping layer has a rough surface.

6. A method for forming a semiconductor device, characterized in that: include: forming a high-k gate dielectric layer above a channel region of a substrate; Depositing a work function metal layer over the high dielectric constant gate dielectric layer; Depositing a first titanium nitride capping layer on the work function metal layer; performing an oxygen treatment on the first titanium nitride cap layer; Depositing a second titanium nitride capping layer on the first titanium nitride capping layer to form a titanium nitride cap; Depositing a silicon cap layer on the titanium nitride cap; depositing a conductive adhesion layer on the silicon cap layer; as well as A gate filling metal layer is deposited on the conductive adhesive layer to form a gate structure.

7. The method according to claim 6, Before depositing the work function metal layer, the method further comprises: depositing a sacrificial capping layer over the high-k gate dielectric layer; Performing a first annealing process on the sacrificial capping layer and the high-k gate dielectric layer; as well as removing the sacrificial cover layer, After depositing the gate filling metal layer, the method further comprises: A second annealing process is performed on the gate structure to diffuse oxygen atoms in the titanium nitride cap into the high-k gate dielectric layer.

8. The method of claim 6, wherein the titanium nitride cap has an oxygenated region between a top region and a bottom region, the oxygenated region having a higher oxygen concentration than the top region and the bottom region.

9. A method for forming a semiconductor device, characterized in that: include: forming a high-k gate dielectric layer over a channel region of a substrate; Depositing a work function metal layer on top of the high dielectric constant gate dielectric layer; depositing a bottom titanium nitride capping layer above the work function metal layer; performing an oxygen treatment on the bottom titanium nitride cap layer; depositing one or more intermediate titanium nitride capping layers on the bottom titanium nitride capping layer; performing an oxygen treatment on the one or more intermediate titanium nitride cap layers; Depositing a top titanium nitride cap layer on the one or more intermediate titanium nitride cap layers to form a titanium nitride cap; Depositing a silicon cap layer on the titanium nitride cap; depositing a conductive adhesion layer on the silicon cap layer; as well as A gate filling metal layer is deposited on the conductive adhesive layer to form a gate structure.

10. The method of claim 9, wherein each of the deposited one or more intermediate titanium nitride capping layers is subjected to an oxygen treatment.

Images