A relaxation oscillator and a calibration circuit

Abstract

The present invention discloses a relaxation oscillator and a calibration circuit. In the oscillator circuit, the bias circuit includes a resistor R1 and MOS transistors M0, M1, and M2, and is used to generate a bias current; the current mirror includes three MOS transistors M7, M8, and M9 connected in sequence, and is used to accurately copy the bias current generated by the bias circuit to charge the capacitor of the relaxation oscillator; the back gate of M0 is connected to the output of the operational amplifier. In the case of layout mismatch, an ERROR voltage is generated at the back gate of M2, and the back gate voltage of M0 is adjusted through the operational amplifier; MOS transistors M5 and M6 are connected to the differential input terminals of the operational amplifier and connected to the current mirror to form negative feedback to adjust the threshold voltage of M0, so that the gate-source voltages of M0 and M2 are equal, and the bias current is restored to the normal value. The relaxation oscillator can reduce the layout matching requirements through the calibration circuit of the present invention, and adjust the back gate voltage of M0 through the loop in the case where the layout is difficult to match, thereby improving the accuracy of the clock signal.

Description

Technical Field

[0001] The present invention relates to the technical field of relaxation oscillators, and particularly to a relaxation oscillator and a calibration circuit. Background Art

[0002] In modern electronic systems, many low-cost monolithic applications require on-chip integrated oscillators to provide stable clock signals. Traditional CMOS standard processes provide various oscillator design options to meet this requirement, including: RC ring oscillators and relaxation oscillators, etc.

[0003] RC ring oscillators are favored by some applications for their simple structure and low cost. However, the frequency stability of such oscillators is usually affected by changes in resistance and capacitance values. Especially under environmental factors such as temperature changes and power supply voltage fluctuations (PVT: Process, Voltage, Temperature), their frequency stability will decrease significantly, thus limiting their use in applications that require high-precision clock signals.

[0004] In contrast, relaxation oscillators are widely welcomed by engineers for their high precision and relatively easy implementation. Relaxation oscillators generate oscillation signals by controlling the charging and discharging process of capacitors, and their frequency stability mainly depends on the matching degree between capacitors and current sources. Many engineers have proposed various innovative designs to improve the PVT stability of relaxation oscillators, such as using constant current sources, temperature compensation circuits, etc.

[0005] However, these designs require a high degree of matching between devices, especially the matching between capacitors and current sources, which increases the difficulty of layout design. In actual production, due to factors such as process deviations and temperature gradients, the performance of the actually produced products often degrades, resulting in the frequency accuracy of the oscillator not meeting the design requirements. To solve this problem, many engineers rely on trimming means to ensure the accuracy of the oscillator. Trimming means usually include fine-tuning the circuit after production to compensate for the influence of process deviations and temperature changes on the circuit performance. However, trimming means not only increase the production cost and complexity, but also cannot fundamentally solve the device matching problem.

[0006] Therefore, how to design a relaxation oscillator with high PVT stability, reduce the influence of the matching degree between key devices of the relaxation oscillator on the accuracy, and reduce the dependence on the process has become an important technical challenge in current low-cost monolithic applications. Summary of the Invention

[0007] The problem to be solved by the present invention is: to provide a relaxation oscillator and a calibration circuit, which enhance the matching degree between devices through circuit design, reduce the influence of the matching degree between key devices of the relaxation oscillator on the accuracy, and reduce the dependence on the process.

[0008] The present invention adopts the following technical solution: A relaxation oscillator calibration circuit, comprising: a bias circuit, a current mirror, and an operational amplifier;

[0009] The bias circuit includes: a resistor R1 and MOS transistors M0, M1, and M2, which are used to generate a bias current; the current mirror includes three MOS transistors M7, M8, and M9 connected in sequence, which are used to copy the bias current generated by the bias circuit; the bias current is copied by the current mirror and used to charge the capacitor of the relaxation oscillator;

[0010] The back gate of MOS transistor M0 is connected to the output of the operational amplifier. In the case of layout mismatch, an ERROR voltage is generated at the back gate of MOS transistor M2. The back gate voltage of MOS transistor M0 is adjusted through the operational amplifier to make the gate-source voltage of MOS transistor M0 equal to the gate-source voltage of MOS transistor M2, and the bias current is restored to the matching value;

[0011] The operational amplifier includes MOS transistors M3, M4, M5, and M6; MOS transistors M3 and M4 are load transistors; the gates of MOS transistors M5 and M6 are connected to the differential input terminals of the operational amplifier, and the sources are connected to the current mirror; the operational amplifier is used to form negative feedback and adjust the threshold voltage of MOS transistor M0.

[0012] Preferably, MOS transistors M0, M1, and M2 are NMOS transistors of the same size. The two ends of resistor R1 are respectively connected to the sources of MOS transistors M0 and M1. The drain of MOS transistor M0 is connected to the drain of MOS transistor M7, and the drain of MOS transistor M2 is connected to the drain of MOS transistor M8; the drain of MOS transistor M1 is connected to the source of MOS transistor M2.

[0013] Preferably, in the current mirror, the three MOS transistors M7, M8, and M9 are all PMOS transistors. The sources of the three MOS transistors are connected together, and the gates are also connected together and connected to the drain of MOS transistor M0; the drain of MOS transistor M7 is connected to the drain of MOS transistor M0, the drain of MOS transistor M8 is connected to the drain of MOS transistor M2, and the drain of MOS transistor M9 is connected to the sources of MOS transistors M5 and M6.

[0014] Preferably, the non-inverting input terminal of the operational amplifier is connected to a fixed voltage , the inverting input terminal is connected between resistor R1 and the source of MOS transistor M0, and the output terminal is connected to the back gate of MOS transistor M0. When there is a layout mismatch, an ERROR voltage is generated between the drain of MOS transistor M1 and the source of MOS transistor M2.

[0015] Preferably, in the calibration circuit, MOS transistors M5 and M6 are PMOS transistors. MOS transistors M5 and M6 are used to connect to the differential input terminals of the operational amplifier. MOS transistor M5 is the inverting input terminal, and MOS transistor M6 is the non-inverting input terminal.

[0016] MOS transistors M3 and M4 are NMOS transistors. The drain of MOS transistor M3 is connected to the drain of MOS transistor M5, the drain of MOS transistor M4 is connected to the drain of MOS transistor M6, and the sources of MOS transistors M3 and M4 are connected to the source of MOS transistor M1.

[0017] Preferably, the gate of MOS transistor M3 is connected to the gate of MOS transistor M1 to form a current mirror load, replicating the current of MOS transistor M1; the gate of MOS transistor M4 is connected to the drain of MOS transistor M4, connected in a diode form, and the drain of MOS transistor M4 is fixed. ;

[0018] The gate of MOS transistor M6 is connected to the drain of MOS transistor M6, and the common-mode input voltage is fixed at the gate-source voltage of MOS transistor M4.

[0019] The drains of MOS transistors M3 and M5 are connected and used as an output to connect to the back gate of MOS transistor M0, forming a loop, and the threshold voltage of MOS transistor M0 is regulated through negative feedback.

[0020] Furthermore, the regulation of the threshold voltage of MOS transistor M0 by negative feedback is as follows:

[0021] When the threshold voltage of MOS transistor M0 is higher than the threshold voltage of MOS transistor M2, the voltage across resistor R1 is lower than the threshold voltage of MOS transistor M1. The voltage at the non-inverting input terminal of the operational amplifier increases, the output voltage increases, the back gate voltage of MOS transistor M0 rises, the threshold voltage drops, and the voltage across resistor R1 rises.

[0022] When the threshold voltage of MOS transistor M2 is higher than the threshold voltage of MOS transistor M0, the voltage across resistor R1 is higher than the threshold voltage of MOS transistor M1. The voltage at the inverting input terminal of the operational amplifier increases, the output voltage drops, the back gate voltage of MOS transistor M0 drops, the threshold voltage rises, and the voltage across resistor R1 drops.

[0023] The back gate voltages of MOS transistors M1, M3, and M4 are the same and are highly matched in the layout.

[0024] The technical solution of the present invention also provides a relaxation oscillator, including the calibration circuit as described above. A bias current is generated through the bias circuit, the bias current generated by the bias circuit is replicated through the current mirror and used to charge the capacitor of the relaxation oscillator, and a negative feedback is formed through the operational amplifier to regulate the back gate voltage of MOS transistor M0.

[0025] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0026] 1. The relaxation oscillator proposed by the present invention can achieve a relatively high-precision oscillation frequency. Through RC devices that are independent of the operating temperature, an oscillation frequency that is basically independent of PVT variations can be achieved.

[0027] 2. The calibration circuit proposed by the present invention can reduce the requirements for layout matching. When it is difficult to match the layout, the back-gate voltage of MOS transistor M0 is adjusted through the loop to improve the accuracy of the clock signal. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the working principle of a relaxation oscillator;

[0029] Figure 2 It is the circuit schematic diagram of the relaxation oscillator;

[0030] Figure 3 It is the schematic diagram of the bias circuit of the present invention;

[0031] Figure 4 It is the schematic diagram of the relaxation oscillator calibration circuit of the present invention. Detailed Embodiments

[0032] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the application will be further elaborated in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments made by other researchers in the field based on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbers in the embodiments of the present invention, they are only set for the convenience of description and explanation, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0033] The basic working principle of the existing relaxation oscillator is as Figure 1 shown. The relaxation oscillator includes: a first current source , a second current source , switches , switches , a capacitor, and a comparator. The relaxation oscillator realizes oscillation by repeatedly charging and discharging the capacitor through the current source.

[0034] The working cycle of the relaxation oscillator is divided into the following two stages:

[0035] The first stage: Switch closes, and the current source charges the capacitor, and the capacitor voltage rises. When the capacitor voltage is higher than , the comparator flips, the switch disconnects, and the capacitor stops charging;

[0036] The second stage: Switch closes, the capacitor starts to discharge, the capacitor voltage drops, and when the capacitor voltage is lower than , the comparator flips and enters the first stage again.

[0037] The schematic diagram of a relaxation oscillator is as shown in Figure 2 As shown, MOS transistors M0, M1, M2 and resistor R1 form a bias circuit for generating the current to charge the capacitor. MOS transistors M7 - M12 are current mirrors for accurately replicating the current generated by the bias circuit. The remaining devices are comparators and combinational logic.

[0038] In the bias circuit, MOS transistors M0, M1, M2 are matching transistors with the same size. The bias current generated by the bias circuit is:

[0039] ;

[0040] where is the gate - source voltage of MOS transistors M0, M1, M2, and is the resistance value of resistor R1. The bias current is replicated by the current mirror and used to charge capacitors C0 and C1.

[0041] Figure 2 In , X0, X1, X2 are all inverters. X0 and X1 are connected in sequence and connected to the gate of MOS transistor M3. X2 is connected to the gate of MOS transistor M5. NAND gates X3 and X4 form an RS flip - flop; MOS transistors M4 and M6 are the input terminals of a common - source amplifier. Ignoring the pull - down delay, when capacitors C0 and C1 are charged to

[0042] , MOS transistors M4 and M6 turn on, the comparator flips, changing the input levels of X3 and X4. Ignoring the propagation delay of the comparator, the period of the relaxation oscillator is:

[0043] where R is the resistance value of R1, and C is the capacitance value of capacitors C0 and C1.

[0044] Under ideal conditions, the oscillation frequency of the relaxation oscillator is determined by RC. However, in the layout, since the back - gates of MOS transistors M0, M1, M2 are connected to different potentials, these three devices need to be placed in different wells during layout implementation, making it difficult to match the devices. The unmatched devices cause the bias current to deviate from the ideal value, thus affecting the oscillation frequency.

[0045] Therefore, the present invention proposes a relaxation oscillator calibration circuit to solve the problem of difficult matching on the layout through circuit design, enhance the matching degree between devices, reduce the influence of the matching degree between key devices of the relaxation oscillator on the accuracy, and thus reduce the dependence on the process.

[0046] In an embodiment of the present invention, the calibration circuit, as shown in Figure 4 includes: a bias circuit, a current mirror, and an operational amplifier.

[0047] The bias circuit includes: resistor R1 and MOS transistors M0, M1, and M2, which are used to generate a bias current; the operational amplifier includes MOS transistors M3, M4, M5, and M6; the current mirror includes three MOS transistors M7, M8, and M9 connected in sequence, which are used to accurately copy the bias current generated by the bias circuit.

[0048] Further, the bias circuit is as Figure 3 shown. MOS transistors M0, M1, and M2 are NMOS transistors of the same size. Two ends of resistor R1 are respectively connected to the sources of MOS transistors M0 and M1. The drain of MOS transistor M0 is connected to the drain of MOS transistor M7, and the drain of MOS transistor M2 is connected to the drain of MOS transistor M8; the drain of MOS transistor M1 is connected to the source of MOS transistor M2.

[0049] The back gate of MOS transistor M0 is connected to the output of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to a fixed voltage , the inverting input terminal is connected between resistor R1 and the source of MOS transistor M0, and the output terminal is connected to the back gate of MOS transistor M0. When there is layout mismatch, an ERROR voltage is generated between the drain of MOS transistor M1 and the source of MOS transistor M2. The ERROR voltage is equivalent to the error caused by layout mismatch.

[0050] In the case of layout mismatch, an ERROR voltage is generated at the back gate of MOS transistor M2. The back gate voltage of MOS transistor M0 is adjusted through the added operational amplifier to make the gate-source voltage of MOS transistor M0 equal to the gate-source voltage of MOS transistor M2, and the bias current is restored to the matching value. The non-inverting input terminal of the operational amplifier is connected to a fixed voltage , the inverting input terminal is connected to the voltage across resistor R1, and the output is connected to the back gate of M0.

[0051] Preferably, in the current mirror, the three MOS transistors M7, M8, and M9 are all PMOS transistors. The sources of the three MOS transistors are connected together, and the gates are also connected together and connected to the drain of MOS transistor M0; the drain of MOS transistor M7 is connected to the drain of MOS transistor M0, the drain of MOS transistor M8 is connected to the drain of MOS transistor M2, and the drain of MOS transistor M9 is connected to the sources of MOS transistors M5 and M6.

[0052] Preferably, in the calibration circuit, MOS transistors M5 and M6 are PMOS transistors, and MOS transistors M3 and M4 are NMOS transistors; MOS transistors M3 and M4 are load transistors, and MOS transistors M5 and M6 are used as the differential input terminals of the operational amplifier.

[0053] Among them, MOS transistor M5 is the inverting input terminal, MOS transistor M6 is the non-inverting input terminal, MOS transistors M3 and M4 are load transistors, and the gate of MOS transistor M3 is connected to the gate of MOS transistor M1 to act as a current mirror load to copy the current of MOS transistor M1.

[0054] MOS transistors M4 and M6 are both connected in the diode configuration, where the gates and drains of MOS transistors M4 and M6 are shorted, and the drain of MOS transistor M4 is equal to a fixed voltage. , the non-inverting input voltage Vg of MOS transistor M6 is equal to Vd, and is fixed at the Vd of MOS transistor M4 and , where Vg is the gate voltage and Vd is the drain voltage.

[0055] The drains of MOS transistors M3 and M5 are used as outputs to connect to the back gate of MOS transistor M0, and the threshold voltage of M0 is regulated through negative feedback.

[0056] In this circuit, the back gate voltages of MOS transistors M1, M3, and M4 are the same and can be highly matched in the layout.

[0057] Specifically, if the threshold voltage of MOS transistor M0 is higher than that of MOS transistor M2, the voltage across resistor R1 is lower than the threshold voltage of M1, which is the gate of MOS transistor M6. The non-inverting input of the operational amplifier increases, the output increases, the back gate voltage of MOS transistor M0 rises, the threshold voltage drops, and the voltage across resistor R1 rises.

[0058] Conversely, if the threshold voltage of MOS transistor M2 is higher than that of MOS transistor M0, the voltage across resistor R1 is higher than the threshold voltage of MOS transistor M1. The inverting input of the operational amplifier increases, the output drops, the back gate voltage of MOS transistor M0 drops, the threshold voltage rises, and the voltage across resistor R1 drops.

[0059] This embodiment also proposes a relaxation oscillator, which includes the above calibration circuit. A bias current is generated by the bias circuit in the calibration circuit. After accurately replicating the bias current generated by the bias circuit through the current mirror in the calibration circuit, a capacitor of the relaxation oscillator is charged, and the back gate voltage of MOS transistor M0 is regulated through negative feedback formed by the operational amplifier.

[0060] The relaxation oscillator proposed in this embodiment can achieve a relatively high-precision oscillation frequency. By using RC devices that are independent of the operating temperature, an oscillation frequency that is basically independent of PVT variations can be achieved. The proposed calibration circuit can reduce the requirements for layout matching. In the case where layout matching is difficult, the back gate voltage of MOS transistor M0 is regulated through the loop to achieve the stability of the bias circuit.

[0061] The above description is only a preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A relaxation oscillator calibration circuit, characterized in that: Applied to relaxation oscillator, including: bias circuit, current mirror, operational amplifier; The bias circuit includes: a resistor R1 and MOS tubes M0, M1, and M2, which are used to generate a bias current; the current mirror includes three MOS tubes M7, M8, and M9 connected in sequence, which are used to replicate the bias current generated by the bias circuit; the bias current is replicated by the current mirror to charge the capacitor of the relaxation oscillator; The back gate of the MOS tube M0 is connected to the output of the operational amplifier. In the case of layout mismatch, the back gate of the MOS tube M2 generates an ERROR voltage. The back gate voltage of the MOS tube M0 is adjusted by the operational amplifier to make the gate-source voltage of the MOS tube M0 equal to the gate-source voltage of the MOS tube M2, and the bias current is restored to the matching value. The operational amplifier includes MOS tubes M3, M4, M5, and M6; MOS tubes M3 and M4 are load tubes; the gates of MOS tubes M5 and M6 are connected to the differential input terminals of the operational amplifier, and the sources are connected to the current mirror; the operational amplifier is used to form negative feedback to adjust the threshold voltage of the MOS tube M0; In the current mirror, the three MOS tubes M7, M8, and M9 are all PMOS tubes, the sources of the three MOS tubes are connected, and the gates are also connected and connected to the drain of the MOS tube M0; the drain of the MOS tube M7 is connected to the drain of the MOS tube M0, the drain of the MOS tube M8 is connected to the drain of the MOS tube M2, and the drain of the MOS tube M9 is connected to the sources of the MOS tubes M5 and M6.

2. The relaxation oscillator calibration circuit according to claim 1, characterized in that: In the bias circuit, MOS tubes M0, M1, and M2 are NMOS tubes of the same size, two ends of the resistor R1 are respectively connected to the sources of the MOS tubes M0 and M1, the drain of the MOS tube M0 is connected to the drain of the MOS tube M7, the drain of the MOS tube M2 is connected to the drain of the MOS tube M8; the drain of the MOS tube M1 is connected to the source of the MOS tube M2.

3. The relaxation oscillator calibration circuit according to claim 2, characterized in that: The non-inverting input terminal of the op amp is connected to a fixed voltage The reverse input terminal is connected between the resistor R1 and the source of the MOS tube M0, and the output terminal is connected to the back gate of the MOS tube M0. When the layout does not match, an ERROR voltage is generated between the drain of the MOS tube M1 and the source of the MOS tube M2.

4. The relaxation oscillator calibration circuit according to claim 3, characterized in that: MOS tubes M5 and M6 are PMOS tubes, and are used to access the differential input terminals of the operational amplifier. MOS tube M5 is the reverse input terminal, and MOS tube M6 is the non-inverting input terminal.

5. The relaxation oscillator calibration circuit according to claim 4, characterized in that: The MOS tubes M3 and M4 are NMOS tubes, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the sources of the MOS tubes M3 and M4 are connected to the source of the MOS tube M1.

6. The relaxation oscillator calibration circuit according to claim 5, characterized in that: The gate of MOS tube M3 is connected to the gate of MOS tube M1 as a current mirror load to copy the current of MOS tube M1; the gate of MOS tube M4 is connected to the drain of MOS tube M4 to form a diode. The drain of MOS tube M4 is equal to a fixed voltage. ; The gate of the MOS tube M6 is connected to the drain of the MOS tube M6, and the same-direction input voltage is fixed to the gate-source voltage of the MOS tube M4; The drains of the MOS tube M3 and the MOS tube M5 are connected to each other, and are connected to the back gate of the MOS tube M0 as an output to form a loop, and the threshold voltage of the MOS tube M0 is adjusted through negative feedback.

7. The relaxation oscillator calibration circuit according to claim 6, characterized in that: The negative feedback adjusts the threshold voltage of the MOS tube M0 as follows: When the threshold voltage of the MOS tube M0 is higher than the threshold voltage of the MOS tube M2, the voltage of the resistor R1 is lower than the threshold voltage of the MOS tube M1, the voltage of the same-direction input terminal of the operational amplifier increases, the output voltage increases, the back gate voltage of the MOS tube M0 increases, the threshold voltage decreases, and the voltage of the resistor R1 increases; When the threshold voltage of the MOS tube M2 is higher than the threshold voltage of the MOS tube M0, the voltage of the resistor R1 is higher than the threshold voltage of the MOS tube M1, the voltage at the reverse input terminal of the operational amplifier increases, the output voltage decreases, the back gate voltage of the MOS tube M0 decreases, the threshold voltage increases, and the voltage of the resistor R1 decreases.

8. The relaxation oscillator calibration circuit according to claim 6, characterized in that: The back gate voltages of the MOS tubes M1, M3, and M4 are the same.

9. A relaxation oscillator, characterized in that: The relaxation oscillator includes a calibration circuit as described in any one of claims 1 to 8, a bias current is generated by the bias circuit, the bias current generated by the bias circuit is copied by the current mirror to charge the capacitor of the relaxation oscillator, and negative feedback is formed by the operational amplifier to adjust the back gate voltage of the MOS tube M0.

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