Processing of tuned transistor threshold voltage

Abstract

The invention discloses a process for tuning a transistor threshold voltage. A method includes forming a source / drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas including nitrogen and hydrogen, and forming a second portion of the semiconductor region. A drive-in process is performed to drive the dipole dopant in the dipole film into the high-k dielectric layer, and a work function layer is deposited on the high-k dielectric layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and more particularly to a process of tuning transistor threshold voltage. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are usually formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.

[0003] The semiconductor industry has been increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated within a given area. However, as the minimum feature size decreases, some new problems have also emerged and need to be solved. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method is provided, including: forming a first source / drain region based on a first portion of a first semiconductor region; forming a first high-k dielectric layer based on a second portion of the first semiconductor region; forming a first dipole film on the first high-k dielectric layer; performing a first treatment process on the first dipole film using a process gas containing nitrogen and hydrogen; performing a first drive-in process to drive a first dipole dopant in the first dipole film into the first high-k dielectric layer; and depositing a first work function layer on the first high-k dielectric layer.

[0005] According to one embodiment of the present disclosure, a method is provided, comprising: forming an interfacial layer on a first semiconductor region and a second semiconductor region; forming a first high-k dielectric layer on the interfacial layer and the first semiconductor region and the second semiconductor region; depositing a dipole film on the first high-k dielectric layer, wherein the dipole film includes a first portion overlapping the first semiconductor region and a second portion overlapping the second semiconductor region; performing a plasma treatment process on the dipole film; removing the second portion of the dipole film; performing a drive-in process to drive a dipole dopant in the dipole film into the first high-k dielectric layer; and forming a first gate electrode and a second gate electrode on the first high-k dielectric layer, wherein the first gate electrode and the second gate electrode are located on the first semiconductor region and the second semiconductor region, respectively.

[0006] According to one embodiment of the present disclosure, a method is provided, comprising: depositing a high-k dielectric layer surrounding a semiconductor nanostructure; depositing a dipole film surrounding the high-k dielectric layer; trimming the dipole film; using nitrogen (N 2 ) and hydrogen (H 2 ) performing a treatment process on the dipole film; performing an annealing process on the treated dipole film; removing the dipole film; depositing a second high-k dielectric layer on the high-k dielectric layer; and forming a gate on the second high-k dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale, but are used for illustration purposes only. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Figure 14-Figure 24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B An intermediate stage in forming a Gate-All-Around (GAA) transistor is shown in accordance with some embodiments.

[0009] Fig.29 A process flow for forming a multi-Vt device according to some embodiments is illustrated. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms, such as "lower," "below," "lower layer," "upper layer," etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) shown in the figures. Spatially relative terms include different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0012] A method for tuning a transistor threshold voltage (Vt) is provided. According to some embodiments of the present disclosure, a dipole film is deposited and can be trimmed to reduce its thickness. 2 ) and hydrogen (H 2 )) is treated with a process gas composed of. This treatment can separate the dipole atoms from their compounds and reduce the adverse effects caused by the heat treatment process, thereby making the dipole drive-in process more effective. It can be understood that although the gate all-around (GAA) transistor is used as an example, the concepts of the present disclosure can be applied to other types of transistors, such as planar transistors, fin field effect transistors (FinFETs), complementary field effect transistors (CFETs), etc.

[0013] The embodiments discussed herein are intended to provide examples so that the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily appreciate the modifications that may be made without exceeding the intended scope of the different embodiments. In the various views and illustrative embodiments, similar reference numerals are used to designate similar elements. Although the method embodiments may be discussed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Figure 14-Figure 24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B An intermediate stage in forming a GAA transistor is shown in accordance with some embodiments. Fig.29 The various processes are shown in the illustrated process flow 200 .

[0015] See also Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., and other substrates and / or structures may also be used, such as a semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments, it may be doped as an n-type semiconductor.

[0016] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes that deposit alternating materials. Fig.29 In the illustrated process flow 200, each process is illustrated as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0017] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed with a first thickness of about to about However, any suitable thickness may be used without departing from the scope of this embodiment.

[0018] Once the first layer 22A is deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, or similar materials, which is different from the first semiconductor material of the first layer 22A. For example, in some embodiments, the first layer 22A is silicon germanium and the second layer 22B can be formed of silicon, or vice versa. It is understood that the first layer 22A and the second layer 22B can use any suitable material combination.

[0019] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique that is similar to the deposition technique used to form the first layer 22A. According to some embodiments, the thickness of the second layer 22B is similar to the thickness of the first layer 22A. The second layer 22B can also be formed with a different thickness than the first layer 22A. According to some embodiments, the second layer 22B can be formed, for example, to be approximately to about A second thickness within the range.

[0020] Once the second layer 22B is formed on the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the topmost layer desired for the multilayer stack 22 is formed. According to some embodiments, the thickness of the first layer 22A is the same or similar to each other, and the thickness of the second layer 22B is the same or similar to each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is also referred to as a sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0021] According to some embodiments, some pad oxide layer(s) and hard mask layer(s) (not shown) are formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0022] refer to Figure 2 , the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in (one or more) etching processes to form trenches 23. The corresponding process is Fig.29 The process flow 200 is illustrated as process 204. The trench 23 extends to the substrate 20. The remaining portion of the multilayer stack is referred to as the multilayer stack 22' below. Below the multilayer stack 22', some portions of the substrate 20 are retained, referred to as substrate strip 20' below. The multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure. The multilayer stack 22' and portions of the underlying substrate strip 20' are collectively referred to as semiconductor strips 24.

[0023] In the embodiments illustrated above, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. In general, a double patterning process or a multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns such as those having a spacing that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0024] Figure 3 The diagram shows the formation process of the isolation regions 26, which are also referred to as shallow trench isolation (STI) regions throughout the description. Fig.29In the process flow 200 shown, the corresponding process flow diagram is process flow 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI region 26 may also include a dielectric material on the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, HDPCVD, or the like. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may then be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material is the STI region 26.

[0025] Then, the STI region 26 is recessed so that the top portion of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portion of the multilayer stack 22' and the substrate strip 20'. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, the NF 3 and NH 3 Argon is used as an etching gas. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical may include HF or the like.

[0026] refer to Figure 4 , a dummy gate stack 30 and a gate spacer 38 are formed on the top surface and sidewalls of the (protruding) fin 28. Fig.29 In the process flow 200 shown, the corresponding process flow diagram is shown as process flow 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer (e.g., a silicon oxide layer). For example, the dummy gate electrode 34 may be formed using polysilicon or amorphous silicon, or other materials such as amorphous carbon.

[0027] Each dummy gate stack 30 may further include a hard mask layer 36 on one (or more) dummy gate electrodes 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. The dummy gate stack 30 may span a single or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The length direction of the dummy gate stack 30 is also perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by (one or more) patterning processes.

[0028] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is made of silicon nitride (SiN), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN) and other dielectric materials, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of the (one or more) dielectric layer is the gate spacer 38.

[0029] Figure 5A and Figure 5B Picture shows Figure 4 Cross-sectional view of the structure shown. Figure 5A Picture shows Figure 4 The reference cross section A1-A1 in FIG. 1 cuts through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38 and is perpendicular to the gate length direction. The figure also illustrates the fin spacer 38 located on the sidewall of the protruding fin 28. Figure 5B Picture shows Figure 4 , which is parallel to the length direction of the protruding fin 28. The fin spacer 39 is also illustrated.

[0030] refer to Fig. 6A and Figure 6B , the portion of the protruding fin 28 that is not directly located at the bottom of the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. Fig.29 In the process flow 200 shown, the corresponding process is illustrated as process 210. For example, C 2 F 6 CF 4 、SO 2 、HBr、Cl 2 and O2 mixture of HBr, Cl 2 , O 2 and CH 2 F 2 The bottom of the recess 42 is at least level with the bottom of the multilayer semiconductor stack 22', or may be lower than (e.g. Figure 6B The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in FIG. Figure 6B shown.

[0031] refer to Fig. 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the corresponding upper nanostructure and lower nanostructure 22B. Fig.29 In the illustrated process flow 200, the corresponding process flow is illustrated as process flow 212. The lateral recessing of the sacrificial semiconductor layer 22A may be achieved by a wet etching process, wherein the etchant used in the process is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may use an immersion process, a spray process, or the like, and may be performed using any suitable process temperature (e.g., between about 400° C. and about 600° C.) and a suitable process time (e.g., between about 100 seconds and about 1,000 seconds). According to an alternative embodiment, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0032] Fig. 8A and Figure 8B The diagram shows the formation process of the internal spacer 44. Fig.29 In the illustrated process flow 200, the corresponding process flow is illustrated as process flow 214. The formation process includes depositing a spacer layer extending into the recess 41, and performing an etching process to remove a portion of the inner spacer layer outside the recess 41, thereby leaving an inner spacer 44 in the recess 41. The inner spacer 44 can be formed or composed of SiOCN, SiON, SiOC, SiCN, or a similar material. The inner spacer 44 can also be porous so that it has a low k value of less than, for example, about 3.5. According to some embodiments, the spacer layer can be etched by a wet etching process, wherein the etching chemistry may include H 2 SO4 , diluted HF, ammonia solution (NH 4 OH, ammonia) or similar substances, or a combination thereof.

[0033] refer to Fig.9A and Fig. 9B , epitaxial source / drain regions 48 are formed in the recess 42. Fig.29 In the illustrated process flow 200, the corresponding process flow is illustrated as process flow 216. According to some embodiments, the source / drain region 48 may stress the nanostructure 22B, which serves as a channel for the corresponding GAA transistor, thereby improving performance. According to some embodiments, the corresponding transistor is n-type, so the epitaxial source / drain region 48 is formed to be n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP) or the like may be grown to form the epitaxial source / drain region 48. After the recess 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 may cause the epitaxial region 48 to expand horizontally and form facets. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other.

[0034] Fig. 10A , Fig. 10B and Fig. 10C A cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 is illustrated. Fig. 10A , Fig. 10B and Fig. 10C Taken from Figure 4 The same cross section as cross sections A2-A2, BB and A1-A1. Fig.29 In the illustrated process flow 200, the corresponding process flow diagram is shown as process flow 218. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may include a dielectric material formed using FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0035] In a subsequent process, a replacement gate stack is formed to replace the dummy gate stack 30. Fig.11A and 11B , a planarization process (eg, a CMP process or a mechanical grinding process) is performed to planarize the top surface of the ILD 52. Fig.29In the process flow 200 shown, the corresponding process is illustrated as process 220. According to some embodiments, the planarization process may remove the hard mask 36 to reveal the dummy gate electrode 34, such as Fig. 11B According to alternative embodiments, the planarization process may expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush with each other within the process variation range.

[0036] Next, if Fig. 12A and Fig. 12B As shown, the dummy gate electrode 34 (and hard mask 36, if any) is removed in one or more etching processes, thereby forming a recess 58. The corresponding process is Fig.29 The process flow 200 shown is illustrated as process 222. Portions of the dummy gate dielectric 32 in the recesses 58 are also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by a dry etching process. For example, the etching process can be performed using the following (one or more) reactive gases: these gases selectively etch the dummy gate electrode 34 at a faster rate than the ILD 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22', including future channel regions in a subsequently completed nanoFET. The corresponding portions of the multilayer stack 22' are between adjacent pairs of epitaxial source / drain regions 48.

[0037] The sacrificial layer 22A is then removed, and recesses 58 are extended between the nanostructures 22B, resulting in a structure such as Fig.13A and Fig. 13B As shown. Fig.29 In the illustrated process flow 200, the corresponding process flow is illustrated as process flow 224. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant that is selective to the material of the sacrificial layer 22A). Compared to the sacrificial layer 22A, the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched. In some embodiments, the sacrificial layer 22A includes SiGe, etc., and the nanostructure 22B includes Si or SiC, etc., and tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) or other etching chemicals to remove the sacrificial layer 22A.

[0038] The above process can be used to form multiple GAA transistors with different Vt. In the subsequent discussion, four device regions are illustrated, each region being used to form a transistor therein. For example, Fig.14Device regions 60-PC, 60-PD, 60-NC, and 60-ND are illustrated where the structures shown are formed using the processes discussed in the previous paragraphs. Device region 60-PD is a p-type transistor region and is a region where a p-type dipole drive-in process is to be performed. Device region 60-PC is a corresponding p-type transistor region where a p-type dipole drive-in process is not performed. Device region 60-ND is an n-type transistor region where an n-type dipole drive-in process is to be performed. Device region 60-NC is a corresponding n-type transistor region where an n-type dipole drive-in process is not performed.

[0039] See also Fig.14 , a gate dielectric 62 is formed to surround the semiconductor nanostructure 22B. Fig.29 In the process flow 200 shown, the corresponding process is illustrated as process 226. According to some embodiments, each gate dielectric 62 includes an interface layer 62A and a high-k dielectric layer 62B on the interface layer 62A. The interface layer 62A can be formed of or include silicon oxide, which can be deposited by a conformal deposition process such as ALD or CVD. According to an alternative embodiment, the interface layer 62A is formed by thermal oxidation. When formed by thermal oxidation, the portion of the interface layer 62A on the top surface of the STI region 26 will not be formed. According to some embodiments, the high-k dielectric layer 62B includes one or more dielectric layers. For example, the high-k dielectric layer 62B may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, a combination thereof and / or a multilayer thereof. The high-k dielectric layer 62B is deposited by a conformal deposition process (e.g., ALD or CVD).

[0040] Figure 14-17 FIG. 6 illustrates dipole doping of an n-type dipole dopant in the device region 60 -ND according to some embodiments. Fig.14 , the dipole film 64 is deposited on the gate dielectric 62 by a conformal deposition process (e.g., CVD, ALD, or the like). Fig.29 In the illustrated process flow 200, the corresponding process is illustrated as process 228. The dipole film 64 is deposited on the device regions 60-PC, 60-PD, 60-NC, and 60-ND. The dipole film 64 may include an n-type dopant, such as La, Sr, Y, Er, Sc, Mg, or the like, or a combination thereof. When the n-type dopant is added to the gate dielectric of an n-type transistor, the effective work function may be reduced, thereby reducing the threshold voltage of the corresponding n-type transistor.

[0041] The dipole film 64 may be deposited as an oxide and / or nitride of the n-type dopant(s). According to some embodiments, the dipole film 64 deposited on the upper nanostructure 22B may be merged with the dipole film 64 deposited on the corresponding lower nanostructure 22B. According to other embodiments, at the end of deposition, the dipole film 64 deposited on the upper nanostructure 22B may be physically separated from the dipole film 64 deposited on the corresponding lower nanostructure 22B.

[0042] According to some embodiments, the dipole film 64 is trimmed in a trimming process 65. The trimming process 65 may be performed by an isotropic etching process to isotropically etch the dipole film 64 to reduce its thickness to a desired value, for example, about 1000 Å. Peace Since the dipole film 64 is thinner, the trimming process 65 can make the subsequent treatment process more effective, and the bonds of the dipole dopants closer to the high-k dielectric layer 62B may be broken, thereby making the subsequent drive-in process more effective.

[0043] According to some embodiments, after the trimming process 65, N 2 and H 2 Treatment process 67 is performed to treat the dipole film 64. Treatment process 67 can improve the efficiency of the drive-in process, so that the atomic percentage (and concentration) of the dipole dopant diffused into the high-k dielectric layer 62B is increased compared to without treatment. The details of treatment process 67 (including process gases, treatment methods, wafer temperature, etc.) can be compared with treatment process 78 ( Fig.19 ) are basically the same.

[0044] According to an alternative embodiment, the dipole film 64 is not treated with N2 and H2 during the entire period from the first time the dipole film 64 begins to be deposited to the end of the drive-in process 70. By not treating the dipole film 64, the dipole doping efficiency is reduced, thereby generating another Vt tuning level.

[0045] According to alternative embodiments, the treatment process 67 is selectively performed on the dipole films 64 of some transistors, while the treatment process 67 is not performed on the dipole films 64 of some other transistors. For example, according to some embodiments, the dipole films 64 will remain in the device regions 60-NC and 60-ND. In the treatment process 67, the dipole film 64 in the device region 60-ND is selectively treated. On the other hand, the dipole film 64 in the device region 60-NC is protected by a mask (not shown) and is not treated. Therefore, due to the higher drive-in efficiency, the dipole dopant concentration (after dopant drive-in) of the high-k dielectric layer 62B in the device region 60-ND is higher than that of the high-k dielectric layer 62B in the device region 60-NC. Therefore, the threshold voltage of the transistor in the device region 60-ND is lower than the threshold voltage of the transistor in the device region 60-ND, thereby generating two Vt tuning levels.

[0046] refer to Fig.15 After the trimming process 65 and the treatment process 67 (if any), a patterned etch mask 66 is formed. According to some embodiments, the patterned etch mask 66 includes a bottom anti-reflective coating (BARC) patterned using a top layer that may include a patterned photoresist. The top layer is used to etch the BARC so that a portion of the BARC remains in the device region 60-ND, and portions of the BARC in the device regions 60-PC, 60-PD, and 60-NC are removed. The etch mask 66 is then removed.

[0047] Refer to Fig.15 , an etching / patterning process 68 is performed to etch the dipole film 64. The corresponding process is Fig.29 The process flow 200 is shown as process 230. The etching process 68 can be performed before or after the treatment process 67 (if performed). In the etching process 68, the etching mask 66 protects the portion of the dipole film 64 in the device region 60-ND, while the portion of the dipole film 64 in the device regions 60-PC, 60-PD and 60-NC is removed. After the etching process 68 is completed, the etching mask 66 is removed.

[0048] Fig.16 A drive-in process 70 is shown, which is performed by an annealing process to drive the dipole dopants in the dipole film 64 into the high-k dielectric layer 62B. Fig.29 In the illustrated process flow 200, the corresponding process flow diagram is shown as process flow 232. The drive-in process 70 may be performed in a process gas, such as N2, He, NH3, Ar or the like, or a mixture thereof. According to some embodiments, the drive-in process 70 is performed by a soak annealing process, a spike rapid thermal annealing process or the like.

[0049] The drive-in process 70 drives the n-type dipole dopant (eg, La) in the dipole film 64 into the corresponding underlying high-k dielectric layer 62B in the device region 60-ND. The circles represent the dipole dopant. The threshold voltage of the resulting transistor is tuned, for example, lowered.

[0050] According to some embodiments, the process conditions such as annealing time and temperature are controlled to make the peak concentration of the dipole dopant (e.g. Fig.28A and Fig.28B The final transistor shown in FIG. 1 is in the high-k dielectric layer 62B and may be closer to the interface between the high-k dielectric layer 62B and the interface layer 62A than the outer surface of the high-k dielectric layer 62B. When the immersion annealing process is used, the annealing duration may be between about 5 seconds and about 5 minutes. The annealing temperature may be between about 550° C. and about 900° C.

[0051] According to some embodiments, after the drive-in process 70, the Fig.16 The dipole membrane 64 is shown. Fig.29 In the process flow 200 shown, the corresponding process flow is illustrated as process flow 234. According to some embodiments, after the drive-in process 70, Fig.16 The dipole film 64 shown is not removed, so the subsequently deposited dipole film 74 ( Fig.18 ) will be deposited on the dipole film 64. According to some alternative embodiments, after the drive-in process 70, Fig.16 The dipole film 64 shown is thinned but not completely removed. The subsequently deposited dipole film 74 ( Fig.18 ) will also be deposited on the thinned dipole film 64. Therefore, Fig.17 In FIG. 6 , the dipole film 64 is indicated by a dotted line, which may be removed, thinned, or neither removed nor thinned.

[0052] Figures 18 to 24 FIG. 4 illustrates p-type dipole doping performed in device region 60 -PD according to some embodiments. Fig.18 , the dipole film 74 is deposited on the gate dielectric 62 by a conformal deposition process (e.g., CVD, ALD, or the like). Fig.29 In the illustrated process flow 200, a corresponding process flow is illustrated as process flow 236. The dipole film 74 is deposited on the device regions 60-PC, 60-PD, 60-NC, and 60-ND.

[0053] The dipole film 74 may include a p-type dopant, which, when added to the gate dielectric of a p-type transistor, may increase the effective work function, thereby reducing the threshold voltage of the corresponding p-type transistor. According to some embodiments, the p-type dopant may include aluminum (Al), zinc (Zn), and / or the like. The dipole film 74 may be an oxide and / or nitride of the dipole dopant. For example, the dipole film 74 may include AlOx, AlOx, AlNx, TiAlxNy, etc., or a combination thereof.

[0054] According to some embodiments, the deposition of dipole film 74 may be performed using a conformal deposition process such as CVD, ALD, or the like. According to some embodiments, in these embodiments, dipole film 64 includes a portion remaining in device region 60-ND, and dipole film 74 is formed on and in contact with the remaining dipole film 64. Otherwise, in device region 60-ND, dipole film 74 is located on and in contact with high-k dielectric layer 62B.

[0055] According to some embodiments, the dipole film 74 deposited on the upper nanostructure 22B may be merged with the dipole film 74 deposited on the corresponding lower nanostructure 22B. According to alternative embodiments, the dipole film 74 deposited on the upper nanostructure 22B may be physically separated from the dipole film 74 deposited on each lower nanostructure 22B at the end of deposition.

[0056] According to some embodiments, Fig.18 As shown, the dipole film 74 is trimmed in a trimming process 76, such as by an isotropic etching process. The resulting structure is shown in FIG. Fig.19 As shown. Fig.29 In the process flow 200 shown, the corresponding process flow is illustrated as process flow 238. Through the trimming process, the thickness of the dipole film 74 can be increased from the thickness T1 ( Fig.18 ) is reduced to thickness T2( Fig.19 ). The thickness T2 of the dipole film 74 may be about Peace between.

[0057] According to some embodiments, Fig.19 As shown, the processing step 78 is performed. Fig.29 In the process flow 200 shown, the corresponding process flow is illustrated as process flow 240. N 2 and H 2 According to some embodiments, the treatment process 78 may be performed in a process chamber, which may be used for an ashing process. According to some embodiments, the treatment process 78 uses a flow rate of N between about 1,000 sccm and about 4,000 sccm. 2, and H at a flow rate between about 1,500 sccm and about 4,500 sccm 2 .

[0058] The treatment process 78 may also be a plasma treatment process, in which the wafer 10 is exposed to a plasma generated by a treatment gas. According to some embodiments, the treatment process 78 may be performed without heating the wafer 10 to minimize the thermal budget and the threshold voltage drift caused by the thermal budget. According to other embodiments, the treatment process may be a thermal treatment process, in which each wafer 10 is heated to a temperature between about 245° C. and about 260° C. The thermal treatment duration may be between about 0.3 minutes and about 15 minutes. The treatment process may also be a thermal treatment process and a plasma treatment process. The plasma treatment duration may be between about 0.3 minutes and about 1.5 minutes.

[0059] According to some embodiments, the process conditions of the treatment process 78 (eg, source power for generating plasma, N 2 and H 2 The partial pressure and / or flow rate) and the processing process 67 ( Fig.14 According to an alternative embodiment, the process conditions of the treatment process 78 are different from the process conditions of the treatment process 67 for treating the dipole film 64.

[0060] According to some embodiments, treatment process 78 may generate radicals and / or ions of hydrogen and nitrogen that are incorporated into high-k dielectric layer 62B. Treatment process 78 may also destroy the bonds of dipole film 64 that are formed between the dipole dopant atoms and the oxygen and / or nitrogen atoms. As a result, the dipole dopant is more likely to enter high-k dielectric layer 62B. Therefore, the concentration and atomic percentage of the dipole dopant in high-k dielectric layer 62B may be higher than if treatment process 78 is not performed. Therefore, the threshold voltage adjustment (reduction of the threshold voltage) caused by the addition of the dipole dopant is more significant.

[0061] The treatment process 78 may be performed on all the dipole films 74 in all the device regions, or may be selectively performed on some device regions but not all the device regions. For example, the treatment process 78 may be performed on the dipole films 74 in the device region 60-PD, but not on the dipole films 74 in the device region 60-PC. According to these embodiments, when the selective treatment process is performed, the dipole films 74 in the device regions 60-PC and 60-PD are not removed, and the drive-in process 82 ( Fig.21) will drive the dipole dopants in device regions 60-PC and 60-PD into their respective high-k dielectric layers 62B. Due to the selective processing process, the high-k dielectric layer 62B in device region 60-PD (which receives the selective processing) will have a higher dipole doping percentage (and dipole dopant concentration) than the high-k dielectric layer 62B in device region 60-PC (which does not receive the selective processing process 78). Therefore, the threshold voltage of the transistor in device region 60-PD will be lower than the threshold voltage of the transistor in device region 60-PC.

[0062] refer to Fig. 20 , forming a patterned etch mask 79. According to some embodiments, the patterned etch mask 79 includes a BARC that is patterned using a top layer that may include a patterned photoresist. The top layer is used to etch the BARC so that a portion of the BARC remains in the device region 60-PD, while portions of the etch mask 79 in the device regions 60-PC, 60-NC, and 60-ND are removed.

[0063] Refer to Fig. 20 , performing (one or more) etching / patterning processes 80 to etch some portions of the dipole film 74. Fig.29 In the process flow 200 shown, the corresponding process diagram is process 242. During the etching process, the etching mask 79 protects the dipole film 74 in the device region 60-PD, while removing the dipole film 74 in the device regions 60-PC, 60-NC, and 60-ND. After the etching process 80 is completed, the etching mask 79 is removed. According to some embodiments (such as Fig.17 ), the dipole film 64 in the device region 60-ND is still not removed.

[0064] According to some embodiments, the treatment process 78 is performed before the dipole film 74 is patterned. According to other embodiments, the treatment process 78 is performed after the dipole film 74 is patterned.

[0065] Fig.21 The driving-in process 82 through the annealing process is shown. Fig.29 In the process flow 200 shown, the corresponding process flow diagram is shown as process flow 244. The driving process 82 can be carried out in a process gas such as N 2 , He, NH 3, Ar or similar gases or mixtures thereof. According to some embodiments, the drive-in process 82 is performed by an immersion annealing process, a spike rapid thermal annealing process or a similar process. According to some embodiments, the process conditions such as annealing time and temperature are controlled so that the peak concentration of the dipole dopant is in the high-k dielectric layer 62B and may be close to the interface between the high-k dielectric layer 62B and the interface layer 62A. When the immersion annealing process is used, the annealing duration may be between about 5 seconds and about 5 minutes. The annealing temperature may be between about 550° C. and about 900° C.

[0066] According to some embodiments, the process conditions (eg, duration, method, and / or temperature) of the drive-in process 82 are different from those of the drive-in process 70 ( Fig.16 ) process conditions to accommodate the different diffusion rates of different dipole dopants.

[0067] The drive-in process 82 drives the p-type dipole dopant (e.g., Al) in the dipole film 74 into the corresponding underlying high-k dielectric layer 62B in the device region 60-PD. The circles represent the dipole dopant. As a result, the threshold voltage of the resulting transistor is tuned, e.g., lowered.

[0068] In some embodiments, when the doping process 82 is performed, some portions of the dipole film 64 remain in the device region 60-PD, and more n-type dipole dopants in the device region 60-PD are also doped into the corresponding portions of the high-k dielectric layer 62B in the dipole film 64 according to the doping process 82. Therefore, the concentration of the n-type dipole dopant in the high-k dielectric layer 62B in the device region 60-ND is further increased, and the threshold voltage of the transistor in the device region 60-ND is further reduced, thereby generating another level of Vt adjustment.

[0069] According to some embodiments, after the drive-in process 82, the Fig.21 The dipole membrane 74 is shown. Fig.29 In the process flow 200 shown, the corresponding process flow diagram is shown as process flow 246. The remaining dipole film 64 is also removed. The resulting structure is as shown in FIG. Fig. 22 shown.

[0070] Fig.23 and Fig.24 The process of forming the remaining portion of the gate stack and the corresponding transistor according to some embodiments is illustrated. Fig.29 In the process flow 200 shown in FIG. 1 , the corresponding process flow diagram is shown as process flow 248. Fig.23, a second high-k dielectric layer 62C is deposited to further form a gate dielectric 62. The material of the second high-k dielectric layer 62C may be the same as or different from the material of the high-k dielectric layer 62B. According to an alternative embodiment, no high-k dielectric layer is deposited on the high-k dielectric layer 62B, and the subsequently deposited conductive layer (including an adhesion layer, a barrier layer, and / or a capping layer) contacts the high-k dielectric layer 62B. Therefore, the high-k dielectric layer 62C is represented by a dotted line, indicating that it may or may not be formed.

[0071] Next, if Fig.24 As shown, a conductive layer 84 and a fill metal 86 are formed. According to some embodiments, the conductive layer 84 and the fill metal 86 in the device regions 60-PC and 60-PD are formed using a common material in a common process, or are formed using different materials in different processes. The conductive layer 84 and the fill metal 86 in the device regions 60-NC and 60-ND may be formed by a common process and a common material, or may be formed by different processes and different materials. For example, the transistors formed in the device regions 60-PC and 60-PD have an opposite conductivity type to the transistors formed in the device regions 60-NC and 60-ND. Therefore, the working function layers in the device regions 60-PC and 60-PD may be formed of a material different from that of the transistors in the device regions 60-NC and 60-ND.

[0072] According to some embodiments, the conductive layer 84 in the device regions 60-PC and 60-PD may include a p-type working functional layer, which may include TiN, TaN, TiSiN, WCN, MOCN, or a combination thereof. The conductive layer 84 in the device regions 60-NC and 60-ND may include an n-type working functional layer, which may include TiAlC, TiAlN, TaAlC, TaAlN, etc., or a combination thereof.

[0073] If the remaining recess 58 ( Fig.13A and 13B ) is not completely filled, a filling metal 86 may be formed to fill the recess 58. The filling metal 86 may include a metal-containing material such as cobalt, ruthenium, aluminum, tungsten, a combination thereof, and / or a multilayer film thereof. Fig.24 As shown, transistors 100 -PC, 100 -PD, 100 -NC, and 100 -ND are formed in device regions 60 -PC, 60 -PD, 60 -NC, and 60 -ND, respectively.

[0074] Fig.25A and FIG. 25B to FIG. 28A and Fig.28B The remaining gate stack and contact plugs formed in accordance with some embodiments are illustrated. Fig.25A and FIG. 25B to FIG. 28A and Fig.28BSubsequent figure numbers in the may be followed by the letters A or B. The letter A indicates that the corresponding figure shows Figure 4 The letter B indicates that the corresponding figure shows the same cross section as A2-A2 in Figure 4 The device regions 60-PC, 60-PD, 60-NC and 60-ND ( Fig. 22 ) can be obtained by Fig.25A and FIG. 25B to FIG. 28A and Fig.28B The process is formed in order to complete the formation of a transistor, the transistor having a tuned or non-tuned threshold voltage. Fig.25A and FIG. 25B to FIG. 28A and Fig.28B The formation process shown can represent Fig.24 The formation process of each transistor in the circuit.

[0075] refer to Fig.25A and Fig.25B , forming a stacked conductive layer 84 and a filling metal 86. The relevant process has been referred to Fig.23 and Fig.24 was discussed. Fig.25A and Fig.25B , high-k dielectric layer 62C is not shown, but it may also be present.

[0076] refer to Fig.26A and Fig.26B After filling the recess 58, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess portion of the gate dielectric and remove the material of the stacked conductive layer 84 and the filling metal 86, which are located above the top surface of the ILD 52. The remaining portions of the conductive layer 84 and the filling metal 86 form a gate electrode 88. The gate electrode 88 and the gate dielectric 62 are collectively referred to as a gate stack 90.

[0077] Next, if Fig.27A and Fig.27B As shown, the gate stack 90 is recessed to form a recess directly above the gate stack 90 and between the opposing portions of the gate spacers 38. A gate mask 92 composed of one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or the like) is filled in the recess and then planarized to remove excess portions of the dielectric material extending onto the ILD 52.

[0078] like Fig.27A and Fig.27BAs shown, ILD 96 is deposited on ILD 52 and gate mask 92. Before forming ILD 96, an etch stop layer (not shown) may or may not be deposited. According to some embodiments, ILD 96 is formed by FCVD, CVD, PECVD, or the like. ILD 96 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0079] exist Fig.28A and Fig.28B In the embodiment, ILD 96, ILD 52, CESL 50, and gate mask 92 are etched to form recesses (occupied by contact plugs 102A and 102B), through which the surfaces of epitaxial source / drain regions 48 and / or gate stack 90 are exposed. The recesses may be formed by etching using an anisotropic etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), or the like).

[0080] After the recess is formed, a silicide region 98 is formed on the epitaxial source / drain region 48 ( Fig.28B ). Then, source / drain contact plugs 102B are formed on the silicide region 98. In addition, a gate contact 102A is formed in the recess and covers and contacts the gate 88. Fig.28B The contact plugs 102A and 102B are shown to have the same cross-section, but in different embodiments, the contact plugs 102A and 102B may be formed with different cross-sections to reduce the risk of shorting each other. Therefore, GAA transistors 100-PC, 100-PD, 100-NC, and 100-ND represented by GAA transistor 100 are formed in device regions 60-PC, 60-PD, 60-NC, and 60-ND, respectively. Fig.24 )middle.

[0081] By treating the dipole film, more dipole dopants can be incorporated into the high-k dielectric layer. For example, when aluminum is used as a p-type dipole dopant, when the aluminum signal in the high-k dielectric layer is detected using energy dispersive spectroscopy (EDS), if no treatment is performed, the signal intensity is 1.7 (normalized value). When a treatment process of about 20 seconds to about 30 seconds is formed on the respective dipole films, the signal intensity can increase to about 1.9, indicating that the aluminum concentration in the high-k dielectric layer is increased.

[0082] The embodiments of the present disclosure have some advantageous features. By performing a processing process, more dipole dopants can be incorporated into the high-k dielectric layer of the transistor, thereby improving the ability to tune the threshold voltage.

[0083] According to some embodiments of the present disclosure, a method includes forming a first source / drain region based on a first portion of a first semiconductor region; forming a first high-k dielectric layer based on a second portion of the first semiconductor region; forming a first dipole film on the first high-k dielectric layer; performing a first treatment process on the first dipole film using a process gas containing nitrogen and hydrogen; performing a first drive-in process to drive a first dipole dopant in the first dipole film into the first high-k dielectric layer; and depositing a first work function layer on the first high-k dielectric layer.

[0084] In one embodiment, the method further comprises removing the first dipole film after the first drive-in process. In one embodiment, the method further comprises depositing a second high-k dielectric layer on the first high-k dielectric layer after removing the first dipole film. In one embodiment, the method further comprises trimming the first dipole film before the first drive-in process. In one embodiment, the first treatment process comprises a plasma treatment process. In one embodiment, the first treatment process is performed without heating the wafer comprising the first dipole film.

[0085] In one embodiment, the first source / drain region is a p-type source / drain region, and the method further includes: forming a second source / drain region based on a first portion of the second semiconductor region, wherein the second source / drain region is n-type; forming a second high-k dielectric layer based on a second portion of the second semiconductor region; forming a second dipole film on the second high-k dielectric layer, wherein the second dipole film includes a second dipole dopant different from the first dipole dopant; performing a second drive-in process to drive the second dipole dopant into the second high-k dielectric layer; and depositing a second work function layer on the second high-k dielectric layer.

[0086] In one embodiment, the method further comprises performing a second treatment process on the second dipole film using an additional process gas comprising nitrogen and hydrogen, wherein the first treatment process and the second treatment process are separate processes. In one embodiment, the first treatment process and the second treatment process are performed using different processing conditions. In one embodiment, the first dipole dopant comprises lanthanum.

[0087] In one embodiment, the first semiconductor region includes a semiconductor nanostructure. In one embodiment, the method further includes forming an additional high-k dielectric layer on the additional semiconductor region, wherein the first dipole film further includes an additional portion formed on the additional high-k dielectric layer; and before the first drive-in process, removing the additional portion of the first dipole film.

[0088] According to some embodiments of the present disclosure, a method includes: forming an interface layer on a first semiconductor region and a second semiconductor region; forming a first high-k dielectric layer on the interface layer and on the first semiconductor region and the second semiconductor region; depositing a dipole film on the first high-k dielectric layer, wherein the dipole film includes a first portion overlapping the first semiconductor region and a second portion overlapping the second semiconductor region; performing a plasma treatment process on the dipole film; removing the second portion of the dipole film; performing a drive-in process to drive a dipole dopant in the dipole film into the first high-k dielectric layer; and forming a first gate electrode and a second gate electrode on the first high-k dielectric layer, wherein the first gate electrode and the second gate electrode are respectively located on the first semiconductor region and the second semiconductor region.

[0089] In one embodiment, the plasma treatment process is performed using a process gas comprising nitrogen and hydrogen. In one embodiment, the first semiconductor region and the second semiconductor region are semiconductor nanostructures, wherein the first portion and the second portion of the dipole film surround the first semiconductor region and the second semiconductor region, respectively. In one embodiment, the method further includes removing the dipole film after the drive-in process; and depositing a second high-k dielectric layer on the first high-k dielectric layer.

[0090] According to some embodiments of the present disclosure, a method includes depositing a high-k dielectric layer surrounding a semiconductor nanostructure; depositing a dipole film surrounding the high-k dielectric layer; trimming the dipole film; and using nitrogen (N 2 ) and hydrogen (H 2 ) treating the dipole film; annealing the treated dipole film; removing the dipole film; depositing a second high-k dielectric layer on the high-k dielectric layer; and forming a gate electrode on the second high-k dielectric layer. In one embodiment, the treating process is performed by a plasma treatment process. In one embodiment, depositing the dipole film includes depositing aluminum oxide. In one embodiment, depositing the dipole film includes depositing lanthanum oxide.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0092] Example

[0093] Example 1. A method for forming a semiconductor structure, comprising: forming a first source / drain region based on a first portion of a first semiconductor region; forming a first high-k dielectric layer based on a second portion of the first semiconductor region; forming a first dipole film on the first high-k dielectric layer; performing a first treatment process on the first dipole film using a process gas containing nitrogen and hydrogen; performing a first drive-in process to drive a first dipole dopant in the first dipole film into the first high-k dielectric layer; and depositing a first work function layer on the first high-k dielectric layer.

[0094] Example 2. The method of Example 1, further comprising: removing the first dipole film after the first drive-in process.

[0095] Example 3. The method of Example 1, further comprising: depositing a second high-k dielectric layer on the first high-k dielectric layer after removing the first dipole film.

[0096] Example 4. The method of Example 1, further comprising: trimming the first dipole film before the first drive-in process.

[0097] Example 5. The method of Example 1, wherein the first treatment process comprises a plasma treatment process.

[0098] Example 6. The method of Example 5, wherein the first treatment process is performed without heating a wafer including the first dipole film.

[0099] Example 7. A method according to Example 1, wherein the first source / drain region is a p-type source / drain region, and the method further includes: forming a second source / drain region based on a first portion of a second semiconductor region, wherein the second source / drain region is n-type; forming a second high-k dielectric layer based on a second portion of the second semiconductor region; forming a second dipole film on the second high-k dielectric layer, wherein the second dipole film includes a second dipole dopant different from the first dipole dopant; performing a second drive-in process to drive the second dipole dopant into the second high-k dielectric layer; and depositing a second work function layer on the second high-k dielectric layer.

[0100] Example 8. The method of Example 7 further includes performing a second treatment process on the second dipole film using an additional process gas including nitrogen and hydrogen, wherein the first treatment process and the second treatment process are independent processes.

[0101] Example 9. The method of Example 8, wherein the first treatment process and the second treatment process are performed using different process conditions.

[0102] Example 10. The method of Example 1, wherein the first dipole dopant comprises lanthanum.

[0103] Example 11. The method of Example 1, wherein the first semiconductor region comprises a semiconductor nanostructure.

[0104] Example 12. The method of claim 1 further includes: forming an additional high-k dielectric layer on an additional semiconductor region, wherein the first dipole film further includes an additional portion formed on the additional high-k dielectric layer; and removing the additional portion of the first dipole film before the first drive-in process.

[0105] Example 13. A method for forming a semiconductor structure, comprising: forming an interface layer on a first semiconductor region and a second semiconductor region; forming a first high-k dielectric layer on the interface layer and the first semiconductor region and the second semiconductor region; depositing a dipole film on the first high-k dielectric layer, wherein the dipole film includes a first portion overlapping with the first semiconductor region and a second portion overlapping with the second semiconductor region; performing a plasma treatment process on the dipole film; removing the second portion of the dipole film; performing a drive-in process to drive the dipole dopants in the dipole film into the first high-k dielectric layer; and forming a first gate electrode and a second gate electrode on the first high-k dielectric layer, wherein the first gate electrode and the second gate electrode are respectively located on the first semiconductor region and the second semiconductor region.

[0106] Example 14. The method of Example 13, wherein the plasma treatment process is performed using a process gas containing nitrogen and hydrogen.

[0107] Example 15. The method of Example 13, wherein the first semiconductor region and the second semiconductor region are semiconductor nanostructures, and wherein the first portion and the second portion of the dipole film surround the first semiconductor region and the second semiconductor region, respectively.

[0108] Example 16. The method of Example 13 further comprising: removing the dipole film after the drive-in process; and depositing a second high-k dielectric layer on the first high-k dielectric layer.

[0109] Example 17. A method for forming a semiconductor structure, comprising: depositing a high-k dielectric layer surrounding a semiconductor nanostructure; depositing a dipole film surrounding the high-k dielectric layer; trimming the dipole film; using nitrogen (N 2 ) and hydrogen (H 2) performing a treatment process on the dipole film; performing an annealing process on the treated dipole film; removing the dipole film; depositing a second high-k dielectric layer on the high-k dielectric layer; and forming a gate electrode on the second high-k dielectric layer.

[0110] Example 18. The method of Example 17, wherein the treatment process is performed by a plasma treatment process.

[0111] Example 19. The method of Example 17, wherein depositing the dipole film comprises depositing aluminum oxide.

[0112] Example 20. The method of Example 17, wherein depositing the dipole film comprises depositing lanthanum oxide.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first source / drain region based on a first portion of the first semiconductor region; forming a first high-k dielectric layer based on a second portion of the first semiconductor region; forming a first dipole film on the first high-k dielectric layer; performing a first treatment process on the first dipole film using a process gas including nitrogen and hydrogen; performing a first drive-in process to drive a first dipole dopant in the first dipole film into the first high-k dielectric layer; as well as A first work function layer is deposited on the first high-k dielectric layer.

2. The method according to claim 1, further comprising: The first dipole film is removed after the first drive-in process.

3. The method according to claim 1, further comprising: After removing the first dipole film, a second high-k dielectric layer is deposited over the first high-k dielectric layer.

4. The method according to claim 1, further comprising: Before the first driving-in process, the first dipole film is trimmed.

5. The method according to claim 1, wherein: The first treatment process includes a plasma treatment process.

6. The method according to claim 5, wherein: The first treatment process is performed without heating the wafer including the first dipole film.

7. The method according to claim 1, wherein: The first source / drain region is a p-type source / drain region, and the method further comprises: forming a second source / drain region based on the first portion of the second semiconductor region, wherein the second source / drain region is n-type; forming a second high-k dielectric layer based on a second portion of the second semiconductor region; forming a second dipole film on the second high-k dielectric layer, wherein the second dipole film includes a second dipole dopant different from the first dipole dopant; performing a second drive-in process to drive the second dipole dopant into the second high-k dielectric layer; and A second work function layer is deposited on the second high-k dielectric layer.

8. The method according to claim 7 further comprises: A second treatment process is performed on the second dipole film using an additional process gas including nitrogen and hydrogen, wherein the first treatment process and the second treatment process are independent processes.

9. A method for forming a semiconductor structure, comprising: forming an interface layer on the first semiconductor region and the second semiconductor region; forming a first high-k dielectric layer on the interface layer and the first semiconductor region and the second semiconductor region; depositing a dipole film on the first high-k dielectric layer, wherein the dipole film includes a first portion overlapping the first semiconductor region and a second portion overlapping the second semiconductor region; performing a plasma treatment process on the dipole film; removing a second portion of the dipole film; performing a drive-in process to drive the dipole dopant in the dipole film into the first high-k dielectric layer; and A first gate electrode and a second gate electrode are formed on the first high-k dielectric layer, wherein the first gate electrode and the second gate electrode are located on the first semiconductor region and the second semiconductor region, respectively.

10. A method for forming a semiconductor structure, comprising: depositing a high-k dielectric layer surrounding the semiconductor nanostructure; depositing a dipole film surrounding the high-k dielectric layer; trimming the dipole membrane; performing a treatment process on the dipole film using nitrogen (N2) and hydrogen (H2); performing an annealing process on the treated dipole film; removing the dipole film; depositing a second high-k dielectric layer on the high-k dielectric layer; as well as A gate electrode is formed on the second high-k dielectric layer.

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