Chip, preparation method thereof and electronic equipment

Abstract

According to the chip, the preparation method thereof and the electronic equipment, the first oxide layer can be used for blocking electric leakage transmitted from the grid electrode to the first doped cap layer, the electric leakage of the grid electrode is prevented from being further transmitted to the source electrode and the drain electrode, and therefore the reliability of a TDGB grid is improved, and the performance of a transistor is improved. The chip comprises a transistor, and the transistor comprises a channel layer, a first doped cap layer and a grid electrode which are sequentially arranged on a substrate. The transistor further comprises a first oxide layer, and the first oxide layer is located on the periphery of the first doped cap layer and surrounds the first doped cap layer. The material of the first oxide layer and the material of the first doped cap layer have at least two identical elements.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip and a method for preparing the same, and an electronic device. Background Art

[0002] Due to the better switching characteristics, faster switching frequency and lower loss of gallium nitride (GaN) materials, GaN high electron mobility transistors (HEMT) have the advantages of small size, lighter weight, higher efficiency and more energy saving, and have been widely used in various electronic devices.

[0003] However, due to the presence of high-concentration two-dimensional electron gas (2DEG), the Schottky gate cannot deplete the 2DEG in the channel layer under zero bias. That is, taking GaN HEMT as an example, when the gate voltage is zero, there is still current flowing through the channel layer, and a negative voltage needs to be applied to the gate to deplete the 2DEG under the gate and put the GaN HEMT into the off state. When GaN HEMT is applied to circuits, it will reduce the safety of the circuit, increase the complexity of the circuit design, and increase power consumption.

[0004] The p-GaN gate technology is to add a p-GaN layer under the gate to raise the energy band of the 2DEG channel position, so that the 2DEG in the channel is depleted, thereby achieving an enhanced mode. The difficulty of this technology lies mainly in the need to etch the p-GaN layer of tens of nanometers, which poses challenges to the roughness, uniformity, and selectivity of the etching process, and is prone to cause problems such as uneven etching and interface damage (including interface states, dangling bonds, etc.). If interface damage occurs, it will cause the gate to leak through the p-GaN sidewall, affecting the time-dependent gate breakdown (TDGB) gate reliability. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a method that can use the first oxide layer to block the leakage of the gate to the first doped cap layer, preventing the leakage of the gate from being further transmitted to the source and drain, thereby improving the reliability of the TDGB gate and improving the performance of the transistor.

[0006] In a first aspect, the present application provides a chip, the chip comprising a transistor, the transistor comprising a channel layer, a first doped cap layer, and a gate sequentially arranged on a substrate. The transistor further comprises a first oxide layer, the first oxide layer is located at the periphery of the first doped cap layer and surrounds the first doped cap layer; the material of the first oxide layer and the material of the first doped cap layer have at least two identical elements.

[0007] In the present application, the material of the first oxide layer and the material of the first doped cap layer can be achieved by thermally oxidizing the second doped cap layer outside the first doped cap layer, so that the material of the first oxide layer and the material of the first doped cap layer include at least two identical elements. The materials of the first doped cap layer and the second doped cap layer are the same. In the process of thermally oxidizing the second doped cap layer, the active dangling bonds are converted into passivated compounds, which are the first oxide layer. The first oxide layer can repair the surface damage of the doped cap layer pattern and reduce the interface state. Because the first oxide layer is located outside the first doped cap layer and surrounds the first doped cap layer, the first oxide layer can be used to block the leakage of the gate to the first doped cap layer, preventing the leakage of the gate from being further transmitted to the source and drain, thereby improving the reliability of the TDGB gate and improving the performance of the transistor.

[0008] For example, a whole doped cap layer is first deposited. Then, etching gas and oxygen-containing gas are alternately introduced into the chamber to alternately dry etch and thermally oxidize the doped cap layer. During this process, the oxygen-containing gas gradually enters part of the doped cap layer from the sidewall of the doped cap layer.

[0009] After the dry etching is completed, the remaining part of the doped cap layer is a doped cap layer pattern, and the doped cap layer pattern includes a first doped cap layer and a second doped cap layer located outside the first doped cap layer. During the thermal oxidation process, the oxygen-containing gas enters the second doped cap layer and undergoes a thermal oxidation reaction with the material of the second doped cap layer, and the second doped cap layer is thermally oxidized into a first oxide layer, thereby achieving that the material of the first oxide layer and the material of the first doped cap layer include at least two identical elements. That is, the material of the second doped cap layer is no longer the same as the material of the first doped cap layer, but is thermally oxidized into the first oxide layer.

[0010] For another example, a whole layer of doped cap layer is first deposited, and then the doped cap layer is etched to obtain a doped cap layer pattern, wherein the doped cap layer pattern includes a first doped cap layer and a second doped cap layer located outside the first doped cap layer, the material of the second doped cap layer is the same as the material of the first doped cap layer, and the pattern of the second doped cap layer is the same as the pattern of the oxide layer to be formed.

[0011] Next, an oxygen-containing gas is introduced, and the oxygen-containing gas enters the second doped cap layer, undergoes a thermal oxidation reaction with the second doped cap layer, and the second doped cap layer is thermally oxidized into a first oxide layer, thereby achieving that the material of the first oxide layer and the material of the first doped cap layer include at least two identical elements.

[0012] In some possible implementations, the transistor further includes a second oxide layer; the second oxide layer is located outside the first oxide layer and surrounds the first oxide layer.

[0013] For example, a whole layer of doped cap layer is first deposited, and then the doped cap layer is etched to obtain a doped cap layer pattern, wherein the doped cap layer pattern includes a first doped cap layer and a second doped cap layer. Then, a second oxide layer is formed around the doped cap layer pattern, and under high temperature conditions, oxygen elements in the second oxide layer gradually enter the second doped cap layer and undergo a thermal oxidation reaction with the second doped cap layer, and the second doped cap layer is thermally oxidized into a first oxide layer, thereby achieving that the material of the first oxide layer and the material of the first doped cap layer include at least two identical elements.

[0014] In some possible implementations, the first doped cap layer may be a P-type cap layer, which has the advantage of a high threshold voltage, and a high threshold voltage can make the enhanced characteristics more stable and easier to control. The P-type cap layer may be the above-mentioned p-GaN cap layer, or a p-InGaN cap layer, a p-AlGaN cap layer, etc. Of course, according to actual needs, the doped cap layer may also be other, and this application does not limit this.

[0015] For example, if the material of the first doped cap layer includes p-GaN, the material of the first oxide layer may include GaxOyNz, wherein GaxOyNz is obtained by the reaction of p-GaN and oxygen, and x, y, and z are all greater than 0.

[0016] In some possible implementations, if the channel layer is grown directly on the substrate, the edge of the channel layer may be warped. Based on this, the transistor may further include a nucleation layer disposed between the substrate and the channel layer, and the material of the nucleation layer may include AlN. By forming the nucleation layer before forming the channel layer, and then growing the channel layer on the nucleation layer, the problem of warping of the channel layer can be avoided.

[0017] In some possible implementations, if the transistor provided in the present application is used in an application scenario with a high breakdown voltage, the transistor further includes a superlattice voltage-resistant layer, and the superlattice voltage-resistant layer is disposed between the substrate and the channel layer. In the case where the transistor includes a nucleation layer, the superlattice voltage-resistant layer is disposed between the nucleation layer and the channel layer. The superlattice voltage-resistant layer may include a plurality of first superlattice voltage-resistant layers and a plurality of second superlattice voltage-resistant layers alternately disposed, and the materials of the first superlattice voltage-resistant layer and the second superlattice voltage-resistant layer may include AlGaN, AlN, GaN, etc.

[0018] Since the bandgap width of the superlattice voltage-withstanding layer is greater than that of the channel layer, the voltage resistance of the superlattice voltage-withstanding layer is higher than that of the channel layer, so the superlattice voltage-withstanding layer is used to improve the overall voltage resistance of the transistor.

[0019] In some possible implementations, the transistor further includes an AlN insertion layer, which is disposed between the channel layer and the barrier layer. The channel layer and the barrier layer can be used to form a heterojunction, thereby forming a two-dimensional electronic device through the heterojunction.

[0020] In some possible implementations, the transistor further includes a source and a drain, and the chip further includes a passivation layer. The source and the drain are located on the channel layer and are disposed on opposite sides of the first oxide layer; the passivation layer is disposed between the source and the first oxide layer, and between the drain and the first oxide layer.

[0021] In a second aspect, the present application provides a method for preparing a chip, comprising: forming a channel layer on a substrate. Forming a doped cap layer on the channel layer, etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer; the material of the first doped cap layer is the same as the material of the doped cap layer pattern, and the first oxide layer is located at the periphery of the first doped cap layer and surrounds the first doped cap layer. Forming a gate on the first doped cap layer.

[0022] In the present application, the material of the first oxide layer and the material of the first doped cap layer can be made to include at least two identical elements by etching and thermally oxidizing the periphery of the doped cap layer. The materials of the first doped cap layer and the second doped cap layer are the same. In the process of thermally oxidizing the second doped cap layer, the active dangling bonds are converted into passivated compounds, which are the first oxide layer. The first oxide layer can repair the surface damage of the doped cap layer pattern and reduce the interface state. Because the first oxide layer is located at the periphery of the first doped cap layer and surrounds the first doped cap layer, the first oxide layer can be used to block the leakage of the gate to the first doped cap layer, preventing the leakage of the gate from being further transmitted to the source and drain, thereby improving the reliability of the TDGB gate and improving the performance of the transistor.

[0023] In some possible implementations, forming a doped cap layer on the channel layer, etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer includes: sequentially forming a doped cap layer and a mask on the channel layer; the pattern of the mask layer is the same as the overall pattern of the first doped layer and the first oxide layer. Alternatingly performing multiple dry etching and at least one thermal oxidation on the doped cap layer to obtain the first doped cap layer and the first oxide layer.

[0024] In some possible implementations, the doped cap layer is alternately dry-etched multiple times and thermally oxidized at least once to obtain a first doped cap layer and a first oxide layer, including: after alternately dry-etching and thermally oxidizing the doped cap layer M times, dry-etching the doped cap layer once to obtain the first doped cap layer and the first oxide layer; wherein M is a positive integer.

[0025] Compared with the solution in which the last gas introduced into the cavity is an oxygen-containing gas, the last gas introduced into the cavity is an etching gas, which can avoid the problem that after the part of the doping cap layer not covered by the mask layer is completely removed, the oxygen-containing gas enters the exposed barrier layer (or AlN insertion layer, or channel layer), causing the exposed barrier layer (or AlN insertion layer, or channel layer) to be thermally oxidized by the oxygen-containing gas.

[0026] In some possible implementations, a doped cap layer is formed on the channel layer, and the doped cap layer is etched and thermally oxidized to obtain a first doped cap layer and a first oxide layer, including: dry etching the doped cap layer to obtain a doped cap layer pattern; the pattern of the doped cap layer pattern is the same as the pattern of the mask layer; and thermally oxidizing the doped cap layer pattern to obtain the first doped cap layer and the first oxide layer.

[0027] In some possible implementations, after dry etching the doped cap layer and before thermally oxidizing the doped cap layer pattern, the chip preparation method further includes: forming a protective layer on a side of the channel layer facing away from the substrate, the protective layer covering the exposed portion of the channel layer.

[0028] Since the protective layer covers the exposed portion of the barrier layer (or the AlN insertion layer, or the channel layer), the exposed portion of the barrier layer (or the AlN insertion layer, or the channel layer) will not be thermally oxidized by the oxygen-containing gas.

[0029] In some possible implementations, a doped cap layer is formed on the channel layer, and the doped cap layer is etched and thermally oxidized to obtain a first doped cap layer and a first oxide layer, including: dry etching the doped cap layer to obtain a doped cap layer pattern; the pattern of the doped cap layer pattern is the same as the pattern of the mask layer. A second oxide layer is formed around the doped cap layer pattern, and the second oxide layer surrounds the doped cap layer pattern. The doped cap layer pattern is thermally oxidized using the second oxide layer to obtain the first doped cap layer and the first oxide layer.

[0030] In some possible implementations, after dry etching the doped cap layer and before forming a second oxide layer around the doped cap layer pattern, the chip preparation method further includes: forming a protective layer on the side of the channel layer facing away from the substrate; the protective layer covers the exposed portion of the channel layer, or the pattern of the protective layer is the same as the pattern of the second oxide layer to be formed.

[0031] Since the protection layer covers the exposed portion of the barrier layer (or the AlN insertion layer, or the channel layer), the exposed portion of the barrier layer (or the AlN insertion layer, or the channel layer) will not be thermally oxidized by the second oxide layer.

[0032] In a third aspect, the present application provides an electronic device, including a circuit board and the chip described in the first aspect, wherein the chip is arranged on the circuit board.

[0033] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 An application scenario diagram of a transistor provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of a transistor based on common source and common gate technology provided in an embodiment of the present application;

[0036] Figure 3a A schematic diagram of etching a p-GaN layer provided in an embodiment of the present application;

[0037] Figure 3b A schematic diagram of a transistor based on p-GaN gate technology provided in an embodiment of the present application;

[0038] Figure 4 IV curves of three different transistors provided in the embodiments of the present application;

[0039] Figure 5a A schematic diagram of a transistor provided for related art;

[0040] Figure 5b for Figure 5a A graph showing the relationship between the service life of a transistor and the gate voltage;

[0041] Figure 6a Simulation effect diagram of transistors corresponding to different passivation layer materials provided for related technologies;

[0042] Figure 6b Simulation effect diagram of transistors corresponding to different passivation layer materials provided for related technologies;

[0043] Figure 7 A comparison chart of the effects before and after the improvement of the etching process of the p-GaN layer provided for the related technology;

[0044] Figure 8 A schematic diagram of a transistor provided in an embodiment of the present application;

[0045] Fig. 9 A schematic diagram of a transistor provided in an embodiment of the present application;

[0046] Fig.10a A schematic diagram of a transistor provided in an embodiment of the present application;

[0047] Fig.10b A schematic diagram of a transistor provided in an embodiment of the present application;

[0048] Fig.11 A schematic diagram of a transistor provided in an embodiment of the present application;

[0049] Fig.12 A schematic diagram of a transistor provided in an embodiment of the present application;

[0050] Fig.13 A schematic diagram of a transistor provided in an embodiment of the present application;

[0051] Fig.14 A schematic diagram of a transistor provided in an embodiment of the present application;

[0052] Fig.15 A flow chart of preparing a transistor provided in an embodiment of the present application;

[0053] Fig.16a A process diagram for preparing a transistor provided in an embodiment of the present application;

[0054] Fig.16b A process diagram for preparing a transistor provided in an embodiment of the present application;

[0055] Fig.16c A process diagram for preparing a transistor provided in an embodiment of the present application;

[0056] Fig.16d A process diagram for preparing a transistor provided in an embodiment of the present application;

[0057] Fig.16e A process diagram for preparing a transistor provided in an embodiment of the present application;

[0058] Fig.17a A process diagram for preparing a transistor provided in an embodiment of the present application;

[0059] Fig.17b A process diagram for preparing a transistor provided in an embodiment of the present application;

[0060] Fig.17c A process diagram for preparing a transistor provided in an embodiment of the present application;

[0061] Fig.17d A process diagram for preparing a transistor provided in an embodiment of the present application;

[0062] Fig.17e is a graph showing the relationship between the progress of the etching process and the oxidation process and the thickness of the removed portion of the doped cap layer;

[0063] Fig.18a A process diagram for preparing a transistor provided in an embodiment of the present application;

[0064] Fig.18b A process diagram for preparing a transistor provided in an embodiment of the present application;

[0065] Fig.18c A process diagram for preparing a transistor provided in an embodiment of the present application;

[0066] Fig.19A diagram of a process for preparing a transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0068] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0069] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0070] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0071] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0072] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, an automobile, a photovoltaic power generation, an uninterruptible power supply (UPS), or other device containing a transistor.

[0073] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), chargers, smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0074] For the sake of convenience, the following text takes an electronic device as an example of a charger. The charger can be a fast charger used to charge smart phones, computers and other devices.

[0075] like Figure 1 As shown, the charger includes a filtering and rectification circuit 11, a power switch 12, a transformer 13, a switch driver circuit 14, and a pulse-width modulated regulation 15.

[0076] The filter and rectifier circuit 11 receives the input voltage and converts the AC input voltage into a DC input voltage, or converts the DC input voltage into an AC input voltage. When the power switch transistor 12 is turned on, the filter and rectifier circuit 11 sends the converted input voltage to the transformer 13 through the power switch transistor 12. After receiving the converted input voltage, the transformer 13 converts the input voltage into the output voltage required by the mobile phone or computer, etc., so as to charge the mobile phone or computer, etc.

[0077] The power switch 12 can be realized by a transistor. Due to the better switching characteristics, faster switching frequency, and lower loss of GaN materials, GaN HEMT has the advantages of small size, lighter weight, higher efficiency, and more energy saving, and has been widely used in various electronic devices.

[0078] As mentioned in the background technology, due to the presence of high-concentration 2DEG, the Schottky gate cannot deplete the 2DEG in the channel layer under zero bias. When GaN HEMT is applied to circuits, it will reduce the safety of the circuit, increase the complexity of circuit design, and increase power consumption. Therefore, realizing an enhanced HEMT in the off state under zero gate bias is crucial to promoting its application in the power field.

[0079] To this end, related technologies propose cascode technology and p-GaN gate technology.

[0080] like Figure 2 As shown in the figure, the common source and common gate technology is to cascade the depletion-mode HEMT high electron mobility crystal and the enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) into an integral device, and control the enhancement-mode MOSFET to make the overall device enhanced. The disadvantage of this technology is that the switching power consumption is large, and the additional enhancement-mode MOSFET increases the volume of the circuit, the difficulty of chip packaging and the cost.

[0081] like Figure 3a As shown in the figure, the p-GaN gate technology is to add a p-GaN layer under the gate to raise the energy band of the 2DEG channel position, so that the 2DEG in the channel is depleted, thereby achieving enhancement mode. However, in the process of etching the p-GaN layer of tens of nanometers, it is easy to cause problems such as uneven etching and interface damage (including interface states, dangling bonds, etc.). If interface damage occurs, the p-GaN surface has many active dangling bonds, etc., which causes the gate to leak through the p-GaN side wall, affecting the reliability of the TDGB gate.

[0082] Specifically, Figure 3b As shown, the two paths of gate leakage through the p-GaN sidewall are: the gate 25 leaks to the source 22 through the p-GaN layer 24 and the passivation layer 40 in turn, and the gate 25 leaks to the drain 23 through the p-GaN layer 24 and the passivation layer 40 in turn.

[0083] Figure 4 The IV curves of GaN HEMT, p-GaN gate technology, and cascode technology are shown respectively. For GaN HEMT, when its gate-source voltage Vgs is less than -2.5V, the on-state current is 0 and the GaN HEMT is disconnected. For p-GaN gate technology, when the gate-source voltage Vgs of the transistor is less than 1.8V, the on-state current is 0 and the transistor is disconnected. For cascode technology, when the gate-source voltage Vgs of the transistor is less than 4V, the on-state current is 0 and the transistor is disconnected.

[0084] It can be seen that GaN HEMT has the problem that the Schottky gate cannot deplete 2DEG under the above zero bias. The turn-on voltage required for the common source and common gate technology is too large, and the switching power consumption is large. For p-GaN gate technology, there is neither the problem of being unable to deplete 2DEG nor the turn-on voltage does not need to be too large. Therefore, p-GaN gate technology is the research focus of this application.

[0085] In order to improve the gate reliability, the related art proposes a gate retraction technology. Figure 3a and Figure 5a As shown, this technology makes the gate sidewall retract 128nm toward the middle compared to the sidewall of the p-GaN layer 24, which can effectively suppress the leakage current at the gate edge and extend the device life. Figure 5b A graph showing the relationship between the gate voltage and the service life of the transistor shows that, when the service life is 10 years, the maximum gate voltage before the improvement is 4V, while the maximum gate voltage after the improvement can reach 6.5V.

[0086] In order to improve gate reliability, the second related technology proposes to reduce leakage of the passivation layer 40 and the sidewall of the p-GaN layer 24 by optimizing the material and quality of the passivation layer 40 .

[0087] For example, Figure 6a As shown, after the material of the passivation layer 40 is changed from silicon dioxide (SiO2) to aluminum oxide (Al2O3) and SiO2, the service life of the transistor is extended.

[0088] For example, Figure 6b As shown, before the improvement, the material of the passivation layer 40 is Al2O3; after the improvement, the material of the passivation layer 40 is a material obtained by high-temperature annealing of Al2O3 at 600°C in a nitrogen (N2) environment, and the service life of the transistor is extended.

[0089] In order to improve gate reliability, the third related technology proposes to reduce the etching damage to the side wall of the p-GaN layer 24 and reduce the leakage of the passivation layer 40 and the side wall of the p-GaN layer 24 by optimizing the etching process.

[0090] like Figure 7 As shown, Reference represents the process before the etching process is improved, Process A represents the process after the etching process of the Schottky interface is improved, and Process B represents the process after the etching process of the Schottky interface and the sidewall of the p-GaN layer 24 is improved. It can be seen that the leakage current of Reference is greater than that of Process A, which is greater than that of Process B.

[0091] However, the above three related technologies still do not solve the large number of interface states, dangling bonds, etc. caused by etching damage, so the gate can still leak through the p-GaN side wall.

[0092] Based on this, Figure 8 As shown, an embodiment of the present application provides a chip, which includes a transistor. In addition to a channel layer 21, a source 22, a drain 23, and a gate 25, the transistor also includes a first doped cap layer 26 and a first oxide layer 271 disposed between the channel layer 21 and the gate 25. The first oxide layer 271 is at the periphery of the first doped cap layer 26 and surrounds the first doped cap layer 26. The material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements.

[0093] In some possible implementations, a thermal oxidation process may be used to achieve that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements.

[0094] For example, a whole doped cap layer is first deposited. Then, etching gas and oxygen-containing gas are alternately introduced into the chamber to alternately dry etch and thermally oxidize the doped cap layer. During this process, the oxygen-containing gas gradually enters part of the doped cap layer from the sidewall of the doped cap layer.

[0095] After the dry etching is completed, the remaining portion of the doped cap layer is a doped cap layer pattern, and the doped cap layer pattern includes a first doped cap layer 26 and a second doped cap layer located outside the first doped cap layer 26. During the thermal oxidation process, the oxygen-containing gas enters the second doped cap layer and undergoes a thermal oxidation reaction with the material of the second doped cap layer. The second doped cap layer is thermally oxidized into a first oxide layer 271, thereby achieving that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements ( Figure 8 ). That is, the material of the second doped cap layer is no longer the same as the material of the first doped cap layer, but is thermally oxidized into the first oxide layer 271.

[0096] For another example, a whole layer of doped cap layer is first deposited, and then the doped cap layer is etched to obtain a doped cap layer pattern, which includes a first doped cap layer 26 and a second doped cap layer located outside the first doped cap layer 26, the material of the second doped cap layer is the same as the material of the first doped cap layer 26, and the pattern of the second doped cap layer is the same as the pattern of the oxide layer 27 to be formed.

[0097] Next, an oxygen-containing gas is introduced, and the oxygen-containing gas enters the second doped cap layer, and a thermal oxidation reaction occurs with the second doped cap layer, and the second doped cap layer is thermally oxidized into a first oxide layer 271, so that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements ( Figure 8 ).

[0098] For another example, a whole layer of doped cap layer is first deposited, and then the doped cap layer is etched to obtain a doped cap layer pattern, wherein the doped cap layer pattern includes a first doped cap layer and a second doped cap layer. Then, a second oxide layer 272 is formed around the doped cap layer pattern. Under high temperature conditions, the oxygen element in the second oxide layer 272 gradually enters the second doped cap layer and undergoes a thermal oxidation reaction with the second doped cap layer. The second doped cap layer is thermally oxidized into a first oxide layer 271, thereby achieving that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements ( Fig. 9 ).

[0099] Of course, other processes may also be used to prepare the first doped cap layer 26 and the first oxide layer 271 , so that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements.

[0100] Regardless of the process used to prepare the first doped cap layer 26 and the first oxide layer 271, during the thermal oxidation of the second doped cap layer, the active dangling bonds are converted into passivated compounds, which are the first oxide layer 271. The first oxide layer 271 can repair the surface damage of the doped cap layer pattern and reduce the interface state. Because the first oxide layer 271 is located at the periphery of the first doped cap layer 26 and surrounds the first doped cap layer 26, the first oxide layer 271 can be used to block the leakage of the gate 25 to the first doped cap layer 26, and prevent the leakage of the gate 25 from being further transmitted to the source 22 and the drain 23, thereby improving the reliability of the TDGB gate and improving the performance of the transistor.

[0101] In addition, by making the first doped cap layer 26 surround the first oxide layer 271 , it is also possible to prevent leakage of the gate 25 from being further transmitted to other conductive structures except the source 22 and the drain 23 .

[0102] In some possible implementations, the first doped cap layer 26 may be a P-type cap layer, which has the advantage of a high threshold voltage, and a high threshold voltage can make the enhanced characteristics more stable and easier to control. The P-type cap layer may be the above-mentioned p-GaN cap layer, or a p-InGaN cap layer, a p-AlGaN cap layer, etc. Of course, according to actual needs, the doped cap layer 26 may also be other, and the embodiments of the present application are not limited to this.

[0103] For example, the material of the first doped cap layer 26 includes p-GaN, and the material of the first oxide layer 271 includes Ga x O y N z Among them, Ga x O y N zObtained by the reaction of p-GaN and oxygen (O), x, y, and z are all greater than 0. The values ​​of x, y, and z can be set according to the concentration of O participating in the reaction.

[0104] Still taking the material of the first doped cap layer 26 including p-GaN as an example, during the growth of p-GaN, ammonia (NH3), hydrogen (H2), bis(cyclopentadienyl)magnesium, and trimethylgallium can be introduced into the cavity, and the temperature in the cavity can be about 950°C. Among them, H2 is used as a carrier, NH3 is used to provide N elements, trimethylgallium is used to provide Ga elements, bis(cyclopentadienyl)magnesium is used as a P-type doping material, and the concentration of magnesium is 4×10 19 cm -3 about.

[0105] In some possible implementations, corresponding to the related art, the embodiment of the present application does not limit the size of the gate 25 in the first direction and the size of the first doped cap layer 26 in the first direction. The first direction is the direction from the source 22 to the drain 23.

[0106] Optional, such as Figure 8 and Fig. 9 As shown, the size of the gate 25 in the first direction is greater than the size of the first doped cap layer 26 in the first direction. On this basis, the size of the gate 25 in the first direction is equal to the sum of the size of the first doped cap layer 26 in the first direction and twice the size of the first oxide layer 271.

[0107] Optional, such as Fig.10a As shown, the size of the gate 25 in the first direction is equal to the size of the first doped cap layer 26 in the first direction. In this case, the first oxide layer 271 exceeds the gate 25 in the first direction.

[0108] Optional, such as Fig.10b As shown, the size of the gate 25 in the first direction is smaller than the size of the first doping cap layer 26 in the first direction. In this case, the first oxide layer 271 exceeds the gate 25 in the first direction.

[0109] In some embodiments, if the channel layer 21 is grown directly on the substrate 20, the edge of the channel layer 21 may be warped. Fig.11 As shown, the transistor may further include a nucleation layer 31 disposed between the substrate 20 and the channel layer 21, and the material of the nucleation layer 31 may include aluminum nitride (AlN). By forming the nucleation layer 31 before forming the channel layer 21, and then growing the channel layer 21 on the nucleation layer 31, the warping problem of the channel layer 21 may be avoided.

[0110] Optionally, during the growth of the nucleation layer 31, NH3, H2, and trimethylaluminum may be introduced into the cavity, and the temperature in the cavity may be about 1100° C. H2 is used as a carrier, NH3 is used to provide N elements, and trimethylaluminum is used to provide Al elements.

[0111] In some possible implementations, the embodiment of the present application does not limit the thickness of the nucleation layer 31 . For example, the thickness of the nucleation layer 31 is about 200 nm.

[0112] In some embodiments, Fig.12 As shown, if the transistor provided in the embodiment of the present application is used in an application scenario with a high breakdown voltage, the transistor further includes a superlattice voltage-resistant layer 32, and the superlattice voltage-resistant layer 32 is disposed between the substrate 20 and the channel layer 21. In the case where the transistor includes a nucleation layer 31, the superlattice voltage-resistant layer 32 is disposed between the nucleation layer 31 and the channel layer 21.

[0113] Since the bandgap width of the superlattice voltage-sustaining layer 32 is greater than that of the channel layer 21 , the voltage resistance of the superlattice voltage-sustaining layer 32 is higher than that of the channel layer 21 , so the superlattice voltage-sustaining layer 32 is used to improve the overall voltage resistance of the transistor.

[0114] For example, if the transistor is used in a high voltage application scenario with a breakdown voltage of 650V, for example, the transistor may include the superlattice voltage-withstanding layer 32. If the transistor is used in a low voltage application scenario with a breakdown voltage of 100V, for example, the transistor may not include the superlattice voltage-withstanding layer 32.

[0115] Optional, such as Fig.12 As shown, the superlattice voltage-resistant layer 32 may include multiple layers of first superlattice voltage-resistant layers 321 and multiple layers of second superlattice voltage-resistant layers 322 that are alternately arranged. The materials of the first superlattice voltage-resistant layers 321 and the second superlattice voltage-resistant layers 322 may include aluminum gallium nitride (AlGaN), AlN, GaN, etc.

[0116] The material of the first superlattice voltage-withstanding layer 321 includes AlN or GaN, and the material of the second superlattice voltage-withstanding layer 322 includes AlGaN. Alternatively, the material of the first superlattice voltage-withstanding layer 321 includes GaN, and the material of the second superlattice voltage-withstanding layer 322 includes AlN.

[0117] During the growth of the multi-layer first superlattice voltage-resistant layer 321 and the multi-layer second superlattice voltage-resistant layer 322, NH3, H2, trimethylaluminum, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 1000° C. Among them, H2 is used as a carrier, NH3 is used to provide N elements, trimethylaluminum is used to provide Al elements, and trimethylgallium is used to provide Ga elements.

[0118] In some possible implementations, the embodiment of the present application does not limit the thickness of the first superlattice voltage-resistant layer 321 and the second superlattice voltage-resistant layer 322, as well as the number of superlattice pairs. Optionally, the thickness of the second superlattice voltage-resistant layer 322 is greater than the thickness of the first superlattice voltage-resistant layer 321, for example, the thickness of the first superlattice voltage-resistant layer 321 is 5 nm, the thickness of the second superlattice voltage-resistant layer 322 is 25 nm, and the number of superlattice pairs is 90 pairs.

[0119] In some embodiments, Fig.13 As shown, the transistor may further include a barrier layer 33, and the barrier layer 33 is disposed between the channel layer 21 and the first doped cap layer 26. A heterojunction may be formed by the channel layer 21 and the barrier layer 33, thereby forming a two-dimensional electronic device through the heterojunction.

[0120] Optionally, the material of the barrier layer 33 may include AlGaN. During the growth of the barrier layer 33, NH3, H2, trimethylaluminum, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 1050° C. H2 is used as a carrier, NH3 is used to provide N elements, trimethylaluminum is used to provide Al elements, and trimethylgallium is used to provide Ga elements.

[0121] In some possible implementations, the present embodiment does not limit the thickness of the barrier layer 33. Optionally, the thickness of the barrier layer 33 may range from 10 nm to 20 nm, for example, the thickness of the barrier layer 33 is 10 nm, 12 nm, 17 nm, or 20 nm.

[0122] In addition, in the case of forming a two-dimensional electron device by doping the channel layer 21 , the transistor in the embodiment of the present application may not include the barrier layer 33 .

[0123] In some embodiments, Fig.14 As shown, the transistor may further include an AlN insertion layer 34, which is disposed between the channel layer 21 and the barrier layer 33. The AlN insertion layer 34 may be used to control the two-dimensional electron device at a better level to improve the performance of the crystal structure.

[0124] During the growth of the AlN insertion layer 34, NH3, H2, and trimethylaluminum may be introduced into the cavity, and the temperature in the cavity may be about 1050° C. H2 is used as a carrier, NH3 is used to provide N elements, and trimethylaluminum is used to provide Al elements.

[0125] In some possible implementations, the present embodiment does not limit the thickness of the AlN insertion layer 34. Optionally, the thickness of the barrier layer 33 may be greater than 0, less than or equal to 1 nm, for example, the thickness of the barrier layer 33 is 0.1 nm, 0.4 nm, 0.75 nm, or 1 nm.

[0126] The present application also provides a method for preparing a chip. Fig.15 As shown, this can be achieved through the following steps:

[0127] S110, such as Fig.16a As shown, a substrate 20 is provided, and a channel layer 21 is formed on the substrate 20 .

[0128] In some possible implementations, before forming the channel layer 21 , the silicon substrate 1 is first placed in a cavity and subjected to high-temperature surface cleaning in a hydrogen atmosphere at a temperature of about 1100° C. for about 5 minutes.

[0129] In some possible implementations, the embodiment of the present application does not limit the material of the channel layer 21 , as long as the material of the channel layer 21 includes a semiconductor material.

[0130] For example, the material of the channel layer 21 includes GaN. During the growth of the channel layer 21, NH3, H2, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 1050° C. H2 is used as a carrier, NH3 is used to provide N elements, and trimethylgallium is used to provide Ga elements.

[0131] The embodiment of the present application does not limit the thickness of the channel layer 21 . Optionally, the thickness of the channel layer 21 may be about 500 nm.

[0132] In some embodiments, Fig.16b As shown, after cleaning the substrate 20, before forming the channel layer 21 on the substrate 20, a nucleation layer 31 may be formed on the substrate 20, and the material of the nucleation layer 31 may include aluminum nitride (AlN). By forming the nucleation layer 31 before forming the channel layer 21, and then growing the channel layer 21 on the nucleation layer 31, the warping problem of the channel layer 21 can be avoided.

[0133] Optionally, during the growth of the nucleation layer 31, NH3, H2, and trimethylaluminum may be introduced into the cavity, and the temperature in the cavity may be about 1100° C. H2 is used as a carrier, NH3 is used to provide N elements, and trimethylaluminum is used to provide Al elements.

[0134] In some possible implementations, the embodiment of the present application does not limit the thickness of the nucleation layer 31 . For example, the thickness of the nucleation layer 31 is 200 nm.

[0135] In some embodiments, Fig.16cAs shown, if the transistor provided in the embodiment of the present application is used in an application scenario with a high breakdown voltage, a superlattice voltage-resistant layer 32 may be formed after forming the nucleation layer 31 and before forming the channel layer 21. Since the bandgap width of the superlattice voltage-resistant layer 32 is greater than the bandgap width of the channel layer 21, the voltage resistance of the superlattice voltage-resistant layer 32 is higher than that of the channel layer 21, thereby utilizing the superlattice voltage-resistant layer 32 to improve the overall voltage resistance of the transistor.

[0136] For example, if the transistor is applied to an application scenario with a high breakdown voltage (e.g., 650V), the transistor may include the superlattice voltage-resistant layer 32. If the transistor is applied to an application scenario with a low breakdown voltage (e.g., 100V), the transistor may not include the superlattice voltage-resistant layer 32.

[0137] Optional, such as Fig.16c As shown, the process of forming the superlattice voltage-resistant layer 32 may include: alternately forming multiple layers of the first superlattice voltage-resistant layer 321 and multiple layers of the second superlattice voltage-resistant layer 322 on the nucleation layer 31, the material of the first superlattice voltage-resistant layer 321 includes AlN, and the material of the second superlattice voltage-resistant layer 322 includes AlGaN.

[0138] During the growth of the multi-layer first superlattice voltage-resistant layer 321 and the multi-layer second superlattice voltage-resistant layer 322, NH3, H2, trimethylaluminum, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 1000° C. Among them, H2 is used as a carrier, NH3 is used to provide N elements, trimethylaluminum is used to provide Al elements, and trimethylgallium is used to provide Ga elements.

[0139] In some possible implementations, the embodiment of the present application does not limit the thickness of the first superlattice voltage-resistant layer 321 and the second superlattice voltage-resistant layer 322, as well as the number of superlattice pairs. Optionally, the thickness of the second superlattice voltage-resistant layer 322 is greater than the thickness of the first superlattice voltage-resistant layer 321, for example, the thickness of the first superlattice voltage-resistant layer 321 is 5 nm, the thickness of the second superlattice voltage-resistant layer 322 is 25 nm, and the number of superlattice pairs is 90 pairs.

[0140] In some embodiments, Fig.16d As shown, after step S110 and before step S120, a barrier layer 33 may be formed on the channel layer 21, and a heterojunction is formed by the channel layer 21 and the barrier layer 33, so as to form a two-dimensional electronic device through the heterojunction.

[0141] Optionally, the material of the barrier layer 33 may include AlGaN. During the growth of the barrier layer 33, NH3, H2, trimethylaluminum, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 1050° C. H2 is used as a carrier, NH3 is used to provide N elements, trimethylaluminum is used to provide Al elements, and trimethylgallium is used to provide Ga elements.

[0142] In some possible implementations, the embodiment of the present application does not limit the thickness of the barrier layer 33. Optionally, the thickness of the barrier layer 33 may be about 12 nm.

[0143] In addition, in the case of forming a two-dimensional electron device by doping the channel layer 21 , the transistor in the embodiment of the present application may not include the barrier layer 33 .

[0144] In some embodiments, Fig.16e As shown, after step S110 and before forming the barrier layer 33 , an AlN insertion layer 34 may be formed on the channel layer 21 . The AlN insertion layer 34 is used to control the two-dimensional electron device at a better level to improve the performance of the crystal hanger.

[0145] During the growth of the AlN insertion layer 34, NH3, H2, and trimethylaluminum may be introduced into the cavity, and the temperature in the cavity may be about 1050° C. H2 is used as a carrier, NH3 is used to provide N elements, and trimethylaluminum is used to provide Al elements.

[0146] In some possible implementations, the embodiment of the present application does not limit the thickness of the AlN insertion layer 34. Optionally, the thickness of the barrier layer 33 may be about 0.4 nm.

[0147] S120, forming a first doped cap layer 26 and a first oxide layer 271 on the channel layer 21 (also known as a barrier layer or an AlN insertion layer), wherein the first oxide layer 271 is located at the periphery of the first doped cap layer 26 and surrounds the first doped cap layer 26, and the material of the first oxide layer 271 and the material of the first doped cap layer 26 have at least two identical elements.

[0148] In some possible implementations, the first doped cap layer 26 may be a P-type cap layer, which has the advantage of a high threshold voltage, and a high threshold voltage can make the enhanced characteristics more stable and easier to control. The P-type cap layer may be the above-mentioned p-GaN cap layer, or a p-InGaN cap layer, a p-AlGaN cap layer, etc. Of course, according to actual needs, the doped cap layer 26 may also be other, and the embodiments of the present application are not limited to this.

[0149] For example, the material of the first doped cap layer 26 includes p-GaN, and the material of the first oxide layer 271 includes Ga x Oy N z Among them, Ga x O y N z Obtained by the reaction of p-GaN and oxygen (O), x, y, and z are all greater than 0. The values ​​of x, y, and z can be set according to the concentration of O participating in the reaction.

[0150] In some possible implementations, the process of forming the first doping layer 26 and the first oxide layer 271 can be implemented by the following three situations:

[0151] The first case, such as Fig.17a As shown, a whole doped cap layer 261 is deposited on the channel layer 21 .

[0152] Still taking the material of the first doped cap layer 26 including p-GaN as an example, during the growth of the doped cap layer 261, NH3, H2, bis(cyclopentadienyl)magnesium, and trimethylgallium may be introduced into the cavity, and the temperature in the cavity may be about 950°C. Among them, H2 is used as a carrier, NH3 is used to provide N elements, trimethylgallium is used to provide Ga elements, bis(cyclopentadienyl)magnesium is used as a P-type doping material, and the concentration of magnesium is 4×10 19 cm -3 about.

[0153] Then, if Fig.17b As shown, a mask layer 41 is formed on the doping cap layer 261. The material of the mask layer 41 may include photoresist, silicon nitride (SiN), SiO2, titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), silicon carbide (TiC), etc. The pattern of the mask layer 41 is the same as the overall pattern of the first doping cap layer 26 and the first oxide layer 271 to be formed.

[0154] Then, if Fig.17c and Fig.17d As shown, under the protection of the mask layer 41, etching gas and oxygen-containing gas are alternately introduced into the chamber to alternately dry-etch and thermally oxidize the doped cap layer 261. In this process, the oxygen-containing gas thermally oxidizes the exposed doped cap layer 261 and gradually enters part of the doped cap layer 261 from the sidewall of the doped cap layer 261.

[0155] After the dry etching is completed, the remaining portion of the doped cap layer 261 is a doped cap layer pattern, and the doped cap layer pattern includes a first doped cap layer 26 and a second doped cap layer located outside the first doped cap layer 26. During the thermal oxidation process, the oxygen-containing gas enters the second doped cap layer, and a thermal oxidation reaction occurs with the material of the second doped cap layer, and the second doped cap layer is thermally oxidized into a first oxide layer 271, so that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements. That is, the material of the second doped cap layer is no longer the same as the material of the first doped cap layer, but is thermally oxidized into the first oxide layer 271.

[0156] In some possible implementations, the embodiments of the present application do not limit the number of dry etching and thermal oxidation times, and the first doped cap layer 26 and the first oxide layer 271 can be obtained by multiple dry etching and at least one thermal oxidation. Fig.17d As shown, the first doped cap layer 26 and the first oxide layer 271 are prepared by 6 dry etchings and 5 thermal oxidations.

[0157] The embodiment of the present application does not limit the etching gas introduced and the duration T0 of each dry etching, as well as the oxygen-containing gas introduced and the duration T1 of each thermal oxidation. For example, during each dry etching, chlorine plasma is introduced into the cavity for 50 seconds continuously. During each thermal oxidation, oxygen plasma is introduced into the cavity for 50 seconds continuously. The total duration is 50s*6+50s*5=550s.

[0158] In some possible implementation methods, the present application uses dry etching to etch the doped cap layer 261. The dry etching is anisotropic. During the dry etching process, the thickness of the portion of the doped cap layer 261 not covered by the mask layer 41 gradually decreases until the portion of the doped cap layer 261 not covered by the mask layer 41 is completely removed, exposing the barrier layer 33 (or AlN insertion layer, or channel layer).

[0159] Furthermore, when the etching gas and the oxygen-containing gas are alternately introduced into the chamber, compared with the last time the gas introduced into the chamber is the oxygen-containing gas, as shown in FIG. Fig.17e As shown, the last gas introduced into the cavity is an etching gas, which can prevent the oxygen-containing gas from entering the exposed barrier layer 33 (or AlN insertion layer, or channel layer) after the portion of the doping cap layer 261 not covered by the mask layer 41 is completely removed, resulting in the problem that the exposed barrier layer 33 (or AlN insertion layer, or channel layer) is thermally oxidized by the oxygen-containing gas. Fig.17d As shown, after 5 dry etchings and 5 thermal oxidations, and then a final dry etching, the first doped cap layer 26 and the first oxide layer 271 are prepared.

[0160] The second case, such as Fig.17aAs shown, a whole doped cap layer 261 is deposited on the channel layer 21. The process of depositing a whole doped cap layer 261 is the same as that of the first case, and will not be described again.

[0161] Then, if Fig.17b As shown, a mask layer 41 is formed on the doping cap layer 261. The material of the mask layer 41 may include photoresist, SiN, SiO2, TiN, TaN, Ti, TiC, etc. The pattern of the mask layer 41 is the same as the overall pattern of the first doping cap layer 26 and the first oxide layer 271 to be formed.

[0162] Then, if Fig.18a As shown, under the protection of the mask layer 41, an etching gas is introduced into the chamber to dry-etch the doped cap layer 261. After the dry etching is completed, the remaining portion of the doped cap layer 261 is a doped cap layer pattern, and the doped cap layer pattern includes a first doped cap layer 26 and a second doped cap layer 28 located outside the first doped cap layer 26. The material of the second doped cap layer 28 is the same as that of the first doped cap layer 26, and the pattern of the second doped cap layer 28 is the same as that of the first oxide layer 271 to be formed.

[0163] Then, if Fig.18b As shown, a protective layer 42 is formed on the barrier layer 33 (or AlN insertion layer, or channel layer), and the protective layer 42 covers the exposed portion of the barrier layer 33 (or AlN insertion layer, or channel layer). The material of the protective layer 42 may include photoresist, SiN, SiO2, TiN, TaN, Ti, SiC, etc.

[0164] Then, if Fig.18c As shown, an oxygen-containing gas is introduced into the chamber, the oxygen-containing gas enters the second doping cap layer 28, and undergoes a thermal oxidation reaction with the second doping cap layer 28, and the second doping cap layer 28 is thermally oxidized into a first oxide layer 271, thereby achieving that the material of the first oxide layer 271 and the material of the first doping cap layer 26 include at least two identical elements.

[0165] Since the protective layer 42 covers the exposed portion of the barrier layer 33 (or the AlN insertion layer, or the channel layer), the exposed portion of the barrier layer 33 (or the AlN insertion layer, or the channel layer) is not thermally oxidized by the oxygen-containing gas.

[0166] The third case, such as Fig.17a As shown, a whole doped cap layer 261 is deposited on the channel layer 21. The process of depositing a whole doped cap layer 261 is the same as that of the first case, and will not be described again.

[0167] Then, if Fig.17bAs shown, a mask layer 41 is formed on the doping cap layer 261. The material of the mask layer 41 may include photoresist, SiN, SiO2, TiN, TaN, Ti, TiC, etc. The pattern of the mask layer 41 is the same as the overall pattern of the first doping cap layer 26 and the first oxide layer 271 to be formed.

[0168] Then, if Fig.18a As shown, under the protection of the mask layer 41, an etching gas is introduced into the chamber to dry-etch the doped cap layer 261. After the dry etching is completed, the remaining portion of the doped cap layer 261 is a doped cap layer pattern, and the doped cap layer pattern includes a first doped cap layer 26 and a second doped cap layer 28 located outside the first doped cap layer 26. The material of the second doped cap layer 28 is the same as that of the first doped cap layer 26, and the pattern of the second doped cap layer 28 is the same as that of the first oxide layer 271 to be formed.

[0169] Then, if Fig.18b As shown, a protective layer 42 is formed on the barrier layer 33 (or AlN insertion layer, or channel layer), and the protective layer 42 covers the exposed portion of the barrier layer 33 (or AlN insertion layer, or channel layer). The material of the protective layer 42 may include photoresist, SiN, SiO2, TiN, TaN, Ti, SiC, etc.

[0170] In some possible implementations, the protection layer 42 may completely cover the exposed portion of the barrier layer 33 (or the AlN insertion layer, or the channel layer), or the pattern of the protection layer 42 may be the same as the pattern of the second oxide layer 272 to be formed.

[0171] Then, if Fig.19 As shown, a second oxide layer 272 is formed on the periphery of the doped cap layer pattern, and the second oxide layer 272 surrounds the doped cap layer pattern. Under high temperature conditions, the oxygen element in the second oxide layer 272 gradually enters the second doped cap layer 28, and undergoes a thermal oxidation reaction with the second doped cap layer 28, and the second doped cap layer 28 is thermally oxidized into the first oxide layer 271, thereby achieving that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements.

[0172] Since the protection layer 42 covers the exposed portion of the barrier layer 33 (or the AlN insertion layer, or the channel layer), the exposed portion of the barrier layer 33 (or the AlN insertion layer, or the channel layer) will not be thermally oxidized by the second oxide layer 272 .

[0173] Of course, other processes may also be used to prepare the first doped cap layer 26 and the first oxide layer 271 , so that the material of the first oxide layer 271 and the material of the first doped cap layer 26 include at least two identical elements, which is not limited in the embodiment of the present application.

[0174] Regardless of the process used to prepare the first doped cap layer 26 and the first oxide layer 271, during the thermal oxidation of the second doped cap layer 28, the active dangling bonds are converted into passivated compounds, which are the first oxide layer 271. The first oxide layer 271 can repair the surface damage of the doped cap layer pattern and reduce the interface state. Because the first oxide layer 271 is located outside the first doped cap layer 26, the first oxide layer 271 can be used to block the leakage of the gate 25 to the first doped cap layer 26, and prevent the leakage of the gate 25 from being further transmitted to the source 22 and the drain 23, thereby improving the reliability of the TDGB gate and improving the performance of the transistor.

[0175] In addition, by making the first doped cap layer 26 surround the first oxide layer 271 , it is also possible to prevent leakage of the gate 25 from being further transmitted to other conductive structures except the source 22 and the drain 23 .

[0176] S130, such as Figure 8 and Fig. 9 As shown, a source 22 and a drain, a gate 25, and a passivation layer 40 are formed to obtain a transistor. The source 22 and the drain 23 are disposed on opposite sides of the first oxide layer 271 (or the second oxide layer), and the gate 25 is disposed on the first doped cap layer 26. The passivation layer 40 is disposed between the source 22 and the oxide layer 27 and the gate 25, and between the drain 23 and the oxide layer 27 and the gate 25, and is used to electrically isolate the gate 25 from the source 22 and the drain 23.

[0177] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip, characterized in that: A transistor is provided, wherein the transistor comprises a channel layer, a first doped cap layer, and a gate which are sequentially arranged on a substrate; The transistor further includes a first oxide layer, which is located at the periphery of the first doped cap layer and surrounds the first doped cap layer; the material of the first oxide layer and the material of the first doped cap layer have at least two same elements.

2. The chip according to claim 1, characterized in that: The transistor further includes a second oxide layer; the second oxide layer is located outside the first oxide layer and surrounds the first oxide layer.

3. The chip according to claim 1 or 2, characterized in that: The material of the first doped cap layer includes p-GaN, and the material of the first oxide layer includes Ga x O y N z ; Among them, x, y, and z are all greater than 0.

4. The chip according to any one of claims 1 to 3, characterized in that: The transistor further includes a nucleation layer, wherein the nucleation layer is disposed between the substrate and the channel layer; and / or, The transistor further includes a plurality of first superlattice voltage-resistant layers and a plurality of second superlattice voltage-resistant layers which are alternately arranged, and the plurality of first superlattice voltage-resistant layers and the plurality of second superlattice voltage-resistant layers are located between the nucleation layer and the channel layer.

5. The chip according to any one of claims 1 to 4, characterized in that: The transistor further includes a barrier layer disposed between the channel layer and the first doped cap layer.

6. The chip according to claim 5, characterized in that: The transistor further includes an AlN insertion layer disposed between the channel layer and the barrier layer.

7. The chip according to any one of claims 1 to 6, characterized in that: The transistor further includes a source and a drain, and the chip further includes a passivation layer; The source electrode and the drain electrode are located on the channel layer and are disposed on opposite sides of the first oxide layer; the passivation layer is disposed between the source electrode and the first oxide layer, and between the drain electrode and the first oxide layer.

8. A method for preparing a chip, characterized in that: include: forming a channel layer on a substrate; forming a doped cap layer on the channel layer, and etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer; The material of the first doped cap layer is the same as that of the doped cap layer pattern, and the first oxide layer is located at the periphery of the first doped cap layer and surrounds the first doped cap layer; A gate is formed on the first doped cap layer.

9. The method for preparing a chip according to claim 8, characterized in that: The step of forming a doped cap layer on the channel layer, etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer comprises: forming the doping cap layer and the mask plate on the channel layer in sequence; the pattern of the mask layer is the same as the overall pattern of the first doping layer and the first oxide layer; The doped cap layer is alternately subjected to multiple dry etchings and at least one thermal oxidation to obtain the first doped cap layer and the first oxide layer.

10. The method for preparing a chip according to claim 9, characterized in that: The step of alternately performing multiple dry etching and at least one thermal oxidation on the doped cap layer to obtain the first doped cap layer and the first oxide layer comprises: After alternately performing M dry etching and M thermal oxidation on the doped cap layer, the doped cap layer is dry etched once to obtain the first doped cap layer and the first oxide layer; wherein M is a positive integer.

11. The method for preparing a chip according to claim 9, characterized in that: The step of forming a doped cap layer on the channel layer, etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer comprises: Dry-etching the doped cap layer to obtain a doped cap layer pattern; the doped cap layer pattern is the same as the mask layer pattern; The doped cap layer pattern is thermally oxidized to obtain the first doped cap layer and the first oxide layer.

12. The method for preparing a chip according to claim 11, characterized in that: After dry etching the doped cap layer and before thermally oxidizing the doped cap layer pattern, the chip preparation method further includes: A protection layer is formed on a side of the channel layer facing away from the substrate, and the protection layer covers an exposed portion of the channel layer.

13. The method for preparing a chip according to claim 9, characterized in that: The step of forming a doped cap layer on the channel layer, etching and thermally oxidizing the doped cap layer to obtain a first doped cap layer and a first oxide layer comprises: Dry-etching the doped cap layer to obtain a doped cap layer pattern; the doped cap layer pattern is the same as the mask layer pattern; forming a second oxide layer on the periphery of the doped cap layer pattern, wherein the second oxide layer surrounds the doped cap layer pattern; The doped cap layer pattern is thermally oxidized by using the second oxide layer to obtain the first doped cap layer and the first oxide layer.

14. The method for preparing a chip according to claim 13, characterized in that: After dry etching the doped cap layer and before forming a second oxide layer around the doped cap layer pattern, the chip preparation method further includes: A protection layer is formed on a side of the channel layer facing away from the substrate; the protection layer covers the exposed portion of the channel layer, or the pattern of the protection layer is the same as the pattern of the second oxide layer to be formed.

15. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 7, wherein the chip is arranged on the circuit board.

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