A staggered floor unit and a method of making the same

Abstract

The disclosure provides a staggered layer unit and a preparation method thereof, which can be applied to the technical field of semiconductors. The staggered layer unit comprises: a first group of field effect transistors and a second group of field effect transistors arranged along a first horizontal direction on a substrate surface; an intermediate dielectric layer surrounding the substrate, the first group of field effect transistors and the second group of field effect transistors; a first staggered layer contact hole connected with a gate stack of a pull-up transistor in the first group of field effect transistors, extending to a lower surface of the substrate in the intermediate dielectric layer and connecting with a common layer of the second group of field effect transistors through the substrate, thereby forming a staggered layer structure with a second staggered layer contact hole for connecting the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a staggered layer cell and a method for manufacturing the same. BACKGROUND

[0002] With the continuous development of the manufacturing process node and key technology of integrated circuits, NS-GAA FET (Nano-Sheet Gate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at the 3nm and below nodes. Further, three-dimensional stacked transistors will become the main technology roadmap after the 1nm node. Among them, three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFET (Vertical Field-Effect Transistor), etc. Among them, three-dimensional stacked integrated transistors are 3DS FET, or also known as CFET (Complementary Field Effect Transistor).

[0003] The main process methods for implementing 3DS FET include two categories: one is sequential integration, and the other is self-aligned simultaneous (or single) integration. The former process method is simple, but is limited by performance and resources; the latter process method has high integration and superior performance, but this method is complex and has multiple process technology challenges. SUMMARY

[0004] In view of this, the present disclosure provides a staggered layer cell and a method for manufacturing the same.

[0005] One aspect of the present disclosure provides a staggered cell, comprising: a first group of field effect transistors and a second group of field effect transistors each arranged along a first horizontal direction on a surface of a substrate; and an interlayer surrounding the substrate, the first group of field effect transistors and the second group of field effect transistors; wherein the first group of field effect transistors and the second group of field effect transistors each comprise a pass transistor and a stacked pull transistor, the stacked pull transistor comprising a lower pull transistor and an upper pull transistor stacked along a vertical direction; the pass transistor, the lower pull transistor and the upper pull transistor each comprising: a channel layer; a source / drain layer interfacing with the channel layer on both sides of the channel layer along the first horizontal direction; a gate stack extending along a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the lower pull transistor, the upper pull transistor and the pass transistor belonging to the same group are coupled via a common layer; a first staggered contact hole interfacing with the gate stack of the pull transistor in the first group of field effect transistors, extending to a lower surface of the substrate in the interlayer and passing through the substrate to interface with the common layer of the second group of field effect transistors, thereby forming a staggered structure with a second staggered contact hole for connecting the gate stack of the pull transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0006] According to embodiments of the present disclosure, the first group of field effect transistors and the second group of field effect transistors are arranged along the second horizontal direction and spaced apart from each other; the first staggered contact hole extends from the gate stack of the pull transistor in the first group of field effect transistors to the lower surface of the substrate in the spacing space and interfaces with the common layer in the second group of field effect transistors inside the substrate; and the second staggered contact hole extends from the gate stack of the pull transistor in the second group of field effect transistors to the common layer in the first group of field effect transistors above the substrate.

[0007] According to embodiments of the present disclosure, a source layer contact hole interfacing with an upper surface of a source layer of the pass transistor in the first group of field effect transistors extends downward to a surface of the interlayer in the spacing space, so as to electrically connect the pass transistor in the first group of field effect transistors with a bit line terminal.

[0008] According to embodiments of the present disclosure, a source layer contact hole interfacing with a lower surface of a source layer of the upper pull transistor in the second group of field effect transistors extends downward from the upper surface of the substrate to a surface of the interlayer, so as to electrically connect the upper pull transistor in the second group of field effect transistors with a power terminal; and a source layer contact hole interfacing with an upper surface of a source layer of the lower pull transistor in the second group of field effect transistors extends downward to a surface of the interlayer in the spacing space, so as to electrically connect the lower pull transistor in the second group of field effect transistors with a ground terminal.

[0009] Another aspect of the present disclosure provides a method for manufacturing a staggered layer cell, comprising: forming a first group of field effect transistors and a second group of field effect transistors on a substrate, the first group of field effect transistors and the second group of field effect transistors being spaced apart from each other and arranged along a first horizontal direction; wherein each of the first group of field effect transistors and the second group of field effect transistors comprises a pass transistor and a stacked pull transistor, the stacked pull transistor comprising a lower pull transistor and an upper pull transistor stacked along a vertical direction; each of the pass transistor, the lower pull transistor and the upper pull transistor comprises a channel layer, a source / drain layer on both sides of the channel layer along the first horizontal direction and a gate stack extending along a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the lower pull transistor, the upper pull transistor and the pass transistor belonging to the same group are coupled via a common layer; forming an intermediate dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate; forming a first staggered layer contact hole and a second staggered layer contact hole in the intermediate dielectric layer to obtain a staggered layer cell; wherein the second staggered layer contact hole is in contact with the gate stack of the pull transistor in the second group of field effect transistors and simultaneously in contact with the common layer of the first group of field effect transistors; the first staggered layer contact hole is in contact with the gate stack of the pull transistor in the first group of field effect transistors and simultaneously extends to a lower surface of the substrate in the intermediate dielectric layer and passes through the substrate to be in contact with the common layer of the second group of field effect transistors, thereby forming a staggered layer structure with the second staggered layer contact hole, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0010] According to embodiments of the present disclosure, the intermediate dielectric layer surrounds the first group of field effect transistors and the second group of field effect transistors; the above manufacturing method further comprises: etching the intermediate dielectric layer from above to form a first opening exposing a source layer of the lower pull transistor in the second group of field effect transistors and a second opening exposing a source layer of the pass transistor in the first group of field effect transistors, wherein a spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with a projection plane of the first opening in the vertical direction, and the spacing space partially overlaps with a projection plane of the second opening in the vertical direction; filling the first opening and the second opening with a conductive material and closing the first opening and the second opening; etching the intermediate dielectric layer in the spacing region between the first group of field effect transistors and the second group of field effect transistors from below to form a third opening exposing the conductive material in the first opening and a fourth opening exposing the conductive material in the second opening; filling the third opening and the fourth opening with a conductive material, thereby forming a source layer contact hole in the intermediate dielectric layer in contact with the source layer of the lower pull transistor in the second group of field effect transistors to facilitate electrical connection of the lower pull transistor in the second group of field effect transistors to a ground terminal, and forming a source layer contact hole in the intermediate dielectric layer in contact with the source layer of the pass transistor in the first group of field effect transistors to facilitate electrical connection of the pass transistor in the first group of field effect transistors to a bit line terminal.

[0011] According to an embodiment of the present disclosure, the pull-up transistor in the second group of field effect transistors and the transmission transistor are electrically connected through the first common layer, and the pull-down transistor in the second group of field effect transistors and the transmission transistor are electrically connected through the first common layer and the second common layer; the first staggered layer contact hole and the second staggered layer contact hole are formed in the intermediate dielectric layer to obtain a staggered layer unit, including: etching the intermediate dielectric layer from above to form a fifth opening that simultaneously exposes the first common layer, the second common layer, and the gate stack of the pull-down transistor in the second group of field effect transistors; filling the fifth opening with conductive material that contacts the first common layer, the second common layer, and the gate stack of the pull-down transistor in the second group of field effect transistors, and closing the fifth opening, thereby forming the second staggered layer contact hole.

[0012] According to an embodiment of the present disclosure, the pull-up transistor in the first group of field effect transistors and the transmission transistor are electrically connected through the third common layer, and the pull-down transistor in the first group of field effect transistors and the transmission transistor are electrically connected through the third common layer and the fourth common layer; the above preparation method further includes: etching the intermediate dielectric layer from above along the surface of the intermediate dielectric layer to form a sixth opening that exposes the third common layer and the fourth common layer, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection plane of the sixth opening in the vertical direction; filling the sixth opening with conductive material and closing the sixth opening; forming the first staggered layer contact hole and the second staggered layer contact hole in the intermediate dielectric layer to obtain a staggered layer unit, further including: etching the intermediate dielectric layer from below along the surface of the intermediate dielectric layer to form a seventh opening that simultaneously exposes at least one of the third common layer and the fourth common layer and the gate stack of the pull-down transistor in the second group of field effect transistors; filling the seventh opening with conductive material and closing the seventh opening, thereby forming the first staggered layer contact hole.

[0013] According to an embodiment of the present disclosure, the above preparation method further includes: etching the substrate and the intermediate dielectric layer from below at the source layer position of the pull-up transistor in the second group of field effect transistors to form a source layer contact hole that is connected to the lower surface of the source layer of the pull-up transistor in the second group of field effect transistors through the substrate and the intermediate dielectric layer, so as to electrically connect the pull-up transistor in the second group of field effect transistors to the power supply end.

[0014] According to an embodiment of the present disclosure, the first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching a substrate; a portion of the substrate remaining after the etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors; forming an intervening dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors, and the substrate includes: etching the portion of the substrate from below until lower surfaces of the lower fins of the first group of field effect transistors and the second group of field effect transistors are exposed; and depositing a dielectric material on the lower surfaces of the lower fins of the first group of field effect transistors and the second group of field effect transistors to obtain the intervening dielectric layer.

[0015] According to an embodiment of the present disclosure, the present disclosure achieves local interconnection between the common layer of the second group of field effect transistors and the gate stack of the pull-down field effect transistor of the first group of field effect transistors through back gate contact by setting the second staggered layer contact hole to be in contact with the gate stack of the pull-down field effect transistor in the second group of field effect transistors and extending in the intervening dielectric layer to be in contact with the common layer of the first group of field effect transistors, and setting the first staggered layer contact hole to be in contact with the gate stack of the pull-down field effect transistor in the first group of field effect transistors and extending in the intervening dielectric layer to the lower surface of the substrate and through the substrate to be in contact with the common layer of the second group of field effect transistors. Thus, the first staggered layer contact hole and the second staggered layer contact hole opposite to the storage site of the first staggered layer contact hole form a staggered layer structure with up-down hierarchical symmetry in physical space, greatly reducing the area of the integrated circuit realized based on the staggered layer unit in the horizontal plane, and the preparation process is simple. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of the development process of an integrated circuit according to an embodiment of the present disclosure is schematically shown.

[0018] Figure 2 A schematic diagram of the evolution path of the core transistor structure of an integrated circuit according to an embodiment of the present disclosure is schematically shown.

[0019] Figure 3 A schematic diagram of a sequential integration process according to an embodiment of the present disclosure is schematically shown.

[0020] Figure 4 A schematic diagram of a self-aligned simultaneous integration process according to an embodiment of the present disclosure is schematically shown.

[0021] Figure 5A A structural schematic diagram of a staggered layer unit according to an embodiment of the present disclosure is schematically shown.

[0022] Figure 5B A schematic diagram of a structure of a field effect transistor in a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0023] Figure 6 A schematic diagram of an SRAM integrated circuit is shown illustratively in accordance with embodiments of the present disclosure.

[0024] Figure 7 A schematic diagram of a single layer SRAM structure is shown illustratively in accordance with embodiments of the present disclosure.

[0025] Figure 8A A schematic diagram of a layer structure of a three-dimensional stacked SRAM structure is shown illustratively in accordance with embodiments of the present disclosure.

[0026] Figure 8B A schematic diagram of a top layer structure in a three-dimensional stacked SRAM structure is shown illustratively in accordance with embodiments of the present disclosure.

[0027] Figure 8C A schematic diagram of a bottom layer structure in a three-dimensional stacked SRAM structure is shown illustratively in accordance with embodiments of the present disclosure.

[0028] Figure 8D A schematic diagram of a backside contact in a three-dimensional stacked SRAM structure is shown illustratively in accordance with embodiments of the present disclosure.

[0029] Figure 9A A schematic diagram of a layer structure of a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0030] Figure 9B A schematic diagram of a top layer structure in a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0031] Figure 9C A schematic diagram of a bottom layer structure in a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0032] Figure 9D A schematic diagram of a backside contact in a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0033] Figure 10A A schematic diagram of an axial view of a mislayered cell extending in a first horizontal direction is shown illustratively in accordance with embodiments of the present disclosure.

[0034] Figure 10B A schematic diagram of an axial view of a mislayered cell extending in a second horizontal direction is shown illustratively in accordance with embodiments of the present disclosure.

[0035] Figures 11A-11E A schematic diagram of Figure 8A an axial view of a mislayered cell is shown illustratively in accordance with embodiments of the present disclosure.

[0036] Figures 12A-12E schematically illustrates Figure 9A schematically illustrates the axial view of each of the staggered cell layer structures.

[0037] Figure 13 schematically illustrates a flow chart of a method for preparing a staggered cell according to an embodiment of the present disclosure.

[0038] Figures 14A-53A 、 Figures 14B-53B 、 Figure 45C 、 Figure 45D 、 Figure 51C 、 Figure 51D 、 Figure 53C and Figure 53D schematically illustrates the axial cross-sectional view of a staggered cell according to an embodiment of the present disclosure.

[0039] Figure 54 schematically illustrates a cross-sectional view of a three-dimensional stacked structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to specific embodiments and drawings.

[0041] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0042] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present specification, and should not be interpreted in an idealized or overly formal manner.

[0043] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should be generally interpreted as including one or more of the relevant items, unless otherwise defined. For example, "a system having at least one of A, B, and C" should be interpreted as including a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc. In the case of using expressions similar to "at least one of A, B, or C, etc.", it should be generally interpreted as including one or more of the relevant items, unless otherwise defined. For example, "a system having at least one of A, B, or C" should be interpreted as including a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.

[0044] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0045] In this embodiment of the disclosure, Figure 1 The illustrated technology development roadmap serves as an example to demonstrate the progress of integrated circuit development. It should be noted that... Figure 1 In this context, "Tech Node" refers to a semiconductor process node, which can be used to represent the critical dimensions achievable in the manufacturing process of integrated circuits. Based on this, refer to... Figure 1 As shown in the technology development roadmap, the integrated circuit fabrication processes are ordered from high to low according to the size represented by the semiconductor process nodes, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D, and StackedFET 11E. Specifically, the dimensions represented by Tech Node 12A of Planar 11A, from highest to lowest, are 90, 65, 45, 32, 28, and 20, in nm; the dimensions represented by Tech Node 12B of Fin FET 11B, from highest to lowest, are 14, 10, 7, 5, and 4, in nm; the dimensions represented by Tech Node 12C of NS-GAA FET 11C, from highest to lowest, are 3 and 2, in nm; and the dimensions represented by Tech Node 12D of VFET 11D and Stacked FET 11E, from highest to lowest, are 1 and 0.7, in nm.

[0046] Furthermore, such as Figure 2 As shown, in the evolution path of the core transistor structure of integrated circuits, it will evolve from Fin FET201 to NS-GAA FET202, Forksheet FET203, and further to three-dimensional stacked integrated transistors in a single chip, namely 3DS FET or CFET (Complementary Field Effect Transistor)204, in order to obtain higher integration density and overall performance.

[0047] like Figure 3 and Figure 4As shown, the main process methods for implementing 3DS FETs include two categories: one is sequential integration process (Sequential 3D), and the other is self-aligned monolithic integration process (Monolithic 3D). Taking two transistors stacked below as an example, in the case of using sequential integration process to manufacture the two transistors, the channel materials of the two transistors can be different from each other; in the case of using self-aligned monolithic integration process to manufacture the two transistors, the channel materials of the two transistors can be the same. For example, the operation of sequential integration process can include: bonding the substrate 301 to the upper part of the bottom device 302 to obtain the intermediate device 303; based on the bonded substrate in the intermediate device, manufacturing the top device to obtain the integrated circuit 304. The self-aligned monolithic integration process can include growing the polysilicon layer 402 surrounding the plurality of channel layers directly on the fin structure 401, and then processing to obtain the integrated circuit 403.

[0048] Therefore, the sequential integration process method is simple, but is limited by performance and resources; the latter self-aligned monolithic integration process method has high integration degree and superior performance, but this method is complex and has various process technical challenges.

[0049] Specifically, the advantages of sequential integration process include: flexible architecture design, channel material can be adjusted as needed, flexible connection setting between transistors, etc. The disadvantages of sequential integration process mainly include: high resource consumption, limitations of preparation process, adhesion, isolation space between N-P, heat budget and lithography alignment.

[0050] The advantages of self-aligned monolithic integration process include: low resource consumption, accurate process control, such as self-aligned top and bottom devices, and narrow isolation space between N-P, etc. The disadvantages mainly include: high process difficulty, such as process with high aspect ratio and interconnection between devices, etc.

[0051] Based on this, the present disclosure provides a staggered cell and its fabrication method, so as to obtain a highly integrated CFET device with a staggered structure through a simple process, namely the aforementioned staggered cell. Specifically, the staggered cell includes: a first group of field-effect transistors and a second group of field-effect transistors respectively arranged along a first horizontal direction on the upper surface of a substrate; and an intermediary dielectric layer surrounding the substrate, the first group of field-effect transistors and the second group of field-effect transistors; wherein, the first group of field-effect transistors and the second group of field-effect transistors each include a transport transistor and a stacked pull-up transistor, the stacked pull-up transistor including a pull-down transistor and a pull-up transistor stacked along a vertical direction; the transport transistor, the pull-down transistor and the pull-up transistor each include: a channel layer; source / drain layers connected to the channel layer on both sides of the channel layer in the first horizontal direction; and on the first horizontal direction... A gate stack extending in a second horizontal direction and surrounding the channel layer; pull-down transistors, pull-up transistors, and transfer transistors belonging to the same group are coupled via a common layer; a first staggered contact hole connected to the gate stack of the pull-up transistors in the first group of field-effect transistors extends in the intervening dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field-effect transistors, thereby forming a staggered structure with the second staggered contact hole used to connect the gate stack of the pull-up transistors in the second group of field-effect transistors and the common layer of the first group of field-effect transistors, such that the first group of field-effect transistors and the second group of field-effect transistors are cross-coupled to each other.

[0052] Figure 5A A schematic diagram of a staggered unit according to an embodiment of the present disclosure is shown. Figure 5B A schematic diagram of a field-effect transistor with a staggered cell according to an embodiment of the present disclosure is shown. It should be noted that, in Figure 5A and Figure 5B In this specification, the extension direction of the X-axis is defined as a first horizontal direction, the extension direction of the Y-axis is defined as a second horizontal direction intersecting the first horizontal direction, and the extension direction of the Z-axis is defined as a vertical direction. In one embodiment of this disclosure, the first horizontal direction and the second horizontal direction may be perpendicular to each other within the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0053] like Figure 5A As shown, the staggered unit 500 of this embodiment includes: a first group of field-effect transistors and a second group of field-effect transistors respectively arranged along a first horizontal direction on the upper surface of the substrate SUB, and an intermediary dielectric layer surrounding the substrate SUB, the first group of field-effect transistors, and the second group of field-effect transistors. The appearance of each field-effect transistor in this embodiment is determined by... Figure 5B As shown. In Figure 5B The field-effect transistor shown includes a gate structure G surrounding a channel layer such as a nanosheet or nanowire (the channel layer is surrounded by the gate structure G). Figure 5A(Not shown in the perspective view), and the source / drain layers L located on both sides of the gate structure G and connected to the channel layer.

[0054] exist Figure 5A Each field-effect transistor shown can be used as a transfer transistor or a pull-up transistor, etc., depending on actual needs. A transfer transistor can be used to transfer write data from a bit line. A pull-up transistor can include pull-up transistors and pull-down transistors. A pull-up transistor can be used to pull up node levels. A pull-down transistor can be used to pull down node levels. Furthermore, in... Figure 5A In order to avoid obscuring the structure of the staggered unit 500, Figure 5A The schematic diagram of the intermediate dielectric layer is omitted. It should be understood that the intermediate dielectric layer in the embodiments of this disclosure can be configured as needed between the structures of the staggered units 500 to ensure electrical isolation between the various field-effect transistors in the staggered units 500.

[0055] Continue to refer to Figure 5A ,exist Figure 5A Two substrate sub-subs are shown arranged along a second horizontal direction. Multiple field-effect transistors integrated into a single structure are disposed on each of these two substrate sub-subs. Therefore, for ease of description, the structures located in this disclosure will be referred to as... Figure 5A The multiple field-effect transistors on the substrate SUB at the lower left are defined as the first group of field-effect transistors mentioned above, and their... Figure 5A The space shown is located in front; and, will be located in Figure 5A The transistor on the upper right substrate is defined as the second group of field-effect transistors mentioned above, and its... Figure 5A Located in the rear of the space shown. The first group of field-effect transistors and the second group of field-effect transistors each include stacked field-effect transistors. For example, the first group of field-effect transistors and the second group of field-effect transistors each include a transport transistor and stacked pull-up transistors, the stacked pull-up transistors including pull-down transistors and pull-up transistors stacked vertically. Each of the transport transistor, pull-down transistor, and pull-up transistor includes: a channel layer; source / drain layers adjoining the channel layer on both sides in a first horizontal direction; and a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer. It should be noted that in embodiments of this disclosure, the transport transistor may also be stacked with another transistor, the actual function of which can be determined based on requirements, and will not be elaborated upon here.

[0056] The following will Figure 5AThe field effect transistors shown in FIG. 1 are defined as pull-up transistors or pull-down transistors for the purpose of understanding the structure of the staggered cell 500 of the embodiments of the present disclosure. It should be understood that the following is only an example, and those skilled in the art can need to set the functions of the field effect transistors in the staggered cell 500.

[0057] For example, the transistor located at the upper left in the first group of field effect transistors is defined as a pass transistor AC1; the transistor located at the upper right in the first group of field effect transistors is defined as a pull-down transistor PD1; and the transistor located at the lower right in the first group of field effect transistors is defined as a pull-up transistor PU1. Referring to FIG. 1, Figure 5A It can be seen that the pass transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the first group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection of the pass transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 can be realized. Moreover, the common layer for electrical connection between the pass transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 corresponds to the first source / drain layer of each of the pass transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1. Among them, the pass transistor AC1 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the pass transistor AC1, and the pass transistor AC1 can be electrically connected to the word line end through the gate contact hole connected to the gate structure G thereof. The pull-up transistor PU1 can be electrically connected to the power supply end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the pull-up transistor PU1; the pull-down transistor PD1 can be electrically connected to the ground end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the pull-down transistor PD1. Based on this, the pull-up transistors in the first group of field effect transistors can be configured as inverters, the pull-up transistor PU1 can realize the level of the pull-up common layer, and the pull-down transistor PD1 can realize the level of the pull-down common layer.

[0058] Correspondingly, the transistor located at the upper right in the second group of field effect transistors is defined as a pass transistor AC2; the transistor located at the lower left in the second group of field effect transistors is defined as a pull-down transistor PD2; and the transistor located at the upper left in the second group of field effect transistors is defined as a pull-up transistor PU2. Referring to FIG. 1, Figure 6It can be seen that the transmission transistor AC2 and the pull-down transistor PU2 are coupled through the common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the second group of field effect transistors are coupled through the connection structure. Based on this, the electrical connection of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 can be realized. Moreover, the common layer for electrical connection between the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 corresponds to the first source / drain layer of each of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2. Among them, the transmission transistor AC2 can be electrically connected to the bit line end through the source layer contact hole connected to the second source layer on the other side of the gate structure of the transmission transistor AC2, and the transmission transistor AC2 can be electrically connected to the word line end through the gate contact hole connected to the gate structure G thereof. The pull-up transistor PU2 can be electrically connected to the power supply end through the source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU2; the pull-down transistor PD2 can be electrically connected to the ground end through the source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD2. Based on this, the pull-up transistor PU2 can realize the level of the pull-up common layer, and the pull-down transistor PD2 can realize the level of the pull-down common layer.

[0059] On this basis, by cross-coupling the first group of field effect transistors and the second group of field effect transistors with each other, an SRAM structure (Static Random-Access Memory) can be formed. As shown in Figure 7 , the SRAM is the core unit circuit of the integrated circuit, and continuously reducing the area of the SRAM unit is the main line of the development of the integrated circuit. The use of the three-dimensional stacked structure (3DS-FET or CFET) of the transistor can greatly reduce the area of the SRAM unit, and the reduced area of the SRAM unit is more than 30%. Referring to Figure 8A and Figure 7 , by comparing the single-layer SRAM structure of Figure 8A and the double-layer SRAM structure in Figure 8A , Figure 7 , it can be seen that the area of the three-dimensional stacked structure realized is smaller than the area of the two-dimensional structure in Figure 8A . Further, Figure 8B , the three-dimensional stacked structure in Figure 8C and Figure 8Aare shown respectively Figure 8D top and bottom structures of the three-dimensional stacked structure. Figure 8A are shown schematically in a fill pattern Figure 5A backside contacts of the three-dimensional stacked structure.

[0060] In a cross-coupling manner of the embodiments of the present disclosure, the first mislayered contact hole QB, which is in contact with the gate stack of the pull-up transistor in the first group of field effect transistors, extends to the lower surface of the substrate SUB in the intervening dielectric layer and passes through the substrate SUB to be in contact with the common layer of the second group of field effect transistors, thereby forming a mislayered structure with the second mislayered contact hole Q for connecting the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other. Wherein, in the case of implementing SRAM based on the mislayered cell of the present disclosure, the first mislayered contact hole QB can be electrically connected to the first signal output terminal, and the second mislayered contact hole Q can be electrically connected to the second signal output terminal.

[0061] Specifically, continuing to refer to Figure 5A It can be seen that the first group of field effect transistors and the second group of field effect transistors are arranged along the second horizontal direction and there is a spacing space between them. The first mislayered contact hole QB extends from the gate stack of the pull-up transistor in the first group of field effect transistors to the lower surface of the substrate SUB in the spacing space and passes through the substrate to be in contact with the common layer in the second group of field effect transistors. The second mislayered contact hole Q extends from the gate stack of the pull-up transistor in the second group of field effect transistors to the common layer in the first group of field effect transistors above the substrate. The spacing space is filled with a dielectric material serving as an intervening dielectric layer.

[0062] In Figure 9A In order to facilitate, the electrical connection configuration of the first mislayered contact hole QB and the second mislayered contact hole Q is shown schematically, and the physical connection manner thereof is only schematic. The physical appearance of the first mislayered contact hole QB and the second mislayered contact hole Q and the physical connection with other components can be known by those skilled in the art according to the following description.

[0063] Based on the above cross-coupling manner, the area of the SRAM cell can be further reduced based on the three-dimensional stacked structure. Figure 9B The circuit topology diagram of the three-dimensional stacked structure of the above mislayered cell is shown. Figure 9C and Figure 9A are shown respectively Figure 9D top and bottom structures of the three-dimensional stacked structure. Figure 9A are shown schematically in a fill pattern Figure 8A backside contacts of the three-dimensional stacked structure.

[0064] Based on this, the present disclosure achieves the local interconnection between the common layer of the second group of field effect transistors and the gate stack of the pull-down transistor of the first group of field effect transistors through the back gate contact by setting the second mislayered contact hole Q to be in contact with the gate stack of the pull-down transistor in the second group of field effect transistors and extending to the common layer of the first group of field effect transistors in the intermediate dielectric layer, and setting the first mislayered contact hole QB to be in contact with the gate stack of the pull-down transistor in the first group of field effect transistors and extending to the lower surface of the substrate SUB in the intermediate dielectric layer and contacting the common layer of the second group of field effect transistors through the substrate SUB. In this way, the first mislayered contact hole QB and the second mislayered contact hole Q opposite to the first mislayered contact hole QB form a mislayered structure with up-down hierarchical symmetry in the physical space, greatly reducing the area of the integrated circuit realized based on the mislayered unit in the horizontal plane, and the preparation process is simple. For example, compared with the 156nm in Figure 9A and Figure 8A It can be seen that, since the first mislayered contact hole QB and the second mislayered contact hole Q constitute a mislayered structure, the first mislayered contact hole QB and the second mislayered contact hole Q have a certain overlap in the Z-axis direction, so the size in the horizontal direction is reduced, that is, the 156nm in Figure 9A is reduced to 136nm in Figure 10A This hierarchical manufacturing structure of storage sites can greatly reduce the area of the SRAM unit based on the CFET and the like. It should be noted that the dimensions marked in the drawings of the present disclosure are examples and do not limit the actual size of the mislayered unit in the present disclosure.

[0065] In the embodiments of the present disclosure, the above-mentioned various source layer contact holes can extend in the intermediate dielectric layer and be exposed to the same surface of the intermediate dielectric layer. For example, the source layer contact hole in contact with the upper surface of the source layer of the transmission transistor AC1 in the first group of field effect transistors extends downward to the surface of the intermediate dielectric layer in the spacing space, so as to electrically connect the transmission transistor AC1 in the first group of field effect transistors with the bit line end. The source layer contact hole in contact with the lower surface of the source layer of the transmission transistor AC2 in the second group of field effect transistors extends through the substrate SUB and to the surface of the intermediate dielectric layer in the spacing space, so as to electrically connect the transmission transistor AC2 in the second group of field effect transistors with the bit line end.

[0066] For example, a source layer contact hole that connects to the lower surface of the source layer of the pull-down transistor PD1 in the first group of field-effect transistors extends downward from the upper surface of the substrate SUB through the substrate SUB to the surface of the intermediate dielectric layer, thereby electrically connecting the pull-down transistor PD1 in the first group of field-effect transistors to the ground terminal. Similarly, a source layer contact hole that connects to the upper surface of the source layer of the pull-up transistor PU1 in the first group of field-effect transistors extends downward within the spacer to the surface of the intermediate dielectric layer, thereby electrically connecting the pull-up transistor PU1 in the first group of field-effect transistors to the power supply terminal.

[0067] For example, a source layer contact hole that connects to the lower surface of the source layer of the pull-up transistor PU2 in the second group of field-effect transistors extends downward from the upper surface of the substrate SUB through the substrate SUB to the surface of the intervening dielectric layer, thereby electrically connecting the pull-up transistor PU2 in the second group of field-effect transistors to the power supply terminal. A source layer contact hole that connects to the upper surface of the source layer of the pull-down transistor PD2 in the second group of field-effect transistors extends downward within the space to the surface of the intervening dielectric layer, thereby electrically connecting the pull-down transistor PD2 in the second group of field-effect transistors to the ground terminal.

[0068] To better understand the structure of the staggered units in this disclosure, the following explanation, combined with the fabrication method of the staggered units, illustrates the content of this disclosure. SRAM is used as an example here. Figure 10B and Figures 11A-11E The various axes of the staggered unit as defined in the embodiments of this disclosure are shown.

[0069] Figure 8A An example is shown Figures 12A-12E The various axes of the three-dimensional stacked structure. Figure 9A An example is shown Figure 13 This paper discloses the three-dimensional structure of the staggered unit along various axes. Among them, the X-X' axis is consistent with the extension direction of the X-axis in Figure 10. The Y1-Y1', Y2-Y2', Y3-Y3', and Y4-Y4' axes are consistent with the extension direction of the Y-axis in Figure 10.

[0070] Figure 13 A flowchart illustrating a method for fabricating a staggered unit according to an embodiment of the present disclosure is shown.

[0071] like Figures 14A-53A As shown, the method for preparing the staggered unit in this embodiment includes operations S1301 to S1303.

[0072] In operation S1301, a first group of field effect transistors and a second group of field effect transistors are formed on a substrate surface and arranged along a first horizontal direction with a spacing between each other; wherein the first group of field effect transistors and the second group of field effect transistors each include a pass transistor and a superposed pull transistor, the superposed pull transistor including a lower pull transistor and an upper pull transistor superposed along a vertical direction; the pass transistor, the lower pull transistor and the upper pull transistor each include a channel layer, a source / drain layer on both sides of the channel layer along the first horizontal direction and in contact with the channel layer, and a gate stack extending along a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the lower pull transistor, the upper pull transistor and the pass transistor belonging to the same group are coupled via a common layer.

[0073] In operation S1302, an intermediate dielectric layer is formed surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate.

[0074] In operation S1303, a first mislayered contact hole and a second mislayered contact hole are formed in the intermediate dielectric layer, obtaining a mislayered unit; wherein the second mislayered contact hole is in contact with the gate stack of the pull transistor in the second group of field effect transistors and at the same time in contact with the common layer of the first group of field effect transistors; the first mislayered contact hole is in contact with the gate stack of the pull transistor in the first group of field effect transistors and at the same time extends to the lower surface of the substrate in the intermediate dielectric layer and passes through the substrate to be in contact with the common layer of the second group of field effect transistors, thereby forming a mislayered structure with the second mislayered contact hole, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0075] In order to better understand the preparation method of the mislayered unit of the present disclosure, the following is based on the cross-sectional view of each axis during the preparation of the mislayered unit, i.e. Figures 14B-53B , Figure 45C , Figure 45D , Figure 51C , Figure 51D , Figure 53C , Figure 53D and Figures 14A-53A to elaborate the content of the embodiments of the present disclosure. It should be noted that in the Figures 14B-53B , Figure 45C , Figure 45D , Figure 51C , Figure 51D , Figure 53C , Figure 53D and Figure 14A shown in the following text, in the case of the same number in the title of each figure in the multiple figures, the preparation process corresponding to the multiple figures is the same. In the case of the same number and different letters in the title of each figure in the multiple figures, the preparation process corresponding to the multiple figures is the same, and the axis corresponding to the multiple figures is different. For example, Figure 14B and Figures 14A-15Aare two axial cross-sectional views of the same preparation process, respectively.

[0076] with a set of stacked field effect transistors as an example, Figures 14B-15B is a cross-sectional view along the X-X' axis during the preparation of the staggered cell. Figures 14A-15A is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered cell. Reference is made to Figures 14B-15B , and Figures 16A-18A The material of the substrate SUB can include silicon, etc. The substrate SUB can be sequentially subjected to pre-processing operations such as well lithography, ion implantation, annealing, and cleaning. Then, the lower layer structure, the intermediate layer 103, and the upper layer structure are sequentially arranged on the pre-processed substrate SUB by using an epitaxial growth process. The lower layer structure and the upper layer structure each include channel layers 101 and sacrificial layers 102 arranged alternately. The material of the sacrificial layer 102 and the intermediate layer 103 can be consistent, such as SiGe or Si, etc. The material of the channel layer 101 can be doped silicon, etc. The channel layer 101 above the intermediate layer 103 and the channel layer 101 below the intermediate layer 103 can have the same or different doping elements.

[0077] In a first embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 can be p-type doped silicon; the material of the channel layer 101 below the intermediate layer 103 can be n-type doped silicon. In a second embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 can be n-type doped silicon; the material of the channel layer 101 below the intermediate layer 103 can be p-type doped silicon. In a third embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 and the material of the channel layer 101 below the intermediate layer 103 can both be n-type doped silicon or both be p-type doped silicon.

[0078] Figures 16B-18B is a cross-sectional view along the X-X' axis during the preparation of the staggered cell. Figures 16A-18A is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered cell. Reference is made to Figures 16B-18B , and Figures 19A-23AThe sidewall 104 can be formed by a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride, etc. In the embodiments of the present disclosure, a core mold 105 can be formed on the upper layer structure, and the core mold 105 is patterned by a photolithography process to obtain a linear pattern extending along the X direction. The material of the core mold 105 can be polysilicon or amorphous silicon, etc. The sidewall 104 is formed in the above region, and the patterned core mold 105 is removed after the sidewall 104 is formed, so that only the sidewall 104 remains on the layer structure, thereby completing the preparation of the sidewall 104. On this basis, the upper layer structure, the middle layer 103, the lower layer structure and the substrate SUB can be etched by an anisotropic etching process according to the pattern of the sidewall 104, to form a fin on the substrate SUB and a substrate etching region distributed on both sides of the fin along the first horizontal direction. In the substrate etching region, a dielectric material 106 is deposited, and the dielectric material 106 is etched to be lower than or equal to the upper surface of the lower fin composed of the substrate by a back etching process, so that the dielectric material 106 serves as a shallow trench isolation. The dielectric material in the embodiments of the present disclosure can include silicon dioxide or silicon nitride, etc.

[0079] Figures 19B-23B is a cross-sectional view along the X-X' axis in the process of preparing the staggered layer unit. Figures 19A-23A is a cross-sectional view along the Y4-Y4' axis in the process of preparing the staggered layer unit. Refer to Figures 19B-23B , and Figures 24A-31AA sacrificial gate spanning the fin can be formed on the dielectric material 106 by thermal oxidation, chemical vapor deposition or sputtering, etc. The sacrificial gate comprises, from bottom to top, a gate oxide layer 107, a silicon layer 108 and a mask layer 109. The material of the gate oxide layer 107 can be SiO2, etc. The material of the silicon layer 108 can be amorphous silicon or polysilicon. The material of the hard mask layer 109 can be oxide, carbide or organic material, etc. A sidewall 110 can be formed on the sidewall of the sacrificial gate by a sidewall formation process. The material of the sidewall can be SiCNO, etc. The upper layer structure, the middle layer and the lower layer structure can be etched according to the pattern of the sacrificial gate and the sidewall 110, so as to expose the sidewall of each of the upper layer structure, the middle layer and the lower layer structure. The middle layer 103 and the sacrificial layer 102 can be arranged to have different etching selectivity, so that the middle layer 103 can be etched at a faster speed compared to the sacrificial layer 102. After the middle layer 103 is etched, an opening 112 is formed. The end of the sacrificial layer 102 in the first horizontal direction is recessed relative to the channel layer 101, forming an opening 111. Based on this, the space released in the fin due to the selective etching of the sacrificial layer 102 and the middle layer 103 can be filled with a dielectric material. The part of the filling of the dielectric material at the end of the sacrificial layer 102 serves as an inner sidewall 113, and the part of the filling of the dielectric material between the lower layer structure and the upper layer structure serves as a device isolation layer 114. In this way, the inner sidewall 113 and the device isolation layer 114 are manufactured at the same time, reducing the steps of the manufacturing process, and avoiding the adverse consequences of misalignment of the upper field effect transistor and the lower field effect transistor in the vertical direction due to the separate preparation of the inner sidewall 113 and the device isolation layer 114 in the stacked field effect transistors.

[0080] Figures 24B-31B is a cross-sectional view along the X-X' axis during the preparation of the staggered layer unit. Figures 24A-31A is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered layer unit. Reference is made to Figures 24B-31B , and Figures 32A-41A, the lower source / drain position definition layer 115 contacting the channel layer 101 is formed on both sides of the channel layer 101 located under the device isolation layer 114, and the sidewall 116 is formed on the lower source / drain position definition layer 115 by using the sidewall formation process. Among them, the material of the lower source / drain position definition layer 115 may include but is not limited to a-C (amorphous carbon). The formation method of the lower source / drain position definition layer 115 includes but is not limited to spin coating. For example, after depositing a-C, the deposited a-C can be planarized, and the a-C can be etched back to a position not higher than the middle position of the device isolation layer 114. The material of the sidewall 116 includes but is not limited to SiNx, etc. Among them, the sidewall 116 is used to protect the channel layer 101 located above the device isolation layer, and to prevent the source / drain from growing at both ends of the channel layer 101 of the upper device during the source / drain growth process of the lower device. When the device types of the upper and lower layers are different, the source / drain materials of the upper and lower devices can be different.

[0081] After forming the sidewall 116, the lower source / drain position definition layer 115 is removed to expose the sidewalls of the channel layer 101 located under the device isolation layer 114, and on the exposed sidewalls of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, so as to form the source / drain layer 117 connected to the lower stacked structure. Among them, the source / drain material can be SiGe or Si. A dielectric material 118 can be deposited on the source / drain layer 117, and the dielectric material 118 is etched to a position not higher than the device isolation layer 114 for electrical isolation of the source / drain layers of the upper and lower devices respectively. The sidewall 116 can be selectively etched to expose the sidewalls of the channel layer 101 located above the device isolation layer 114. On the exposed sidewalls of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, so as to form the source / drain layer 119 connected to the upper stacked structure. On this basis, the source / drain layers 117 and 119 are subjected to source / drain activation, so as to activate the source / drain layers 117 and 119.

[0082] Figures 32B-41B is a cross-sectional view along the X-X' axis during the process of preparing the staggered unit. Figures 32A-41A is a cross-sectional view along the Y4-Y4' axis during the process of preparing the staggered unit. Refer to Figures 32B-41B , and Figures 42A-45A , a dielectric material 120 is formed on the substrate SUB and the dielectric material 120 is planarized. The planarization can remove the mask layer 109 in the sacrificial gate and expose the silicon layer 108. Then, using the etch-back process, the silicon layer 108 and the sacrificial layer 102 are etched, so as to form the cavity 121_1 exposed due to etching at the original position of the silicon layer 108 inside the sidewall 110 and the inner sidewall 113, and form the cavity 121_2 exposed due to etching at the original position of the sacrificial layer 102.

[0083] A gate stack is formed in sequence on the inner sidewalls of the cavities 121_1 and 121_2, which surrounds the channel layer 101. The gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The material of the gate dielectric layer 122 can be a high-k dielectric material, where k represents the dielectric constant. The high-k dielectric material includes one or a combination of HfO2, HfSiO x , HfON, HfSiON, HfAlO x , HfLaO x , Al2O3, ZrO2, ZrSiO x , Ta2O5, or La2O3. The material of the P-type work function layer 123 can be titanium nitride or the like. A protective layer 124 is formed on the substrate SUB and is etched to a top surface between the top surface and the bottom surface of the device isolation layer 114, so as to shield the cavities of the underlying devices. The protective layer 124 protects the P-type work function layer 123 in the cavities below the device isolation layer 114, while exposing the P-type work function layer 123 in the cavities above the device isolation layer 114.

[0084] The P-type work function layer 123 above the device isolation layer 114 is etched by using a selective etching process, while the gate dielectric layer 122 above the device isolation layer 114 is retained. Then, an N-type work function layer 125 is formed around the gate dielectric layer 122 above the device isolation layer 114. Thus, different gate stacks are formed around the channel layer 101 above and below the device isolation layer 114, respectively. Thus, the channel layer 101, the gate stack, and the source / drain layer 119 above the device isolation layer 114 are configured as an N-type field effect transistor, and the channel layer 101, the gate stack, and the source / drain layer 117 above the device isolation layer 114 are configured as a P-type field effect transistor, thereby obtaining a stacked field effect transistor.

[0085] It should be understood that the above is only one embodiment of the present disclosure, and in the preparation process of other embodiments of the present disclosure, an N-type field effect transistor or a P-type field effect transistor can be formed as needed by changing the doping type of the source / drain layer and forming a corresponding type of work function layer. For example, the upper N-type field effect transistor can be formed as a P-type field effect transistor, and / or the lower P-type field effect transistor can be formed as an N-type field effect transistor.

[0086] After the N-type field effect transistor and the P-type field effect transistor are prepared, the protective layer 124 is removed, so as to release the cavities under the device isolation layer 114. Then, the conductive material is deposited in the whole cavity 121_1 and the whole cavity 121_2, so as to form the conductive layer 126, thereby completing the preparation of the gate structure. The conductive material in the embodiment of the present disclosure can include tungsten or the like. After the conductive layer 126 is formed, the conductive layer 126 can be planarized, and the dielectric material is deposited on the planarized conductive layer 126. On this basis, the contact hole 127 which is in contact with the source / drain layer 119 can be formed in the dielectric material 120.

[0087] Specifically, taking four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors as an example, Figures 42B-45B is a cross-sectional view along the X-X' axis in the process of preparing the staggered layer unit. Figure 45C is a cross-sectional view along the Y3-Y3' axis in the process of preparing the staggered layer unit. Figure 45D is a cross-sectional view along the Y1-Y1' axis in the process of preparing the staggered layer unit. Figures 42A-45A is a cross-sectional view along the Y2-Y2' axis in the process of preparing the staggered layer unit.

[0088] On this basis, Figures 42B-45B 5, Figure 45C , Figure 45D and Figure 45D shows a cross-sectional schematic diagram of a structure integrated with the above eight field effect transistors. On the upper surface of the dielectric material 120, the dielectric material 120 is etched until the source / drain layer 119 is exposed, thereby forming the opening 128_1, the opening 128_2 and the opening 128_3 in the dielectric material 120. Among them, the opening 128_2 includes the opening 128_21 corresponding to the first group of field effect transistors and the opening 128_22 corresponding to the second group of field effect transistors. On this basis, the opening 128_2 is continuously etched according to the position of the source / drain layer 117 as the common layer, so that the opening 128_2 exposes the source / drain layer 119 and the source / drain layer 117 at the same time. The conductive material is filled in the opening 128_1, the opening 128_2 and the opening 128_3, thereby forming the contact hole 127_1, the contact hole 127_2 and the contact hole 127_3. Among them, the contact hole 127_2 includes the contact hole 127_21 formed by filling the opening 128_21 and the contact hole 127_22 formed by filling the opening 128_22. The dielectric material is deposited on the contact hole 127_1, the contact hole 127_2 and the contact hole 127_3. It should be noted that, in the process of etching the dielectric material 120, the dielectric material 120 is etched to expose the source / drain layer 119, and the dielectric material 120 is etched to expose the source / drain layer 117. Figure 45DA structure protruding above the upper surface of the conductive layer 126 is present on the right side of the middle. This structure serves as a connection line extending in a direction perpendicular to the plane of the paper (corresponding to the first horizontal direction). Also, the conductive layer 126 on the left side of the middle extends to the left side in order to draw out a pad for connecting a word line terminal from the back surface. Figures 46A-48A The conductive layer 126 on the left side of the middle extends to the left side in order to draw out a pad for connecting a word line terminal from the back surface.

[0089] Figures 46B-48B is a cross-sectional view along the X-X' axis during the process of manufacturing the staggered cell. Figures 46A-48A is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing the staggered cell. Reference is made to Figures 46B-48B , and Figures 46A-48A . Note that in Figures 46B-48B , and Figures 49A-51A , the stacked field effect transistors are inverted in order to facilitate description, and the same applies to the other drawings below. Note that "above" and "below" in the following are described with respect to the staggered cell before inversion. After inverting the stacked field effect transistors, another substrate USUB can be bonded above the stack, the material of which is the same as that of the substrate SUB described above. In the embodiment of the present disclosure, the first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching the substrate SUB; the remaining portion of the substrate after etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors, respectively. An intervening dielectric layer is formed to surround the first group of field effect transistors, the second group of field effect transistors, and the substrate, including etching the portion of the substrate from below until the lower surfaces of the lower fins of the first group of field effect transistors and the second group of field effect transistors are exposed. A dielectric material is deposited on the lower surfaces of the lower fins of the first group of field effect transistors and the second group of field effect transistors, respectively, to obtain the intervening dielectric layer. In this way, the lower fins of the first group of field effect transistors and the second group of field effect transistors can be electrically isolated from each other.

[0090] Continuing with the example of four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors, Figures 49B-51B is a cross-sectional view along the X-X' axis during the process of manufacturing the staggered cell. Figure 51C is a cross-sectional view along the Y1-Y1' axis during the process of manufacturing the staggered cell. Figure 51D is a cross-sectional view along the Y2-Y2' axis during the process of manufacturing the staggered cell. Figures 49A-51A is a cross-sectional view along the Y3-Y3' axis during the process of manufacturing the staggered cell.

[0091] Reference is made to Figures 49B-51B , Figure 51C , Figure 51D and Figure 52ADepositing dielectric material under the substrate SUB and performing lithography on the dielectric material and the substrate SUB together to form an opening 131 exposing the lower source layer and openings 132_1 and 132_2 exposing the conductive material in contact with the upper source layer. And depositing conductive material in the openings 131, 132_1 and 132_2 to form a backside contact hole via the opening 131 exposing the lower source layer and backside via holes via the openings 132_1 and 132_2 exposing the conductive material in contact with the upper source layer. The conductive material filled in the opening 131 can be used as a backside contact hole (BSCON) to electrically connect to the power supply terminal; the conductive material filled in the openings 132_1 and 132_2 can be used as backside via holes (BSVPR) to electrically connect to the ground terminal and the bit line terminal respectively.

[0092] After the deposition of the conductive material, the conductive material exposed to the outside of the dielectric material is planarized. According to an embodiment of the present disclosure, the above preparation method further comprises: etching the substrate SUB and the intermediate dielectric layer from below according to the position of the source layer of the pull-up transistor in the second group of field effect transistors to form a source layer contact hole through the substrate SUB and the intermediate dielectric layer and in contact with the lower surface of the source layer of the pull-up transistor PU2 in the second group of field effect transistors, so as to electrically connect the pull-up transistor PU2 in the second group of field effect transistors to the power supply terminal. Based on a similar method, the pull-down transistor PD2 in the first group of field effect transistors can be electrically connected to the ground terminal, which is not described here. Then, multi-layer back-end interconnection and passivation protection processes can be performed.

[0093] According to an embodiment of the present disclosure, the above preparation method further comprises: etching the intermediate dielectric layer from above to form a first opening exposing the source layer of the pull-down transistor in the second group of field effect transistors and a second opening exposing the source layer of the pass transistor in the first group of field effect transistors, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection plane of the first opening in the vertical direction, and the spacing space partially overlaps with the projection plane of the second opening in the vertical direction. Fill the conductive material in the first opening and the second opening, and close the first opening and the second opening. Thus, a contact hole 127_11 formed based on the first opening and a contact hole 127_12 formed based on the first opening can be obtained.

[0094] The intermediate dielectric layer in the spaced region between the first group of field effect transistors and the second group of field effect transistors is etched from below to form a third opening 132_1 exposing the conductive material in the first opening and a fourth opening 132_2 exposing the conductive material in the second opening. The third opening 132_1 and the fourth opening 132_2 are filled with conductive material, thereby forming a source layer contact hole in the intermediate dielectric layer that is connected to the source layer of the pull-down transistor PD2 in the second group of field effect transistors, so as to electrically connect the pull-down transistor PD2 in the second group of field effect transistors to the ground terminal, and forming a source layer contact hole in the intermediate dielectric layer that is connected to the source layer of the pass transistor AC1 in the first group of field effect transistors, so as to electrically connect the pass transistor AC1 in the first group of field effect transistors to the bit line terminal. The source layer contact hole in the first group of field effect transistors that is connected to the source layer of the pull-up transistor PU1 in the first group of field effect transistors and the like can be prepared based on the same method, which will not be described here.

[0095] Figure 52B is a cross-sectional view along the X-X' axis in the process of preparing the mislayered unit. Figure 53A is a cross-sectional view along the Y4-Y4' axis in the process of preparing the mislayered unit.

[0096] Figure 53B is a cross-sectional view along the X-X' axis in the process of preparing the mislayered unit. Figure 53C is a cross-sectional view along the Y1-Y1' axis in the process of preparing the mislayered unit. Figure 53D is a cross-sectional view along the Y2-Y2' axis in the process of preparing the mislayered unit. Figure 54 is a cross-sectional view along the Y3-Y3' axis in the process of preparing the mislayered unit. Figure 53D is a cross-sectional view along the Y3-Y3' axis of the three-dimensional stacked structure in some embodiments that does not involve the first mislayered contact hole QB. By comparing Figure 54 and Figure 53C It can be clear that the mislayered unit of the present disclosure involving the first mislayered contact hole QB is structurally different from the three-dimensional stacked structure that does not involve the first mislayered contact hole QB.

[0097] According to an embodiment of the present disclosure, the pull-up transistor PD2 in the second group of field effect transistors is electrically connected to the transmission transistor AC2 through the first common layer, and the pull-down transistor in the second group of field effect transistors is electrically connected to the transmission transistor through the first common layer and the second common layer. The first staggered layer contact hole QB and the second staggered layer contact hole Q are formed in the intermediate dielectric layer to obtain a staggered layer unit, including: etching the intermediate dielectric layer from above to form a fifth opening that simultaneously exposes the first common layer, the second common layer, and the gate stack of the pull-down transistor in the second group of field effect transistors. Fill the conductive material that contacts the first common layer, the second common layer, and the gate stack of the pull-down transistor in the second group of field effect transistors in the fifth opening, and close the fifth opening, thereby forming the second staggered layer contact hole Q.

[0098] According to an embodiment of the present disclosure, the pull-up transistor in the first group of field effect transistors is electrically connected to the transmission transistor through the third common layer, and the pull-down transistor in the first group of field effect transistors is electrically connected to the transmission transistor through the third common layer and the fourth common layer. The above preparation method further comprises: etching the intermediate dielectric layer from above along the surface of the intermediate dielectric layer to form a sixth opening that exposes the third common layer and the fourth common layer, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection plane of the sixth opening in the vertical direction; fill the conductive material in the sixth opening, and close the sixth opening;

[0099] The first staggered layer contact hole and the second staggered layer contact hole are formed in the intermediate dielectric layer to obtain a staggered layer unit, and further comprising: etching the intermediate dielectric layer from below along the surface of the intermediate dielectric layer to form a seventh opening that simultaneously exposes at least one of the third common layer and the fourth common layer and the gate stack of the pull-down transistor in the second group of field effect transistors. Fill the conductive material in the seventh opening, and close the seventh opening, thereby forming the first staggered layer contact hole QB. On this basis, referring to Figure 53C It can be seen that the conductive material on the left side in Figure 53C corresponds to the gate structure of the transmission transistor AC1 in the first group of field effect transistors, which is electrically connected to the word line. In Figure 53C the conductive material on the right side corresponds to the gate structure of the pull-down transistor in the second group of field effect transistors, which is connected to the second staggered layer contact hole Q. And the conductive material filled into the opening 134 is a contact hole electrically connected to the first bit line end, the conductive material filled into the opening 133_1 is a contact hole electrically connected to the ground end, and the conductive material filled into the opening 133_2 is a contact hole electrically connected to the second bit line end complementary to the first bit line end. And in ​ the left conductive layer 126 is led out from the back of the device, thereby being electrically connected to the word line end WL at the back of the device.

[0100] Based on this, the second mislayered contact hole Q is arranged to be connected with the gate stack of the pull-up transistor in the second group of field effect transistors, and extends to the common layer of the first group of field effect transistors in the intermediate dielectric layer, and the first mislayered contact hole QB is arranged to be connected with the gate stack of the pull-up transistor in the first group of field effect transistors, and extends to the lower surface of the substrate SUB in the intermediate dielectric layer and is connected with the common layer of the second group of field effect transistors through the substrate SUB, thereby realizing the local interconnection between the common layer of the second group of field effect transistors and the gate stack of the pull-up transistor in the first group of field effect transistors through the back gate contact. In this way, the first mislayered contact hole QB and the second mislayered contact hole Q opposite to the first mislayered contact hole QB form a mislayered structure of upper and lower hierarchical symmetry in physical space, greatly reducing the area of the integrated circuit realized based on the mislayered unit in the horizontal plane, and reducing the preparation difficulty and the simple process. Based on this, based on the mislayered unit in the present disclosure, the SRAM cell structure of the back QB and the front Q storage bit not limited to the same vertical plane can be realized. Moreover, based on the mislayered unit in the present disclosure, the same SRAM cell structure of the back Q and the front QB storage bit can also be realized.

[0101] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A staggered unit, comprising: A first group of field-effect transistors and a second group of field-effect transistors are respectively arranged along a first horizontal direction on the upper surface of the substrate; as well as An intermediate dielectric layer surrounding the substrate, the first group of field-effect transistors, and the second group of field-effect transistors; The first group of field-effect transistors and the second group of field-effect transistors each include a transmission transistor and stacked pull-up transistors, wherein the stacked pull-up transistors include pull-down transistors and pull-up transistors stacked in a vertical direction. Each of the transmission transistor, the pull-down transistor, and the pull-up transistor includes: a channel layer; source / drain layers adjoining the channel layer on both sides of the channel layer in the first horizontal direction; a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; and pull-down transistors, pull-up transistors, and transmission transistors belonging to the same group being coupled via a common layer. A first staggered contact hole, which is connected to the gate stack of the pull-out transistors in the first group of field-effect transistors, extends in the intervening dielectric layer to the lower surface of the substrate and passes through the substrate to connect with the common layer of the second group of field-effect transistors. This forms a staggered structure with the second staggered contact hole, which is used to connect the gate stack of the pull-out transistors in the second group of field-effect transistors and the common layer of the first group of field-effect transistors, such that the first group of field-effect transistors and the second group of field-effect transistors are cross-coupled to each other.

2. The staggered-level unit according to claim 1, wherein, The first group of field-effect transistors and the second group of field-effect transistors are arranged along the second horizontal direction and are spaced apart from each other; The first staggered contact hole extends from the gate stack of the pull-out transistors in the first group of field-effect transistors toward the spacer to the lower surface of the substrate, and passes through the interior of the substrate to connect with the common layer in the second group of field-effect transistors; as well as The second staggered contact hole extends from the gate stack of the pull-out transistors in the second group of field-effect transistors toward the spacing space and connects to the common layer in the first group of field-effect transistors above the substrate.

3. The staggered-level unit according to claim 2, wherein, A source layer contact hole, which is connected to the upper surface of the source layer of the transmission transistor in the first group of field-effect transistors, extends downward within the space to the surface of the intervening dielectric layer, so as to facilitate electrical connection between the transmission transistor in the first group of field-effect transistors and the bit line terminal.

4. The staggered-level unit according to claim 2, wherein, A source layer contact hole, which is connected to the lower surface of the source layer of the pull-up transistor in the second group of field-effect transistors, extends downward from the upper surface of the substrate through the substrate to the surface of the intermediate dielectric layer, thereby making the pull-up transistor in the second group of field-effect transistors electrically connected to the power supply terminal. The source layer contact hole, which is connected to the upper surface of the source layer of the pull-down transistor in the second group of field-effect transistors, extends downward within the space to the surface of the intervening dielectric layer, thereby electrically connecting the pull-down transistor in the second group of field-effect transistors to the ground terminal.

5. A method for preparing a staggered unit, comprising: A first group of field-effect transistors and a second group of field-effect transistors are formed on the upper surface of a substrate, spaced apart from each other and arranged along a first horizontal direction; wherein the first group of field-effect transistors and the second group of field-effect transistors each include a transmission transistor and a stacked pull-up transistor, the stacked pull-up transistors including a pull-down transistor and a pull-up transistor stacked along a vertical direction; each of the transmission transistor, the pull-down transistor and the pull-up transistor includes: a channel layer, a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction, and a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the pull-down transistor, the pull-up transistor and the transmission transistor belonging to the same group are coupled through a common layer; An intermediate dielectric layer is formed surrounding the first group of field-effect transistors, the second group of field-effect transistors, and the substrate; A first staggered contact hole and a second staggered contact hole are formed in the intervening dielectric layer to obtain a staggered unit; wherein, the second staggered contact hole is connected to the gate stack of the pull-out transistors in the second group of field-effect transistors, and is simultaneously connected to the common layer of the first group of field-effect transistors; the first staggered contact hole is connected to the gate stack of the pull-out transistors in the first group of field-effect transistors, and simultaneously extends in the intervening dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field-effect transistors, thereby forming a staggered structure with the second staggered contact hole, such that the first group of field-effect transistors and the second group of field-effect transistors are cross-coupled with each other.

6. The method according to claim 5, wherein, The intermediate dielectric layer encapsulates the first group of field-effect transistors and the second group of field-effect transistors; The method further includes: The intermediate dielectric layer is etched from above to form a first opening that exposes the source layer of the pull-down transistor in the second group of field-effect transistors and a second opening that exposes the source layer of the transport transistor in the first group of field-effect transistors. The spacing between the first group of field-effect transistors and the second group of field-effect transistors partially overlaps with the projection surface of the first opening in the vertical direction, and the spacing also partially overlaps with the projection surface of the second opening in the vertical direction. The first opening and the second opening are filled with conductive material, and the first opening and the second opening are then sealed. The intermediate dielectric layer located in the spacer region between the first group of field-effect transistors and the second group of field-effect transistors is etched from below to form a third opening that exposes the conductive material in the first opening and a fourth opening that exposes the conductive material in the second opening. Conductive material is filled into the third and fourth openings to form a source layer contact hole in the intervening dielectric layer that connects to the source layer of the pull-down transistor in the second group of field-effect transistors, so that the pull-down transistor in the second group of field-effect transistors is electrically connected to the ground terminal, and a source layer contact hole is formed in the intervening dielectric layer that connects to the source layer of the transmission transistor in the first group of field-effect transistors, so that the transmission transistor in the first group of field-effect transistors is electrically connected to the bit line terminal.

7. The method according to claim 5, wherein, In the second group of field-effect transistors, the pull-up transistor and the transmission transistor are electrically connected through the first common layer, and the pull-down transistor and the transmission transistor are electrically connected through the first common layer and the second common layer. The process of forming a first staggered contact hole and a second staggered contact hole within the intervening medium layer to obtain a staggered unit includes: The intermediate dielectric layer is etched from above to form a fifth opening that simultaneously exposes the gate stack of the first common layer, the second common layer, and the pull-out transistors in the second group of field-effect transistors; The fifth opening is filled with conductive material that is in contact with the gate stack of the first common layer, the second common layer and the second group of field-effect transistors, and the fifth opening is closed to form the second staggered contact hole.

8. The method according to claim 7, wherein, The pull-up transistor and the transmission transistor in the first group of field-effect transistors are electrically connected through a third common layer, and the pull-down transistor and the transmission transistor in the first group of field-effect transistors are electrically connected through the third common layer and the fourth common layer. The method further includes: The intermediate dielectric layer is etched from above along its surface to form a sixth opening that exposes the third common layer and the fourth common layer, wherein the spacing between the first group of field-effect transistors and the second group of field-effect transistors partially overlaps with the vertical projection surface of the sixth opening. The sixth opening is filled with conductive material and then sealed. The process of forming a first staggered contact hole and a second staggered contact hole in the intercalary medium layer to obtain a staggered unit further includes: The intermediate dielectric layer is etched from below along its surface to form a seventh opening that simultaneously exposes at least one of the third and fourth common layers and the gate stack of the pull-out transistors in the second group of field-effect transistors; The seventh opening is filled with conductive material and then sealed to form the first staggered contact hole.

9. The method according to claim 5, wherein, The method further includes: According to the source layer position of the pull-up transistor in the second group of field-effect transistors, the substrate and the intervening dielectric layer are etched from below to form a source layer contact hole that passes through the substrate and the intervening dielectric layer and connects to the lower surface of the source layer of the pull-up transistor in the second group of field-effect transistors, so as to facilitate the electrical connection of the pull-up transistor in the second group of field-effect transistors to the power supply terminal.

10. The method according to claim 5, wherein, The first group of field-effect transistors and the second group of field-effect transistors each include a lower fin formed by etching the substrate; The remaining portion of the substrate after etching is connected between the lower fins of the first group of field-effect transistors and the second group of field-effect transistors; The formation of the intervening dielectric layer surrounding the first group of field-effect transistors, the second group of field-effect transistors, and the substrate includes: The substrate is etched from below until the lower surfaces of the lower fins of the first group of field-effect transistors and the second group of field-effect transistors are exposed; A dielectric material is deposited on the lower surface of the lower fins of the first group of field-effect transistors and the second group of field-effect transistors to obtain the intermediary dielectric layer.

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