Semiconductor device and method

Abstract

Device comprising: a fin (52) protruding from a semiconductor substrate; a gate stack over and along a side wall of the fin (52); a gate spacer (85) along a side wall of the gate stack and along the side wall of the fin (52); an epitaxial source / drain region (82) in the fin (52) and adjacent to the gate spacer (85); and a corner spacer (94) between the gate stack and the gate spacer (85), wherein the corner spacer (94) extends along the side wall of the fin (52), wherein a first area between the gate stack and the side wall of the fin (52) is free of the corner spacer (94), and wherein a second area between the gate stack and the gate spacer (85) is free of the corner spacer (94); and a dielectric dummy gate layer extending along the side wall of the fin (52), wherein the dielectric dummy gate layer is located between the corner spacer (94) and the fin (52).

Description

BACKGROUND

[0001] Semiconductor devices (components) are used in a wide variety of electronic applications, such as PCs, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers over a semiconductor substrate, and structuring the various layers using lithography to form circuit components and elements.

[0002] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area.

[0003] The prior art relevant to the invention is given by US 2014 / 0239393 A1, US 2015 / 0084102 A1 and US 2017 / 0084714 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should also be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1 illustrates a three-dimensional view of an example of a FinFET according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Fig. Figure 7 shows cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B and Fig. 13C are different views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 14A, Fig. 14B and Fig. 14C are different views of an intermediate stage in the deposition of a dielectric layer in the fabrication of FinFETs according to some embodiments. Fig. 15A, Fig. 15B and Fig. Figure 15C shows cross-sectional views of an intermediate stage in the deposition of a dielectric layer during the fabrication of FinFETs according to some embodiments. Fig. 16A, Fig. 16B and Fig. 16C are different views of an intermediate stage in the formation of corner spacers in the fabrication of a FinFET according to some embodiments. Fig. 17A, Fig. 17B, Fig. 17C and Fig. Figure 17D shows cross-sectional views of an intermediate stage in the deposition of a dielectric layer during the fabrication of FinFETs according to some embodiments. Fig. 18A, Fig. 18B, Fig. 18C, Fig. 18D, Fig. 19A, Fig. 19B, Fig. 20A and Fig. 20B are different views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B and Fig. 24C are different views of intermediate stages in the fabrication of FinFETs with corner spacers according to some embodiments. DETAILED DESCRIPTION

[0005] The invention is defined by the subject matter of the independent claims. Particular embodiments are given by the additional features of the dependent claims. The following disclosure.

[0006] The following disclosure provides many different embodiments or exemplary embodiments for implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various discussed embodiments and / or configurations.

[0007] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the device in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0008] Several embodiments describe processes for forming spacers that separate the corners of a dummy gate stack in a FinFET device from adjacent epitaxial source / drain regions. In some embodiments, after removal of the dummy gate stack, a dielectric layer is deposited in the well formed at the former location of the dummy gate stack. The dielectric layer is then etched such that portions of the dielectric layer remain in the corner regions of the well. These remaining portions of the dielectric layer form "corner spacers" that prevent the dummy gate stack from forming in the corner regions of the well. The corner spacers are located between the dummy gate stack and the epitaxial source / drain regions, thus increasing the separation distance between the dummy gate stack and the epitaxial source / drain regions.This increased separation distance between the replacement gate stack and the epitaxial source / drain regions can reduce parasitic capacitance and / or leakage current between the replacement gate stack and the epitaxial source / drain regions, and can therefore improve the speed, performance, reliability and / or yield of a FinFET device.

[0009] Fig. Figure 1 illustrates a three-dimensional view of an example of a FinFET according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulation regions 56 are arranged in the substrate 50, and the fin 52 extends above and between adjacent insulation regions 56. Although the insulation regions 56 are described / illustrated as separate from the substrate 50, the term "substrate," as used here, can refer to a semiconductor substrate alone or to a semiconductor substrate with insulation regions. Furthermore, although the fin 52 is illustrated as a single material continuous with the substrate 50, the fin 52 and / or the substrate 50 can comprise a single material or multiple materials. In this context, the fin 52 refers to the portion extending between the adjacent insulation regions 56.

[0010] A dielectric gate layer 96 is located along side walls and over an upper surface of the fin 52, and a gate electrode 98 is located above the dielectric gate layer 96. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the dielectric gate layer 96 and the gate electrode 98. Fig. Figure 1 further illustrates reference section planes used in subsequent figures. Section plane AA runs along a longitudinal axis of the gate electrode 98 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Section plane BB is perpendicular to section plane AA and runs along a longitudinal axis of the fin 52 and in a direction of, for example, current flow between the source / drain regions 82 of the FinFET. Section plane DD is parallel to section plane AA and passes through a source / drain region 82 of the FinFET. Section plane EE is parallel to section plane BB and passes through the gate electrode 98 of the FinFET. For clarity, subsequent figures refer to these reference section planes.

[0011] Some of the embodiments discussed herein are related to FinFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, nanostructured (e.g., nanofilm, nanowire, gate-all-around, or the like) field-effect transistors (NSFETs), or similar devices.

[0012] Fig. Figures 2 to 20B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. Figure 7 illustrates the reference section plane AA, which, apart from multiple fins / FinFETs, is in Fig. 1 is illustrated. Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 16A, Fig. 18A, Fig. 19A and Fig. 20A are along the in Fig. The reference section plane AA shown in section 1 illustrates this, and Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 16B, Fig. 18B, Fig. 18D, Fig. 19B and Fig. 20B are illustrated along a similar section plane BB, which, apart from multiple fins / FinFETs, are in Fig. 1 is illustrated. Fig. 8C, Fig. 9C, Fig. 10C, Fig. 13C, Fig. 14C, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D and Fig. 18C are shown as top views in the in Fig. 8A and Fig. Section plane CC is illustrated in Figure 8B. Section plane CC is a cross-section through the channel region 58 and the epitaxial source / drain regions 82 (see Figure 8B). Fig. 10A-E) of a fin 52 and is parallel to a main surface of the substrate 50. Fig. 10D and Fig. 10E are illustrated in the reference section plane DD, which, apart from multiple fins / FinFETs, are in Fig. 1 is illustrated. Fig. 15A, Fig. 15B and Fig. 15C are in the in Fig. 1 and Fig. 14C illustrates the reference section plane EE.

[0013] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0014] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. The p-region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-region 50N can be physically separated from the p-region 50P (as illustrated by the divider 51), and any number of device features (e.g., other active components, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P.

[0015] In Fig. 3. Fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching grooves into it. The etching can be any acceptable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or combinations thereof. The etching can be anisotropic.

[0016] The fins can be structured by any suitable method. For example, the fins 52 can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the fabrication of structures with smaller dimensions than, for example, achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed adjacent to the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins.In some embodiments, the mask (or other layer) can remain on the fins 52.

[0017] In Fig. In the embodiment 4, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert to another material such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. After the insulating material has been formed, an annealing process may be performed.In one embodiment, the insulating material 54 is configured such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a lining (not shown) can first be formed along a surface of the substrate 50 and the fins 52. A filler material, for example, those discussed above, can then be formed over the lining.

[0018] In Fig. 5. A removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fins 52. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like may be used. The planarization process exposes the fins 52 such that the upper surfaces of the fins 52 and the insulating material 54 are flat after completion of the planarization process. In embodiments in which a mask remains on the fins 52, the planarization process may expose or remove the mask such that the upper surfaces of the mask or of the fins 52 and the insulating material 54 are flat after completion of the planarization process.

[0019] In Fig. 6. The insulating material 54 is recessed to form trench insulation areas (shallow trench insulation or STI areas) 56. The insulating material 54 is recessed such that upper sections of the fins 52 protrude between adjacent STI areas 56 in the n-area 50N and the p-area 50P. Furthermore, the upper surfaces of the STI areas 56 can have a flat surface as illustrated, a convex surface, a concave surface (e.g., by dishing), or a combination thereof. The upper surfaces of the STI areas 56 can be made flat, convex, and / or concave by appropriate etching. The STI areas 56 can be deepened using an acceptable etching process, for example an etching process that is selective with respect to the insulating material 54 (i.e., that etches the insulating material 54 at a faster rate than the fin material 52).For example, oxide removal can be used, which employs diluted hydrofluoric acid (dHF).

[0020] The one with reference to Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. The process described in Section 6 merely represents an example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over an upper surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer, forming fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins 52. For example, the fins 52 can be formed in Fig. The fins 52 are recessed, and a material different from the fins 52 can be epitaxially grown over them. In such embodiments, the fins 52 comprise the recessed material as well as the epitaxially grown material arranged over it. In a further embodiment, a dielectric layer can be formed over an upper surface of the substrate 50, and grooves can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the grooves using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 52.In some embodiments where homoepitactic or heteroepitactic structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby avoiding prior and subsequent implantations; however, in-situ and implantation doping can also be used together.

[0021] Furthermore, it can be advantageous to epitaxially grow a different material in the n-region 50N (e.g., an NMOS region) than the material in the p-region 50P (e.g., a PMOS region). In various embodiments, upper sections of the fins 52 can be made of silicon germanium (Si₂). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The available materials for forming III-V compound semiconductors include, but are not limited to, for example, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0022] Furthermore, in Fig. Six suitable troughs (not shown) are formed in the fins 52 and / or the substrate 50. In some embodiments, a p-trough can be formed in the n-region 50N and an n-trough can be formed in the p-region 50P. In some embodiments, a p-trough or an n-trough is formed in both the n-region 50N and the p-region 50P.

[0023] In embodiments with different trough types, the different implantation steps for the n-region 50N and the p-region 50P can be implemented using a photoresist and / or other masks (not shown). For example, a photoresist can be formed over the fins 52 and the STI regions 56 in the n-region 50N. The photoresist is patterned to expose the p-region 50P of the substrate 50. The photoresist can be formed using a spin-coating technique and patterned using acceptable photolithography techniques. After the photoresist has been patterned, n-foreign substance implantation is performed in the p-region 50P, and the photoresist can serve as a mask that essentially prevents n-foreign substances from being implanted into the n-region 50N. The n-foreign substances can be phosphorus, arsenic, antimony, or the like, at a concentration of less than or equal to 1018 cm -3 , such as between approximately 10 16 cm -3 and approximately 10 18 cm -3 The photoresist is implanted into the area. After implantation, it is removed, for example by a suitable ashing process.

[0024] Following the implantation of the p-region 50P, a photoresist is formed over the fins 52 and the STI regions 56 within the p-region 50P. The photoresist is patterned to expose the n-region 50N of the substrate 50. The photoresist can be formed using a spin-coating technique and patterned using acceptable photolithography techniques. After the photoresist has been patterned, p-foreign material implantation can be performed in the n-region 50N, and the photoresist can serve as a mask, essentially preventing p-foreign materials from being implanted into the p-region 50P. The p-foreign materials can be boron, boron fluoride, indium, or the like, with a concentration of less than or equal to 10 18 cm -3 , such as between approximately 10 16 cm -3 and approximately 10 18 cm -3The photoresist is implanted into the area. After implantation, it can be removed, for example, by a suitable ashing process.

[0025] Following the implantation of the n-region 50N and the p-region 50P, a annealing step can be performed to repair implantation damage and activate the implanted p- and / or n-substances. In some embodiments, the grown materials of epitaxial fins can be doped in situ during growth, thus avoiding the need for implantation; however, in-situ and implantation doping can also be used together.

[0026] In Fig. A dielectric dummy layer 60 is formed on the fins 52. The dielectric dummy layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed over the dielectric dummy layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dielectric dummy layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be made of a conductive or a non-conductive material and can be selected from the group which includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials that exhibit high etch selectivity for etching insulating regions, such as the STI regions 56 and / or the dielectric dummy layer 60. The mask layer 64 can comprise one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the n region 50N and the p region 50P. It should be noted that the dielectric dummy layer 60 is shown, for illustrative purposes only, to cover only the fins 52.In some embodiments, the dielectric dummy layer 60 can be deposited such that the dielectric dummy layer 60 covers the STI regions 56 and extends over the STI regions and between the dielectric dummy layer 62 and the STI regions 56.

[0027] Fig. Figures 8A to 20B illustrate various additional steps in the manufacture of embodiment devices. Fig. Figures 8A to 20B illustrate features either in the n-domain (50N) or the p-domain (50P). For example, the features in Fig. The structures illustrated in Figures 8A to 20B are applicable to both the n-domain 50N and the p-domain 50P. Differences between the structures of the n-domain 50N and those of the p-domain 50P are described (where applicable) in the text accompanying each figure. Fig. 8C, Fig. 9C, Fig. 10C, Fig. 13C, Fig. 14C, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D and Fig. 18C are shown as top views through the structure in the Fig. 8A and Fig. Figure 8B illustrates the sectioning plane CC. It should be noted that the sectioning plane shown in Figure 8B illustrates the sectioning plane CC. Fig. 8A and Fig. The section plane CC shown in 8B lies below the upper surface of the channel areas 58 of the fins 52.

[0028] In Fig. 8A, Fig. 8B and Fig. 8C can be used for mask layer 64 (see Fig. 7) can be structured using acceptable photolithography and etching techniques to form masks 74. The structure of the masks 74 can then be transferred to the dummy gate layer 62. In some embodiments (not illustrated), the structure of the masks 74 can also be transferred to the dielectric dummy layer 60 by an acceptable etching technique to form dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The structure of the masks 74 can be used to physically separate the individual dummy gates 72 from adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding epitaxial fins 52.

[0029] Also in Fig. 8A-C: Gate sealing spacers 80 can be formed on exposed surfaces of the dummy gates 72, the masks 74, and / or the fins 52. The gate sealing spacers 80 can be formed by thermal oxidation or by deposition followed by anisotropic etching. The gate sealing spacers 80 can be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0030] With reference to Fig. In some embodiments, the masks 74 or the dummy gates 72 near the fins 52 may have a flared profile. In some cases, the flared profile may be due to topography or loading that affects the lithography and / or etching steps forming the masks 74 or the dummy gates 72. For example, in some cases, a dummy gate 72 with an aspect ratio (height:width) of approximately 4:1 or greater is more likely to form with a flared profile near the fins 52. The dummy gates 72 may have a flared profile such that they have a width W2 near the fins 52 that is greater than a width W1 far from the fins 52. In some embodiments, regions of the dummy gates 72 far from the fins 52 may have a width W1 that is between approximately 10 nm and approximately 30 nm.In some embodiments, areas of the dummy gates 72 near the fins 52 can have a width W2 ranging from approximately 11 nm to approximately 40 nm. The width W2 can be greater than the width W1 by a width W3 ranging from approximately 1 nm to approximately 10 nm. In some embodiments, the width W3 can be in the range of approximately 10% to approximately 30% of the width W1. Other widths are possible, and the areas of the dummy gates 72 with expanded profiles can have a different shape or size than that shown. In some embodiments, the photolithography or etching steps are controlled to produce a desired expanded profile of the dummy gates 72 near the fins 52, for example, by appropriately selecting the aspect ratio of the dummy gates 72. In some embodiments, sections of the dummy gates 72 formed on the upper surfaces of the fins 52 (e.g., as in Figure 1) have a wide profile. Fig. (8B shown) no widened profile near the fins 52. In this way, a dummy gate 72 can be formed which has a widened profile near the side walls of a fin 52 and not near an upper surface of the fin 52. The sections of the dummy gates 72 formed on the upper surfaces of the fins 52 can have a width approximately equal to width W1 or width W2, or a different width, approximately a width between widths W1 and W2, or a completely different width.

[0031] After the formation of the gate sealing spacers 80, implantations for weakly doped source / drain regions (LDD regions) (not explicitly illustrated) can be performed. In the embodiments with different component types, similar to the above with reference to Fig. Following the implantation procedure discussed in section 6, a mask, such as a photoresist, can be formed over the n-region 50N, exposing the p-region 50P, and foreign materials of an appropriate type (e.g., p-foreign substances) can be implanted into the exposed fins 52 in the p-region 50P. The mask can then be removed. The n-foreign substances can be any of the previously discussed n-foreign substances, and the p-foreign substances can be any of the previously discussed p-foreign substances. The concentration of foreign matter in the lightly doped source / drain regions can range between 10 15 cm -3 and 10 19 cm -3A tempering step can be used to repair implant damage and activate the implanted foreign materials.

[0032] In Fig. 9A, Fig. 9B and Fig. 9C Gate spacers 86 are formed on the gate sealing spacers 80 along side walls of the dummy gates 72 and the masks 74. The gate spacers 86 can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. The gate spacers 86 can be formed from a single layer of insulating material or from multiple layers of different insulating materials. The gate sealing spacers 80 and the gate spacers 86 can be collectively referred to as spacers 85. With reference to Fig. 9C can, in some embodiments, increase the thickness S1 of the spacers 85 in areas far from the fins 52 to approximately 15×10 -10 m and approximately 1100 × 10 -10m lie. In some embodiments, the thickness S2 of the spacers 85 in areas near the fins 52 is approximately 5×10 -10 m and approximately 1000×10 -10 m , which is approximately 10×10 -10 m to approximately 100×10 -10 m can be smaller than S1. In some embodiments, the ratio of the thicknesses S2:S1 is between approximately 1:1.1 and approximately 1:1.5. Other thicknesses or relative thicknesses are possible.

[0033] It should be noted that the preceding disclosure describes a general process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, or a different sequence of steps may be employed (e.g., the gate sealing spacers 80 may not be etched before the formation of the gate sealing spacers 86, resulting in "L-shaped" gate sealing spacers; spacers may be formed and removed; and / or the like). Furthermore, the n-type and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed before the formation of the gate sealing spacers 80, while LDD regions for p-type devices may be formed after the formation of the gate sealing spacers 80.

[0034] In Fig. 10A, Fig. 10B and Fig. In 10C, epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is arranged between respective adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 can extend into and penetrate the fins 52. In some embodiments, the gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance, so that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gates of the resulting FinFETs. In some embodiments, the epitaxial source / drain regions 82 can extend below the gate spacers 86, as shown in Fig. Figure 10B-C shows that a material for the epitaxial source / drain regions 82 can be selected such that a mechanical stress is exerted in the corresponding channel regions 58, thereby improving performance.

[0035] The epitaxial source / drain regions 82 in the n-region 50N can be formed by masking the p-region 50P and etching the source / drain regions of the fins 52 in the n-region 50N to create depressions in the fins 52. The epitaxial source / drain regions 82 in the n-region 50N are then epitaxially grown in the depressions. The epitaxial source / drain regions 82 can comprise any acceptable material, such as one suitable for n-FinFETs. For example, if the fin 52 is made of silicon, the epitaxial source / drain regions 82 in the n-region 50N can comprise materials that exert tensile stress in the channel region 58, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 82 in the n-region 50N may have surfaces raised from the respective surfaces of the fins 52 and may have facets.

[0036] The epitaxial source / drain regions 82 in the p-region 50P can be formed by masking the n-region 50N and etching the source / drain regions of the fins 52 in the p-region 50P to create depressions in the fins 52. The epitaxial source / drain regions 82 in the p-region 50P are then epitaxially grown in these depressions. The epitaxial source / drain regions 82 can comprise any acceptable material, such as one suitable for p-FinFETs. For example, if the fin 52 is made of silicon, the epitaxial source / drain regions 82 in the p-region 50P can comprise materials that exert a pressure load in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain regions 82 in the p-region 50P may have surfaces raised from the respective surfaces of the fins 52 and may have facets.

[0037] The epitaxial source / drain regions 82 and / or the fins 52 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by an annealing step. The source / drain regions can contain a foreign substance concentration of approximately 10 19 cm -3 and approximately 10 21 cm -3 exhibit. The n- and / or p-substances for source / drain regions can be any of the previously discussed substances. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0038] Fig. 10D and Fig. Figure 10E illustrates cross-sections of a FinFET in the reference section plane DD. As a result of the epitaxial processes used to form the epitaxial source / drain regions 82 in the n-region 50N and the p-region 50P, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward across the side walls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as shown by Fig. Figure 10D illustrates this. In other embodiments, adjacent source / drain regions 82 remain separated after completion of the epitaxy process, as shown by Fig. 10D is illustrated. In the Fig. 10C and Fig. In the embodiments illustrated in Figure 10D, gate spacers 86 are formed that cover a section of the sidewalls of the fins 52 and extend over the STI areas 56, thereby inhibiting epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacers 86 can be modified to remove the spacer material, allowing the epitaxially grown area to extend to the surface of the STI area 56.

[0039] In Fig. 11A and Fig. 11B will be a first interlayer dielectric (ILD) 88 above the in Fig. 10A and Fig. The structure illustrated in Figure 10B is deposited. The first ILD 88 can be formed from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is arranged between the first ILD 88 and the epitaxial source / drain regions 82, the masks 74, and the gate spacers 86. The CESL 87 can comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a lower etch rate than the material of the overlying first ILD 88.

[0040] In Fig. 12A and Fig. 12B A planarization process, such as CMP, can be performed to ensure that the top surface of the first ILD 88 is in the same plane as the top surfaces of the dummy gates 72 or the masks 74. The planarization process can also remove the masks 74 on the dummy gates 72 and can remove sections of the gate sealing spacers 80 and the gate spacers 86 along the side walls of the masks 74. After the planarization process, the top surfaces of the dummy gates 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 can be flat. Accordingly, the top surfaces of the dummy gates 72 are exposed by the first ILD 88. In some embodiments, the masks 74 can remain, in which case the planarization process causes the upper surface of the first ILD 88 to lie in the same plane as the upper surfaces of the masks 74.

[0041] In Fig. 13A, Fig. 13B and Fig. 13C the dummy gates 72 and the masks 74 (if present) are removed in one etching step (or several etching steps) such that recesses 90 are formed. Fig. Figures 13A-B illustrate cross-sectional views in the reference section plane AA and BB, respectively. Fig. 13C shows a top view of the in Fig. The reference section plane CC shown in Figure 13A-B shows a section through the channel region 58 and the epitaxial source / drain regions 82. In some embodiments, the dummy gates 72 are removed, leaving the dielectric dummy layer 60 exposed by the recesses 90. In some embodiments, the recess 90 is laterally bounded by the dielectric dummy layer 60 and the spacers 85. Each recess 90 lies above a channel region 58 of a respective fin 52, which is arranged between adjacent pairs of the epitaxial source / drain regions 82. During removal, the dielectric dummy layer 60 can be used as an etch stop layer when etching the dummy gates 72.

[0042] In some embodiments, the widened profile of the dummy gates 72 near the fins 52 results in the recesses 90 having a widened profile near the fins 52, as shown in Fig. Figure 13C illustrates this. For example, areas of the recesses 90 near the fins 52 may have a width W5 that is greater than the width W4 of areas of the recesses 90 far from the fins 52. In some embodiments, areas of the recesses 90 that are far from the fins 52 may have a width W4 that is approximately the same as the width W1 (see Figure 13C). Fig. 8C). In some embodiments, areas of the recesses 90 that are near the fins 52 may have a width W5 of approximately 100×10 -10 m and approximately 300×10 -10 m lies, which is approximately 1×10 -10 m to approximately 1200×10 -10m larger than the width W3. In this way, the depressions 90 can have corner regions 91 adjacent to the fins 52, which project laterally compared to regions of the depressions 90 that are farther from the fins 52. The depressions 90 can extend closer to the epitaxial source / drain regions 82 than regions of the depressions 90 that are farther from the fins 52. Exemplary corner regions 91 are shown in Fig. 13C is indicated.

[0043] In some embodiments, the corner regions 91 can be spaced by a distance D1, which is between approximately 0.5×10 -10 m and approximately 600×10 -10 m lies, along which fins 52 protrude and by a distance D2, which is between approximately 0.5×10 -10 m and approximately 600×10 -10 m lies, projecting perpendicularly to the fins 52. Other distances are possible. In other embodiments, the corner areas 91 can have a different shape or size than in Fig. 13C shows. For example, the side walls of the spacers 85 at the corner areas 91 can be straight, curved, concave, convex, irregular, etc.

[0044] In some embodiments, the dummy gates 72 are removed by an anisotropic dry etching process. The anisotropic dry etching process may involve the use of one (or more) reactive gases that selectively etch the dummy gates 72 without significantly etching the first ILD 88 or the gate spacers 86. In some embodiments, the anisotropic dry etching process involves generating a plasma with a power output between approximately 10 watts and approximately 1000 watts. The anisotropic dry etching process may be carried out at a pressure between approximately 5 mTorr and approximately 500 mTorr and a process temperature between approximately 40 °C and approximately 100 °C. The anisotropic dry etching process may have a bias power of between approximately 10 watts and approximately 800 watts. In some embodiments, one or more process gases such as HBr, Cl₂, H₂, N₂, O₂, C₂ may be used in the anisotropic dry etching process. x F y , CH x F yor the like, or combinations thereof, may be used. For example, in some embodiments, the anisotropic etching process includes flows of HBr at a flow rate between approximately 10 sccm and approximately 500 sccm, flows of Cl₂ at a flow rate between approximately 10 sccm and approximately 200 sccm, flows of He at a flow rate between approximately 50 sccm and approximately 1000 sccm, flows of CF₄ at a flow rate between approximately 1 sccm and approximately 50 sccm, flows of CH₂F₂ at a flow rate between approximately 5 sccm and approximately 20 sccm, and / or flows of O₂ at a flow rate between approximately 5 sccm and approximately 20 sccm. Other process gases or process conditions are possible.

[0045] In Fig. 14A, Fig. 14B and Fig. According to some embodiments, 14C deposits a dielectric layer 92 over the structure and within the recesses 90. The dielectric layer 92 can be deposited as a conformal layer extending over the STI areas 56, the ILD 88, the CESL 87, the gate sealing spacers 80, and the gate spacers 86. The dielectric layer 92 can extend along the sidewalls of the recesses 90 and over the dielectric dummy layer 60 within the recesses 90. Fig. Sections of the dielectric layer 92 deposited on side walls are referred to as dielectric layer 92, and sections deposited on upper surfaces (e.g., the side surfaces) are referred to as dielectric layer 92'. In some embodiments, the dielectric layer 92 is configured such that it has a thickness T1 on the upper surfaces of the dielectric dummy layer 60 within the recesses 90, which is between approximately 0.5 × 10 -10 m and approximately 300×10 -10 The dielectric layer 92 can have a thickness T2 on the side walls of the dielectric dummy layer 60, which is between approximately 0.5 × 10 -10 m and approximately 300×10 -10 m lies. In some embodiments, the dielectric layer 92 is applied to side walls of the gate spacers 85 with a thickness T3 of approximately 0.5 × 10 -10 m and approximately 300×10 -10m formed. The thicknesses T1, T2 and / or T3 can be similar or different thicknesses. As in Fig. As shown in Figure 14C, the dielectric layer 92 fills or partially fills the corner regions 91 of the recesses 90. Filling the corner regions 91 with the dielectric layer 92 enables the formation of corner spacers 94, which are described in more detail with reference to Fig. 16A-C. Accordingly, the amount of material deposited in the dielectric layer 92 can be based on the size of the corner regions 91. In some embodiments, the dielectric layer 92 fills the corner regions 91 laterally up to a thickness T4, measured from the corner of the corner regions 91. The thickness T4 can be between approximately 0.5 × 10 -10 m and approximately 600×10 -10 m lies and can be greater than, less than or approximately equal to the distance D1 (see Fig. 13C). Other thicknesses are possible.

[0046] The dielectric layer 92 can be formed with a substantially uniform thickness along a surface or with a varying thickness along a surface. For example, the dielectric layer 92 can be formed with a thickness profile on the sidewalls of the well 90 that is uniform or that varies, such that it is thickest near the top of the well 90 or thickest near the bottom of the well 90. Other thickness profiles are possible, such as forming a dielectric layer 92 with vertical surfaces, inclined surfaces, flat surfaces, curved surfaces, convex surfaces, concave surfaces, irregular surfaces, etc. In some embodiments, the thickness profile of the dielectric layer 92 is controlled by controlling parameters or properties of the deposition process. For example, a more conformal deposition process can produce a thickness profile that matches the one described in Fig. 15A is similar to the one shown (described in more detail below), or a less conformal deposition process can produce a thickness profile similar to that shown in Fig. 15B or Fig. 15C is similar (described in more detail below). In some embodiments, the thickness profile of the dielectric layer 92 can be controlled, for example, to ensure that the corner regions 91 are completely filled, or to prevent the formation of corner spacers 94 (see Fig. 16C) with the desired size, shape, or thickness profile. The formation of corner spacers 94 with a specific thickness profile is described below with reference to Fig. 16C discussed in more detail.

[0047] To illustrate with examples Fig. 15A, Fig. 15B and Fig. 15C dielectric layers 92 with different thickness profiles according to some embodiments. Fig. Figures 15A-C illustrate cross-sectional views along the in Fig. 1 and Fig. Reference section plane EE specified in 14C. Fig. Figure 15A shows a dielectric layer 92 with a substantially uniform thickness on the bottom and side walls of the depression 90, similar to that in Figure 15A. Fig. 14A-C shown dielectric layer 92. For example, the one in Fig. Figure 15A shows that the dielectric layer 92 has a substantially uniform thickness T1 on the dielectric dummy layer 60 and a substantially uniform thickness T3 on the sidewalls of the gate spacers 85. The thicknesses T1 and T3 can be similar or different.

[0048] Fig. Figure 15B illustrates a dielectric layer 92 with a thickness profile such that the dielectric layer 92 has a greater thickness near the bottom of the depression 90 and a smaller thickness near the top of the depression 90. For example, the dielectric layer 92 near the top of the depression 90 may have an upper thickness T3T that is less than a lower thickness T3B near the bottom of the depression 90. In some embodiments, the upper thickness T3T may be between approximately 5% and approximately 95% of the lower thickness T3B. In some embodiments, the dielectric layer 92 may have a thickness T1 on the dielectric dummy layer 60 that is greater than the upper thickness T3T and may be similar to the lower thickness T3B. Other relative thicknesses are possible.

[0049] Fig. Figure 15C illustrates a dielectric layer 92 with a thickness profile such that the dielectric layer 92 has a greater thickness near the top of the depression 90 and a smaller thickness near the bottom of the depression 90. For example, the dielectric layer 92 near the top of the depression 90 may have an upper thickness T3T that is greater than a lower thickness T3B near the bottom of the depression 90. In some embodiments, the lower thickness T3B may be between approximately 5% and approximately 95% of the upper thickness T3T. In some embodiments, the dielectric layer 92 may have a thickness T1 on the dielectric dummy layer 60 that is smaller than the upper thickness T3T and may be similar to the lower thickness T3B. Other relative thicknesses are possible.

[0050] The dielectric layer 92 can be a dielectric material, such as an oxide, a nitride, or the like. In some embodiments, the dielectric material is a silicon-based material, such as silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxynitride, silicon oxycarbonitride, or the like. Other dielectric materials are possible. In some embodiments, the dielectric layer 92 has multiple layers of different dielectric materials. In some embodiments, the dielectric layer 92 is made of a material that can be selectively etched relative to the materials of other features, such as the gate spacers 85 and the channel region 58. The dielectric layer 92 can be deposited using a suitable deposition process, such as CVD, PECVD, PVD, ALD, or the like, or combinations thereof.

[0051] In Fig. 16A, Fig. 16B and Fig. In some embodiments, an etching process is carried out to etch the dielectric layer 92 and form corner spacers 94. In some embodiments, the etching process removes the dielectric layer 92 from the bottom and sidewall surfaces of the recesses 90, but incompletely etches the dielectric layer 92 in and near the corner regions 91. The etching process may also remove the dielectric layer 92 from the top surfaces of the STI regions 56, the ILD 88, the CESL 87, the gate sealing spacers 80, and / or the gate spacers 86. In this way, after the etching process, sections of the dielectric layer 92 remain in the corner regions 91. In some cases, the narrow geometry of the corner regions 91 and / or the comparatively thicker dielectric layer 92 in the corner regions 91 may allow an etching rate of the dielectric layer 92 that is slower near the corner regions 91 than far away from the corner regions 91.In some embodiments, the etching process can be controlled to stop etching after removing sections of the dielectric layer 92 far from the corner regions 91, but before removing sections of the dielectric layer 92 near the corner regions 91. In this way, the dielectric layer 92 can be incompletely etched in the corner regions 91. The remaining sections of the dielectric layer 92 partially or completely fill the corner regions 91 and are referred to herein as corner spacers 94. In some embodiments, the etching process can also etch through the dielectric dummy layer 60 to expose the channel region 58, as shown in [reference]. Fig. 16A-C is shown.

[0052] As in Fig. As shown in Figure 16C, the corner spacers 94 cover sections of the spacers 85 and / or the dielectric dummy layer 60 near the corner regions 91. Each corner spacer 94 has a side wall 95 extending from a gate spacer 85 to the dielectric dummy layer 60. In some embodiments, the corner spacer 94 can extend along the fins 52 (e.g., along the dielectric dummy layer 60) by a distance T5, which is between approximately 0.5 × 10 -10 m and approximately 600×10 -10 m lies, and can be positioned perpendicular to the fins 52 (e.g. along the gate spacers 85) by a distance T6 of approximately 0.5×10 -10 m and approximately 600×10 -10 extend to m. In some embodiments, the distance T5 is greater than the distance D1 (see Fig. 13C) of the corner regions 91, but in other embodiments may be approximately equal to or less than the distance D1. The distance T6 may be greater than, approximately equal to, or less than the distance D2 (see Fig. 13C) of the corner regions 91. Other distances are possible. In some embodiments, the side wall 95 can have an angle A1 to the dielectric dummy layer 60 between approximately 10° and approximately 90°.

[0053] In some embodiments, the corner spacers 94 have a substantially uniform size (e.g., spacings T5, spacing T6, and / or cross-sectional area) or a substantially uniform shape in a vertical direction from near the top of the recess 90 to near the bottom of the recess 90. In other embodiments, the corner spacers 94 may have varying sizes, shapes, or cross-sectional areas in a vertical direction. For example, in some embodiments, a dielectric layer 92 may be deposited with a greater thickness near the bottom of the recess 90, as shown in Fig. As shown in Figure 15B, this allows the formation of corner spacers 94 that are larger near the top of the depression 90 than near the bottom of the depression 90. Similarly, the deposition of a dielectric layer 92 with a greater thickness near the bottom of the depression 90, as shown in Figure 15B, can also be achieved. Fig. As shown in Figure 15C, this allows the formation of corner spacers 94 that are larger near the bottom of the depression 90 (e.g., exhibiting larger distances T5 and / or T6) than near the top of the depression 90. In this way, the separation distance S3 between a gate electrode 98 and an epitaxial source / drain region 82 (see Figure 15C) can be increased. Fig. 18C) can be controlled such that it is different at different points along a vertical direction, which can enable better control of the capacitance between the gate electrode 98 and the epitaxial source / drain region 82, as described in more detail below.

[0054] Fig. Figure 16C illustrates the corner spacers 94 as having an approximately triangular shape with a straight side wall 95; however, the corner spacers 94 can be designed to have other shapes. For example, the side wall 95 can have a curved shape, a convex shape, a concave shape, an irregular shape, or the like, or a combination thereof. Some examples of corner spacers 94 of different shapes are given below with reference to Fig. 17A-D described. The shape of the corner spacers 94 can be controlled by controlling the shape of the corner regions 91, the thickness of the dielectric layer 92, and / or parameters of the etching process that etches the dielectric layer 92. In some cases, the shape of the side walls 95 can be controlled to control the separation distance S3 or to control the shape of the dielectric gate layer 96 and the gate electrode 98 (see Fig. 18C). For example, a convex side wall 95 can increase the separation distance S3.

[0055] In some embodiments, the etching process that etches the dielectric layer 92 and forms the corner spacers 94 comprises one or more dry etching processes, one or more wet etching processes, or combinations thereof. For example, the etching process may include a plasma etching process, which may be an isotropic etching process, an anisotropic etching process, or a combination thereof. In some embodiments, the plasma etching process includes the use of one (or more) reactive gases that selectively etch the dielectric layer 92 relative to other features such as the first ILD 88, the gate sealing spacers 80, the gate spacers 86, etc. In some embodiments, the plasma etching process is carried out in a process chamber, with process gases being introduced into the process chamber. The process gases may comprise a single gas or a mixture of gases.The process gases can include CF4, C2F6, CH3F, C4F6, CHF3, CH2F2, Cl2, C4H6, BCl3, SiCl4, SF6, HBr, H2, NF3, or the like, other gases, or combinations thereof. In some embodiments, the process gases can include other gases used to control the selectivity of the plasma etching process, such as O2, CO2, SO2, CO, SiCl4, N2, or the like, other gases, or combinations thereof. For example, in some cases, increasing the amount of O2 in the process gas can increase the selectivity of the plasma etching process for silicon dioxide. The process gases can also include carrier gases such as Ar, He, Ne, Xe, or the like, or combinations thereof.

[0056] The process gases can flow into the process chamber at a rate between approximately 10 sccm and approximately 5000 sccm. The plasma etching process can be performed using a bias power between approximately 0 watts and approximately 3000 watts and with a plasma power between approximately 10 watts and approximately 3000 watts. The plasma etching process can be performed at a temperature between approximately 40 °C and approximately 100 °C. The pressure in the process chamber can be between approximately 1 mTorr and approximately 10 Torr. Other process conditions are possible. In some embodiments, the plasma is a direct plasma. In other embodiments, the plasma is a remote plasma generated in a separate plasma generation chamber connected to the process chamber.Process gases can be activated to plasma by any suitable plasma generation method, such as by using a transformer-coupled plasma generator, inductively coupled plasma generator (ICP) systems, magnetically enhanced reactive ion etching techniques, electron cyclotron resonance techniques, or the like.

[0057] In some embodiments, the plasma etching process may include, for example, an atomic layer etching (ALE) process, a RIE process, or another plasma process. For instance, the plasma etching process can be performed using a bias power between approximately 100 watts and approximately 800 watts and with a plasma power between approximately 10 watts and approximately 500 watts. The plasma etching process can be performed at a temperature between approximately 40 °C and approximately 100 °C. The pressure in the process chamber can range from approximately 5 mTorr to approximately 100 Torr.In some embodiments, the anisotropic etching process includes flows of HBr at a flow rate between approximately 10 sccm and approximately 500 sccm, flows of Cl₂ at a flow rate between approximately 10 sccm and approximately 200 sccm, flows of Ar at a flow rate between approximately 100 sccm and approximately 1000 sccm, flows of C₄F₆ at a flow rate between approximately 10 sccm and approximately 100 sccm, and / or flows of O₂ at a flow rate between approximately 10 sccm and approximately 100 sccm. Other process gases or process conditions are possible.

[0058] The etching process can be performed in a single etching step or using multiple steps. In some embodiments, a first etching process is used to etch the dielectric layer 92 to expose the dielectric dummy layer 60 and form the corner spacers 94, and then a second etching process is used to etch the exposed portions of the dielectric dummy layer 60. In these embodiments, the first etching process and / or the second etching process can comprise a single etching step or multiple etching steps. Fig. Figures 16A-C show one embodiment in which the dielectric dummy layer 60 is etched; however, in other embodiments, the dielectric dummy layer 60 is not etched and remains above the channel region 58. In some embodiments, the dielectric layer 92 can be incompletely etched by controlling the duration of the etching process in order to form the corner spacers 94. For example, the etching process (or a step of the etching process) can be carried out until the dielectric layer 92 is removed from the side walls of the gate spacers 95 and from above the channel region 58, but can be stopped before the dielectric layer 92 is completely removed from the corner regions 91.

[0059] In some embodiments, the corner spacers 94 can be formed in one area of ​​the substrate 50 using an etching process different from that used to form the corner spacers 94 in another area of ​​the substrate 50. In this way, different areas can, for example, have corner spacers 94 of different shapes or sizes. In some embodiments, the dielectric layer 92 can be etched in one area to form corner spacers 94, while in another area the dielectric layer 92 can be completely removed without forming corner spacers 94. In some embodiments, the dielectric layer 92 can be etched in one area to form corner spacers 94, while in another area the dielectric layer 92 is not etched and remains in the recesses 90.When different methods such as those described are used, various masking steps can be employed to mask or expose appropriate areas. An exemplary embodiment in which the dielectric layer 92 is not etched in a separate area is described below with reference to [reference]. Fig. 21A-C to Fig. 24A-C described.

[0060] It will now be on Fig. Reference is made to 17A-D; there corner spacers 94 of different shapes are shown according to some embodiments. Fig. Figures 17A-D show a detailed view of the in Fig. 16C specified range 93. The in Fig. The shapes of the corner spacers 94 shown in 17A-D or other shapes of corner spacers 94 can be controlled by controlling the parameters or properties of the etching process, for example controlling the over-etching, the process gas flow rates, the plasma power, the bias power or other parameters or properties. Fig. Figure 17A illustrates an exemplary corner spacer 94 with a side wall 95 that is concave and has essentially straight sections. In some cases, forming a corner spacer 94 with a concave side wall 95 may allow the formation of a larger gate electrode 98. The side wall 95 may have an angle A1 to the dielectric dummy layer 60. In some embodiments, one end of the side wall 95 may be approximately flush with the gate spacer 85, as shown in Fig. Figure 17A is shown. In other embodiments, one end of the side wall 95 may have an angle to the gate spacer 85. Fig. Figure 17B illustrates an exemplary corner spacer 94 with a side wall 95 that is concave and curved. In some embodiments, increasing the preload power, increasing the degree of over-etching by extending the process time, or increasing the plasma power can produce a corner spacer 94 that has a more concave or curved side wall. Fig. Figure 17C illustrates an exemplary corner spacer 94 with a side wall 95 that is substantially flush with the spacer 85. In this way, the corner spacer 94 fills the corner region 91 but does not extend significantly outside of the corner region 91, and thus the corner spacer 94 has a cross-sectional area similar to that of the corner region 91. In some embodiments, increasing the degree of over-etching can form a corner spacer 94 that extends less outside the corner region 91 (e.g., forms a smaller corner spacer 94). In some embodiments, increasing the bias power of the etching process can form a corner spacer 94 that is more flush with a side wall of the gate spacer 85 (e.g., with the gate sealing spacers 80).In other embodiments, the corner spacer 94 may incompletely fill a corner area 91 or protrude from a corner area 91. Fig. Figure 17D illustrates an example of an irregularly shaped corner spacer 94. As shown in Fig. As shown in Figure 17D, a corner spacer 94 can have a side wall 95 that is approximately flush with the etched side wall of the dielectric dummy layer 60, which can allow a larger separation distance S3 (see Figure 17D). Fig. 18C). The in Fig. The side wall 95 shown in Figure 17D has a convex area that can also allow for a larger separation distance S3. As described below, a larger separation distance S3 can enable lower parasitic capacitance and improved device performance. In some embodiments, an irregular profile can be formed by controlling the relative strength of the over-etching and the bias power. The Fig. The corner spacers 94 shown in Figures 17A-D are examples. Corner spacers 94 and their side walls 95 of other sizes or shapes are possible, and all such variations are considered to be within the scope of protection of the present disclosure.

[0061] In Fig. 18A, Fig. 18B, Fig. 18C and Fig. In some embodiments, a dielectric gate layer 96 and gate electrodes 98 for replacement gates are formed within the recesses 90. Fig. Figure 18D illustrates a detailed view of area 97 from Fig. 18B. The dielectric gate layer 96 can comprise one or more layers deposited in the recesses 90, for example, on the upper surfaces and sidewalls of the fins 52 (e.g., on the channel regions 58) and on the sidewalls of the spacers 85. The dielectric gate layers 96 are also deposited on the sidewalls 95 of the corner spacers 94 and on the dielectric dummy layer 60. The dielectric gate layer 96 can also be formed on the upper surface of the first ILD 88 (not shown in the figures). In some embodiments, the dielectric gate layer 96 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like.In some embodiments, the dielectric gate layer 96, for example, comprises an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying dielectric material with a high k-value, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric gate layer 96 may have a dielectric layer with a k-value (permittivity) greater than approximately 7.0. The formation methods for the dielectric gate layer 96 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments in which portions of the dielectric dummy layer 60 remain in the recesses 90, the dielectric gate layer 96 may comprise a material of the dielectric dummy layer 60 (e.g., silicon oxide).

[0062] The gate electrodes 98 are deposited above the dielectric gate layer 96 and fill the remaining sections of the wells 90. The gate electrodes 98 can comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, in Fig. Figure 18B-C illustrates a gate electrode 98 with a single layer; however, the gate electrode 98 can comprise any number of lining layers 98A, any number of work function-setting layers 98B, and a filler material 98C, as shown by Fig. Figure 18D illustrates this. After filling the wells 90, a planarization process, such as CMP, can be performed to remove excess sections of the dielectric gate layer 96 and the material of the gate electrodes 98, the excess sections of which lie above the top surface of the ILD 88. The remaining sections of the material of the gate electrodes 98 and the dielectric gate layer 96 thus form substitute gates of the resulting FinFETs. The gate electrodes 98 and the dielectric gate layer 96 can be collectively referred to as the "substitute gate," "gate structure," or "gate stack." The gate and the gate stack can extend along sidewalls of a channel region 58 of the fins 52.

[0063] With reference to Fig. In embodiment 18C, the corner spacers 94 prevent the deposition of the dielectric gate layers 86 and the gate electrodes 98 in at least one section of the corner regions 91. Thus, the presence of the corner spacers 94 increases the overall separation distance S3 between the epitaxial source / drain regions 82 and the gate electrode 98 near the corner regions 91. Without the corner spacers 94, for example, the dielectric gate layer 96 would be deposited in the corner regions 91 and would be separated from the epitaxial source / drain regions 82 by a distance S4. In some embodiments, the distance S4 can be approximately 10 × 10 -10 m and approximately 100×10 -10The distances are approximately 10 × ... -10 m and approximately 700×10 -10 m. In some embodiments, the distance S5 can be approximately 0.5×10 -10 m to approximately 600×10 -10 m greater than the distance S4. Other distances or relative distances are possible. In this way, the separation distance S3 between the epitaxial source / drain regions 82 and the adjacent gate electrodes 98 can be increased by forming the corner spacers 94. In some embodiments, the separation distance S3 can be between approximately 10 × 10 -10 m and approximately 800×10 -10m. In some embodiments, the use of corner spacers 94, as described herein, can reduce the separation distance S3 between a gate electrode 98 and an adjacent source / drain region 82 by approximately 10×10 -10 m to approximately 700×10 -10 Increase the value by m. Other distances or relative distances are possible. It is also understood that the value in Fig. The distances S3, S4 and / or S5 shown in Figure 18C are intended to represent relative distances between the epitaxial source / drain regions 82 and the associated features. For example, the distances S3, S4 and / or S5 could represent minimum distances, mean distances, "effective" distances, approximate distances, or the like.

[0064] In some embodiments, the presence of the corner spacers 94 results in the gate stack being formed such that it has rounded or chamfered edges near the corner regions 91. For example, the gate stacks near the fins 52 may be shaped approximately like a rectangle with rounded corners (e.g., in the shape of a 'stadium' or oval) or approximately like a rectangle with chamfered corners. Other shapes of the gate stack are possible and depend on the specific shape(s) of the corner spacers 94. By etching the dielectric layer 92 to form the corner spacers 94, the separation distance S3 can be increased without significantly reducing the size of the gate stack, which can occur if the dielectric layer 92 remains unetched.The separation distance S3 can also depend on the specific shape(s) of the corner spacer(s) 94, and the shape or size of the corner spacer 94 can be controlled to control the separation distance S3. For example, a corner spacer 94 configured with a convex side wall 95 (e.g., as in . Fig. 17D, or the like) allow a larger separation distance S3 than a corner spacer 94 designed with a concave side wall 95 (e.g. as in Fig. (as shown in Figure 17B, or the like). Forming a comparatively larger corner spacer 94 can allow for a comparatively larger separation distance S3, and forming a comparatively smaller corner spacer 94 can allow for a comparatively smaller separation distance S3. In some cases, the specific shape or size of the corner spacers 94 or gate stack and the specific separation distance S3 can be formed as required for a specific application, device, or structure.

[0065] In some cases, device performance can be improved by forming corner spacers 94 that increase the separation distance S3 between the gate electrodes 98 and the epitaxial source / drain regions 82. For example, increasing the separation distance S3 can reduce the parasitic capacitance between the gate electrodes 98 and the epitaxial source / drain regions 82, which can increase device speed. In some cases, increasing the separation distance S3 can reduce the leakage current between the gate stack and the epitaxial source / drain regions 82. Furthermore, increasing the separation distance S3 can reduce the likelihood of short circuits forming between the gate stack and the epitaxial source / drain regions 82 during device fabrication (e.g., due to conductive residues or the like). This can improve yield, process flexibility, and device reliability.

[0066] The formation of the dielectric gate layer 96 in the n-region 50N and the p-region 50P can be carried out simultaneously, so that the dielectric gate layer 96 in each region is formed from the same materials, and the formation of the gate electrodes 98 can be carried out simultaneously, so that the gate electrodes 98 in each region are formed from the same materials. In some embodiments, the dielectric gate layer 96 in each region can be formed by different processes, so that the dielectric gate layer 96 can be made from different materials, and / or the gate electrodes 98 in each region can be formed by different processes, so that the gate electrodes 98 can be made from different materials. If different processes are used, different masking steps can be used to mask or expose appropriate regions.

[0067] In Fig. 19A and Fig. In embodiment 19B, a gate mask 106 is formed over the gate stack (which comprises a dielectric gate layer 96 and a corresponding gate electrode 98), the gate mask being positioned between opposing sections of the gate spacers 86. In some embodiments, forming the gate mask 106 involves recessing the gate stack, such that a recess is formed directly over the gate stack and between opposing sections of gate spacers 86. A gate mask 106, comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess sections of the dielectric material extending over the first ILD 88.

[0068] As also in Fig. 19A and Fig. As illustrated in Figure 19B, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 108 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable process, such as CVD and PECVD. The gate contacts 110 formed subsequently ( Fig. 20A and Fig. 20B) penetrate the second ILD 108 and the gate mask 106 to contact the upper surface of the recessed gate electrode 98.

[0069] In Fig. 20A and Fig. According to some embodiments, gate contacts 110 and source / drain contacts 112 of 20B are formed by the second ILD 108 and the first ILD 88. Openings for the source / drain contacts 112 are formed by the first ILD 88 and the second ILD 108, and openings for the gate contact 110 are formed by the second ILD 108 and the gate mask 106. The openings can be formed using acceptable photolithography and etching techniques. A lining (not shown), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, can be performed to remove excess material from a surface of the ILD 108.The remaining lining and conductive material form the source / drain contacts 112 and the gate contacts 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contacts 110 are physically and electrically coupled to the gate electrodes 98. The source / drain contacts 112 and the gate contacts 110 can be formed in different processes or in the same process. Although they are shown to be formed in the same section plane, it is understood that the source / drain contacts 112 and the gate contacts 110 can be formed in different section planes, thus preventing short-circuiting of the contacts.

[0070] Fig. 21A-C to Fig. Figures 24A-C illustrate intermediate steps in the formation of corner spacers 94 in a first area 150A of a substrate 50 and not in a second area 140B of the substrate 50 according to some embodiments. Fig. Figures 21A-C illustrate a structure that is in Fig. The substrate 50 is similar to that shown in Figure 14A-C (e.g., after deposition of a dielectric layer 92), except that the substrate 50 has a first region 150A for forming devices of a first type (e.g., core logic region) and a second region 150B for forming devices of a second type (e.g., input / output region). The first region 150A may be physically separated from the second region 150B (as illustrated by the divider 151), and any number of device features (e.g., other active devices, doped regions, insulating structures, etc.) may be arranged between the first region 150A and the second region 150B. The first region 150A and / or the second region 150B may overlap or be separated from the n region 50N and / or the p region. Fig. 21A, Fig. 22A, Fig. 23A and Fig. Figure 24A illustrates cross-sectional views of the first area 150A and the second area 150B in the reference section plane AA. Fig. 21B, Fig. 22B, Fig. 23B and Fig. Figure 24B illustrates top views of the first area 150A in the section plane CC, and Fig. 21C, Fig. 22C, Fig. 23C and Fig. Figure 24C illustrates top views of the second area 150B in the section plane CC. In other embodiments, the substrate 50 may have more than two areas.

[0071] Fig. Figures 21A-C illustrate the first region 150A and the second region 150B after the deposition of the dielectric layer 92, similar to Fig. 14A-C. Fig. Figures 21A-C show the components of the first area 150A and the second area 150B with similar features; however, in other embodiments, different areas may have different components or components with different properties, and all such variations are considered to be within the scope of protection of the present disclosure.

[0072] In Fig. In some embodiments, a mask layer 152 is formed and structured in 22A-C. The mask layer 152 can be formed over the dielectric layer 92 in the first region 150A and the second region 150B. The mask layer 152 can, for example, be a photoresist, a photoresist structure, or the like, and can be formed using a spin coating process or another suitable technique. The mask layer 152 can then be structured to expose the first region 150A. The mask layer 152 can be structured using acceptable photolithographic techniques. As in Fig. As shown in Figure 22A-C, the structured mask layer 152 covers the dielectric layer 92 in the second region 150B, including within the recesses 90 of the second region 150B.

[0073] In Fig. In some embodiments of 23A-C, an etching process is carried out to etch the dielectric layer 92 in the first region 150A. The etching process can be similar to that described in relation to Fig. 16A-C described and accordingly forms corner spacers 94 in the recesses 90 of the first area 150A. Fig. 23A and Fig. Figure 23B shows that the dielectric dummy layer 60 of the first region 150A was etched by the etching process; however, in other embodiments, the dielectric dummy layer 60 can remain on the channel regions 58. As shown in Fig. 23A and Fig. As shown in Figure 23C, the mask layer 152, which covers the second region 150B, prevents the etching of the dielectric layer 92 of the second region 150B by the etching process.

[0074] In Fig. In 24A-C, according to some embodiments, the mask layer 152 is removed and gate stacks are formed in the first region 150A and the second region 150B. The mask layer 152 can be removed using a suitable process, such as an etching process or an ashing process. The gate stacks can be formed similarly to those described in relation to Fig. The gate stacks described in Section 18A-C comprise a dielectric gate layer 96 and a gate electrode 98, which can be formed using suitable techniques, such as those described above. In some embodiments, the gate stacks in the first region 150A can be formed simultaneously with the gate stacks in the second region 150B. In other embodiments, the dielectric gate layer 96 and / or a gate electrode 98 in the first region 150A can be formed before the removal of the mask layer 152, whereas the dielectric gate layer 96 and / or the gate electrode 98 in the second region 150B can be formed after the removal of the mask layer 152.

[0075] As in Fig. As shown in Figure 24A-C, the gate stacks can be formed on the dielectric layer 92 in the second region 150B. In this way, the dielectric gate layers for the devices in the second region 150B can comprise the dielectric layer 92 and the dielectric dummy layer 60, resulting in the device having an effectively thicker dielectric gate layer. Furthermore, the presence of the dielectric layer 92 within the recesses 90 can provide additional separation between the gate electrodes 98 and the epitaxial source / drain regions 82 to reduce leakage current or capacitance. In some cases, the thicker dielectric gate layer can be used for devices with comparatively higher power or voltage ratings, such as input / output devices or the like.In this way, the corner spacers 94 and thicker dielectric gate layers for components can be formed in separate areas, but using some of the same processing steps. The in . Fig. The embodiment described in 21A-24C is an example, and other variations are possible, including additional masking steps, additional deposition steps, additional etching steps, or the like.

[0076] The disclosed FinFET embodiments could also be applied to nanostructured devices such as nanostructured (e.g., nanofilm, nanowire, gate all-around, etc.) field-effect transistors (NSFETs). In one NSFET embodiment, the fins are replaced by nanostructures formed by structuring a stack with alternating channel and sacrificial layer sequences. Dummy gate stacks and source / drain regions are formed similarly to the embodiments described above. After removing the dummy gate stacks, the sacrificial layers in channel regions can be partially or completely removed.In some embodiments, a dielectric layer similar to the dielectric layer 92 described herein can be formed and etched, with areas of the dielectric layer being incompletely etched to leave residual sections similar to the corner spacers 94 described herein. The replacement gate structures are formed in a similar manner to the embodiments described above; the replacement gate structures can partially or completely fill openings left by the removal of the sacrificial layers, and the replacement gate structures can partially or completely surround the channel layers in the channel regions of the NSFET devices. The ILDs and the contacts to the replacement gate structures and the source / drain regions can be formed in a similar manner to the embodiments described above.

[0077] The embodiments described herein offer several advantages. The techniques described herein enable the formation of corner spacers adjacent to the gate spacers and the channel region of a fin. The corner spacers can be formed by depositing a dielectric layer after the removal of dummy gates and subsequently controlling the etching of the dielectric layer such that sections of the dielectric layer remain as corner spacers. The corner spacers are left in position during the formation of the replacement gate stack, resulting in sections of the replacement gate stack being separated from the epitaxial source / drain regions by the corner spacers.This additional separation provided by the corner spacers can reduce the parasitic capacitance between the gate stack and the epitaxial source / drain regions, which can improve the high-speed performance of the device. Additionally, the use of corner spacers can reduce leakage current between the gate stack and the epitaxial source / drain regions. The size or shape of the corner regions can be controlled for a specific application. Furthermore, the use of corner spacers can separate the gate stack from the epitaxial source / drain regions without significantly reducing the size of the gate stack. In some cases, masking steps can be used to create corner spacers in separate regions of a substrate.In some cases, the corner spacers described herein can be designed without restricting the process window for gate stack formation or exacerbating DIBL (drain-induced barrier leakage) effects. Thus, in some cases, the corner spacers can achieve the advantages described herein without significant process changes, device layout modifications, or impacts on other aspects of device performance.

[0078] According to one embodiment, a device comprises a fin projecting from a semiconductor substrate; a gate stack above and along a side wall of the fin; a gate spacer along a side wall of the gate stack and along the side wall of the fin; an epitaxial source / drain region in the fin and adjacent to the gate spacer; and a corner spacer between the gate stack and the gate spacer, the corner spacer extending along the side wall of the fin, wherein a first region between the gate stack and the side wall of the fin is free of the corner spacer, and a second region between the gate stack and the gate spacer is free of the corner spacer. The device includes a dielectric dummy gate layer extending along the side wall of the fin, the dielectric dummy gate layer being located between the corner spacer and the fin.In one embodiment, the gate stack comprises a dielectric gate layer that physically contacts the corner spacer. In another embodiment, the corner spacers comprise silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxynitride, or silicon oxycarbonitride. In another embodiment, the corner spacer extends along the sidewall of the fin by a distance in the range of 0.5 × 10⁻⁶. -10 m up to 600×10 -10 In one embodiment, the corner spacer has a triangular cross-section in a top view. In another embodiment, the surface of the corner spacer extending along the side wall of the gate stack has a concave profile. In another embodiment, the gate stack comprises a gate dielectric and a gate electrode, the gate dielectric physically contacting the fin.

[0079] According to one embodiment, a device comprises a fin above a substrate; a gate structure on an upper surface and opposite side walls of the fin; a gate spacer along the opposite side walls of the gate structure, wherein first sections of the gate spacers have a first width, wherein second sections of the gate spacers have a second width that is greater than the first width, the first sections being closer to the fin than the second sections, the first width and the second width being measured in a first direction parallel to a side wall of the fin; a dielectric dummy material on the fin, the dielectric dummy material extending between the fin and the gate spacers; and corner spacers, each of the corner spacers being arranged between the gate structure and a corresponding first section of the gate spacers.In one embodiment, the second sections of the gate spacer physically contact the gate structure. In another embodiment, a first section of the gate structure has a third width, and a second section of the gate structure has a fourth width that is greater than the third width, the first section of the gate structure being closer to the fin than the second section of the gate structure, with the third and fourth widths being measured in the first direction. In another embodiment, the first sections of the gate spacers are separated in the first direction by a first distance, the first distance being greater than the fourth width. In another embodiment, the corner spacers have convex sidewalls facing the gate structure. In another embodiment, the corner spacer has a length measured in a second direction, which is in the range of 0.5 × 10. -10 m up to 600×10-10 m lies, with the second direction being orthogonal to the side wall of the fin. In one embodiment, a section of the corner spacer having the greatest width in the first direction physically contacts the dielectric dummy material. In another embodiment, the material of the corner spacer is different from the dielectric dummy material.

[0080] According to one embodiment, a method for forming a semiconductor device comprises forming a fin projecting from a substrate; forming a dummy gate structure extending over a channel region of the fin; forming a first spacer layer on sidewalls of the dummy gate structure; epitaxially growing source / drain regions on the fin adjacent to the channel region; removing the dummy gate structure to form a well; depositing a second spacer layer within the well; performing an etching process on the second spacer layer, wherein, after performing the etching process, remaining portions of the second spacer layer remain within the well to form corner spacers, the corner spacers being separated from one another, the corner spacers being located at corner regions of the well adjacent to the fin;and forming a replacement gate structure within the recess and on the corner spacers. In one embodiment, the etching process exposes the channel region. In one embodiment, forming the replacement gate structure comprises depositing a dielectric gate material on the corner spacers and on the channel region in the recess, wherein the dielectric gate material physically contacts the channel region and the first spacer layer; and depositing a gate electrode material on the dielectric gate material. In one embodiment, the remaining sections of the second spacer layer each have a length in the range of 0.5 × 10⁻⁶; -10 m up to 600×10 -10 m up.

Claims

[1] Device comprising: a fin (52) protruding from a semiconductor substrate; a gate stack over and along a side wall of the fin (52); a gate spacer (85) along a side wall of the gate stack and along the side wall of the fin (52); an epitaxial source / drain region (82) in the fin (52) and adjacent to the gate spacer (85); and a corner spacer (94) between the gate stack and the gate spacer (85), wherein the corner spacer (94) extends along the side wall of the fin (52), wherein a first area between the gate stack and the side wall of the fin (52) is free of the corner spacer (94), and wherein a second area between the gate stack and the gate spacer (85) is free of the corner spacer (94); and a dielectric dummy gate layer extending along the side wall of the fin (52), wherein the dielectric dummy gate layer is located between the corner spacer (94) and the fin (52). [2] Device according to claim 1, wherein the gate stack comprises a dielectric gate layer (96) that physically contacts the corner spacer (94). [3] Device according to one of the preceding claims, wherein the corner spacer (94) comprises silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxynitride or silicon oxycarbonitride. [4] Device according to one of the preceding claims, wherein the corner spacer (94) extends along the side wall of the fin (52) by a distance in the range of 0.5×10 -10 m up to 600×10 -10 m lies. [5] Device according to one of the preceding claims, wherein the corner spacer (94) has a triangular cross-section in a top view. [6] Device according to one of the preceding claims, wherein the surface of the corner spacer (94) extending along the side wall of the gate stack has a concave profile. [7] Device according to one of the preceding claims, wherein the gate stack comprises a gate dielectric and a gate electrode (98), wherein the gate dielectric physically contacts the fin (52). [8] Device comprising: a fin (52) over a substrate (50); a gate structure on an upper surface and opposite side walls of the fin (52); a gate spacer (85) along the opposite side walls of the gate structure, wherein first sections of the gate spacers (85) have a first width, wherein second sections of the gate spacers (85) have a second width which is greater than the first width, wherein the first sections are closer to the fin (52) than the second sections, wherein the first width and the second width are measured in a first direction parallel to a side wall of the fin (52); a dielectric dummy material on the fin (52), wherein the dielectric dummy material extends between the fin (52) and the gate spacers (85); and Corner spacers (94), wherein each of the corner spacers (94) is arranged between the gate structure and a corresponding first section of the gate spacers (85). [9] Device according to claim 8, wherein the second sections of the gate spacers (85) physically contact the gate structure. [10] Device according to claim 8 or 9, wherein a first section of the gate structure has a third width, wherein a second section of the gate structure has a fourth width which is greater than the third width, wherein the first section of the gate structure is closer to the fin (52) than the second section of the gate structure and wherein the third width and the fourth width are measured in the first direction. [11] Device according to claim 10, wherein the first sections of the gate spacers (85) are separated in the first direction by a first distance, wherein the first distance is greater than the fourth width. [12] Device according to claim 10 or 11, wherein the corner spacers (94) have convex side walls facing the gate structure. [13] Device according to any one of the preceding claims 8 to 12, wherein the corner spacer (94) has a length measured in a second direction which is in the range of 0.5×10 -10 m up to 600×10 -10 m lies, with the second direction being orthogonal to the side wall of the fin (52). [14] Device according to any one of the preceding claims 8 to 13, wherein a section of the corner spacer (94) having the greatest width in the first direction physically contacts the dielectric dummy material. [15] Device according to any one of the preceding claims 8 to 14, wherein a material of the corner spacer (94) is different from the dielectric dummy material. [16] Method for forming a semiconductor device, the method comprising: Formation of a fin (52) that protrudes from a substrate (50); Forming a dummy gate structure extending over a channel area (58) of the fin (52); Forming a first spacer layer on the side walls of the dummy gate structure; epitaxial growth of source / drain areas on the fin (52) adjacent to the channel area (58); Removing the dummy gate structure to form a recess (90); Deposition of a second spacer layer within the depression (90); Performing an etching process on the second spacer layer, wherein, after performing the etching process, remaining sections of the second spacer layer remain within the recess (90) to form corner spacers (94), wherein the corner spacers (94) are separated from each other, and wherein the corner spacers (94) are located at corner regions of the recess (90) adjacent to the fin (52); and Forming a replacement gate structure within the recess (90) and on the corner spacers (94). [17] Method according to claim 16, wherein the etching process exposes the channel area (58). [18] Method according to claim 16 or 17, wherein forming the replacement gate structure comprises: Deposition of a dielectric gate material on the corner spacers (94) and on the channel region (58) in the recess (90), wherein the dielectric gate material physically contacts the channel region (58) and the first spacer layer; and Deposition of a gate electrode material onto the dielectric gate material. [19] Method according to any one of the preceding claims 16 to 18, wherein the remaining sections of the second spacer layer each have a length in the range of 0.5×10 -10 m up to 600×10 -10 exhibit m.

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