Pixel unit and driving method, image sensor

Abstract

The present invention provides a pixel unit and a driving method, and an image sensor, wherein the pixel unit includes: a P-type doping region, a photodiode region and a floating diffusion region located in the P-type doping region, a transfer transistor connected to the floating diffusion region, a reset transistor, a source follower transistor, and a row selection transistor; wherein a first N-type doping region is formed in the P-type doping region on the side of the photodiode region away from the floating diffusion region, and a P-type doping region is spaced between the first N-doping region and the photodiode region, and the first N-doping region, the P-type doping region, and the photodiode region form a parasitic NPN transistor. The present invention controls the potential of the first N-type doping region to put the parasitic NPN transistor in an amplified state, thereby achieving the purpose of charging the photodiode region, avoiding the operation of charging the photodiode by exposure, and can perform photoelectric performance testing on a conventional WAT test machine, solving the problem of incompatibility between photoelectric testing and conventional WAT testing equipment.

Description

Technical Field

[0001] Pixel unit and driving method, and image sensor. Background Art

[0002] A pixel unit of a CMOS image sensor generally includes a photodiode and multiple transistors. According to the number of transistors included, the pixel unit of a CMOS image sensor can be divided into a 3T (3-transistor) type, a 4T (4-transistor) type, and a 5T (5-transistor) type.

[0003] 4T-APS (4T Active Pixel Sensor) consists of a transfer transistor TG, a source follower transistor SF (Source Follower), a reset transistor Reset and a row selection transistor Select. It has the advantages of high integration, fast response speed, low power consumption and low cost. It is one of the most widely used pixel units. Figure 1 This is a schematic diagram of the structure of a conventional 4T-APS pixel unit. Please refer to Figure 1 As shown, the photodiode region PD is N-type doped, and under the action of the P+ doped region on the top, a clamped photodiode (PPD) structure is formed. The photodiode region has no external electrode, and the potential is controlled by the transfer transistor TG (TG in the figure represents the gate of the transfer transistor). When the transfer transistor is turned off, its potential is in a floating state.

[0004] The function of the photodiode region is to generate and store photogenerated electrons when the 4T-APS chip is working. First, the potential of the photodiode region is pulled up through the transfer transistor and the reset transistor, so that it is in a reverse bias state with the surrounding P-type doped region (PW), forming a wide depletion region. Under light conditions, the depletion region will generate photogenerated electrons. Under the action of the electric field, these electrons move to the center of the photodiode region and accumulate.

[0005] Full well capacity FWC, blooming, lag and quantum efficiency are key parameters for evaluating the structural characteristics of photodiodes. Charge transfer efficiency (CTE) is the ratio of electrons entering the floating diffusion region FD node to the electrons collected in the photodiode region during the charge transfer process, and is a key indicator for evaluating the performance of transfer transistors.

[0006] However, whether testing the PPD performance or testing the performance of the transfer transistor or amplifier circuit, the PPD needs to be charged through exposure before testing. The exposure process requires additional light source control equipment and a special test machine, which is incompatible with conventional WAT (Wafer Acceptance Test) test machines.

[0007] How to test the above parameters on a conventional WAT test machine is an urgent problem to be solved. Summary of the invention

[0008] The purpose of the present invention is to provide a pixel unit and a driving method, and an image sensor, which solve the problem that photoelectric testing is incompatible with conventional WAT testing equipment, and can perform photoelectric testing on a WAT ​​testing machine.

[0009] In order to solve the above technical problems, the present invention provides a pixel unit, including: a P-type doped region, a photodiode region and a floating diffusion region located in the P-type doped region, a transfer transistor, a reset transistor, a source follower transistor and a row selection transistor connected to the floating diffusion region; wherein a first N-type doped region is formed in the P-type doped region on the side of the photodiode region away from the floating diffusion region, and the P-type doped region is spaced between the first N-type doped region and the photodiode region, and the first N-type doped region, the P-type doped region and the photodiode region form a parasitic NPN transistor.

[0010] Optionally, the first N-type doping region is located inside the P-type doping region and close to a lower portion of the photodiode region.

[0011] Optionally, it also includes a second N-type doping region and a third N-type doping region located in the P-type doping region and sequentially located on the first N-type doping region to lead out the first N-type doping region; the doping concentration of the third N-type doping region is greater than the doping concentration of the second N-type doping region, and the doping concentration of the second N-type doping region is greater than the doping concentration of the first N-type doping region.

[0012] Optionally, a shallow trench isolation structure is further included, wherein the shallow trench isolation structure isolates the P-type doping region from the second N-type doping region and the third N-type doping region.

[0013] Optionally, the bottom of the second N-type doping region is lower than the bottom of the shallow trench isolation structure; and the bottom of the first N-type doping region is higher than the bottom of the photodiode region.

[0014] Optionally, the depth of the center of the first N-type doping region is 105%~115% of the depth of the shallow trench isolation structure; in the direction perpendicular to the P-type doping region, the thickness of the first N-type doping region is between 0.3μm~0.5μm.

[0015] Optionally, a distance between the first N-type doping region and the photodiode region is greater than a width of a depletion region in the P-type doping region when a collector junction formed by the photodiode region and the P-type doping region is reverse biased.

[0016] Accordingly, the present invention further provides a method for driving a pixel unit, which drives the pixel unit as described above, and the driving method comprises the following steps:

[0017] In the reset stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned on, the first N-type doped region is connected to 0V, the P-type doped region is connected to 0V, and the power supply voltage pulls up the potential of the photodiode region and the floating diffusion region, so that the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased fully depleted state;

[0018] In the charging stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned off, the first N-type doped region is connected to a negative voltage, and the P-type doped region is connected to 0V, so that the emitter junction formed by the first N-type doped region and the P-type doped region is in a forward biased state, the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased state, and the parasitic NPN transistor is in an amplifying state; the electrons emitted from the first N-type doped region are attracted by the reverse biased electric field of the collector junction and accumulate in the photodiode region. With the accumulation of electrons in the photodiode region, the potential of the photodiode region gradually decreases, and the reverse biased electric field of the collector junction gradually weakens until the photodiode region is full of electrons and the collector junction is in an unbiased state. At this time, the photodiode region reaches a full well state and charging is terminated;

[0019] In the charge transfer stage, the row selection transistor is turned on, the reset transistor is turned off, the transfer transistor is turned on, and the first N-type doped region is connected to 0V, so that the electrons in the photodiode region are transferred to the floating diffusion region through the transfer transistor and read out through the amplifier circuit.

[0020] Optionally, the negative voltage is between -1.2V and -0.7V.

[0021] Correspondingly, the present invention also provides an image sensor, including a row selection circuit and a column selection circuit, and also including a pixel array, wherein the pixel array includes a plurality of pixel units arranged in an array, and the pixel units are the pixel units described above.

[0022] In summary, the pixel unit and driving method and image sensor provided by the present invention include: a P-type doped region, a photodiode region and a floating diffusion region located in the P-type doped region, a transfer transistor connected to the floating diffusion region, a reset transistor, a source follower transistor and a row selection transistor; wherein a first N-type doped region is formed in the P-type doped region on the side of the photodiode region away from the floating diffusion region, and the P-type doped region is spaced between the first N-type doped region and the photodiode region, and the first N-type doped region, the P-type doped region and the photodiode region form a parasitic NPN transistor. The unexpected effect of the present invention is that the pixel unit provided by the present invention forms a parasitic NPN transistor, and the parasitic NPN transistor is placed in an amplified state by controlling the potential of the first N-type doped region, so as to achieve the purpose of charging the photodiode region, avoid the operation of charging the photodiode by exposure, and can be tested for photoelectric performance on a conventional WAT test machine, solving the problem of incompatibility between photoelectric testing and conventional WAT testing equipment.

[0023] In addition, the unexpected effect of the present invention is that, in the present invention, only the first N-type doping region is added to the P-type doping region, and no additional photolithography process is required. The change to the conventional pixel structure is relatively small, and the newly added first N-type doping region has no effect on the working characteristics of the photodiode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of a conventional 4T-APS pixel unit.

[0025] Figure 2 It is a schematic diagram of the structure of a pixel unit provided by an embodiment of the present invention.

[0026] Figure 3 It is a schematic diagram of the relationship between the distance D between the first N-type doping region and the photodiode region and the width L of the depletion region in the P-type doping region when the collector junction formed by the photodiode region and the P-type doping region is reverse biased. DETAILED DESCRIPTION

[0027] Figure 1 This is a schematic diagram of the structure of a conventional 4T-APS pixel unit. Please refer to Figure 1 As shown, the pixel unit includes: a P-type substrate P-sub, a P-type doped region PW (also called a P-well) located in the P-type substrate, a photodiode region PD and a floating diffusion region FD located in the P-type doped region, a transfer transistor TG connected to the floating diffusion region (TG in the figure represents the gate of the transfer transistor), a reset transistor Reset, a source follower transistor SF and a row selection transistor Select.

[0028] The photodiode region and the P+ doped layer on the top thereof form a clamped photodiode PPD, a shallow trench isolation structure STI is formed on one side of the P-type doped region to isolate the pixel unit, and a gate oxide layer is formed between the gate of the transmission transistor and the P-type substrate.

[0029] The first end of the reset transistor is connected to the power supply voltage Vdd, and the second end is connected to the floating diffusion area. The gate of the source follower transistor is connected to the floating diffusion area, the first end is connected to the power supply power supply, and the second end is connected to the first end of the row selection transistor. The second end of the row selection transistor is connected to the output terminal Vout, wherein the first end is a source or a drain, and the second end is a drain or a source.

[0030] As described in the background technology, Figure 1 The pixel structure shown, whether testing the PPD performance or testing the performance of the transfer transistor or the amplifier circuit, requires charging the PPD through exposure before testing. The exposure process requires additional light source control equipment and a special test machine, which is incompatible with conventional WAT test machines.

[0031] In view of the above problems, the present invention provides a pixel unit including: a P-type doped region, a photodiode region and a floating diffusion region located in the P-type doped region, a transfer transistor, a reset transistor, a source follower transistor and a row selection transistor connected to the floating diffusion region; wherein a first N-type doped region is formed in the P-type doped region on a side of the photodiode region away from the floating diffusion region, and the P-type doped region is spaced between the first N-type doped region and the photodiode region, and the first N-type doped region, the P-type doped region and the photodiode region form a parasitic NPN transistor.

[0032] Accordingly, the present invention further provides a method for driving a pixel unit, which drives the pixel unit as described above, comprising the following steps:

[0033] In the reset stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned on, the first N-type doped region is connected to 0V, the P-type doped region is connected to 0V, and the power supply voltage pulls up the potential of the photodiode region and the floating diffusion region, so that the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased fully depleted state;

[0034] In the charging stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned off, the first N-type doped region is connected to a negative voltage, and the P-type doped region is connected to 0V, so that the emitter junction formed by the first N-type doped region and the P-type doped region is in a forward biased state, the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased state, and the parasitic NPN transistor is in an amplifying state; the electrons emitted from the first N-type doped region are attracted by the reverse biased electric field of the collector junction and accumulate in the photodiode region. With the accumulation of electrons in the photodiode region, the potential of the photodiode region gradually decreases, and the reverse biased electric field of the collector junction gradually weakens until the photodiode region is full of electrons and the collector junction is in an unbiased state. At this time, the photodiode region reaches a full well state and charging is terminated;

[0035] In the charge transfer stage, the row selection transistor is turned on, the reset transistor is turned off, the transfer transistor is turned on, and the first N-type doped region is connected to 0V, so that the electrons in the photodiode region are transferred to the floating diffusion region through the transfer transistor and read out through the amplifier circuit.

[0036] Correspondingly, the present invention also provides an image sensor, including a row selection circuit and a column selection circuit, and also including a pixel array, wherein the pixel array includes a plurality of pixel units arranged in an array, and the pixel units are the pixel units described above.

[0037] The present invention sets a first N-type doping region in a pixel unit, and the first N-type doping region, a P-type doping region and a photodiode region form a parasitic NPN transistor. The parasitic NPN transistor is placed in an amplified state by controlling the potential of the first N-type doping region, thereby achieving the purpose of charging the photodiode region and avoiding the operation of charging the photodiode by exposure. The photoelectric performance test can be performed on a conventional WAT test machine, and the problem of incompatibility between the photoelectric test and the conventional WAT test equipment is solved.

[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0039] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0040] Figure 2 is a schematic diagram of the structure of a pixel unit provided by an embodiment of the present invention. Figure 2 As shown, the pixel unit provided by the embodiment of the present invention includes: a P-type doping region PW, a photodiode region PD and a floating diffusion region FD located in the P-type doping region PW, a transfer transistor TG connected to the floating diffusion region FD (TG in the figure represents the gate of the transfer transistor), a reset transistor Reset, a source follower transistor SF and a row selection transistor Select; wherein, a first N-type doping region DNW is formed in the P-type doping region PW on the side of the photodiode region PD away from the floating diffusion region FD, the P-type doping region PW is spaced between the first N-type doping region DNW and the photodiode region PD (that is, there is also a P-type doping region PW between the first N-type doping region DNW and the photodiode region PD), and the first N-type doping region DNW, the P-type doping region PW and the photodiode region PD form a parasitic NPN transistor.

[0041] In the NPN parasitic transistor, the first N-type doping region DNW is an emitter, the P-type doping region PW is a base, and the photodiode region PD is a collector.

[0042] In one embodiment of the present invention, the first N-type doping region DNW is located inside the P-type doping region PW and close to the lower portion of the photodiode region PD. That is, in a direction perpendicular to the P-type doping region PW ( Figure 2In the vertical direction of the photodiode region PD), the thickness of the first N-type doping region DNW is less than the thickness of the photodiode region PD, and in the direction perpendicular to the P-type doping region PW, the photodiode PD is divided into an upper part and a lower part, and the projection of the first N-type doping region DNW on the photodiode region PD is located in the lower part of the photodiode region PD (wherein the projection is Figure 2 horizontal projection as shown).

[0043] The pixel structure also includes a second N-type doping region NW and a third N-type doping region N+ located in the P-type doping region PW and sequentially located on the first N-type doping region DNW to lead out the first N-type doping region DNW; the doping concentration of the third N-type doping region N+ is greater than the doping concentration NW of the second N-type doping region, and the doping concentration of the second N-type doping region NW is greater than the doping concentration DNW of the first N-type doping region.

[0044] The pixel structure further includes a shallow trench isolation structure STI, and the shallow trench isolation structure STI isolates the second N-type doping region NW, the third N-type doping region N+ and the P-type doping region PW. That is, one side of the second N-type doping region NW and the third N-type doping region N+ is a shallow trench isolation structure STI, and the other side of the shallow trench isolation structure STI is a P-type doping region and a photodiode region PD. Of course, a shallow trench isolation structure STI is also formed on the other side of the second N-type doping region NW and the third N-type doping region N+ to isolate the pixel unit from the rest of the structure.

[0045] In one embodiment of the present invention, the bottom of the second N-type doping region NW is lower than the bottom of the shallow trench isolation structure STI, and the bottom of the first N-type doping region DNW is higher than the bottom of the photodiode region PD. Exemplarily, the depth of the center of the first N-type doping region DNW (the distance from the center to the upper surface of the P-type doping region PW) is 105% to 115% of the depth of the shallow trench isolation structure STI (the distance from the bottom of the shallow trench isolation structure STI to the upper surface of the P-type doping region PW), preferably 110%. For example, the depth of the shallow trench isolation structure STI is 0.9μm, and the depth of the center of the first N-type doping region DNW is 0.99μm. In the direction perpendicular to the P-type doping region PW ( Figure 2 In the vertical direction of the first N-type doping region DNW, the thickness of the first N-type doping region DNW is between 0.3 μm and 0.5 μm. Of course, this is not limited to this.

[0046] In one embodiment of the present invention, in order to avoid the first N-type doping region DNW from having a significant impact on the photodiode region PD, the distance between the first N-type doping region DNW and the photodiode region PD is greater than the width of the depletion region in the P-type doping region PW when the collector junction formed by the photodiode region PD and the P-type doping region PW is reverse biased. Figure 3 It is a schematic diagram of the relationship between the distance D between the first N-type doping region and the photodiode region and the width L of the depletion region in the P-type doping region when the collector junction formed by the photodiode region and the P-type doping region is reverse biased. Please refer to Figure 3 As shown, the distance between the first N-type doping region DNW and the photodiode region PD is D (that is, the width of the P-type doping region PW between the first N-type doping region DNW and the photodiode region PD is D), the depletion region of the collector junction formed by the photodiode region PD and the P-type doping region PW is located between the two dotted lines when the collector junction is reverse biased, and the width of the depletion region in the P-type doping region PW is L, where D is greater than L.

[0047] Please refer to Figure 2 As shown, the pixel unit also includes a P-type substrate P-sub, and the P-type doped region PW is located in the P-type substrate P-sub. A P+ doped region is also formed in the P-type doped region PW, and the P+ doped region is located above the photodiode region PD, and one side edge of the P+ doped region exceeds the edge of the photodiode region PD and extends to contact the shallow trench isolation structure STI. The photodiode region PD forms a clamped photodiode structure under the action of the P+ doped region. A lightly doped region is also formed in the P-type doped region PW on the side of the floating diffusion region FD close to the gate of the transfer transistor. A gate oxide layer is also formed between the gate of the transfer transistor and the P-type substrate.

[0048] The first end of the reset transistor Reset is connected to the power supply voltage Vdd, and the second end is connected to the floating diffusion area FD. The gate of the source follower transistor SF is connected to the floating diffusion area FD, the first end is connected to the power supply Vdd, and the second end is connected to the first end of the row selection transistor Select. The second end of the row selection transistor Select is connected to the output terminal Vout, wherein the first end is a source or a drain, and the second end is a drain or a source. A connecting line can also be set on the third N-type doping area N+ to transmit a signal to the first N-type doping area DNW, and a connecting line is also set on the P+ doping area to transmit a signal to the P-type doping area PW. A dielectric layer and a contact plug penetrating the dielectric layer are also formed on the P-type doping area PW, and the present invention does not limit this.

[0049] The pixel unit provided by the present invention forms a parasitic NPN transistor, and the parasitic NPN transistor is placed in an amplified state by controlling the electric potential of the first N-type doping region DNW, thereby achieving the purpose of charging the photodiode region PD, avoiding the operation of charging the photodiode region PD by exposure, and being able to perform photoelectric performance testing on a conventional WAT testing machine, thus solving the problem of incompatibility between photoelectric testing and conventional WAT testing equipment.

[0050] In addition, in the present invention, only the first N-type doping region DNW is added to the P-type doping region PW (of course, the second N-type doping region NW and the third N-type doping region N+ may also be added). It is only necessary to modify the existing mask without adding additional photolithography processes. The change to the conventional pixel structure is relatively small, and the newly added first N-type doping region DNW has no effect on the working characteristics of the photodiode.

[0051] Accordingly, the present invention further provides a method for driving a pixel unit, which drives the pixel unit as described above, and the driving method comprises the following steps:

[0052] In the reset stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned on, the first N-type doped region is connected to 0V, the P-type doped region is connected to 0V, and the power supply voltage pulls up the potential of the photodiode region and the floating diffusion region, so that the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased fully depleted state;

[0053] In the charging stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned off, the first N-type doped region is connected to a negative voltage, and the P-type doped region is connected to 0V, so that the emitter junction formed by the first N-type doped region and the P-type doped region is in a forward biased state, the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased state, and the parasitic NPN transistor is in an amplifying state; the electrons emitted from the first N-type doped region are attracted by the reverse biased electric field of the collector junction and accumulate in the photodiode region. With the accumulation of electrons in the photodiode region, the potential of the photodiode region gradually decreases, and the reverse biased electric field of the collector junction gradually weakens until the photodiode region is full of electrons and the collector junction is in an unbiased state. At this time, the photodiode region reaches a full well state and charging is terminated;

[0054] In the charge transfer stage, the row selection transistor is turned on, the reset transistor is turned off, the transfer transistor is turned on, the first N-type doped region is connected to 0V, and the electrons in the photodiode region are transferred to the floating diffusion region through the transfer transistor and read out through the amplifier circuit.

[0055] Please refer to Figure 2As shown, in the reset stage, the row selection transistor Select is turned off, the reset transistor Reset is turned on, the transfer transistor TG is turned on, the first N-type doped region DNW is connected to 0V, the P-type doped region PW is connected to 0V, and the power supply voltage Vdd raises the potentials of the photodiode region PD and the floating diffusion region FD, so that the collector junction formed by the photodiode region PD and the P-type doped region PW is in a reverse-biased fully depleted state.

[0056] In the charging stage, the row selection transistor Select is turned off, the reset transistor Reset is turned on, the transfer transistor TG is turned off, the first N-type doped region DNW is connected to a negative voltage, the P-type doped region PW is connected to 0V, so that the emitter junction formed by the first N-type doped region DNW and the P-type doped region PW is in a forward-biased state, the collector junction formed by the photodiode region PD and the P-type doped region PW is in a reverse-biased state, and the parasitic NPN transistor is in an amplified state; the electrons emitted from the first N-type doped region DNW are attracted by the reverse-biased electric field of the collector junction (i.e., the collector junction formed by the photodiode region PD and the P-type doped region PW) and accumulate in the photodiode region PD. As the electrons in the photodiode region PD accumulate, the potential of the photodiode region PD gradually decreases, and the reverse-biased electric field of the collector junction (i.e., the collector junction formed by the photodiode region PD and the P-type doped region PW) gradually weakens until the photodiode region PD is full of electrons and the collector junction is in an unbiased state. At this time, the photodiode region PD reaches the full well state and the charging ends.

[0057] In an embodiment of the present invention, the negative voltage is between -1.2V and -0.7V. For example, the negative voltage is -1V, that is, in the charging stage, the first N-type doped region DNW is connected to -1V.

[0058] In the charge transfer stage, the row selection transistor Select is turned on, the reset transistor Reset is turned off, the transfer transistor TG is turned on, the first N-type doped region DNW is connected to 0V, so that the electrons in the photodiode region PD are transferred to the floating diffusion region FD through the action of the transfer transistor TG and read out by the amplifier circuit.

[0059] According to the above driving method, by controlling the potential of the first N-type doped region DNW to make the parasitic NPN transistor in an amplified state, the purpose of charging the photodiode region PD is achieved, the operation of charging the photodiode PD by exposure is avoided, and the optoelectronic performance test can be carried out on a conventional WAT test machine platform, solving the problem of incompatibility between optoelectronic testing and conventional WAT testing equipment.

[0060] Correspondingly, the present invention also provides an image sensor, including a row selection circuit and a column selection circuit, and also including a pixel array, wherein the pixel array includes a plurality of pixel units arranged in an array, and the pixel units are the pixel units described above.

[0061] The pixel unit and driving method and image sensor provided by the present invention include: a P-type doped region, a photodiode region and a floating diffusion region located in the P-type doped region, a transfer transistor connected to the floating diffusion region, a reset transistor, a source follower transistor and a row selection transistor; wherein a first N-type doped region is formed in the P-type doped region on the side of the photodiode region away from the floating diffusion region, the P-type doped region is spaced between the first N-type doped region and the photodiode region, and the first N-type doped region, the P-type doped region and the photodiode region form a parasitic NPN transistor. The unexpected effect of the present invention is that the pixel unit provided by the present invention forms a parasitic NPN transistor, and the parasitic NPN transistor is placed in an amplified state by controlling the potential of the first N-type doped region, so as to achieve the purpose of charging the photodiode region, avoid the operation of charging the photodiode by exposure, and can be tested for photoelectric performance on a conventional WAT test machine, solving the problem of incompatibility between photoelectric testing and conventional WAT testing equipment.

[0062] In addition, the unexpected effect of the present invention is that, in the present invention, only the first N-type doping region is added to the P-type doping region, and no additional photolithography process is required. The change to the conventional pixel structure is relatively small, and the newly added first N-type doping region has no effect on the working characteristics of the photodiode.

[0063] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A pixel unit, characterized in that: include: A P-type doped region, a photodiode region and a floating diffusion region located in the P-type doped region, a transfer transistor, a reset transistor, a source follower transistor and a row selection transistor connected to the floating diffusion region; wherein a first N-type doped region is formed in the P-type doped region on a side of the photodiode region away from the floating diffusion region, and the P-type doped region is spaced between the first N-type doped region and the photodiode region, and the first N-type doped region, the P-type doped region and the photodiode region form a parasitic NPN transistor; The distance between the first N-type doping region and the photodiode region is greater than the width of the depletion region in the P-type doping region when the collector junction formed by the photodiode region and the P-type doping region is reverse biased.

2. The pixel unit according to claim 1, characterized in that: The first N-type doping region is located inside the P-type doping region and close to a lower portion of the photodiode region.

3. The pixel unit according to claim 2, characterized in that: It also includes a second N-type doping region and a third N-type doping region located in the P-type doping region and sequentially located on the first N-type doping region to lead out the first N-type doping region; the doping concentration of the third N-type doping region is greater than the doping concentration of the second N-type doping region, and the doping concentration of the second N-type doping region is greater than the doping concentration of the first N-type doping region.

4. The pixel unit according to claim 3, characterized in that: It also includes a shallow trench isolation structure, which isolates the P-type doping region from the second N-type doping region and the third N-type doping region.

5. The pixel unit according to claim 4, characterized in that: The bottom of the second N-type doping region is lower than the bottom of the shallow trench isolation structure; the bottom of the first N-type doping region is higher than the bottom of the photodiode region.

6. The pixel unit according to claim 5, characterized in that: The depth of the center of the first N-type doping region is 105% to 115% of the depth of the shallow trench isolation structure; in a direction perpendicular to the P-type doping region, the thickness of the first N-type doping region is between 0.3 μm and 0.5 μm.

7. A method for driving a pixel unit, characterized in that: The method for driving the pixel unit according to any one of claims 1 to 6 comprises the following steps: In the reset stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned on, the first N-type doped region is connected to 0V, the P-type doped region is connected to 0V, and the power supply voltage pulls up the potential of the photodiode region and the floating diffusion region, so that the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased fully depleted state; In the charging stage, the row selection transistor is turned off, the reset transistor is turned on, the transfer transistor is turned off, the first N-type doped region is connected to a negative voltage, and the P-type doped region is connected to 0V, so that the emitter junction formed by the first N-type doped region and the P-type doped region is in a forward biased state, the collector junction formed by the photodiode region and the P-type doped region is in a reverse biased state, and the parasitic NPN transistor is in an amplifying state; the electrons emitted from the first N-type doped region are attracted by the reverse biased electric field of the collector junction and accumulate in the photodiode region. With the accumulation of electrons in the photodiode region, the potential of the photodiode region gradually decreases, and the reverse biased electric field of the collector junction gradually weakens until the photodiode region is full of electrons and the collector junction is in an unbiased state. At this time, the photodiode region reaches a full well state and charging is terminated; In the charge transfer stage, the row selection transistor is turned on, the reset transistor is turned off, the transfer transistor is turned on, and the first N-type doped region is connected to 0V, so that the electrons in the photodiode region are transferred to the floating diffusion region through the transfer transistor and read out through the amplifier circuit.

8. The driving method of the pixel unit according to claim 7, characterized in that: The negative voltage is between -1.2V and -0.7V.

9. An image sensor, comprising a row selection circuit and a column selection circuit, characterized in that: It also includes a pixel array, which includes a plurality of pixel units arranged in an array, and the pixel unit is the pixel unit according to any one of claims 1 to 6.

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