System and method for detecting particles using a detector during an examination

Abstract

Systems, apparatus, and methods include a detector including a detection element (400) including a portion of a silicon substrate (402), the portion including a front side (410) of the portion of the silicon substrate, the front side (410) including a PIN diode, the PIN diode including a p-type region (404a) and an n-type region (403a); a back side (420) opposite the front side of the portion of the silicon substrate, the back side (420) comprising a substantially uniform surface; and a layer (421) on the back side of the portion of the silicon substrate; wherein a region between the p-type region and the n-type region is configured to form a depletion region (407) when a reverse bias voltage is applied between the p-type region (404a) and the n-type region (403a), and the PIN diode is configured to detect electrons entering the back side of the portion of the silicon substrate and reaching the depletion region through the portion of the silicon substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 63 / 403,534, filed on September 2, 2022, and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The description herein relates to the field of inspection systems, and more particularly to systems for detecting particles using detectors during inspection. Background Art

[0004] During the manufacturing process of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to the design and are free of defects. Inspection systems that utilize optical microscopes typically have resolutions down to a few hundred nanometers; and the resolution is limited by the wavelength of light. As the physical size of IC components continues to decrease to less than 100 nanometers or even less than 10 nanometers, there is a need for inspection systems that can have higher resolution than systems that utilize optical microscopes.

[0005] Charged particle (e.g., electron) beam microscopes capable of resolutions down to less than one nanometer, such as scanning electron microscopes (SEMs) or transmission electron microscopes (TEMs), are used as practical tools for inspecting IC components with feature sizes less than 100 nanometers. Using an SEM, electrons from a single primary electron beam or electrons from multiple primary electron beams can be focused on a location of interest on an inspected wafer. The primary electrons interact with the wafer and may be backscattered or may cause the wafer to emit secondary electrons. The intensity of the electron beam, including backscattered electrons and secondary electrons, may vary based on the characteristics of the internal and external structures of the wafer, thereby indicating whether the wafer has defects. Summary of the invention

[0006] Embodiments of the present disclosure provide devices, systems, and methods for detecting particles using a detector. In some embodiments, the systems and methods may include a silicon substrate thinned to a thickness of 30 μm or less; a front side of the silicon substrate, the front side including a lateral PIN diode formed by a p-type implant and an n-type implant; a region between the p-type implant and the n-type implant, the region being configured to form a depletion region when a reverse bias is applied between the p-type implant and the n-type implant; a back side of the silicon substrate opposite to the front side, the back side including a substantially uniform surface; and a protective layer on the substantially uniform surface on the back side of the silicon substrate, wherein the lateral PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region.

[0007] In some embodiments, a detector may include a plurality of detection elements, wherein a detection element of the plurality of detection elements includes a portion of a silicon substrate, the portion including a front side of the portion of the silicon substrate, the front side including a PIN diode, the PIN diode including a p-type region and an n-type region; a back side of the portion of the silicon substrate opposite to the front side, the back side including a substantially uniform surface; and a layer on the back side of the portion of the silicon substrate; wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode is configured to detect electrons that enter the back side of the portion of the silicon substrate and pass through the portion of the silicon substrate to reach the depletion region.

[0008] In some embodiments, a detector may include a plurality of detection elements, wherein a detection element of the plurality of detection elements includes a portion of a silicon substrate, the portion including a front side of the portion of the substrate, the front side including a PIN diode, the PIN diode including a p-type region and an n-type region; a back side of the portion of the substrate opposite to the front side, the back side including a substantially uniform surface; and a layer on the back side of the portion of the substrate; wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode is configured to receive electrons incident on the back side of the portion of the substrate.

[0009] In some embodiments, a detector may include a plurality of detection elements, wherein a detection element of the plurality of detection elements includes a portion of a substrate, the portion including a front side of the portion of the substrate, the front side including a p-type region and an n-type region, the p-type region and the n-type region forming a PIN diode; and a back side of the portion of the substrate opposite to the front side, the back side including a substantially uniform surface; wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode is configured to receive electrons passing through the portion of the substrate from the back side of the portion of the substrate.

[0010] In some embodiments, a method of forming a detector detection element may include: forming a PIN diode on a front side of a silicon substrate by implanting a p-type dopant in the silicon substrate to form a p-type region and implanting an n-type dopant to form an n-type region, wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; thinning a back side of the silicon substrate opposite to the front side, wherein the back side includes a substantially uniform surface; and forming a layer on the back side of the silicon substrate, wherein the PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system according to an embodiment of the present disclosure.

[0012] Figure 2A It is a diagram illustrating an embodiment according to the present disclosure. Figure 1 Schematic diagram of an exemplary multi-beam system that is a portion of an exemplary charged particle beam inspection system.

[0013] Figure 2B It is a diagram illustrating an embodiment according to the present disclosure. Figure 1 Schematic diagram of an exemplary single beam system that is a portion of an exemplary charged particle beam inspection system.

[0014] Figure 3A is a schematic representation of an exemplary structure of a detector according to an embodiment of the present disclosure.

[0015] Figure 3B is a schematic illustration of a cross-sectional structure of a substrate of a detector according to an embodiment of the present disclosure.

[0016] Figure 3C is a schematic illustration of a cross-sectional structure of a substrate of a detector according to an embodiment of the present disclosure.

[0017] Figure 3D is a schematic illustration of an individual detection element according to an embodiment of the present disclosure.

[0018] Figure 4 is a schematic illustration of an individual detection element according to an embodiment of the present disclosure.

[0019] Figure 5 is a schematic illustration of an individual detection element according to an embodiment of the present disclosure.

[0020] Fig. 6A , Figure 6B and Figure 6C is a schematic illustration of the metal geometry of an individual detection element according to an embodiment of the present disclosure.

[0021] Figure 7 is a schematic illustration of a detector according to an embodiment of the present disclosure.

[0022] Fig. 8A and Figure 8B is a flow chart illustrating an exemplary process of forming a detection element according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Now, reference is made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with various aspects related to the subject matter as described in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the present disclosure is not limited thereto. Similarly, other types of charged particle beams may be applied. Further, other imaging systems may be used, such as optical imaging, photoelectric detection, x-ray detection, extreme ultraviolet inspection, deep ultraviolet inspection, etc., wherein they generate images of corresponding types.

[0024] Electronic devices consist of circuits formed on a silicon wafer called a substrate. Many circuits can be formed together on the same silicon wafer and are called an integrated circuit or IC. The size of these circuits has been reduced significantly so that many of them can fit on a substrate. For example, an IC chip in a smartphone can be as small as a thumbnail but can include over 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0025] Manufacturing these extremely small ICs is a complex, time-consuming, and expensive process that typically involves hundreds of individual steps. An error in even one step can result in a defect in the finished IC, rendering it useless. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process, that is, to increase the overall yield of the process.

[0026] An integral part of improving yield is monitoring the chipmaking process to ensure that it produces a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be performed using a scanning electron microscope (SEM). The SEM can be used to image these extremely small structures, in effect, taking a "photo" of the structure of the wafer. The image can be used to determine whether the structure was formed in the proper manner and whether it was formed in the proper location. If the structure has a defect, the process can be adjusted so that the defect is less likely to occur again. Defects may be generated during various stages of semiconductor processing. For the reasons stated above, it is important to detect defects as early as possible, accurately and efficiently.

[0027] The working principle of SEM is similar to that of a camera. A camera takes a picture by receiving and recording the brightness and color of light reflected or emitted from a person or object. SEM takes a "picture" by receiving and recording the energy or amount of electrons reflected or emitted from a structure. Before taking such a "picture", an electron beam can be provided to the structure, and when the electrons are reflected or emitted ("emitted") from the structure, the detector of the SEM can receive and record the energy or amount of these electrons to generate an image. In order to take such a "picture", some SEMs use a single electron beam (referred to as a "single-beam SEM"), while some SEMs use multiple electron beams (referred to as a "multi-beam SEM") to take multiple "pictures" of the wafer. By using multiple electron beams, the SEM can provide more electron beams to the structure for obtaining these multiple "pictures", thereby generating more electrons emitted from the structure. Thus, the detector can receive more emitted electrons at the same time and generate images of the structure of the wafer with higher efficiency and faster speed.

[0028] For example, a typical detector can be pixelated (e.g., including multiple detection elements) so that each detection element can receive particles (e.g., photons, charged particles such as electrons, protons, etc.) projected from the sample and output a detection signal. The detection signal can be used to reconstruct an image of the structure of the sample under inspection and can be used to reveal defects in the sample.

[0029] However, typical detection systems are subject to constraints. A typical inspection system may include a detection element with a lateral or vertical PIN diode on a substrate, which detects particles by front-side illumination. That is, the detection element detects particles by receiving particles on the front side of the detection element through the PIN diode rather than receiving particles on the back side of the detection element through the substrate. Due to the carrier loss on the front side of the PIN diode, the detection element that detects particles (especially) low-energy particles (for example, electrons less than 5 keV) by front-side illumination exhibits low responsiveness and low response speed. For example, carrier loss may occur due to a surface protective layer, a large amount of doped regions, a surface metal layer, or electrical contacts on the front side of the PIN diode. For example, carrier loss may occur because the surface metal layer or electrical contacts on the front side of the PIN diode absorb some electrons. Detection elements with vertical PIN diodes are also subject to constraints, such as the need to incorporate complex substrate vias to integrate the PIN diode into a readout integrated circuit.

[0030] Furthermore, the sensing element substrate is usually too thick to detect particles by backside illumination. Although sensing elements with a pure boron layer can achieve higher responsivity using frontside or backside illumination, these sensing elements have a low response speed to low energy particles due to the high sheet resistance of the thin junction layer.

[0031] Some of the disclosed embodiments provide systems and methods that address some or all of these disadvantages by providing a detector including a lateral PIN diode on a thin substrate and using a back-side illuminated detection element. The disclosed embodiments may include: providing a silicon substrate with a PIN diode on the front side of the substrate; a back side of the silicon substrate, the back side including a substantially uniform surface (e.g., a surface without implanted dopants, a material with zero implanted dopant concentration, zero PIN diodes, zero cathodes, zero anodes, etc.); a protective layer on the back side of the silicon substrate, wherein the PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region of the PIN diode, thereby improving the detection response speed, responsivity, and fill factor with an acceptable level of parasitic capacitance, and is easily integrated with a readout integrated circuit.

[0032] For the sake of clarity, the relative sizes of the components in the drawings may be exaggerated. In the following description of the drawings, identical or similar reference signs refer to identical or similar components or entities, and only the differences with respect to individual embodiments are described.

[0033] As used herein, unless expressly stated otherwise, the term "or" encompasses all possible combinations, except those that are not feasible. For example, if it is stated that a component may include A or B, then unless expressly stated otherwise or not feasible, the component may include A or B or A and B. As a second example, if it is stated that a component may include A, B, or C, then unless expressly stated otherwise or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0034] Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detectors and detection methods in a system utilizing an electron beam. However, the present disclosure is not limited thereto. Similarly, other types of charged particle beams may be applied. Further, the systems and methods for detection may be other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0035] Figure 1 An exemplary electron beam inspection (EBI) system 100 according to an embodiment of the present disclosure is illustrated. The EBI system 100 may be used for imaging. Figure 1As shown, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, an electron beam tool 104, and an equipment front end module (EFEM) 106. The electron beam tool 104 is located in the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include one or more additional loading ports. The first loading port 106a and the second loading port 106b receive a wafer front opening transport box (FOUP), which contains a wafer to be inspected (e.g., a semiconductor wafer or a wafer made of one or more other materials) or a sample to be inspected (wafers and samples can be used interchangeably). A "lot" is a plurality of wafers that can be loaded for batch processing.

[0036] One or more robotic arms (not shown) in the EFEM 106 can transport the wafer to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown), which removes gas molecules in the load / lock chamber 102 to reach a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules in the main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by the electron beam tool 104. The electron beam tool 104 can be a single beam system or a multi-beam system.

[0037] The controller 109 is electronically connected to the electron beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. Figure 1 106, but it should be appreciated that the controller 109 may be part of the structure.

[0038] In some embodiments, the controller 109 may include one or more processors (not shown). The processor may be a general-purpose electronic device or a special-purpose electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of the following: a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a general array logic (GAL), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a system on a chip (SoC), an application-specific integrated circuit (ASIC), and any type of circuit capable of data processing. The processor may also be a virtual processor comprising one or more processors distributed across multiple machines or devices coupled via a network.

[0039] In some embodiments, the controller 109 may also include one or more memories (not shown). The memory may be a general-purpose electronic device or a special-purpose electronic device capable of storing code and data accessible by a processor (e.g., via a bus). For example, the memory may include any combination of any number of the following: random access memory (RAM), read-only memory (ROM), optical disk, disk, hard disk drive, solid-state drive, flash drive, secure digital (SD) card, memory stick, compact flash (CF) card, or any type of storage device. The code may include an operating system (OS) and one or more applications (or "apps") for a specific task. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0040] Embodiments of the present disclosure may provide a single charged particle beam imaging system ("single beam system"). Compared to a single beam system, a multi-charged particle beam imaging system ("multi-beam system") may be designed to optimize throughput for different scanning modes. Embodiments of the present disclosure provide a multi-beam system that can optimize throughput for different scanning modes and accommodate different throughput and resolution requirements by using beam arrays with different geometries.

[0041] Now, refer to Figure 2A ,Should Figure 2A is a diagram illustrating an embodiment according to the present disclosure including as Figure 1 Schematic diagram of an exemplary electron beam tool 104 of a multi-beam inspection tool that is part of an EBI system 100. In some embodiments, the electron beam tool 104 can be operated as a single beam inspection tool. Figure 1The multi-beam electron beam tool 104 (also referred to herein as the apparatus 104) includes an electron source 201, a Coulomb aperture plate (or "gun aperture plate") 271, a converging lens 210, a source conversion unit 220, a primary projection system 230, an electric stage 209, and a sample holder 207 supported by the electric stage 209 to hold a sample 208 to be inspected (e.g., a wafer or a photomask). The multi-beam electron beam tool 104 may also include a secondary projection system 250 and an electronic detection device 240. The primary projection system 230 may include an objective lens 231. The electronic detection device 240 may include a plurality of detection elements 241, 242, and 243. The beam splitter 233 and the deflection scanning unit 232 may be located inside the primary projection system 230.

[0042] The electron source 201, the Coulomb aperture plate 271, the converging lens 210, the source conversion unit 220, the beam splitter 233, the deflection scanning unit 232, and the primary projection system 230 may be aligned with the primary optical axis 204 of the apparatus 104. The secondary projection system 250 and the electron detection device 240 may be aligned with the secondary optical axis 251 of the apparatus 104.

[0043] The electron source 201 may include a cathode (not shown) and an extractor or an anode (not shown), wherein during operation, the electron source 201 is configured to emit primary electrons from the cathode, and the primary electrons are extracted or accelerated by the extractor and / or the anode to form a primary electron beam 202, which forms a (virtual or real) primary beam cross 203. The primary electron beam 202 can be visualized as being emitted from the primary beam cross 203.

[0044] The source conversion unit 220 may include an image forming element array (not shown), an aberration compensator array (not shown), a beam limiting aperture array (not shown), and a pre-bent micro-deflector array (not shown). In some embodiments, the pre-bent micro-deflector array deflects multiple primary beam waves 211, 212, 213 of the primary electron beam 202 to vertically enter the beam limiting aperture array, the image forming element array, and the aberration compensator array. In some embodiments, the device 104 can be operated as a single beam system so that a single primary beam wave is generated. In some embodiments, the converging lens 210 is designed to focus the primary electron beam 202 to become a parallel beam and vertically incident on the source conversion unit 220. The image forming element array may include a plurality of micro-deflectors or micro-lenses to affect the multiple primary beam waves 211, 212, 213 of the primary electron beam 202 and form multiple parallel images (virtual images or real images) of the primary beam intersection 203, one parallel image for each of the primary beam waves 211, 212, and 213. In some embodiments, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include a plurality of micro lenses to compensate for the field curvature aberration of the primary beam waves 211, 212, and 213. The astigmatism compensator array may include a plurality of micro stigmatizers to compensate for the astigmatism aberration of the primary beam waves 211, 212, and 213. The beam limiting aperture array may be configured to limit the diameters of the individual primary beam waves 211, 212, and 213. Figure 2A Three primary beams 211, 212 and 213 are shown as an example, and it should be appreciated that the source conversion unit 220 may be configured to form any number of primary beams. The controller 109 may be connected to Figure 1 The controller 109 may be used to control various parts of the EBI system 100, such as the source conversion unit 220, the electronic detection device 240, the primary projection system 230, or the motorized stage 209. In some embodiments, as explained in further detail below, the controller 109 may perform various image and signal processing functions. The controller 109 may also generate various control signals to govern the operation of the charged particle beam inspection system.

[0045] The converging lens 210 is configured to focus the primary electron beam 202. The converging lens 210 may also be configured to adjust the current of the primary beam waves 211, 212, 213 downstream of the source conversion unit 220 by varying the focal length of the converging lens 210. Alternatively, the current may be varied by changing the radial size of the beam limiting apertures corresponding to the individual primary beam waves within the beam limiting aperture array. The current may be varied by changing both the radial size of the beam limiting apertures and the focal length of the converging lens 210. The converging lens 210 may be an adjustable converging lens that may be configured such that the position of its first principal plane is movable. The adjustable converging lens may be configured to be magnetic, which may cause the off-axis beam waves 212 and 213 to illuminate the light source conversion unit 220 at a rotation angle. The rotation angle varies with the focal length of the adjustable converging lens or the position of the first principal plane. The converging lens 210 may be an anti-rotation converging lens configured to keep the rotation angle constant while changing the focal length of the converging lens 210. In some embodiments, the converging lens 210 may be an adjustable anti-rotation converging lens, wherein the rotation angle does not change when the focal length of the converging lens 210 and the position of its first principal plane change. In some embodiments, the converging lens 210 may be an adjustable anti-rotation converging lens, wherein the rotation angle does not change when the focal length of the converging lens 210 and the position of its first principal plane change.

[0046] The objective lens 231 may be configured to focus the beams 211, 212, and 213 onto the sample 208 for inspection, and in the current embodiment, three detection spots 221, 222, and 223 may be formed on the surface of the sample 208. In operation, the Coulomb aperture plate 271 is configured to block peripheral electrons of the primary electron beam 202 to reduce the Coulomb effect. The Coulomb effect may enlarge the size of each of the probe spots 221, 222, and 223 of the primary beams 211, 212, and 213, thereby reducing the inspection resolution.

[0047] The beam splitter 233 may be, for example, a Wien filter ( Figure 2A 2 (not shown), the Wien filter includes an electrostatic deflector that generates an electrostatic dipole field and a magnetic dipole field. In operation, the beam splitter 233 can be configured to exert an electrostatic force on individual electrons of the primary beam waves 211, 212, and 213 through the electrostatic dipole field. The electrostatic force is equal in magnitude to the magnetic force exerted on the individual electrons by the magnetic dipole field of the beam splitter 233 but opposite in direction. Therefore, the primary beam waves 211, 212, and 213 can pass through the beam splitter 233 at least substantially straight with at least substantially zero deflection angle.

[0048] In operation, the deflection scanning unit 232 is configured to deflect the primary beam waves 211, 212, and 213 so that the probe spots 221, 222, and 223 are scanned across individual scanning areas in a segment of the surface of the sample 208. In response to the incident of the primary beam waves 211, 212, and 213 or the detection spots 221, 222, and 223 on the sample 208, electrons emerge from the sample 208 and three secondary electron beams 261, 262, and 263 are generated. Each of the secondary electron beams 261, 262, and 263 typically includes secondary electrons (electron energy ≤ 50 eV) and backscattered electrons (electron energy is between 50 eV and the landing energy of the primary beam waves 211, 212, and 213). The beam splitter 233 is configured to deflect the secondary electron beams 261, 262, and 263 toward the secondary projection system 250. The secondary projection system 250 then focuses the secondary electron beams 261, 262, and 263 onto the detection elements 241, 242, and 243 of the electron detection device 240. The detection elements 241, 242, and 243 are arranged to detect the corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals, which are sent to the controller 109 or a signal processing system (not shown), for example, to construct an image of the corresponding scanned area of ​​the sample 208.

[0049] In some embodiments, the detection elements 241, 242, and 243 detect the corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signals (not shown) to the image processing system (e.g., the controller 109). In some embodiments, each detection element 241, 242, and 243 may include one or more pixels. The intensity signal output of the detection element may be the sum of the signals generated by all pixels within the detection element.

[0050] In some embodiments, the controller 109 may include an image processing system including an image acquisition device (not shown) and a storage device (not shown). The image acquisition device may include one or more processors. For example, the image acquisition device may include a computer, a server, a mainframe, a terminal, a personal computer, any kind of mobile computing device, etc., or a combination thereof. The image acquisition device may be communicatively coupled to the electronic detection device 240 of the device 104 through a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, radio, etc., or a combination thereof. The image acquisition device may receive a signal from the electronic detection device 240 and may construct an image. Thus, the image acquisition device may acquire an image of the sample 208. The image acquisition device may also perform various post-processing functions, such as generating a contour, superimposing an indicator on the acquired image, etc. The image acquisition device may be configured to perform adjustments to the brightness and contrast of the acquired image, etc. The storage device may be a storage medium such as a hard disk, a flash drive, a cloud storage device, a random access memory (RAM), other types of computer-readable memory, etc. The storage device may be coupled to the image acquirer and may be used to save the scanned raw image data as raw images and post-processed images.

[0051] In some embodiments, the image acquirer can acquire one or more images of the sample based on the imaging signal received from the electronic detection device 240. The imaging signal can correspond to a scanning operation for performing charged particle imaging. The acquired image can be a single image including multiple imaging areas. The single image can be stored in a storage device. The single image can be an original image that can be divided into multiple areas. Each of the multiple areas can include an imaging area containing features of the sample 208. The acquired image can include multiple images of a single imaging area of ​​the sample 208 that has been sampled multiple times in a time series. The multiple images can be stored in a storage device. In some embodiments, the controller 109 can be configured to perform an image processing step using multiple images of the same position of the sample 208.

[0052] In some embodiments, the controller 109 may include a measurement circuit system (e.g., an analog-to-digital converter) to obtain the distribution of the detected secondary electrons. The electron distribution data collected during the detection time window combined with the corresponding scan path data of each of the primary beams 211, 212, and 213 incident on the wafer surface can be used to reconstruct an image of the inspected wafer structure. The reconstructed image can be used to reveal various features of the internal or external structure of the sample 208, and thus can be used to reveal any defects that may exist in the wafer.

[0053] In some embodiments, the controller 109 may control the motorized stage 209 to move the sample 208 during the inspection of the sample 208. In some embodiments, the controller 109 may enable the motorized stage 209 to continuously move the sample 208 at a constant speed in one direction. In other embodiments, the controller 109 may enable the motorized stage 209 to change the movement speed of the sample 208 over time depending on the steps of the scanning process.

[0054] although Figure 2A The apparatus 104 is shown using three primary electron beams, but it should be appreciated that the apparatus 104 may use one, two, or more primary electron beams. The present disclosure does not limit the number of primary electron beams used in the apparatus 104. In some embodiments, the apparatus 104 may be a SEM for lithography. In some embodiments, the electron beam tool 104 may be a single beam system or a multi-beam system.

[0055] For example, Figure 2B As shown, the electron beam tool 100B (also referred to herein as the device 100B) can be a single beam inspection tool for the EBI system 10 according to an embodiment of the present disclosure. The device 100B includes a wafer holder 136, which is supported by a motorized stage 134 to hold a wafer 150 to be inspected. The electron beam tool 100B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. The electron beam tool 100B also includes a beam limiting aperture 125, a converging lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 can be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. During imaging, an electron beam 161 emitted from the tip of cathode 103 may be accelerated by the voltage of anode 121, pass through gun aperture 122, beam limiting aperture 125, converging lens 126, and focused into a detection spot 170 by a modified SORIL lens, and impinge on the surface of wafer 150. The detection spot 170 may be scanned across the surface of wafer 150 by a deflector such as deflector 132c or other deflectors in the SORIL lens. Secondary particles or scattered primary particles (such as secondary electrons or scattered primary electrons emitted from the wafer surface) may be collected by detector 144 to determine the intensity of the beam and enable an image of an area of ​​interest on wafer 150 to be reconstructed.

[0056] An image processing system 199 may also be provided, which includes an image acquisition device 120, a storage device 130 and a controller 109. The image acquisition device 120 may include one or more processors. For example, the image acquisition device 120 may include a computer, a server, a mainframe, a terminal, a personal computer, any kind of mobile computing device, etc., or a combination thereof. The image acquisition device 120 may be connected to the detector 144 of the electron beam tool 100B through a medium such as an electrical conductor, an optical cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, radio, or a combination thereof. The image acquisition device 120 may receive a signal from the detector 144 and may construct an image. Thus, the image acquisition device 120 may acquire an image of the wafer 150. The image acquisition device 120 may also perform various post-processing functions, such as generating a profile, superimposing an indicator on the acquired image, etc. The image acquisition device 120 may be configured to perform adjustments to the brightness and contrast of the acquired image, etc. The storage device 130 may be a storage medium, such as a hard disk, a random access memory (RAM), a cloud storage device, other types of computer-readable memory, etc. The storage device 130 may be coupled to the image acquirer 120 and may be used to store the scanned raw image data as raw images and post-processed images. The image acquirer 120 and the storage device 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage device 130 and the controller 109 may be integrated together as an electronic control unit.

[0057] In some embodiments, the image acquirer 120 may acquire one or more images of the sample based on the imaging signal received from the detector 144. The imaging signal may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image including a plurality of imaging regions, which may contain various features of the wafer 150. The single image may be stored in the storage device 130. Imaging may be performed on an imaging frame basis.

[0058] The convergence and illumination optics of an electron beam tool may include or be supplemented by an electromagnetic quadrupole electron lens. Figure 2B As shown, the electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, the first quadrupole lens 148 may be controlled to adjust the beam current, and the second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0059] Figure 2BA charged particle beam arrangement is illustrated, where the inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with the wafer 150. The detector 144 may be positioned along the optical axis 105, such as at Figure 2B The primary electron beam may be configured to travel along the optical axis 105. Thus, the center of the detector 144 may include a hole so that the primary electron beam can pass through to reach the wafer 150.

[0060] Now, refer to Figure 3A ,Should Figure 3A FIG. 3 is a schematic representation of an exemplary structure of a detector 300 according to an embodiment of the present disclosure. Figure 2A and Figure 2B , the detector 300 may be provided as the detector 144 or the electronic detection device 240. Although Figure 3A One array is shown in FIG. 3 , but it will be appreciated that the detector 300 may include multiple arrays, such as one array for each secondary electron beam.

[0061] Detector 300 may include an array of detection elements including detection elements 311, 312, and 313. The detection elements may be arranged in a planar two-dimensional array, the plane of the array being substantially perpendicular to the incident direction of the incoming charged particles. In some embodiments, detector 300 may be arranged to be tilted relative to the incident direction.

[0062] The detector 300 may include a substrate 310. The substrate 310 may be a semiconductor substrate that may include a detection element. The detection element may include a diode. The detection element may also be an element similar to a diode that can convert incident energy into a measurable signal. The detection element may include, for example, a PIN diode, an avalanche diode, an electron multiplier tube (EMT), etc., or a combination thereof. Additionally, the term "detection element" may include or encompass a "sensing element", "sensor element", "detection unit" or "detector segment", etc. In some embodiments, a pixel on the detector may be a detection element.

[0063] Region 325 may be provided between adjacent detection elements. Region 325 may be an isolation region that isolates the sides or corners of adjacent detection elements from each other. Region 325 may include an insulating material that is a material different from that of other regions of the detection surface of detector 300. Region 325 may be provided as in Figure 3A The cross-shaped area seen in the plan view of FIG. Area 325 may be provided as a square. In some embodiments, area 325 may not be provided between adjacent sides of the detection element. For example, in some embodiments, no isolation area may be provided on the detection surface of the detector.

[0064] The detection element can generate an electrical signal that is equivalent to the charged particles received in the active area of ​​the detection element. For example, the detection element can generate a current signal that is equivalent to the energy of the received electrons. The preprocessing circuit can convert the generated current signal into a voltage that can represent the intensity of the electron beam spot or a portion thereof. The preprocessing circuit system may include, for example, a preamplifier circuit system. The preamplifier circuit system may include, for example, a charge transfer amplifier (CTA), a transimpedance amplifier (TIA), or an impedance conversion circuit coupled to a CTA or TIA, etc. In some embodiments, a signal processing circuit system may be provided that provides an output signal in arbitrary units in time. One or more substrates, such as tube cores, may be provided, and the one or more substrates may form a circuit layer for processing the output of the detection element. The tube cores may be stacked together in the thickness direction of the detector. Other circuit systems may also be provided for other functions. For example, a switch actuation circuit system may be provided that controls the switch elements used to connect the detection elements to each other.

[0065] Now, refer to Figure 3B , Figure 3B A schematic diagram of a cross-sectional structure of a substrate 310 according to an embodiment of the present disclosure is shown, which substrate 310 may be an example of a structure included in a PIN detector. The substrate 310 may include one or more layers. For example, the substrate 310 may be configured to have a plurality of layers stacked in a thickness direction, the thickness direction being substantially parallel to the incident direction of the electron beam. In some embodiments, the substrate 310 may have a plurality of layers stacked in a direction perpendicular to the incident direction of the electron beam. The substrate 310 may be provided with a sensor surface 301 for receiving incident charged particles. Detection elements (e.g., detection elements 311, 312, and 313) may be disposed in a sensing layer of the substrate 310. Region 325 may be disposed between adjacent detection elements. For example, the substrate 310 may include a groove, or other structures made of or filled with an insulating material. In some embodiments, the region 325 may extend completely or partially through the substrate 310.

[0066] like Figure 3C As shown, in some embodiments, according to embodiments of the present disclosure, region 325 cannot be set between detection elements. For example, in a cross-sectional view, there may be no insulating material between the sides of adjacent detection elements. In a cross-sectional view, multiple detection elements may be connected. Isolation between adjacent detection elements can still be achieved by other means (such as by controlling the electric field). For example, the electric field can be controlled between each detection element.

[0067] Although the accompanying drawings may show the detection elements 311, 312, and 313 as discrete units, such division may not actually exist. For example, the detection elements of the detector may be formed by semiconductor devices constituting PIN diode devices. The PIN diode device may be manufactured as a substrate having multiple layers, the multiple layers including a p-type region, an intrinsic region, and an n-type region. In a cross-sectional view, one or more of such layers may be connected. However, in some embodiments, the detection elements may be physically spaced between them. In addition to the sensor layer, other layers may also be provided, such as, for example, a circuit layer and a readout layer.

[0068] As an example of another layer, the detector 300 can be provided with one or more circuit layers, which are adjacent to the sensor layer. One or more circuit layers can include line conductors, interconnects, and various electronic circuit components. One or more circuit layers can include a processing system. One or more circuit layers can include a signal processing circuit system. One or more circuit layers can be configured to receive an output current detected from a detection element in the sensor layer. For example, one or more circuit layers and the sensor layer can be arranged in the same or separate tube cores.

[0069] Figure 3D 2 shows a schematic representation of an individual detection element according to an embodiment of the present disclosure, which may be an example of one of the detection elements 311, 312, and 313. Figure 3D , a detection element 311A ​​is shown. The detection element 311A ​​may include a semiconductor structure of a p-type layer 321, an intrinsic layer 322, and an n-type layer 323. The detection element 311A ​​may include two terminals, such as an anode and a cathode. The detection element 311A ​​may be reverse biased, and a depletion region 330 may be formed and may span a portion of the length of the p-type layer 321, substantially the entire length of the intrinsic layer 322, and a portion of the length of the n-type layer 323. In the depletion region 330, charge carriers may be removed, and new charge carriers generated in the depletion region 330 may be cleared depending on their charge. For example, when an incoming charged particle reaches the sensor surface 301, electron-hole pairs may be generated, and holes 351 may be attracted toward the p-type layer 321, while electrons 352 may be attracted toward the n-type layer 323. In some embodiments, a protective layer may be provided on the sensor surface 301.

[0070] In operation, the depletion region of the detection element can act as a capture region. Incoming charged particles can interact with the semiconductor material in the depletion region and generate new charge. For example, the detection element can be configured so that charged particles with a certain amount or more of energy can cause electrons of the lattice of the semiconductor material to be expelled, thereby generating electron-hole pairs. Due to, for example, the electric field in the depletion region, the resulting electrons and holes can be caused to travel in opposite directions. The generation of carriers traveling toward the terminals of the detection element can correspond to the flow of current in the detection element.

[0071] In a comparative example, a photodiode may be configured to generate a charge in response to receiving a photon. The energy of a photon may correspond to its wavelength or frequency. Typically, the energy of a photon in the visible spectrum may be on the order of about 1 eV. However, in a semiconductor photodiode, typically about 3.6 eV may be required to generate an electron-hole pair. Therefore, a photodiode may encounter difficulties such as the following when generating a detection current.

[0072] Generally speaking, the energy level of a photon may be similar to the energy level required to generate an electron-hole pair in a semiconductor photodiode. Therefore, in order to stably and reliably generate an electrical signal, it may be necessary for a high-energy photon to be incident on a semiconductor photodiode. When the frequency of a photon is at or above a certain level, the photon may have enough energy to generate an electron-hole pair.

[0073] Further, the current generated by the electron-hole pair in response to the photon arrival event may be relatively low. The current generated in response to the photon arrival event may not be sufficient to overcome the background noise. Some diodes (such as photodiodes biased to avalanche or Geiger counting mode) can use amplification to generate a larger level of electrical signals, so that a useful detection signal can be generated. In some embodiments, the photodiode can be biased to an avalanche mode of operation. In some embodiments, amplification can be provided by a gain block attached to the photodiode. An avalanche effect can be generated based on the strong internal electric field generated by the bias voltage. The avalanche effect can be used to achieve amplification caused by impact ionization.

[0074] Figure 4 Schematic diagram of an individual detection element according to an embodiment of the present disclosure is shown, which may be an example of one detection element among detection elements 311, 312 and 313. Figure 4, a detection element 400 is shown. The detection element 400 may include a substrate (e.g., a silicon substrate) 401 having a lateral PIN diode, wherein a first PIN diode includes an n-type region 403a (e.g., an n-type dopant), a p-type region 404a (e.g., a p-type dopant), and an intrinsic region 405a; a second PIN diode includes an n-type region 403b, a p-type region 404a, and an intrinsic region 405b; and a third PIN diode includes an n-type region 403b, a p-type region 404b, and an intrinsic region 405c. Although three PIN diodes are shown, it should be understood that the detection element 400 may include any number of PIN diodes. The PIN diodes may be formed on the front side 410 of the detection element 400. In some embodiments, a passivation layer 411 may be formed on the front side 410.

[0075] The detection element 400 may include terminals, such as a cathode 413a on the n-type region 403a, an anode 414a on the p-type region 404a, a cathode 413b on the n-type region 403b, and an anode 414b on the p-type region 404b. When a reverse bias is applied between the n-type region 403a and the p-type region 404a, the region between the n-type region 403a and the p-type region 404a may form a depletion region 407a. The depletion region 407a may span a portion of the length of the n-type region 403a, substantially the entire length of the intrinsic region 405a, and a portion of the length of the p-type region 404a. In the depletion region 407a, charge carriers may be removed, and new charge carriers generated in the depletion region 407a may be swept away according to their charge. For example, when incoming charged particles (e.g., electrons) reach the front side 410, electron-hole pairs may be generated, and the holes may be attracted toward the p-type region 404a, while the electrons may be attracted toward the n-type region 403a. Likewise, a depletion region 407b may be formed between the n-type region 403b and the p-type region 404a, and a depletion region 407c may be formed between the n-type region 403b and the p-type region 404b.

[0076] In operation, the depletion region of the detection element 400 can act as a capture region. Incoming charged particles may interact with the semiconductor material of the depletion region and generate new charges. For example, the detection element 400 can be configured so that charged particles with a certain amount of energy or more can drive electrons from the lattice of the semiconductor material, thereby generating electron-hole pairs. Due to, for example, the electric field of the depletion region, the resulting electrons and holes can be caused to travel in opposite directions. The generation of carriers moving toward the terminals of the detection element 400 can correspond to the flow of current in the detection element 400.

[0077] In some embodiments, a passivation layer 421 may be formed on a back side 420 of the substrate 401 opposite to the front side 410. Unlike the front side 410 including the n-type regions 403a to 403b and the p-type regions 404a to 404b, the back side 420 may include a substantially uniform surface (e.g., a surface without implanted dopants, a material with a zero implanted dopant concentration, zero PIN diodes, zero cathodes, zero anodes, etc.). The substantially uniform surface of the back side 420 may be located between the front side 410 and the passivation layer 421.

[0078] The substrate 401 may include a dopant concentration greater than zero, where the dopant is a non-implanted dopant. The non-implanted dopant may be added to the silicon substrate as the silicon substrate is formed. For example, the dopant may be added to molten silicon and become part of the silicon substrate as the silicon crystal grows to form the silicon substrate.

[0079] To detect particles, the PIN diode of the detection element 400 can be configured to detect particles 422 (e.g., charged particles) that enter the back side 420 and pass through the silicon substrate 401 to the depletion region. In some embodiments, the passivation layer 421 can include a material that is substantially transparent to electrons (e.g., SiN, thin metal, etc.) so that the particles 422 (electrons) can pass through the detection element 400 from the back side 420 and the PIN diode of the detection element 400 can detect the electrons. Therefore, when the detection element 400 is used to detect electrons, the passivation layer 421 will not include materials that are opaque to electrons, such as SiO2.

[0080] Advantageously, the detection element 400 can detect particles using a lateral PIN diode by backside illumination (e.g., the backside of the substrate can be exposed to secondary electrons while the front side of the substrate can not be exposed to secondary electrons), thereby improving the responsivity, response speed, and fill factor of the detection element 400. The detection responsivity can be described as the ratio of the output to the input (e.g., the output current to the input current) of the detection element. The detection response speed can be described as the time for an electrical signal to be generated by the detection element when a particle lands on the detection element. The detection fill factor can be described as the percentage of detection elements that generate a signal in a certain area of ​​the detector.

[0081] Backside illumination detection of the detection element 400 can exhibit increased responsivity and response speed during detection by avoiding carrier losses that typically occur with frontside illumination detection, such as carrier losses due to a frontside surface protection layer, a frontside heavily doped region, a surface metal layer, or electrical contacts on the front side of a PIN diode. For example, carrier losses may occur due to the absorption of some electrons by a surface metal layer or electrical contacts on the front side of a PIN diode.

[0082] Advantageously, the detection element 400 can use a thin substrate, thereby allowing the PIN diode on the front side 410 to detect particles 422 entering the back side 420. For example, the thickness of the substrate 402 can be less than 20 μm or less than 30 μm so that the particles 422 can reach the front side 410 with high responsivity and high response speed. The thin substrate 402 also avoids the use of trenches and additional implants in the detection element 400, which are usually required for backside illumination detection using thick substrates.

[0083] Because substrate 401 is thin (eg, less than 20 μm or less than 30 μm), depletion regions 407a to 407c may include backside 420 such that the entire substrate 40 is depleted. Advantageously, fully depleted substrate 401 may result in high responsivity and high response speed of detection element 400.

[0084] In some embodiments, the thickness of the substrate 402 can be adjusted or controlled to control the detection response speed of the detection element 400. In some embodiments, the detection responsivity, response speed, fill factor, and parasitic effects of the detection element 400 can be adjusted or controlled by adjusting the PIN diode (such as the width of the n-type regions 403a to 403b and the p-type regions 404a to 404b, the dopant concentration of the n-type regions 403a to 403b and the p-type regions 404a to 404b, the width of the intrinsic regions 405a to 405c, etc.).

[0085] Some typical detection elements may use substrates with a thickness greater than 30 μm, which may be subject to constraints. For example, a detection element with a substrate thickness greater than 30 μm may exhibit low responsiveness and low response speed due to the inability of particles to reach the front side of the detection element or the slow arrival of particles at the front side of the detection element. Detection elements with a substrate thickness greater than 30 μm may also require more complex manufacturing due to the need for additional grooves and implants to enable particles to reach the front side of the detection element with high responsiveness and high response speed. The embodiments of the present disclosure overcome these constraints by using a substrate with a thickness less than 20 μm or less than 30 μm.

[0086] Some detection elements may also include implanted dopants on the back side of the detection element (i.e., implanted dopants on the side of the detection element where the particles enter, implanted dopants on both the front and back sides, etc.), which are subject to constraints. For example, a detection element with implanted dopants on the back side of the detection element may exhibit low responsiveness and low response speed due to carrier loss on the back side of the detection element. For example, carrier loss may occur because the implanted dopants on the back side of the detection element absorb some electrons. The various embodiments of the present disclosure overcome these constraints by using a back side with a substantially uniform surface (e.g., a surface without implanted dopants, a material with zero implanted dopant concentration, zero PIN diodes, zero cathodes, zero anodes, etc.).

[0087] Figure 5 A schematic diagram of an individual detection element, which may be an example of one of the detection elements 311 , 312 , 313 , and 400 , and a readout integrated circuit according to an embodiment of the present disclosure is shown.

[0088] like Figure 5 As shown, the detection element 500 may include a substrate (eg, a silicon substrate) 501 (eg, Figure 4 401), wherein the PIN diode includes an n-type region 503 (eg, an n-type dopant) (eg, Figure 4 n-type regions 403a to 403b), p-type region 504 (eg, p-type dopant) (eg, Figure 4 p-type regions 404a to 404b) and an intrinsic region 505 (eg, Figure 4 The intrinsic regions 405a to 405c of the detection element 500 may be formed on the front side 510 (eg, Figure 4 In some embodiments, a passivation layer 511 (eg, Figure 4 passivation layer 411).

[0089] The sensing element 500 may include a terminal, such as a cathode 513 (eg, Figure 4 cathodes 413a to 413b) and an anode 514 on the p-type region 504 (eg, Figure 4 When a reverse bias is applied between the n-type region 503 and the p-type region 504, a depletion region 507 (eg, Figure 4 The depletion region 507 may span a portion of the length of the n-type region 503, substantially the entire length of the intrinsic region 505, and a portion of the length of the p-type region 504. Because the substrate 501 is thin (e.g., less than 20 μm or less than 30 μm), the depletion region 507 may include a back side 520 so that the entire substrate 501 is depleted. Advantageously, the fully depleted substrate 501 may result in high responsivity and high response speed of the detection element 500.

[0090] In some embodiments, the back side 520 (eg, Figure 4 A passivation layer 521 (eg, Figure 4504). Unlike the front side 510 including the n-type region 503 and the p-type region 504, the back side 520 may include a substantially uniform surface (e.g., a surface without implanted dopants, a material with zero implanted dopant concentration, zero PIN diodes, zero cathodes, zero anodes, etc.). To detect particles, the PIN diodes of the detection element 500 may be configured to detect particles 522 (e.g., charged particles) that enter the back side 520 and pass through the silicon substrate 501 to reach the depletion region 507 (e.g., Figure 4 In some embodiments, the passivation layer 521 may include a material that is substantially transparent to electrons (e.g., SiN, thin metal, etc.) so that the particles 522 (electrons) can pass through the detection element 500 from the back side 520 and the PIN diode of the detection element 500 can detect the electrons. Therefore, when the detection element 500 is used to detect electrons, the passivation layer 521 will not include a material that is opaque to electrons, such as SiO2.

[0091] like Figure 5 As shown, since the cathode 513 and the anode 514 are located on the same front side 510, the detection element 500 can be easily integrated directly into the readout integrated circuit 520 (e.g., CMOS ASIC) without the need for through-wafer vias in the substrate 501. For example, the detection element 500 can be bonded to the readout integrated circuit 550 using a bonding material 551 (e.g., solder bumps).

[0092] Fig. 6A , Figure 6B and Figure 6C A schematic illustration of the metal geometry of an individual detection element, which may be an example of one of the detection elements 311 , 312 , 313 , 400 , and 500 , is shown according to an embodiment of the present disclosure.

[0093] like Fig. 6A As shown, the detection element 600a (eg, Figure 4 The detection element 400, Figure 5 The detection element 500 may include its front side 610a (eg, Figure 4 The front side 410, Figure 5 The cathode 613a (e.g., Figure 4 The cathodes 413a to 413b, Figure 5 The cathode 513) and the anode 614a (e.g., Figure 4 Anodes 414a to 414b, Figure 5In some embodiments, the cathode 613a and anode 614a of the detection element 600a can be arranged to be interlaced. In some embodiments, the metal geometry of the coarser detection element 600a can be adjusted to control or adjust the detection responsiveness, response speed, parasitic effects or losses from the front side 610a.

[0094] like Figure 6B As shown, the detection element 600b (eg, Figure 4 The detection element 400, Figure 5 The detection element 500 may include its front side 610b (eg, Figure 4 The front side 410, Figure 5 The cathode 613b (e.g., Figure 4 The cathodes 413a to 413b, Figure 5 The cathode 513) and the anode 614b (e.g., Figure 4 Anodes 414a to 414b, Figure 5 In some embodiments, the cathode 613b and anode 614b of the detection element 600b can be arranged concentrically in a circular shape. In some embodiments, the metal geometry of the detection element 600b can be adjusted to control or adjust the detection responsiveness, response speed, parasitic effects or losses from the front side 610b.

[0095] like Figure 6C As shown, the detection element 600c (eg, Figure 4 The detection element 400, Figure 5 The detection element 500 may include a front side 610c (eg, Figure 4 The front side 410, Figure 5 The cathode 613c (e.g., Figure 4 The cathodes 413a to 413b, Figure 5 The cathode 513) and the anode 614c (e.g., Figure 4 Anodes 414a to 414b, Figure 5 In some embodiments, the cathode 613c and anode 614c of the detection element 600c can be arranged concentrically in a hexagonal shape. In some embodiments, the metal geometry of the detection element 600c can be adjusted to control or adjust the detection responsiveness, response speed, parasitic effects or losses from the front side 610c. In some embodiments, the metal geometry of the detection element 600c can be used to reduce the breakdown voltage of the detection element 600c.

[0096] In some embodiments, the metal geometry of detection elements 600a, 600b, and 600c can improve the uniformity and consistency of detection responsivity, response speed, and fill factor across the detector.

[0097] Now, refer to Figure 7 , Figure 7 FIG. 7 is a schematic diagram illustrating an exemplary structure of a detector 700 (eg, the detector 300 of FIG. 3 ) according to an embodiment of the present disclosure. The detector 700 may be provided as a reference. Figure 2A and Figure 2B The detector 144 or the electronic detection device 240. Although Figure 7 One array is shown in FIG. 7 , but it will be appreciated that detector 700 may include multiple arrays, such as one array for each secondary electron beam.

[0098] The detector 700 may include an array of detection elements, including detection elements 701 (e.g., 311, 312, 313, 400, 500, 600a, 600b, 600c). The detection elements may be arranged in a planar two-dimensional array, with the plane of the array being substantially perpendicular to the incident direction of the incoming charged particles. In some embodiments, the detector 700 may be arranged to be tilted relative to the incident direction. The PIN diodes of the detection elements may be positioned in a lateral geometry to provide a greater density of PIN diodes per unit area. For example, the array may include any combination of any number of p-type regions and n-type regions in an alternating order.

[0099] like Figure 7 As shown, the detection element 701 may include its front side 710 (eg, Figure 4 The front side 410, Figure 5 The cathode 713 (e.g., Figure 4 The cathodes 413a to 413b, Figure 5 The cathode 513) and the anode 714 (e.g., Figure 4 Anodes 414a to 414b, Figure 5 Although the cathode 713 and the anode 714 are arranged to be staggered with each other (e.g., Fig. 6A Detection element 600a), but it should be understood that the metal geometry of the detection element 701 is not limited, and other metal geometries (e.g., Figure 6B The detection element 600b, Figure 6C Detection element 600c).

[0100] Now, refer to Fig. 8A and Figure 8B , Fig. 8A and Figure 8B800A and 800B are illustrated for forming a detection element (e.g., 311, 312, 313, 400, 500, 600a, 600b, 600c, 701) according to an embodiment of the present disclosure. For illustrative purposes, the steps of processes 800A and 800B may be performed by a computing device (e.g., Figure 1 , Figure 2A , Figure 2B The system execution may be implemented on the features of the controller 109 of the computing device or otherwise use the features of the computing device. It should be appreciated that the illustrated processes 800A and 800B may be altered to modify the order of steps and include additional steps.

[0101] For example, Fig. 8A The process 800A shows that at step 801, a substrate 801a (eg, silicon, SOI, etc.) may be prepared (eg, Figure 4 Substrate 401, Figure 5 In some embodiments, the substrate 801a may be an intrinsic region (eg, Figure 4 The intrinsic regions 405a to 405c, Figure 5 A thick substrate (e.g., 500 μm to 600 μm) having an intrinsic region 505.

[0102] At step 802, layer 802a may be used to implant p-type dopants into substrate 801a to form p-type region 802b (eg, Figure 4 p-type regions 404a to 404b, Figure 5 In some embodiments, layer 802a (e.g., SiN, SiO2, diazo naphthoquinone-based photoresist (DNQ-Novolak), etc.) may be capable of blocking ions from entering an area of ​​substrate 801a outside p-type region 802b. In some embodiments, p-type region 802b may be adjusted to adjust the depletion region of the PIN diode. For example, the p-type region 802b may be adjusted by adjusting the depth, width, or dopant concentration of p-type region 802b. In some embodiments, layer 802a may be a deposited and patterned photoresist. The photoresist may be deposited and patterned before ion implantation, and the photoresist may be removed after ion implantation. In some embodiments, layer 802a may include an insulator and a photoresist. An insulator and a photoresist may be deposited, and the photoresist may be patterned. Using the photoresist pattern, the insulator may be patterned using a selective etching process. The photoresist may be removed and ion implantation may be performed.

[0103] At step 803, n-type dopants may be implanted into substrate 801a using layer 803a to form n-type region 803b (eg, Figure 4 n-type regions 403a to 403b, Figure 5 In some embodiments, the layer 803a (e.g., SiN, SiO2, diazo naphthoquinone-based photoresist (DNQ-Novolak), etc.) can block ions from entering the substrate 801a region outside the n-type region 803b. In some embodiments, the n-type region 803b can be adjusted to adjust the depletion region of the PIN diode. For example, the n-type region 803b can be adjusted by adjusting the depth, width, or dopant concentration of the n-type region 803b.

[0104] At step 804, a metal layer may be deposited on the p-type region 802b and patterned to form an anode 804a, and a metal layer may be deposited on the n-type region 803b and patterned to form a cathode 804b. For example, by photolithographic patterning using a sacrificial mask, a metal layer may be selectively deposited on the p-type region 802b and the n-type region 803b, followed by metal filling or metal deposition. In some embodiments, the anode 804a and the cathode 804b may be alloys or pure metals (e.g., aluminum (Al), tungsten (W), silicide (TiSi2, MoSi2, PtSi, CoSi2, WSi2), etc.).

[0105] At step 805, a first passivation layer 805a may be formed on the anode 804a and the cathode 804b, and a second passivation layer 805b may be formed on the first passivation layer 805a. In some embodiments, the passivation layers 805a and 805b may be used as insulators. In some embodiments, the thickness of the passivation layers 805a and 805b may be adjusted. For example, the passivation layer 805b (e.g., 5 μm to 10 μm) may be thicker than the passivation layer 805a (e.g., 100 nm). In some embodiments, the passivation layer 805a may be used to reduce the recombination losses from the surface of the substrate 801a, which may be thin (e.g., less than 100 nm). In some embodiments, the passivation layer 805b may be optionally included for mechanical support of the step of thinning the substrate 801a (step 808), wherein the thicker layer provides more support.

[0106] like Figure 8B As shown, in process 800B, Fig. 8A At step 806 after step 805, via holes 806a and 806b may be patterned in the passivation layers 805a and 805b such that the via holes 806a and 806b are aligned with the anode 804a and the cathode 804b, respectively, so that the anode 804a and the cathode 804b may be exposed from the passivation layers 805a and 805b.

[0107] At step 807 , a carrier substrate 807 a may be attached to the passivation layer 805 b in preparation for thinning the substrate.

[0108] At step 808, the back side 808a of the substrate 801a may be thinned such that the thickness of the substrate 801a is reduced (e.g., to a thickness of 20 μm, 30 μm, etc.), while the carrier substrate 807a is attached to the passivation layer 805b. In some embodiments, the substrate 801a may be thinned by a chemical-based etching (e.g., polishing via chemical mechanical polishing (CMP), dry etching, etc.) or grinding process. As discussed above, the thinned substrate allows the directionality of electrons to travel from the back side of the substrate 801a to the PIN diode without losing their energy or path direction within the intrinsic region.

[0109] At step 809, layer 809a (eg, Figure 4 Layer 421, Figure 5 The layer 521 of can be deposited on the back side 808a of the thinned substrate 801a. In some embodiments, the layer 809a can protect the substrate 801a and include a material that is substantially transparent to electrons (eg, SiN, thin metal, etc.).

[0110] In step 810, the carrier substrate 807a may be removed. In some embodiments, when the passivation layer 805b is included for mechanical support of the substrate thinning step, the passivation layer 805b may remain in the final detection element or may be removed.

[0111] The embodiments may also be described using the following terms.

[0112] 1. A detector, comprising:

[0113] Silicon substrate, thinned to 30μm or less thickness;

[0114] The front side of the silicon substrate includes a lateral PIN diode formed by a p-type implant and an n-type implant;

[0115] a region between the p-type implant and the n-type implant configured to form a depletion region when a reverse bias is applied between the p-type implant and the n-type implant;

[0116] A back side of the silicon substrate opposite the front side comprises a substantially uniform surface; and

[0117] a protective layer on the substantially uniform surface on the back side of the silicon substrate,

[0118] The lateral PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region.

[0119] 2. A detector according to clause 1, wherein the protective layer comprises a material that is substantially transparent to electrons.

[0120] 3. The detector of any of clauses 1 to 2, wherein the substantially uniform surface of the back side of the silicon substrate comprises an implanted dopant concentration of substantially zero.

[0121] 4. The detector of clause 3, wherein the silicon substrate comprises a dopant concentration greater than zero, wherein the dopant of the dopant concentration is a non-implanted dopant.

[0122] 5. The detector of clause 4, wherein the non-implanted dopant is added to the silicon substrate as the silicon substrate is formed.

[0123] 6. The detector according to any of clauses 1 to 5, wherein the substantially uniform surface of the back side of the silicon substrate is located between the front side and the protective layer.

[0124] 7. The detector according to any of clauses 1 to 6, wherein the back side of the silicon substrate comprises zero PIN diodes.

[0125] 8. The detector according to any of clauses 1 to 7, wherein the back side of the silicon substrate comprises zero anodes and zero cathodes.

[0126] 9. The detector according to any of clauses 1 to 8, wherein the back side of the silicon substrate is configured to be exposed to secondary electrons and the front side of the silicon substrate is configured not to be exposed to secondary electrons.

[0127] 10. The detector according to any of clauses 1 to 9, wherein the lateral PIN diode comprises an anode on the p-type implant and a cathode on the n-type implant.

[0128] 11. The detector according to clause 10, wherein the cathodes and the anodes are arranged to be interlaced with each other.

[0129] 12. The detector according to clause 10, wherein the cathode and the anode are concentrically arranged in a circular shape.

[0130] 13. The detector according to clause 10, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

[0131] 14. The detector of clause 10, wherein the lateral PIN diode is bonded to a readout integrated circuit via the cathode and the anode.

[0132] 15. A detector comprising:

[0133] A plurality of detection elements, wherein the detection elements of the plurality of detection elements include:

[0134] The silicon substrate includes:

[0135] a front side of the portion of the silicon substrate including a PIN diode, the PIN diode including a p-type region and an n-type region;

[0136] a back side of the portion of the silicon substrate opposite the front side comprising a substantially uniform surface; and

[0137] a layer on the back side of the portion of the silicon substrate;

[0138] in:

[0139] A region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and

[0140] The PIN diode is configured to detect electrons that enter the back side of the portion of the silicon substrate and pass through the portion of the silicon substrate to the depletion region.

[0141] 16. The detector of clause 15, wherein the layer comprises a material that is substantially transparent to electrons.

[0142] 17. The detector of any of clauses 15 to 16, wherein the portion of the silicon substrate has a thickness of 30 μm or less.

[0143] 18. The detector of any of clauses 15 to 17, wherein the substantially uniform surface of the back side of the portion of the silicon substrate comprises an implanted dopant concentration of substantially zero.

[0144] 19. The detector of clause 18, wherein the portion of the silicon substrate comprises a dopant concentration greater than zero, wherein the dopant of the dopant concentration is a non-implanted dopant.

[0145] 20. The detector of clause 19, wherein the non-implanted dopant is added to the portion of the silicon substrate as the portion of the silicon substrate is formed.

[0146] 21. A detector according to any of clauses 15 to 20, wherein the substantially uniform surface of the back side of the portion of the silicon substrate is located between the front side and the layer.

[0147] 22. The detector of any of clauses 15 to 21, wherein the back side of the portion of the silicon substrate comprises zero PIN diodes.

[0148] 23. The detector of any of clauses 15 to 22, wherein the back side of the portion of the silicon substrate comprises zero anodes and zero cathodes.

[0149] 24. The detector of any of clauses 15 to 23, wherein the back side of the portion of the silicon substrate is configured to be exposed to secondary electrons and the front side of the portion of the silicon substrate is configured not to be exposed to secondary electrons.

[0150] 25. The detector of any of clauses 15 to 24, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region.

[0151] 26. The detector according to clause 25, wherein the cathodes and the anodes are arranged to be interleaved with each other.

[0152] 27. The detector according to clause 25, wherein the cathode and the anode are concentrically arranged in a circular shape.

[0153] 28. The detector according to clause 25, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

[0154] 29. The detector of clause 25, wherein the PIN diode is coupled to a readout integrated circuit via the cathode and the anode.

[0155] 30. A detector, comprising a plurality of detection elements, wherein the detection elements in the plurality of detection elements comprise:

[0156] The silicon substrate includes:

[0157] a front side of the portion of the silicon substrate including a PIN diode, the PIN diode including a p-type region and an n-type region;

[0158] a back side of the portion of the substrate opposite the front side comprising a substantially uniform surface; and

[0159] a layer on the back side of the portion of the substrate;

[0160] in

[0161] A region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and

[0162] The PIN diode is configured to receive electrons incident on the back side of the portion of the substrate.

[0163] 31. A detector according to clause 30, wherein the layer comprises a material that is substantially transparent to electrons.

[0164] 32. A detector according to any of clauses 30 to 31, wherein the thickness of the portion of the substrate is 30 μm or less.

[0165] 33. A detector according to any of clauses 30 to 32, wherein the substantially uniform surface of the back side of the portion of the substrate comprises an implanted dopant concentration of substantially zero.

[0166] 34. The detector of clause 33, wherein the portion of the substrate comprises a dopant concentration greater than zero, wherein the dopant of the dopant concentration is a non-implanted dopant.

[0167] 35. The detector of clause 34, wherein the non-implanted dopant is added to the portion of the substrate as the portion of the substrate is formed.

[0168] 36. A detector according to any of clauses 30 to 35, wherein the substantially uniform surface of the back side of the portion of the substrate is located between the front side and the layer.

[0169] 37. A detector according to any of clauses 30 to 36, wherein the back side of the portion of the substrate comprises zero PIN diodes.

[0170] 38. A detector according to any of clauses 30 to 37, wherein the back side of the portion of the substrate comprises zero anodes and zero cathodes.

[0171] 39. A detector according to any of clauses 30 to 38, wherein the back side of the portion of the substrate is configured to be exposed to secondary electrons and the front side of the portion of the substrate is configured not to be exposed to secondary electrons.

[0172] 40. The detector of any of clauses 30 to 39, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region.

[0173] 41. A detector according to clause 40, wherein the cathodes and the anodes are arranged to be interlaced with each other.

[0174] 42. The detector according to clause 40, wherein the cathode and the anode are concentrically arranged in a circular shape.

[0175] 43. The detector of clause 40, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

[0176] 44. The detector of clause 40, wherein the PIN diode is coupled to a readout integrated circuit via the cathode and the anode.

[0177] 45. A detector, comprising a plurality of detection elements, wherein the detection elements in the plurality of detection elements comprise:

[0178] Parts of the substrate include:

[0179] a front side of the portion of the substrate including a p-type region and an n-type region, the p-type region and the n-type region forming a PIN diode;

[0180] a back side of the portion of the substrate opposite the front side comprising a substantially uniform surface;

[0181] in:

[0182] A region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and

[0183] The PIN diode is configured to receive electrons passing through the portion of the substrate from the back side of the portion of the substrate.

[0184] 46. ​​The detector of clause 45, wherein the portion of the substrate has a thickness of 30 μm or less.

[0185] 47. A detector according to any of clauses 45 to 46, wherein the substantially uniform surface of the back side of the portion of the substrate comprises an implanted dopant concentration of substantially zero.

[0186] 48. The detector of clause 47, wherein the portion of the substrate comprises a dopant concentration greater than zero, wherein the dopant of the dopant concentration is a non-implanted dopant.

[0187] 49. The detector of clause 48, wherein the non-implanted dopant is added to the portion of the substrate as the portion of the substrate is formed.

[0188] 50. A detector according to any of clauses 45 to 49, wherein the substantially uniform surface of the back side of the portion of the substrate is located between the front side and the layer.

[0189] 51. A detector according to any of clauses 45 to 50, wherein the back side of the portion of the substrate comprises zero PIN diodes.

[0190] 52. A detector according to any of clauses 45 to 51, wherein the back side of the portion of the substrate comprises zero anodes and zero cathodes.

[0191] 53. A detector according to any of clauses 45 to 52, wherein the back side of the portion of the substrate is configured to be exposed to secondary electrons and the front side of the portion of the substrate is configured not to be exposed to secondary electrons.

[0192] 54. The detector of any of clauses 45 to 53, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region.

[0193] 55. A detector according to clause 54, wherein the cathodes and the anodes are arranged to be staggered with each other.

[0194] 56. The detector of clause 54, wherein the cathode and the anode are concentrically arranged in a circular shape.

[0195] 57. The detector of clause 54, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

[0196] 58. The detector of clause 54, wherein the PIN diode is coupled to a readout integrated circuit via the cathode and the anode.

[0197] 59. A method of forming a detection element of a detector, the method comprising:

[0198] forming a PIN diode on the front side of the silicon substrate by implanting p-type dopants in the silicon substrate to form a p-type region and implanting n-type dopants in the silicon substrate to form an n-type region,

[0199] wherein the region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region;

[0200] thinning a back side of the silicon substrate opposite the front side, wherein the back side comprises a substantially uniform surface; and

[0201] forming a layer on the back side of the silicon substrate,

[0202] The PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region.

[0203] 60. The method of clause 59, further comprising: implanting the p-type dopant and the n-type dopant using a photoresist.

[0204] 61. The method of clause 60, further comprising depositing a metal layer on the p-type region and patterning the metal layer to form an anode, and depositing a metal layer on the n-type region and patterning the metal layer to form a cathode.

[0205] 62. The method of clause 61, wherein the cathodes and the anodes are arranged to be interleaved with each other.

[0206] 63. The method of clause 61, wherein the cathode and the anode are concentrically arranged in a circular shape.

[0207] 64. The method of clause 61, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

[0208] 65. The method of any of clauses 61 to 64, further comprising depositing a first passivation layer on the patterned metal layer and depositing a second passivation layer on the first passivation layer, the second passivation layer being thicker than the first passivation layer.

[0209] 66. The method of clause 65, further comprising patterning vias in the first passivation layer and the second passivation layer, wherein the vias are aligned with the cathode and the anode.

[0210] 67. The method of clause 66, further comprising attaching a carrier substrate to the second passivation layer.

[0211] 68. The method of clause 67, wherein thinning the back side of the silicon substrate comprises reducing the thickness of the silicon substrate to 30 μm or less while attaching the carrier substrate to the second passivation layer.

[0212] 69. The method of any of clauses 67 to 68, wherein thinning the back side of the silicon substrate comprises grinding or dry etching the back side of the silicon substrate.

[0213] 70. The method of any of clauses 59 to 69, further comprising depositing the layer on the back side of the silicon substrate after thinning the back side of the silicon substrate.

[0214] 71. A method according to any of clauses 59 to 70, wherein the layer comprises a material that is transparent to electrons.

[0215] 72. The method of any of clauses 67 to 71, further comprising: removing the carrier substrate.

[0216] 73. The method of any of clauses 59 to 72, wherein the substantially uniform surface of the back side of the substrate comprises an implant concentration of zero.

[0217] 74. The method of any of clauses 72 to 73, further comprising: bonding the PIN diode to a readout integrated circuit via the cathode and the anode.

[0218] 75. A detector formed by any one of clauses 59 to 74, the detector comprising:

[0219] A plurality of detection elements, wherein the detection elements of the plurality of detection elements include:

[0220] The silicon substrate includes:

[0221] a front side of the portion of the silicon substrate including a PIN diode, the PIN diode including a p-type region and an n-type region;

[0222] a back side of the portion of the silicon substrate opposite the front side comprising a substantially uniform surface; and

[0223] a layer on the back side of the portion of the silicon substrate;

[0224] in:

[0225] A region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and

[0226] The PIN diode is configured to detect electrons that enter the back side of the portion of the silicon substrate and pass through the silicon substrate to the depletion region.

[0227] It should be appreciated that the embodiments of the present invention are not limited to the exact constructions that have been described above and illustrated in the drawings, and that various modifications and changes may be made without departing from the scope of the present invention.

Claims

1. A detector, comprising: A plurality of detection elements, wherein the detection elements of the plurality of detection elements include: The silicon substrate includes: a front side of the portion of the silicon substrate including a PIN diode, the PIN diode including a p-type region and an n-type region; a back side of the portion of the silicon substrate opposite the front side comprising a substantially uniform surface; and a layer on the back side of the portion of the silicon substrate; in: A region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias voltage is applied between the p-type region and the n-type region, and The PIN diode is configured to detect electrons that enter the back side of the portion of the silicon substrate and pass through the portion of the silicon substrate to the depletion region.

2. The detector of claim 1, wherein the layer comprises a material that is substantially transparent to electrons. 3 . The detector according to claim 1 , wherein the thickness of the portion of the silicon substrate is 30 μm or less.

4. The detector of claim 1, wherein the substantially uniform surface of the backside of the portion of the silicon substrate comprises an implanted dopant concentration of substantially zero. 5 . The detector of claim 4 , wherein the portion of the silicon substrate comprises a dopant concentration greater than zero, wherein the dopant of the dopant concentration is a non-implanted dopant.

6. The detector of claim 5, wherein the non-implanted dopant is added to the portion of the silicon substrate as the portion of the silicon substrate is formed.

7. The detector of claim 1, wherein the substantially uniform surface of the back side of the portion of the silicon substrate is located between the front side and the layer.

8. The detector of claim 1, wherein the back side of the portion of the silicon substrate comprises zero PIN diodes.

9. The detector of claim 1, wherein the back side of the portion of the silicon substrate includes zero anodes and zero cathodes.

10. The detector of claim 1, wherein the back side of the portion of the silicon substrate is configured to be exposed to secondary electrons and the front side of the portion of the silicon substrate is configured not to be exposed to secondary electrons.

11. The detector of claim 1, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region.

12. The detector according to claim 11, wherein the cathode and the anode are arranged to be staggered with each other.

13. The detector according to claim 11, wherein the cathode and the anode are concentrically arranged in a circular shape.

14. The detector of claim 11, wherein the cathode and the anode are concentrically arranged in a hexagonal shape.

15. A method of forming a detection element of a detector, the method comprising: forming a PIN diode on the front side of the silicon substrate by implanting p-type dopants in the silicon substrate to form a p-type region and implanting n-type dopants in the silicon substrate to form an n-type region, wherein the region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias voltage is applied between the p-type region and the n-type region; thinning a back side of the silicon substrate opposite the front side, wherein the back side comprises a substantially uniform surface; as well as forming a layer on the back side of the silicon substrate, The PIN diode is configured to detect electrons that enter the back side of the silicon substrate and pass through the silicon substrate to the depletion region.

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