Chip batch testing method based on power supply switching, and its system, device, and medium

Abstract

The present application discloses a method and system, device, and medium for batch testing of chips based on power supply switching, which relates to the field of chip testing. The method includes: controlling all power switches to close according to the obtained power control instruction, and controlling the power supply module to output a first power supply voltage to the chips to be tested; according to the first test power supply signal corresponding to the first test list, controlling all test switches to close, controlling the power supply module to output a first test voltage to the chips to be tested, and performing a first parallel test based on the first test task on a batch of chips to be tested. After obtaining the first test result and encoding it, generating a first gating signal to determine the test objects of the second test task; continuing to simultaneously perform a second parallel test on the test objects based on the second test task. When all the test tasks in the first test list are completed, controlling the power supply module to switch and output a second test voltage to continue testing the second test list. It can automatically perform power supply switching and improve the testing efficiency of a batch of chips to be tested.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a method, system, device, and medium for batch testing of chips based on power supply switching. Background Art

[0002] Chip testing is an important stage in chip manufacturing to ensure chip quality. With the development of very large scale integrated circuits, due to the complexity of their design, ultra-large chips require more multiple testing processes to produce high-quality chips to meet customer needs.

[0003] Currently, different types of chips have different requirements for power supply voltages. For chips with specific power supply voltage requirements, a power supply output needs to be specifically configured to target the power supply voltage. When replacing chips with different power supply voltage requirements, it is necessary to re-determine the power supply voltage requirements of the chips to be tested and then configure the target power supply voltage required for the new power output. Moreover, in the testing process of a type of chip, different testing tasks are involved, and some of these testing tasks need to be carried out at different testing voltages. During the process of batch testing of the same type of chips, after each type of testing task is completed, it is necessary to manually adjust the output testing voltage or manually replace another power supply module to provide an appropriate testing voltage to prepare for the next testing task. Also, in batch testing, in the case where the test results of some chips are incorrect, it is necessary to manually cut off the power supply separately to remove the chips with incorrect test results, no longer conduct the subsequent tests on them, and continue to execute the next testing task to batch test the remaining chips. It can be seen that the power on / off and power supply switching in the current testing process all involve manual operations, the operations are complex, and the overall testing efficiency of batch testing of chips is relatively low. Summary of the Invention

[0004] This application aims to at least solve one of the technical problems existing in the prior art. For this purpose, this application proposes a method, system, device, and medium for batch testing of chips based on power supply switching, which can automatically perform power supply switching during the process of batch testing of chips and improve the testing efficiency of chips to be tested in batches.

[0005] In a first aspect, an embodiment of this application provides a method for batch testing of chips based on power supply switching, which is applied to the host computer of a testing system. The system further includes: a test board and a power supply module; the test board includes: a plurality of chips to be tested, a set of power switches and test switches provided corresponding to each chip to be tested; two output terminals of the power supply module are electrically connected to the chips to be tested through the power switches and the test switches respectively;

[0006] The method includes:

[0007] Obtain power control instructions and at least one test list from the first test configuration file; the test voltages required for test tasks under the same test list are the same; the test voltages required for test tasks under different test lists are different;

[0008] Control all the power switches to close according to the power control instructions, and control the power supply module to output a first power voltage to the chip under test;

[0009] Control all the test switches to close and control the power supply module to output a first test voltage to the chip under test according to the first test power supply signal corresponding to the first test list;

[0010] Simultaneously perform a first parallel test process based on the first test task on a batch of the chips under test to obtain a first test result code;

[0011] Determine the chips under test that pass the first test task as the test objects of the second test task according to the first gating signal generated based on the first test result code;

[0012] Continue to simultaneously perform a second parallel test process based on the second test task on the test objects. When all the test tasks in the first test list are completed, control the power supply module to switch and output a second test voltage to continue testing the second test list.

[0013] In a second aspect, an embodiment of the present application provides a test system, including: a host computer, a test board and a power supply module that are respectively communicatively connected to the host computer; the test board includes: a plurality of chips under test, a set of power switches and test switches provided corresponding to each chip under test; two output terminals of the power supply module are electrically connected to the chips under test through the power switches and the test switches respectively; the host computer is used to execute the chip batch test method based on power supply switching according to any one of the embodiments in the first aspect.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, including at least one processor and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the chip batch test method based on power supply switching according to any one of the embodiments in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions for causing a computer to execute the chip batch test method based on power supply switching according to any one of the embodiments in the first aspect.

[0016] Embodiments of the present application include: The test system includes: a host computer, a test board and a power supply module that are respectively communicatively connected to the host computer; the test board includes: a plurality of chips to be tested, a set of power switches and test switches provided corresponding to each chip to be tested; two output terminals of the power supply module are respectively electrically connected to the chips to be tested through the power switches and the test switches; during the process of batch testing of chips using this test system, first, through the host computer, obtain a power control instruction and at least one test list from a first test configuration file; the test voltages required for the test tasks under the same test list are the same; the test voltages required for the test tasks under different test lists are different; secondly, according to the power control instruction, control all the power switches to close, and control the power supply module to output a first power voltage to the chips to be tested; then, according to the first test power supply signal corresponding to the first test list, control all the test switches to close, and control the power supply module to output a first test voltage to the chips to be tested; then, simultaneously perform a first parallel test process based on the first test task on the batch of chips to be tested to obtain a first test result code; then, according to the first gating signal generated based on the first test result code, determine the chips to be tested that pass the first test task as the test objects of the second test task; finally, continue to simultaneously perform a second parallel test process based on the second test task on the test objects, and when all the test tasks in the first test list are completed, control the power supply module to switch and output a second test voltage to continue testing the second test list; automatically perform power supply switching and automatically test the next test list, improving the test efficiency. That is to say, the embodiments of the present application can automatically perform power supply switching during the process of batch testing of chips, improving the test efficiency of the batch of chips to be tested. Description of the Drawings

[0017] Figure 1 It is a schematic structural diagram of a test system for performing a chip batch test method based on power supply switching provided by an embodiment of the present application;

[0018] Figure 2 It is a schematic specific structural diagram of a test system provided by an embodiment of the present application;

[0019] Figure 3 It is a schematic step flow diagram of a chip batch test method with power supply switching provided by an embodiment of the present application;

[0020] Figure 4 It is a schematic diagram of a first test configuration file provided by an embodiment of the present application;

[0021] Figure 5 It is a schematic diagram of the specific process of a first parallel test process provided by an embodiment of the present application;

[0022] Figure 6 It is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0023] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0024] It should be noted that although the logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be executed in a sequence different from that in the flowchart. In the description of the present application, the meaning of "several" is one or more, and the meaning of "multiple" is two or more. The descriptions of "first" and "second" are only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0026] The present application provides a method and a test system, an electronic device, and a computer-readable storage medium for batch testing of chips based on power supply switching, which relate to the field of chip testing. The method includes: controlling all power switches to close according to the obtained power control instruction, and controlling the power supply module to output a first power supply voltage to the chips to be tested; according to the first test power supply signal corresponding to the first test list, controlling all test switches to close, controlling the power supply module to output a first test voltage to the chips to be tested, and performing a first parallel test on the batch of chips to be tested based on the first test task. After obtaining the first test result and encoding it, generating a first gating signal to determine the test objects of the second test task; continuing to simultaneously perform a second parallel test on the test objects based on the second test task. When all the test tasks in the first test list are completed, controlling the power supply module to switch and output a second test voltage to continue testing the second test list. It can automatically perform power supply switching and improve the test efficiency of the batch of chips to be tested.

[0027] The embodiments of the present application will be further described below with reference to the accompanying drawings.

[0028] As Figure 1 shown, the test system 100 includes: a host computer 110, a test board 130 and a power supply module 120 that are respectively communicatively connected to the host computer 110; the test board 130 includes: a plurality of chips to be tested, and a set of power switches K1 and test switches K2 provided corresponding to each chip to be tested; two output terminals of the power supply module 120 are respectively electrically connected to the chips to be tested through the power switches K1 and the test switches K2.

[0029] Specifically, the multiple chips to be tested on the test board 130 are arranged in M rows and N columns to improve the utilization rate of the test board 130.

[0030] Specifically, a plurality of chip bases for inserting chips to be tested are provided on the test board 130. Specifically, the specifications of the test board 130 can be expanded. As the surface area of the test board 130 increases, more chips to be tested can be inserted. Therefore, the embodiments of the present application do not specifically limit the size of the test board 130 and the number of chips to be tested.

[0031] Specifically, the two output terminals of the power supply module 120 are: a power supply voltage output terminal 121 and a test voltage output terminal 122. Among them, the power supply voltage output terminal 121 is electrically connected to the chip to be tested through a power switch K1, and the test voltage output terminal 122 is electrically connected to the chip to be tested through a test switch K2.

[0032] Specifically, there are different voltage levels in the power supply module 120, and voltages with different voltage values can be output according to needs. The present application does not specifically limit the voltage levels of the power supply module 120, which can be designed according to actual requirements.

[0033] Specifically, the chip to be tested, the power switch K1, and the test switch K2 can be arranged on the same surface of the test board 130; or the chip to be tested can be arranged on one surface of the test board 130, and the chip to be tested, the power switch K1 can be correspondingly arranged on another surface of the test board 130.

[0034] Specifically, the power switch K1 is used to control the on / off of the power supply path between the power supply module 120 and the chip to be tested, and the test switch K2 is used to control the on / off of the test path between the power supply module 120 and the chip to be tested.

[0035] As Figure 2 shown, the test system 100 further includes: an indication module and a camera module electrically connected to the host computer 110. The indication module includes a plurality of indicator lights, and the indicator light unit is used to indicate the test results of each corresponding chip to be tested; the camera module faces the indication module.

[0036] Specifically, an indicator light unit includes a red LED, a green LED, and a yellow LED. Therefore, an indicator light unit can emit red light, or green light, or yellow light. The different colors of light emitted by an indicator light unit are used to indicate different test results of a corresponding chip to be tested. In this way, the tester can timely discover the chips to be tested that fail the test or need to be retested through the indicator light unit, and quickly remove them for further verification.

[0037] Specifically, the arrangement of the indicator light units in the indication module is the same as the arrangement of the chips to be tested on the test board 130, and the indicator light units correspond to the chips to be tested one by one. When the power switch K1 corresponding to the chip to be tested is turned off, power cannot be supplied to the chip to be tested, and at the same time, power cannot be supplied to the corresponding indicator light unit, and the indicator light unit goes out.

[0038] Specifically, the imaging module takes pictures of the indication module, and can obtain an indicator light image, and record the test situation after completing a test task through the indicator light image; through the recorded different indicator light images, it is possible to quickly know the chip test situation after each test task is completed.

[0039] The host computer 110 is used to execute the chip batch testing method based on power supply switching provided in the embodiments of the present application, and control the power supply module 120, the power switch K1, the test switch K2, the chips to be tested, the indication module, and the imaging module to work together to achieve chip batch testing based on power supply switching, so that during the process of batch testing of chips, power supply switching can be automatically performed, and the testing efficiency of the batch of chips to be tested can be improved.

[0040] Those skilled in the art can understand that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or combine some components, or different component arrangements. The system architecture and application scenarios described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0041] Based on the above system structure, the following presents various embodiments of the chip batch testing method based on power supply switching of the present application.

[0042] As Figure 3 shown, the chip batch testing method based on power supply switching can be applied to a host computer as Figure 1 shown. The testing system further includes: a test board and a power supply module; the test board includes: a plurality of chips to be tested, a set of power switches and test switches corresponding to each chip to be tested; two output terminals of the power supply module are respectively electrically connected to the chips to be tested through the power switches and the test switches. The chip batch testing method based on power supply switching may include but is not limited to steps S110 to S160.

[0043] Step S110: Obtain a power control instruction and at least one test list from a first test configuration file; the test voltages required for the test tasks under the same test list are the same; the test voltages required for the test tasks under different test lists are different.

[0044] Step S120: Control all power switches to close according to the power control instruction, and control the power supply module to output a first power voltage to the chip under test.

[0045] Step S130: Control all test switches to close according to the first test power supply signal corresponding to the first test list, and control the power supply module to output a first test voltage to the chip under test.

[0046] Step S140: Simultaneously perform a first parallel test process based on the first test task on a batch of chips under test to obtain a first test result code.

[0047] Step S150: Determine the chips under test that pass the first test task as the test objects of the second test task according to the first gating signal generated based on the first test result code.

[0048] Step S160: Continue to simultaneously perform a second parallel test process based on the second test task on the test objects. When all the test tasks in the first test list are completed, control the power supply module to switch and output a second test voltage to continue testing the second test list.

[0049] Specifically, in the embodiment of the present application, a batch of chips under test connected on the test board are all of the same chip type.

[0050] Through steps S110 to S160, in the process of batch testing of chips using this test system, through the host computer, first, obtain the power control instruction and at least one test list from the first test configuration file; the test voltages required for the test tasks under the same test list are the same; the test voltages required for the test tasks under different test lists are different; secondly, control all power switches to close according to the power control instruction, and control the power supply module to output a first power voltage to the chip under test; then, control all test switches to close according to the first test power supply signal corresponding to the first test list, and control the power supply module to output a first test voltage to the chip under test; then, simultaneously perform a first parallel test process based on the first test task on a batch of chips under test to obtain a first test result code; then, determine the chips under test that pass the first test task as the test objects of the second test task according to the first gating signal generated based on the first test result code; finally, continue to simultaneously perform a second parallel test process based on the second test task on the test objects. When all the test tasks in the first test list are completed, control the power supply module to switch and output a second test voltage to continue testing the second test list; automatically perform power supply switching and automatically test the next test list, improving the test efficiency. Therefore, the embodiment of the present application can automatically perform power supply switching during the batch testing of chips and improve the test efficiency of a batch of chips under test.

[0051] Before step S110, according to some embodiments of the present application, before obtaining the power control instruction and at least one test list from the first test configuration file, the method further includes steps S210 to S250.

[0052] Step S210: Obtain the chip type of the chip under test input, and determine a candidate test task list and a power control instruction; wherein, the candidate test task list includes a plurality of different candidate tasks; the power control instruction is used to indicate the power supply voltage required for different chip types.

[0053] Step S220: In response to the task selection instruction, determine a plurality of test tasks to be executed from the plurality of candidate tasks.

[0054] Step S230: In response to the test plan creation instruction, determine the test voltage required for each test task; perform classification processing according to the test voltage, cluster the test tasks with the same test voltage to generate a test list, and obtain at least one test list; wherein, the test tasks under different test lists require different test voltages.

[0055] Step S240: Generate a corresponding test power supply signal according to the test voltage corresponding to each test list.

[0056] Step S250: In response to the configuration file creation instruction, generate a first test configuration file according to the power control instruction, at least one test list, and the test power supply signal corresponding to each test list.

[0057] In step S210, it can be understood that the power supply voltages required for different types of chips under test are different. For example, the VCC operating voltage range of the eMMC storage chip is 2.7V to 3.6V, and the typical operating voltage is 3.3V; for NAND Flash, VCC is usually 3.3V or 5V; the power supply voltage required for some chips for specific power management reaches 19V. Therefore, different power control instructions need to be generated based on different voltage requirements to control the power supply module to output the power supply voltages required for different chip types.

[0058] Specifically, if the first test configuration file is configured based on the chip of model A, the first power supply voltage is configured as Ua; if the second test configuration file is configured based on the chip of model B, the first power supply voltage is configured as Ub.

[0059] It can be understood that for different types of chips, there are different test purposes, so different test tasks need to be selected. Therefore, based on the pre-entered mapping relation table, which is used to represent the mapping relation between the chip type and the candidate test task list, when the tester inputs the chip type of the chip to be tested on the host computer, based on this mapping relation table, a candidate test task list is recommended to facilitate the tester to select the required test tasks. The candidate test task list includes multiple different candidate tasks, which can all be pre-configured. Therefore, this application does not make specific restrictions on the chip type and the corresponding candidate test task list.

[0060] In step S220, the tester makes a task selection through a click operation to generate a task selection instruction, and the host computer determines multiple test tasks to be executed in response to this task selection instruction, laying a foundation for generating the first test configuration file.

[0061] In step S230, after selecting the test tasks to be executed, the required test voltages for different test tasks may be different or the same. For example: Specifically, when performing read / write performance testing on a chip, different reference voltages are required to ensure the accuracy and reliability of the test; based on different reference voltage requirements, the read / write performance test is split into different test tasks with different test voltage requirements. Therefore, in order to reduce the switching frequency of the test voltage, during the process of creating a test plan, all the test tasks to be executed are classified based on the test voltages required for each test task, so that the test tasks under one test list require the same test voltage, while the test tasks between different test lists require different test voltages.

[0062] In step S240, corresponding test power supply signals are generated based on the different test voltages required for each test list, so as to control the power supply module to output the required test voltage when executing the test tasks in the test list.

[0063] Through step S250, the generated first test configuration file is as Figure 4 shown, providing a reference for subsequent chip testing.

[0064] Through steps S210 to S250, the first test configuration file is generated according to the actual test requirements, providing a reference for subsequent automatic batch testing of chips.

[0065] To further illustrate steps S110 to S130, specifically, in response to a test start instruction, according to the power control instructions, at least one test list, and the test power supply signals corresponding to the test list obtained from the first test configuration file, first, control all power switches to close, and control the power supply module to output a first power voltage to the chips under test to ensure that each chip under test and the indicator light units corresponding to each test chip are normally started, preparing for the test; then, control all test switches to close and control the power supply module to output a first test voltage to the chips under test, thereby creating a test environment and preparing for batch testing of the chips under test.

[0066] According to some embodiments of the present application, step S140 is further illustrated. Step S140 includes but is not limited to steps S310 to S350.

[0067] Step S310: Simultaneously control a batch of chips under test to execute the first test task in the first test list, and generate an initial code according to the preset first coding rule and the initial test results of each chip under test.

[0068] Step S320: When the initial code includes a code value of 2, subtract 1 from all non-zero code values in the initial code to obtain a retest control signal; wherein, the retest control signal includes: a high-level signal and a low-level signal.

[0069] Step S330: Close the corresponding test switch in response to the high-level signal of the retest control signal, and disconnect the corresponding test switch in response to the low-level signal of the retest control signal to determine the retest objects.

[0070] Step S340: Perform parallel retest processing on the retest objects based on the first test task to obtain the final retest results of each retest object.

[0071] Step S350: Generate a first test result code according to the preset second coding rule, the final retest results of each retest object, and the initial code, and end the first parallel test process.

[0072] According to some embodiments of the present application, step S310 is further illustrated. Among them, generating an initial code according to the preset first coding rule and the initial test results of each chip under test includes but is not limited to steps S311 to S312.

[0073] Step S311: Obtain the first coding rule, where the first coding rule is: when the initial test result is: test passed, determine the corresponding code value as 1; when the initial test result is: test failed, determine the corresponding code value as 0; when the initial test result is: retest required, determine the corresponding code value as 2.

[0074] Step S312: According to the chip arrangement order on the test board, sequentially obtain the initial test results of the chips to be tested one by one for encoding, and obtain the initial encoding.

[0075] Specifically, when performing the first test task on the chip to be tested, there are different test situations, such as: test passed, test failed, test timeout, test case crashed, etc.; when situations such as test timeout and test case crashed occur, the test is not completed and there is no definite test result (test passed or test failed). Therefore, generally, the chip to be tested needs to be retested. So, in this application, when situations such as test timeout and test case crashed occur, the test result is determined to be: retest required. Based on different test results, a first encoding rule is pre-configured.

[0076] Take an example to illustrate steps S311 to S312. Example 1: Complete the first test task for the chip to be tested U0, the chip to be tested U1, the chip to be tested U2, and the chip to be tested U3, and obtain the initial test results of each chip to be tested. As Figure 5 shown, when the initial test result of the chip to be tested U0 is: test passed, the corresponding code value is determined to be 1; when the initial test result of the chip to be tested U1 is: test failed, the corresponding code value is determined to be 0; when the initial test result of the chip to be tested U2 is: retest required, the corresponding code value is determined to be 2; when the initial test result of the chip to be tested U3 is: retest required, the corresponding code value is determined to be 2; the initial test result of the chip to be tested U4 is: retest required, the corresponding code value is determined to be 2; sequentially splice the code values corresponding to each chip to be tested in the order of the chips to be tested to obtain the initial encoding: 10222.

[0077] Through steps S311 to S312, an initial encoding representing the test situations of each chip to be tested is generated, providing a reference for generating a retest control signal for retest processing later.

[0078] Specifically, step S140 further includes: after generating the initial encoding according to the preset first encoding rule and the initial test results of each chip to be tested, if the initial encoding does not include the code value 2, it can be determined that there is no chip to be tested that needs to be retested in the batch of chips to be tested; the first parallel test process can be directly ended, and the initial encoding can be directly output as the first test result encoding.

[0079] To further illustrate steps S320 to S330, specifically, if the initial code includes the code value 2, it can be determined that there are chips to be retested among the batch of chips to be tested. At this time, all non-zero code values in the initial code need to be decremented by 1 to obtain a retest control signal; the retest control signal includes high-level signals with an amplitude of 1 and low-level signals with an amplitude of 0. Then, in response to the high-level signal, the corresponding test switch is closed to determine that the corresponding chip to be tested needs to be retested; in response to the low-level signal, the corresponding test switch is opened to determine that the corresponding chip to be tested does not need to be retested. After traversing the level signals in the retest control signal, the retest objects are determined; the chips to be tested that pass or fail the test are all non-retest objects.

[0080] Take an example to illustrate steps S320 to S330. Example 2, as Figure 5 shown, the initial code obtained through Example 1 is: 10222. Then it is determined that there are chips to be retested. At this time, all non-zero code values in the initial code are decremented by 1 to obtain a retest control signal: 00111. Correspondingly, based on the retest control signal 0011, the chips to be tested U2, U3, and U4 are determined as retest objects.

[0081] According to some embodiments of the present application, steps S340 are further illustrated. Step S340 includes but is not limited to steps S341 to S343.

[0082] Step S341: Based on the first test task, retest the retest objects simultaneously to obtain the current retest results of each retest object.

[0083] Step S342: When the current retest result indicates that there are still retest objects that need to be retested and the number of retests is less than the number threshold, perform the retest process again to obtain a new current retest result.

[0084] Step S343: When the current retest result indicates that there are no retest objects that need to be retested, or when the number of retests is equal to the number threshold, end the parallel retest process and determine the final retest results of each retest object based on the last obtained retest results.

[0085] To further illustrate step S341, when the retest process of the retest objects based on the first test task is completed, there are also different test situations, such as: passing the test, failing the test, timing out during the test, the test case crashing, etc. Specifically, in the case of a test timeout, the test case crashing, etc., it is determined that the retest result is: need to be retested; the retest results also include: passing the test, failing the test. After the retest process is completed, the current retest results of each retest object are obtained, providing a reference for the next retest process.

[0086] Specifically, although setting the retest process can improve the reliability of batch testing, the retest process cannot be carried out indefinitely. Therefore, a number threshold is set to limit the number of executions of the retest process, ensuring the smooth continuation of the overall batch testing while improving the reliability.

[0087] Specifically, the number threshold can be pre-configured as needed, and the present application does not make specific restrictions on the value of the number threshold.

[0088] To further illustrate steps S342 to S343, if the current retest result indicates that there are still retest objects that need to be retested and the number of retests is less than the number threshold, then the retest process is carried out again to obtain a new current retest result; until the latest current retest result indicates that there are no retest objects that need to be retested or the number of retests is equal to the number threshold, the parallel retest process is ended, and the final retest results of each retest object are determined based on the last obtained retest result, thereby providing a reference for generating the final first test result code.

[0089] Specifically, the final retest result is one of the following: test passed, test failed, retest required.

[0090] Through steps S341 to S343, the chips to be tested can be automatically retested, improving the reliability of the test results of the automatically carried out batch testing.

[0091] To further illustrate step S350, the preset second coding rule is as follows: when the final retest result is "test passed", the corresponding code value 2 in the initial code is modified to code value 1; when the final retest result is "test passed", the corresponding code value 2 in the initial code is modified to code value 0; when the final retest result is "retest required", the corresponding code value 2 in the initial code is not modified; based on the preset second coding rule and the final retest results of each retest object, the initial code is modified to obtain the first test result code, laying a foundation for determining the test objects of the second test task by generating the first gating signal subsequently.

[0092] Take an example to illustrate steps S341 to S343 and step S350. Example 3: Based on Example 1 and Example 2, determine that the chips to be tested U2, U3, and U4 are objects for retesting. Based on the first test task, simultaneously perform the first retest on the chips to be tested U2, U3, and U4. The current retest result of the chip to be tested U2 is that the test passes; the current retest result of the chip to be tested U3 is: retest required; the current retest result of the chip to be tested U4 is: retest required. According to the current retest results, determine that the chips to be tested U3 and U4 are new objects for retesting. Based on the first test task, simultaneously perform the second retest on the chips to be tested U3 and U4. The current retest result of the chip to be tested U3 is: the test fails; the current retest result of the chip to be tested U4 is: retest required. If the number threshold is 2, end the parallel retest process. Based on the retest results obtained last time, as Figure 5 shown, determine the final retest results of each retest object: the final retest result of the chip to be tested U2 is that the test passes, the final retest result of the chip to be tested U3 is that the test fails, and the final retest result of the chip to be tested U4 is: retest required. Then, modify the initial code 10222 obtained through Example 1 based on the preset second coding rule, and the obtained first test result code is: 10102 (corresponding to: the chips to be tested U0, U1, U2, U3, and U4 respectively).

[0093] Through steps S310 to S350, complete the first parallel test process based on the first test task for a batch of chips to be tested, obtain the first test result code, and lay a foundation for determining the test objects of the second test task by generating the first gating signal subsequently.

[0094] According to some embodiments of the present application, the test system further includes: an indication module and a camera module electrically connected to the upper computer. The indication module includes a plurality of indicator lights, and the indicator light unit is used to indicate the test results of each corresponding chip to be tested; the camera module faces the indication module. The method for batch testing of chips based on power supply switching according to the embodiments of the present application further includes but is not limited to steps S410 to S450.

[0095] Step S410: After each test task is completed, generate an indicator light control signal according to the test result code of the test task; the indicator light control signal includes at least one of the following: a first level signal with an amplitude of 0, a second level signal with an amplitude of 1, and a third level signal with an amplitude of 2.

[0096] Step S420: In response to the first level signal, control the corresponding indicator light unit to turn on a red light.

[0097] Step S430: In response to the second level signal, control the corresponding indicator light unit to turn on a green light.

[0098] Step S440: In response to the third level signal, control the corresponding indicator light unit to emit yellow light.

[0099] Step S450: Control the camera module to face the indicator module to capture an image of the indicator light, and save the image of the indicator light; the image of the indicator light is used to represent the test situation of a test task.

[0100] For step S410, specifically, for each completed test task, a test result code will be generated accordingly. Specifically, after completing the first test task in the first test list, the first test result code is obtained correspondingly; after completing the second test task in the first test list, the second test result code is obtained correspondingly, and so on.

[0101] Through steps S420 to S450, after obtaining the test result code, convert the test result code into an indicator light control signal. In response to the first level signal, control the corresponding indicator light unit to emit red light to prompt the tester that the first test task of the corresponding chip under test fails; in response to the second level signal, control the corresponding indicator light unit to emit green light to prompt the tester that the first test task of the corresponding chip under test passes; in response to the third level signal, control the corresponding indicator light unit to emit yellow light to prompt the tester that the number of retest processes for the corresponding chip under test based on the first test task exceeds the number threshold and manual assistance for detection is required. By controlling the indicator light unit to emit different colors of light, prompt the tester to promptly discover the chips under test that fail the test or need to be retested, and quickly remove them for further verification.

[0102] It should be noted that for the chips under test that fail the first test task and the number of retest processes based on the first test task exceeds the number threshold, the embodiments of the present application will no longer continue to perform the second test task on them. Instead, the tester will remove the chips under test that fail the first test task and the number of retest processes based on the first test task exceeds the number threshold for further maintenance.

[0103] Through step S450, for each completed test task, and based on the indicator light control signal converted from the test result code, after controlling the indicator module to complete its work, control the camera module to face the indicator module to capture an image of the indicator light, and save the image of the indicator light, so as to record the test situation of the chips under test in each test task.

[0104] Through steps S410 to S450, visually display the test situation of each chip under test in each test task through the indicator module, and record the test situation of each chip under test in each test task through the camera module, so as to facilitate subsequent verification of the batch test situation.

[0105] To further illustrate step S150, step S150 includes but is not limited to steps S151 to S153:

[0106] Step S151: Obtain a preset third coding rule, where the third coding rule is: modify all code values of 2 to code values of 0.

[0107] Step S152: Modify the first test result coding based on the preset third coding rule to obtain a first gating signal. The first gating signal includes a low-level signal with an amplitude of 0 and a high-level signal with an amplitude of 1.

[0108] Step S153: In response to the low-level signal of the first gating signal, disconnect a group of power switches and test switches of the corresponding chip under test; in response to the high-level signal of the first gating signal, close a group of power switches and test switches of the corresponding chip under test. Thus, for the chips under test that fail the first test task and whose retest processing times based on the first test task exceed the threshold, the second test task is no longer continued; the remaining chips under test that pass the first test task are determined as the test objects for the second test task.

[0109] It should be noted that when the power switch is disconnected, the power supply module will no longer provide the power supply voltage for the corresponding chip under test, shutting down the test chip; at the same time, the indicator unit corresponding to the chip under test will also be turned off and extinguished. At the same time, disconnect the test switches of the chips under test that do not participate in the second test task to avoid incorrect input of the output test voltage to the chips under test and damaging the chips under test.

[0110] Steps S151 to S153 automatically determine the test objects for the second test task, laying a foundation for the subsequent second test task.

[0111] During the subsequent second test task, since the first power supply voltage required in the first test configuration file remains unchanged, the power supply voltage output terminal of the power supply module is controlled to continuously output the first power supply voltage; since the test voltages required for different test tasks in the same test list are the same, during the execution of the second test task, the test voltage output terminal of the power supply module is controlled to continuously output the first test voltage.

[0112] To further illustrate step S160, step S160 includes but is not limited to:

[0113] First, perform a second parallel test process based on the second test task on the test objects determined through step S153 to obtain a second test result coding. The specific process of the second parallel test process is the same as the specific process of performing the first parallel test process. Refer to the embodiment regarding step S140 and will not be elaborated here.

[0114] Next, modify the second test result encoding based on a preset third encoding rule to obtain a second strobe signal; based on the second strobe signal, determine the chips under test that have passed the first test task as the test objects for the third test task. The specific processes of generating the second strobe signal and determining the test objects for the third test task are the same as those in the embodiment of step S150, and will not be elaborated here.

[0115] Then, continue with the third test task until all the test tasks in the first test list are completed.

[0116] Then, automatically control the power supply module to switch the output to the second test voltage and continue testing the second test list.

[0117] According to some embodiments of the present application, step S160 is further described. Among them, controlling the power supply module to switch the output to the second test voltage and continue testing the second test list includes, but is not limited to, steps S161 to S165.

[0118] Step S161: Sequentially obtain the second test list and the second test voltage corresponding to the second test list.

[0119] Step S121: Determine the chips under test that have passed all the test tasks in the first test list as the new chips under test, control the test switches of the new chips under test to close, and control the power supply module to output the second test voltage to the chips under test; disconnect the power switches and test switches of the remaining chips except the new chips under test.

[0120] Step S163: For the new chips under test, simultaneously perform the first parallel test process of the first test task based on the second test list to obtain the first test result encoding.

[0121] Step S164: According to the first strobe signal generated based on the first test result encoding, determine the chips under test that have passed the first test task as the test objects for the second test task.

[0122] Step S165: Continue to simultaneously perform the second parallel test process of the second test task on the test objects until all the test tasks in the second test list are completed.

[0123] The test of the second test list is completed through steps S161 to S165.

[0124] Specifically, the test process based on the second test list implemented through steps S161 to S165 is the same as the test process based on the second test list implemented through steps S110 to S160, and will not be elaborated here.

[0125] Specifically, when all the test lists in the first test configuration file are executed, the chip batch testing method based on power supply switching in the embodiments of the present application is completed. Specifically, when executing another test configuration file (such as the second test configuration file), the power supply voltage output by the power supply module needs to be automatically switched; when executing a new test list of a test configuration file, the test voltage output by the power supply module needs to be automatically switched. There are different voltage levels in the power supply module, and voltages with different voltage values can be output according to needs.

[0126] As Figure 6 shown, the present application also provides an electronic device, including:

[0127] A processor 601, which can be implemented by means of a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc., and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present application;

[0128] A memory 602, which can be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory, etc. The memory 602 can store an operating system and other application programs. When implementing the technical solutions provided by the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 602 and are called by the processor 601 to execute the chip batch testing method based on power supply switching in the embodiments of the present application;

[0129] An input / output interface 603, which is used to implement information input and output;

[0130] A communication interface 604, which is used to implement communication interaction between this device and other devices, and can implement communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0131] A bus 605, which transmits information between various components of the device (such as the processor 601, the memory 602, the input / output interface 603, and the communication interface 604);

[0132] Among them, the processor 601, the memory 602, the input / output interface 603, and the communication interface 604 are communicatively connected to each other inside the device through the bus 605.

[0133] The embodiments of the present application also provide a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, it implements the above-mentioned chip batch testing method based on power supply switching.

[0134] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely located relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] Those of ordinary skill in the art will understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0136] The above is a specific description of the preferred embodiments of this application, but this application is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of this application, and these equivalent deformations or substitutions are all included within the scope defined by this application.

Claims

1. A chip batch testing method based on power supply switching, characterized in that: The host computer used in the test system further comprises: a test board and a power supply module; the test board comprises: a plurality of chips to be tested, a group of power switches and a test switch corresponding to each chip to be tested; two output ends of the power supply module are electrically connected to the chip to be tested through the power switch and the test switch respectively; The method comprises: Obtaining a power control instruction and at least one test list from a first test configuration file; the test voltages required for the test tasks under the same test list are the same; the test voltages required for the test tasks under different test lists are different; Controlling all the power switches to close according to the power control instruction, and controlling the power supply module to output a first power supply voltage to the chip under test; According to the first test power supply signal corresponding to the first test list, control all the test switches to close and control the power supply module to output the first test voltage to the chip to be tested; Simultaneously, a first parallel test process based on a first test task is performed on the batch of chips to be tested to obtain a first test result code; According to a first selection signal generated based on the first test result code, determining the chip under test that passes the first test task as a test object of a second test task; Continue to perform a second parallel test process based on the second test task on the test object at the same time, and when all the test tasks in the first test list are completed, control the power supply module to switch to output a second test voltage to continue testing the second test list; The simultaneously performing a first parallel test process based on a first test task on the batch of chips to be tested to obtain a first test result code includes: At the same time, the batch of chips to be tested are controlled to execute the first test task in the first test list, and an initial code is generated according to a preset first coding rule and an initial test result of each chip to be tested; When the initial code includes a code value of 2, all code values ​​in the initial code that are not 0 are subtracted by 1 to obtain a retest control signal; wherein the retest control signal includes: a high level signal and a low level signal; In response to a high level signal of the retest control signal, the corresponding test switch is closed, and in response to a low level signal of the retest control signal, the corresponding test switch is opened to determine a retest object; Performing parallel retest processing on the retest objects based on the first test task to obtain final retest results of each of the retest objects; A first test result code is generated according to a preset second coding rule, a final retest result of each of the retest objects, and the initial code, and the first parallel test process is ended.

2. The chip batch testing method based on power supply switching according to claim 1 is characterized in that: The generating the initial code according to the preset first coding rule and the initial test results of each of the chips to be tested includes: Obtain the first coding rule, the first coding rule is: when the initial test result is: the test passed, the corresponding code value is determined to be 1; when the initial test result is: the test failed, the corresponding code value is determined to be 0; when the initial test result is: retest is required, the corresponding code value is determined to be 2; According to the chip arrangement order on the test board, the initial test results of the chips to be tested are obtained one by one in sequence and encoded to obtain the initial code.

3. The chip batch testing method based on power supply switching according to claim 1 is characterized in that: The performing parallel retest processing on the retest objects based on the first test task to obtain final retest results of the retest objects includes: Retest the retest objects based on the first test task at the same time to obtain current retest results of each of the retest objects; When the current retest result indicates that there are still retest objects that need to be retested, and the number of retests is less than the number threshold, the retest process is performed again to obtain a new current retest result; When the current retest result indicates that no retest object needs to be retested, or when the number of retests is equal to the number threshold, the parallel retest process is terminated, and a final retest result of each retest object is determined based on the last retest result obtained.

4. The chip batch testing method based on power supply switching according to claim 1 is characterized in that: The test system further comprises: an indication module and a camera module electrically connected to the host computer, the indication module comprising a plurality of indicator light units, the indicator light units being used to indicate the test result of each corresponding chip to be tested; the camera module is oriented toward the indication module; The method further comprises: Each time a test task is completed, an indicator light control signal is generated according to the test result code of the test task; the indicator light control signal includes at least one of the following: a first level signal with an amplitude of 0, a second level signal with an amplitude of 1, and a third level signal with an amplitude of 2; In response to the first level signal, controlling the corresponding indicator light unit to light up red; In response to the second level signal, controlling the corresponding indicator light unit to light up green; In response to the third level signal, controlling the corresponding indicator light unit to light up yellow; The camera module is controlled to shoot an indicator light image toward the indication module, and the indicator light image is saved; the indicator light image is used to represent the test situation of a test task.

5. The chip batch testing method based on power supply switching according to claim 1, characterized in that: Before acquiring the power control instruction and at least one test list from the first test configuration file, the method further includes: Obtaining the chip type of the chip to be tested as input, and determining a candidate test task list and a power control instruction; wherein the candidate test task list includes a plurality of different candidate tasks; and the power control instruction is used to indicate the power supply voltage required for different chip types; In response to a task selection instruction, determining a plurality of test tasks to be executed from the plurality of candidate tasks; In response to a test plan creation instruction, the test voltage required for each of the test tasks is determined; classification processing is performed according to the test voltages, and the test tasks with the same test voltages are clustered to generate a test list to obtain at least one test list; wherein the test voltages required for the test tasks under different test lists are different; Generate a corresponding test power supply signal according to the test voltage corresponding to each of the test lists; In response to the configuration file creation instruction, the first test configuration file is generated according to the power control instruction, the at least one test list, and the test power supply signal corresponding to each test list.

6. The chip batch testing method based on power supply switching according to any one of claims 1 to 5, characterized in that: The controlling the power supply module to switch to output the second test voltage to continue testing the second test list includes: sequentially acquiring a second test list and a second test voltage corresponding to the second test list; Determine the chip to be tested that has passed all the test tasks in the first test list as a new chip to be tested, control the test switch of the new chip to be tested to close, and control the power supply module to output a second test voltage to the chip to be tested; and disconnect the power switches and the test switches of the remaining chips except the new chip to be tested; Performing a first parallel test process on the new chip to be tested based on the first test task in the second test list at the same time to obtain a first test result code; According to a first selection signal generated based on the first test result code, determining the chip under test that passes the first test task as a test object of a second test task; Continue to perform the second parallel test processing based on the second test task on the test object at the same time until all the test tasks in the second test list are completed.

7. A testing system, characterized in that: include: A host computer, a test board and a power supply module respectively connected to the host computer for communication; The test board comprises: a plurality of chips to be tested, and a group of power switches and test switches corresponding to each chip to be tested; The two output ends of the power supply module are electrically connected to the chip to be tested through the power switch and the test switch respectively; the host computer is used to execute the chip batch testing method based on power supply switching as described in any one of claims 1 to 6.

8. An electronic device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the chip batch testing method based on power supply switching as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the chip batch testing method based on power supply switching according to any one of claims 1 to 6.

Images