RGMII Ethernet interface time sequence processing circuit and method based on lookup table

Abstract

The invention discloses an RGMII Ethernet interface time sequence processing circuit and method based on a lookup table, and the circuit and method are applied to an FPGA, and the FPGA comprises a time delay module and a time delay control module. RGMII input signals are respectively connected to six external signal pins of the FPGA; wherein the six external signal pins are respectively connected to an input signal end of the delay module. Five groups of time delay units are arranged in the time delay module and are respectively used for delaying five-bit signals input by the time delay module; each delay unit corresponds to seven delay selection signal ends and is used for selecting eight lookup tables in the delay units, delay TAPs corresponding to different selected lookup tables are different, and delay values corresponding to different delay TAPs are different; and a delay selection signal end of the delay module is connected to the delay control module. According to the invention, the time sequence adjustment of the RGMII Ethernet interface can be completed.

Description

Technical Field

[0001] The present invention relates to the technical field of power communication, and in particular to a RGMII Ethernet interface timing processing circuit and method based on a lookup table. Background Art

[0002] In the power system, communication interfaces based on Ethernet technology are distributed throughout various secondary intelligent devices and test systems, such as the Ethernet interface for sending SV data of the merging unit, the Ethernet interface for receiving and sending SV and GOOSE data of the protection device, and the Ethernet interface of the simulation process layer and the Ethernet interface of the interval layer in the test system, which will use Ethernet communication in large quantities. Generally speaking, the Ethernet interface consists of chips such as the PHY chip that implements the physical layer and the MAC controller of the link layer. The secondary test equipment of the power system with FPGA as the main carrier of the core MAC controller often needs to have more than 8 or even up to 24 Ethernet interfaces. The RGMII (Reduced GigabitMedia Independant Interface) interface is generally used between the physical layer PHY chip and the FPGA chip. The RGMII interface uses source clock synchronization technology, that is, a clock chip follows 4 data signals and 1 control signal, and the rising and falling edges of each clock cycle transmit data simultaneously, thereby achieving the ability to transmit high-speed bandwidth with a few signals. In Gigabit Ethernet mode, the clock frequency is generally 125Mhz, and the four data signals transmit data on both edges of the clock, that is, 125Mhz*4*2=1000 Mbps.

[0003] Based on the source clock synchronization and dual-edge data transmission characteristics of RGMII, for FPGA reception, it is necessary to correctly capture the interface data. Generally, two methods are used. Method 1: For high-end FPGAs with IO receiving delay units (IDELAY), the delay of the IO receiving delay unit is adjusted to achieve the purpose of correct sampling of synchronous clock and data; Method 2: The static timing constraint method is used to inform the FPGA synthesis software of the phase relationship between the clock and data of the RGMII interface, and the FPGA synthesis software automatically debugs the internal wiring delay to achieve the purpose of correct sampling of synchronous clock and data. Although the above two methods can effectively achieve the purpose of correct sampling, high-end FPGAs with IO receiving delay units are only available on high-end devices of Xilinx, and low-end FPGAs or domestic FPGAs do not have such modules; when the number of interfaces is small and the wiring resources are not so congested, the static timing constraint method can also be sampled normally, but when there are up to 8 Ethernet interfaces or even more, the static timing method is often difficult to have a good timing convergence effect, and some Ethernet interfaces cannot be sampled normally.

[0004] In view of this, it is necessary to design a new circuit and method to enable FPGA to correctly capture the data of the RGMII interface. Summary of the invention

[0005] The purpose of the present invention is to provide a timing processing circuit and method for an RGMII Ethernet interface based on a lookup table, which can complete the timing adjustment of the RGMII Ethernet interface.

[0006] The technical solution provided by this application is:

[0007] A RGMII Ethernet interface timing processing circuit based on a lookup table is applied to an FPGA, wherein the FPGA comprises: a delay module and a delay control module;

[0008] The RGMII input signal includes a source synchronous clock signal RGMII_CLK, a four-bit input data signal RGMII_RXD, and an input data valid signal RGMII_RXEN, which are respectively connected to six external signal pins of the FPGA; wherein the six external signal pins are: RGMII_RXCLK_PIN, RGMII_RXD[3:0]_PIN, RGMII_RXEN_PIN;

[0009] RGMII_RXD[3:0]_PIN are connected to the input signal terminal DIN[3:0] of the delay module respectively;

[0010] RGMII_RXEN_PIN is connected to the input signal terminal DIN[4] of the delay module;

[0011] The delay module has 5 groups of delay units inside, which are respectively used to delay the 5-bit signal input by the input signal terminal DIN[4:0]; each delay unit includes 8 lookup tables; each delay unit corresponds to 7 delay selection signal terminals of the delay module, which are used to select the 8 lookup tables of the delay unit; different lookup tables have different delay TAPs, and different delay TAPs have different delay values;

[0012] The five groups of delay units correspond to 35 delay selection signal terminals DSEL[34:0] of the delay module, and the delay selection signal terminal DSEL[34:0] of the delay module is connected to the delay control module; the delay control module provides a 35-bit delay selection signal, and each 7-bit delay selection signal controls an input signal of the delay module;

[0013] Among them, [n:0] represents the nth to 0th bit.

[0014] In a possible implementation, the correspondence between the delay selection signal, the selected lookup table, the delay TAP and the delay value is shown in the following table:

[0015]

[0016] Among them, LUT-1~LUT-8 represent the 1st to 8th lookup tables respectively, and the symbol / represents and.

[0017] In a possible implementation, the FPGA further includes: a sampling module; the output signal terminal DOUT[4:0] of the delay module is respectively connected to the input signal terminal DIN[4:0] of the sampling module, so that the sampling module receives the front-end delayed data RGMII_RXD_DELAY[3:0] and RGMII_RXEN_DELAY as 5 input data;

[0018] The synchronous clock of the sampling module is connected to RGMII_RXCLK_PIN;

[0019] The output signal terminals QOUT_L[3:0] and QOUT_H[3:0] of the sampling module respectively output the double-delayed sampling data of RGMII_RXD_DELAY[3:0] as the RGMII output data signals RGMII_RXDATA[7:4] and RGMII_RXDATA[3:0]; the output signal terminal QOUT_H[4] of the sampling module outputs the double-delayed sampling data of RGMII_RXEN_DELAY as the RGMII output data valid signal RGMII_RXDATAEN.

[0020] RGMII_RXDATA[7:0] and RGMII_RXDATAEN can be used as the back-end module Ethernet to receive data.

[0021] In one possible implementation, there are 5 groups of independent and identical sampling units inside the sampling module; each input data enters a separate sampling unit to complete the double-delay data to single-edge data output; there are three independent D flip-flops inside the sampling unit, namely D-FF-0, D-FF-1 and D-FF-2, among which D-FF-0 is used to sample the rising edge data of the input data, D-FF-1 is used to sample the falling edge data of the input data, and D-FF-2 synchronizes the falling edge data to the rising edge and outputs it.

[0022] In a possible implementation, the sampling module output signal terminals RGMII_RXDATA[7:0] and RGMII_RXDATAEN are connected to the delay control module as input judgment signals of the delay control module;

[0023] The clock input signal of the delay control module is RGMII_RXCLK_PIN, the input signal terminal RGMII_DIN[7:0] of the delay control module is connected to RGMII_RXDATA[7:0], and the input signal terminal RGMII_DEN of the delay control module is connected to RGMII_RXDATAEN; in the delay control module, the input signal is synchronously analyzed to see whether it is sampled correctly, and the value of the delay selection signal is adjusted to achieve correct dual-edge sampling.

[0024] In a second aspect, the present application provides a RGMII Ethernet interface timing processing method based on a lookup table, the above-mentioned RGMII Ethernet interface timing processing circuit based on a lookup table, the method comprising:

[0025] The delay control module adjusts the value of the delay selection signal, thereby selecting the lookup table of the five groups of delay units in the delay module to select the corresponding delay TAP and delay value, and delaying the 5-bit signal inputted from the delay input signal terminal DIN[4:0] accordingly.

[0026] In a possible implementation, the delay control module synchronously analyzes whether the input signal is sampled correctly and adjusts the value of the delay selection signal to achieve correct double-edge sampling, including:

[0027] Step 1: Select a RGMII_RXD[i]_PIN signal, where i=0,1,2,3;

[0028] Step 2: Set the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN, that is, set the corresponding delay value;

[0029] Step 3: Wait for the rising edge of RGMII_DEN from low to high, and record the number of cycles that RGMII_DIN[i] remains at a low level.

[0030] Step 4, determine whether the number of cycles that RGMII_DIN[i] continues to be at a low level is 7. If it is 7, it indicates that the above delay value is set correctly and can be sampled normally, then execute step 5; if it is not 7, it indicates that the above delay value is set incorrectly, jump to step 2 to reset the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN;

[0031] Step 5, record the value of the delay selection signal corresponding to the current RGMII_RXD[i]_PIN and its corresponding delay value, and write them into the delay module, and the delay value corresponding to RGMII_RXD[i]_PIN is adjusted;

[0032] Step 6, determine whether the delay value adjustment corresponding to RGMII_RXD[3:0]_PIN has been completed. If not, jump to step 1 to select the next input data signal; if all are completed, end the adjustment.

[0033] In a possible implementation, the delay value of RGMII_RXEN_PIN is set to the middle value of the delay value of RGMII_RXD[3:0]_PIN, and the value of the delay selection signal corresponding to RGMII_RXEN_PIN and its corresponding delay value are recorded and written into the delay module.

[0034] Beneficial effects:

[0035] The present invention uses the conventional lookup table (LUT) resources inside the FPGA as a delay unit, and reasonably adjusts the number of lookup tables to complete the timing adjustment of the RGMII Ethernet interface, and realizes the correct sampling of the RGMII Ethernet interface by the FPGA. The present invention can be applied to many high-end, mid-to-low-end FPGAs in Europe and the United States, and domestic FPGAs, and has a wide range of applications and is not restricted by specific devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a typical Ethernet PHY and MAC connection diagram;

[0037] Figure 2 This is a delay and sampling block diagram in one embodiment of the present application;

[0038] Figure 3 A delay unit inside a delay module in one embodiment of the present application;

[0039] Figure 4 A sampling unit inside a sampling module in one embodiment of the present application;

[0040] Figure 5 The RGMII timing of a typical Ethernet PHY and MAC chip;

[0041] Figure 6 This is a delay value adjustment flow chart in one embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application.

[0043] like Figure 1The figure shows a typical Ethernet PHY and MAC connection diagram. It includes the following modules or units: Ethernet PHY chip, FPGA that implements data link layer functions, and the RGMII input signal connected to it, where the RGMII input signal is composed of a source synchronous clock signal RGMII_CLK, a four-bit (4-bit) data signal of RGMII_RXD, and an input data valid signal RGMII_RXEN.

[0044] The embodiment of the present application discloses a RGMII Ethernet interface timing processing circuit based on a lookup table, which is applied to FPGA. In order to accurately collect RGMII input signals, the FPGA includes the following modules: a delay module responsible for delay, a delay control module responsible for delay adjustment,

[0045] The RGMII input signal is first connected to the external signal pins (PIN) of the FPGA, namely RGMII_RXCLK_PIN, RGMII_RXD[3:0]_PIN, and RGMII_RXEN_PIN, a total of 6 signal lines.

[0046] Furthermore, the FPGA also includes a sampling module responsible for sampling data, such as Figure 2 shown.

[0047] Furthermore, the four signals of RGMII_RXD are connected to the input signal terminal DIN[3:0] of the delay module, and RGMII_RXEN_PIN is connected to the input signal terminal DIN[4] of the delay module. The output signal terminal DOUT[4:0] of the delay module is connected to the input signal terminal DIN[4:0] of the sampling module, that is, the 5-bit output signal of the delay module is used as the 5-bit input signal of the sampling module. The output signal terminals QOUT_L[3:0] and QOUT_H[3:0] of the sampling module respectively output the double-delayed sampling data of RGMII_RXD_DELAY[3:0] as the RGMII output data signals RGMII_RXDATA[7:4] and RGMII_RXDATA[3:0]; the output signal terminal QOUT_H[4] of the sampling module outputs the double-delayed sampling data of RGMII_RXEN_DELAY as the RGMII output data valid signal RGMII_RXDATAEN.

[0048] Furthermore, the delay selection signal terminal DSEL[34:0] of the delay module is connected to the delay control module, and the sampling module output signal terminals RGMII_RXDATA[7:0] and RGMII_RXDATAEN are also connected to the delay control module. The delay selection signal is 35 bits, and each 7-bit delay selection signal controls an input signal of the delay module, for example, bits 6-0 control the input signal terminal DIN[0] of the delay module, and bits 13-7 control the input signal terminal DIN[1] of the delay module, and so on.

[0049] Among them, [n:0] represents the nth to 0th bit.

[0050] Furthermore, the delay module is used to delay the 5-bit signal input from the input signal terminal DIN[4:0]. It has 5 groups of identical delay units, each of which is used to delay the 5-bit signal. Each delay unit corresponds to 7 delay selection signal terminals. Each group of delay units consists of 8 lookup tables (LUTs). Selecting different lookup tables corresponds to different delay TAPs, and different delay TAPs correspond to different delay values. The delay value corresponding to a delay TAP is determined to be about 0.5ns according to the manual, such as Figure 3 As shown. Each lookup table is a data selector with three inputs and one output. The input IN0 of each lookup table is connected to the delayed signal, the input IN1 is connected to the output signal end of the previous lookup table, and SEL is the input selection signal. The IN1 and SEL of the first lookup table LUT-1 are simultaneously connected to the delayed signal. The logical expressions of the 2nd to 8th lookup tables LUT-2 to 8 are: when SEL=0, select IN0 output; when SEL=1, select IN1 output. When the last lookup table LUT-8 is selected, it is delayed by 1 TAP; when the 1st lookup table LUT-1 to the 8th lookup table LUT-8 are all selected, it is delayed by 8 TAP. The entire delay correspondence is shown in Table 1 below:

[0051]

[0052] The RGMII input signal is further sent to the back-end sampling module after being delayed. The sampling module input signal terminal DIN[4:0] is connected to the output signal terminal DOUT[4:0] of the delay module, and the data RGMII_RXD_DELAY[3:0] and RGMII_RXEN_DELAY after the front-end delay are connected. The synchronous clock of the sampling module is connected to RGMII_RXCLK_PIN, and the double-delayed sampling data is output to RGMII_RXDATA[7:0] and RGMII_RXDATAEN; further RGMII_RXDATA[7:0] and RGMII_RXDATAEN can be used as the input judgment signal of the delay control module and as the Ethernet receiving data of the back-end module. There are 5 groups of independent and identical sampling units inside the sampling module. Each input data enters a separate sampling unit to complete the double-delay data to single-edge data output, such as Figure 4 There are three independent D flip-flops inside the sampling unit, namely D-FF-0, D-FF-1 and D-FF-2, where D-FF-0 is used to sample the rising edge data of the input data, D-FF-1 is used to sample the falling edge data of the input data, and D-FF-2 synchronizes the falling edge data to the rising edge and outputs it.

[0053] Furthermore, the rising edge output signal terminal QOUT_H[0] of the DIN[0] input signal is connected to RGMII_RXDATA[0], and the falling edge output signal terminal QOUT_L[0] is connected to RGMII_RXDATA[4]. The dual edge outputs of other input signals are connected in this way.

[0054] The clock input signal of the delay control module is RGMII_RXCLK_PIN, the input signal terminal RGMII_DIN[7:0] of the delay control module is connected to RGMII_RXDATA[7:0], and the input signal terminal RGMII_DEN of the delay control module is connected to RGMII_RXDATAEN. In the delay control module, the input signal is synchronously analyzed to see if it is sampled correctly, and the delay selection signal is adjusted to achieve correct dual-edge sampling.

[0055] The RGMII input signal consists of a source synchronous clock signal RGMII_CLK, a four-bit input data signal RGMII_RXD, and an input data valid signal RGMII_RXEN. In general, the clock frequency in gigabit mode is 125Mhz, the clock cycle T is 8ns, and the data is transmitted along both edges. The rising edge transmits the lower four bits of data, and the falling edge transmits the higher four bits. The effective time of the double-delay data is 4ns. In the data transmission of the Ethernet RGMII interface, in order to facilitate the back-end synchronization, the data frame will start with 7 0x55s, that is, the signal characteristics are alternating high and low, and when the rising edge is sampled, it continues for 7 high levels, and when the falling edge is sampled, it continues for 7 low levels, such as Figure 5 shown.

[0056] Furthermore, the following takes the i-th RGMII_RXD[i]_PIN signal acquisition and processing process as an example. Figure 6 , explaining the specific steps of analyzing whether the sampling is correct and delaying the selection of the signal value:

[0057] Step 1: Select a RGMII_RXD[i]_PIN signal, where i=0,1,2,3;

[0058] Step 2: Set the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN, that is, set the corresponding delay value;

[0059] For example, DSEL[6:0]=0000000 can be set according to the rules in Table 1 above, that is, the delay value is set to 0.5ns. If sampling cannot be performed normally under this delay value, the value of the delay selection signal is reset to the next value in Table 1, corresponding to the next delay value in Table 1;

[0060] Step 3: Wait for the rising edge of RGMII_DEN from low to high, and record the number of cycles that RGMII_DIN[i] remains at a low level.

[0061] Step 4, determine whether the number of cycles that RGMII_DIN[i] continues to be at a low level is 7. If it is 7, it indicates that the above delay value is set correctly and can be sampled normally, then execute step 5; if it is not 7, it indicates that the above delay value is set incorrectly, jump to step 2 to reset the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN;

[0062] Step 5, record the value of the delay selection signal corresponding to the current RGMII_RXD[i]_PIN and its corresponding delay value, and write them into the delay module, and the delay value corresponding to RGMII_RXD[i]_PIN is adjusted;

[0063] Step 6, determine whether the delay value adjustment corresponding to RGMII_RXD[3:0]_PIN has been completed. If not, jump to step 1 to select the next input data signal; if all are completed, end the adjustment.

[0064] Set the delay value of RGMII_RXEN_PIN to the middle value of the delay value of RGMII_RXD[3:0]_PIN, record the value of the delay selection signal corresponding to RGMII_RXEN_PIN and its corresponding delay value, and write them into the delay module.

[0065] Thus, the value of the entire 35-bit delay selection signal is written to the delay selection signal terminal DSEL[34:0] of the delay module.

[0066] Obviously, those skilled in the art should understand that the above-mentioned units or steps of the present application can be implemented by a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0067] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A RGMII Ethernet interface timing processing circuit based on a lookup table, characterized in that: Applied to FPGA, the FPGA includes: a delay module and a delay control module; The RGMII input signal includes a source synchronous clock signal RGMII_CLK, a four-bit input data signal RGMII_RXD, and an input data valid signal RGMII_RXEN, which are respectively connected to six external signal pins of the FPGA; wherein the six external signal pins are: RGMII_RXCLK_PIN, RGMII_RXD[3:0]_PIN, RGMII_RXEN_PIN; RGMII_RXD[3:0]_PIN are connected to the input signal terminal DIN[3:0] of the delay module respectively; RGMII_RXEN_PIN is connected to the input signal terminal DIN[4] of the delay module; The delay module has 5 groups of delay units inside, which are respectively used to delay the 5-bit signal input by the input signal terminal DIN[4:0]; each delay unit includes 8 lookup tables; each delay unit corresponds to 7 delay selection signal terminals of the delay module, which are used to select the 8 lookup tables of the delay unit; different lookup tables have different delay TAPs, and different delay TAPs have different delay values; The five groups of delay units correspond to 35 delay selection signal terminals DSEL[34:0] of the delay module, and the delay selection signal terminal DSEL[34:0] of the delay module is connected to the delay control module; the delay control module provides a 35-bit delay selection signal, and each 7-bit delay selection signal controls an input signal of the delay module; Among them, [n:0] represents the nth to 0th bit.

2. The circuit according to claim 1, characterized in that The corresponding relationship between the delay selection signal, the selected lookup table, the delay TAP and the delay value is shown in the following table: ； Among them, LUT-1~LUT-8 represent the 1st to 8th lookup tables respectively, and the symbol / represents and.

3. The circuit according to claim 1, characterized in that The FPGA further includes: a sampling module; the output signal terminal DOUT[4:0] of the delay module is respectively connected to the input signal terminal DIN[4:0] of the sampling module, so that the sampling module receives the front-end delayed data RGMII_RXD_DELAY[3:0] and RGMII_RXEN_DELAY as 5 input data; The synchronous clock of the sampling module is connected to RGMII_RXCLK_PIN; The output signal terminals QOUT_L[3:0] and QOUT_H[3:0] of the sampling module respectively output the double-delayed sampling data of RGMII_RXD_DELAY[3:0] as the RGMII output data signals RGMII_RXDATA[7:4] and RGMII_RXDATA[3:0]; the output signal terminal QOUT_H[4] of the sampling module outputs the double-delayed sampling data of RGMII_RXEN_DELAY as the RGMII output data valid signal RGMII_RXDATAEN.

4. The circuit according to claim 3, characterized in that There are 5 groups of independent and identical sampling units inside the sampling module; each input data enters a separate sampling unit to complete the double-delay data to single-edge data output; there are three independent D flip-flops inside the sampling unit, namely D-FF-0, D-FF-1 and D-FF-2, among which D-FF-0 is used to sample the rising edge data of the input data, D-FF-1 is used to sample the falling edge data of the input data, and D-FF-2 synchronizes the falling edge data to the rising edge and outputs it.

5. The circuit according to claim 4, characterized in that The sampling module output signal terminals RGMII_RXDATA[7:0] and RGMII_RXDATAEN are connected to the delay control module as input judgment signals of the delay control module; The clock input signal of the delay control module is RGMII_RXCLK_PIN, the input signal terminal RGMII_DIN[7:0] of the delay control module is connected to RGMII_RXDATA[7:0], and the input signal terminal RGMII_DEN of the delay control module is connected to RGMII_RXDATAEN; in the delay control module, the input signal is synchronously analyzed to see whether it is sampled correctly, and the value of the delay selection signal is adjusted to achieve correct dual-edge sampling.

6. A RGMII Ethernet interface timing processing method based on a lookup table, characterized in that: Based on the RGMII Ethernet interface timing processing circuit based on a lookup table according to any one of claims 1 to 5, the method comprises: The delay control module adjusts the value of the delay selection signal, thereby selecting the lookup table of the five groups of delay units in the delay module to select the corresponding delay TAP and delay value, and delaying the 5-bit signal inputted from the delay input signal terminal DIN[4:0] accordingly.

7. The method according to claim 6, characterized in that Based on the RGMII Ethernet interface timing processing circuit based on the lookup table according to claim 5, the method includes: the delay control module synchronously analyzes whether the input signal is sampled correctly, and adjusts the value of the delay selection signal to achieve correct double-edge sampling, including: Step 1: Select a RGMII_RXD[i]_PIN signal, where i=0,1,2,3; Step 2: Set the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN, that is, set the corresponding delay value; Step 3: Wait for the rising edge of RGMII_DEN from low to high, and record the number of cycles that RGMII_DIN[i] remains at a low level. Step 4, determine whether the number of cycles that RGMII_DIN[i] continues to be at a low level is 7. If it is 7, it indicates that the above delay value is set correctly and can be sampled normally, then execute step 5; if it is not 7, it indicates that the above delay value is set incorrectly, jump to step 2 to reset the value of the delay selection signal corresponding to RGMII_RXD[i]_PIN; Step 5, record the value of the delay selection signal corresponding to the current RGMII_RXD[i]_PIN and its corresponding delay value, and write them into the delay module, and the delay value corresponding to RGMII_RXD[i]_PIN is adjusted; Step 6, determine whether the delay value adjustment corresponding to RGMII_RXD[3:0]_PIN has been completed. If not, jump to step 1 to select the next input data signal; if all are completed, end the adjustment.

8. The method according to claim 7, characterized in that Set the delay value of RGMII_RXEN_PIN to the middle value of the delay value of RGMII_RXD[3:0]_PIN, record the value of the delay selection signal corresponding to RGMII_RXEN_PIN and its corresponding delay value, and write them into the delay module.

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