Data migration method and device, electronic equipment and storage medium

Abstract

The invention relates to a data migration method and device, electronic equipment and a storage medium. The method comprises the steps that a data migration instruction is obtained, the data migration instruction comprises a logic unit identifier and address information, the logic unit identifier is used for representing a logic unit for data migration, the address information comprises a source address and auxiliary information, and the auxiliary information comprises a destination address corresponding to the source address; the source address is an address of a first logic block in the logic unit, and the destination address is an address of a second logic block in the logic unit; and in response to the data migration instruction, migrating data corresponding to the first logic block to the second logic block. According to the mode of directly migrating the data from one logic block to another logic block in response to the data migration instruction, the data migration efficiency and performance are improved, and the power consumption in the data migration process is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a data migration method, device, electronic device and storage medium. Background Art

[0002] The basic unit of reading and writing of flash media is the block, which cannot be overwritten. Before each new write, the block needs to be erased and then rewritten. The number of times a flash media block can be erased is limited. This feature is called the life of the flash media. In addition, writing to the flash media after erasing will cause a large delay in a single IO. Therefore, in order to improve the performance of the flash media, a log-type file system F2FS (Flash-Friendly File System) is used. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a data migration method, device, electronic device and storage medium.

[0004] According to a first aspect of an embodiment of the present disclosure, a data migration method is provided, the method comprising:

[0005] Acquire a data migration instruction, the data migration instruction including a logical unit identifier and address information, the logical unit identifier is used to characterize a logical unit for data migration, the address information includes a source address and auxiliary information, the auxiliary information includes a destination address corresponding to the source address, the source address is an address of a first logical block in the logical unit, and the destination address is an address of a second logical block in the logical unit;

[0006] In response to the data migration instruction, the data in the first logical block is migrated to the second logical block.

[0007] In some embodiments, the auxiliary information further includes N, wherein N is the number of the plurality of consecutive logic blocks, and N is an integer greater than 1;

[0008] The step of migrating the data in the first logic block to the second logic block in response to the data migration instruction includes:

[0009] In response to the data migration instruction, data in N consecutive logical blocks in the first interval are respectively migrated to N consecutive logical blocks in the second interval, wherein the first logical block is the first logical block in the first interval, the second logical block is the first logical block in the second interval, and the N logical blocks before data migration correspond one-to-one to the N logical blocks after data migration.

[0010] In some embodiments, the data migration instruction includes M sets of address information, where M is an integer greater than 1;

[0011] The step of migrating the data in the first logic block to the second logic block in response to the data migration instruction includes:

[0012] In response to the data migration instruction, data in the logic block corresponding to the source address in each set of the address information is migrated to the logic block corresponding to the destination address in the address information.

[0013] In some embodiments, the data migration instruction includes K groups of address information, and the auxiliary information in each group of the address information includes a destination address and L, wherein K is the number of discrete groups of logic blocks, L included in the auxiliary information in the kth group of address information is the number of logic blocks in the kth group of logic blocks, K is an integer greater than 1, k is a positive integer not greater than K, and L is a positive integer;

[0014] The step of migrating the data in the first logic block to the second logic block in response to the data migration instruction includes:

[0015] In response to the data migration instruction, data in L consecutive logical blocks in the kth first interval are migrated to L consecutive logical blocks in the kth second interval, wherein the logical block corresponding to the kth source address is the first logical block in the kth first interval, and the logical block corresponding to the kth destination address is the first logical block in the kth second interval.

[0016] In some embodiments, the data migration instruction further includes an operation code, and the operation code is used to instruct to perform a data migration operation.

[0017] According to a second aspect of an embodiment of the present disclosure, there is provided an electronic device, the electronic device comprising a processor and a memory.

[0018] The processor is configured to send a data migration instruction to the memory, the data migration instruction including a logic unit identifier and address information, the logic unit identifier is used to represent the logic unit for data migration, the address information includes a source address and auxiliary information, the auxiliary information includes a destination address corresponding to the source address, the source address is an address of a first logic block in the logic unit, and the destination address is an address of a second logic block in the logic unit;

[0019] The memory is configured to receive the data migration instruction sent by the processor;

[0020] The memory is further configured to migrate the data in the first logic block to the second logic block in response to the data migration instruction.

[0021] In some embodiments, the memory is further configured to send a data migration success notification to the processor.

[0022] In some embodiments, the memory includes a plurality of physical blocks, the physical blocks being flash memory media storing data;

[0023] The memory is further configured to determine, in response to the data migration instruction and a preset mapping relationship, a first physical block corresponding to the first logical block and a second physical block corresponding to the second logical block, wherein the preset mapping relationship is used to characterize a mapping relationship between the logical block and the physical block;

[0024] The first physical block is configured to migrate data in the first physical block to the second physical block.

[0025] In some embodiments, the memory further comprises a flash memory controller;

[0026] The first physical block is configured to send data in the first physical block to the memory of the flash controller;

[0027] The flash memory controller is configured to send data in the first physical block to the second physical block.

[0028] In some embodiments, when the destination address in the auxiliary information is empty, the first physical block is also configured to determine a third physical block, migrate the data in the first physical block to the third physical block, and update the preset mapping relationship. The updated preset mapping relationship includes a mapping relationship between the third physical block and a third logical block corresponding to the third physical block.

[0029] According to a third aspect of an embodiment of the present disclosure, a data migration device is provided, the device comprising:

[0030] an information acquisition module, configured to acquire a data migration instruction, the data migration instruction including a logic unit identifier and address information, the logic unit identifier being used to characterize a logic unit for data migration, the address information including a source address and auxiliary information, the auxiliary information including a destination address corresponding to the source address, the source address being an address of a first logic block in the logic unit, and the destination address being an address of a second logic block in the logic unit;

[0031] The data migration module is configured to migrate the data in the first logic block to the second logic block in response to the data migration instruction.

[0032] In some embodiments, the auxiliary information further includes N, wherein N is the number of the plurality of consecutive logic blocks, and N is an integer greater than 1;

[0033] The data migration module is configured as follows:

[0034] In response to the data migration instruction, data in N consecutive logical blocks in the first interval are respectively migrated to N consecutive logical blocks in the second interval, wherein the first logical block is the first logical block in the first interval, the second logical block is the first logical block in the second interval, and the N logical blocks before data migration correspond one-to-one to the N logical blocks after data migration.

[0035] In some embodiments, the data migration instruction includes M sets of address information, where M is an integer greater than 1;

[0036] The data migration module is configured as follows:

[0037] In response to the data migration instruction, data in the logic block corresponding to the source address in each set of the address information is migrated to the logic block corresponding to the destination address in the address information.

[0038] In some embodiments, the data migration instruction includes K groups of address information, and the auxiliary information in each group of the address information includes a destination address and L, wherein K is the number of discrete groups of logic blocks, L included in the auxiliary information in the kth group of address information is the number of logic blocks in the kth group of logic blocks, K is an integer greater than 1, k is a positive integer not greater than K, and L is a positive integer;

[0039] The data migration module is configured as follows:

[0040] In response to the data migration instruction, data in L consecutive logical blocks in the kth first interval are migrated to L consecutive logical blocks in the kth second interval, wherein the logical block corresponding to the kth source address is the first logical block in the kth first interval, and the logical block corresponding to the kth destination address is the first logical block in the kth second interval.

[0041] In some embodiments, the data migration instruction further includes an operation code, and the operation code is used to instruct to perform a data migration operation.

[0042] According to a fourth aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0043] processor;

[0044] a memory for storing processor-executable instructions;

[0045] The processor is configured to execute the method as described in the first aspect of the embodiment of the present disclosure.

[0046] According to a fifth aspect of an embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method described in the first aspect of the embodiment of the present disclosure.

[0047] The above method of the present disclosure has the following beneficial effects:

[0048] The method provided by the embodiment of the present disclosure obtains a data migration instruction, which includes a logical unit identifier and address information. The logical unit identifier is used to characterize the logical unit for data migration. The address information includes a source address and auxiliary information. The auxiliary information includes a destination address corresponding to the source address. In response to the data migration instruction, data in a first logical block corresponding to the source address is migrated to a second logical block corresponding to the destination address. This data migration method improves the efficiency and performance of data migration and reduces power consumption during the data migration process.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0051] Figure 1 is a schematic diagram of a data migration process in a related technology according to an exemplary embodiment;

[0052] Figure 2 is a flow chart showing a data migration method according to an exemplary embodiment;

[0053] Figure 3 is a flow chart showing another data migration method according to an exemplary embodiment;

[0054] Figure 4 is a schematic diagram showing a data migration process according to an exemplary embodiment;

[0055] Figure 5 is a schematic diagram showing a data migration manager according to an exemplary embodiment;

[0056] Figure 6 is a flow chart showing another data migration method according to an exemplary embodiment;

[0057] Figure 7 is a schematic diagram showing another data migration process according to an exemplary embodiment;

[0058] Figure 8 is a flow chart showing another data migration method according to an exemplary embodiment;

[0059] Fig. 9 is a schematic diagram showing another data migration process according to an exemplary embodiment;

[0060] Fig.10 is a flow chart showing another data migration method according to an exemplary embodiment;

[0061] Fig.11 is a schematic diagram showing another data migration process according to an exemplary embodiment;

[0062] Fig.12 is a block diagram of a data migration device according to an exemplary embodiment;

[0063] Fig.13 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0064] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0065] In the related art, F2FS adopts an append-write method, that is, the newly written data is not overwritten at the original location, and a space will be reallocated to complete the write operation. After F2FS adopts append-write, a lot of old data will be generated, and the new data and the old data will be mixed together, thus forming space fragmentation. In order to free up space, it is necessary to defragment the space, which is called space garbage collection. Space garbage collection is achieved through data migration, that is, valid data is migrated to new space, and the old space is treated as invalid space and will be released and reused. Among them, the space is used to store data, and the space can be a storage space in a physical block, and the physical block is a flash memory medium for storing data.

[0066] For example, see Figure 1The schematic diagram of the migration process shown in FIG. 1 shows that in step ①, the processor applies for memory resources; in steps ②, ③ and ④, the processor obtains the data to be migrated from the memory and copies the data from the original space to the applied memory resources; in steps ⑤, ⑥ and ⑦, the processor sends the data from the memory resources to the new space in the memory. In this process, steps ③, ④, ⑤, ⑥ and ⑦ all require copying of the migrated data, that is, multiple data copies are required, which consumes a lot of power, and multiple data copies will also affect the overall performance of the electronic device.

[0067] It should be noted that the processor may also be called a host (Host), and the memory may also be called a storage chip, a device (Device) end, etc.

[0068] The data migration method provided in the embodiment of the present disclosure is executed by an electronic device, which may be a mobile phone, a tablet computer, a laptop computer, a wearable device, or other device capable of storing data and performing data migration.

[0069] Figure 2 is a flow chart of a data migration method according to an exemplary embodiment, which is executed by an electronic device, see Figure 2 , the method comprises the following steps:

[0070] Step S201, obtain a data migration instruction, the data migration instruction includes a logical unit identifier and address information, the logical unit identifier is used to characterize the logical unit for data migration, the address information includes a source address and auxiliary information, the auxiliary information includes a destination address corresponding to the source address, the source address is the address of the first logical block in the logical unit, and the destination address is the address of the second logical block in the logical unit.

[0071] The data migration instruction indicates data migration, and the data migration instruction includes a logic unit identifier and address information. The logic unit identifier is used to characterize the logic unit for data migration, and then data migration is performed on the logic unit. The source address is the address of the logic block corresponding to the data to be migrated. The embodiment of the present disclosure takes the first logic block as an example. The destination address is the address of the logic block corresponding to the data after migration. The embodiment of the present disclosure takes the second logic block as an example. The first logic block and the second logic block are different.

[0072] Optionally, the auxiliary information may directly include the destination address corresponding to the source address, or may include other information, and the destination address may be determined by the other information. For example, the auxiliary information includes addresses corresponding to multiple logical blocks that can store data, and any one of the multiple addresses may be used as the destination address.

[0073] Step S202 , in response to the data migration instruction, migrate the data corresponding to the first logic block to the second logic block.

[0074] The data corresponding to the first logical block is the data to be migrated, the data is stored in the first physical block corresponding to the first logical block, the first logical block is a mapping of the first physical block, the second logical block is the logical block corresponding to the data after migration, the migrated data is stored in the second physical block corresponding to the second logical block, the second logical block is a mapping of the second physical block. The physical block is a flash memory medium for storing data.

[0075] The method provided by the embodiment of the present disclosure obtains a data migration instruction, which includes a logical unit identifier and address information. The logical unit identifier is used to characterize the logical unit for data migration. The address information includes a source address and auxiliary information. The auxiliary information includes a destination address corresponding to the source address. In response to the data migration instruction, data in a first logical block corresponding to the source address is migrated to a second logical block corresponding to the destination address. This data migration method improves the efficiency and performance of data migration, reduces power consumption during data migration, and improves user experience.

[0076] The present disclosure also provides an electronic device, which includes a processor and a memory. Figure 2 The data migration method shown can also be executed by the processor and the memory.

[0077] Figure 3 is a flowchart of another data migration method according to an exemplary embodiment, which is executed by a processor and a memory, see Figure 2 , the method comprises the following steps:

[0078] Step S301: The processor sends a data migration instruction to the memory.

[0079] Step S302: the memory receives a data migration instruction sent by the processor.

[0080] Step S303 : In response to the data migration execution, the memory migrates the data corresponding to the first logic block to the second logic block.

[0081] Figure 3 The embodiment shown is shown in the above Figure 2 The implementation method shown will not be repeated here. Figure 2 The embodiment shown is different in that Figure 3 In the illustrated embodiment, the processor interacts with the memory. When data migration is required, the processor sends a data migration instruction to the memory, and the memory receives the data migration instruction.

[0082] According to the method provided by the embodiment of the present disclosure, during the data migration process, the processor only needs to send a data migration instruction to the memory, and the subsequent data migration process is executed in the memory. There is no need to copy the data in the memory to the processor, thereby improving the efficiency and performance of data migration and reducing power consumption during the data migration process.

[0083] In the disclosed embodiment, when data migration is performed, data corresponding to one logic block may be migrated, or data corresponding to multiple logic blocks may be migrated. The multiple logic blocks may be continuous logic blocks, discrete logic blocks, or discrete continuous logic blocks, that is, the discrete logic blocks include continuous logic blocks. The above data migration situations are described below:

[0084] The first case: Migrate the data corresponding to one logical block at a time.

[0085] The data migration instruction includes a logic unit identifier, a source address and a destination address, that is, the auxiliary information is the destination address, and the electronic device responds to the data migration instruction to migrate the data corresponding to the first logic block corresponding to the source address to the second logic block corresponding to the destination address. Optionally, the data migration instruction also includes an operation code, which is used to instruct the execution of the data migration operation.

[0086] It should be noted that the various parameters included in the data migration instruction are agreed upon in the data migration protocol. When the data migration instruction is obtained, the various parameters included in the data migration instruction can be determined according to the agreed data migration protocol.

[0087] In one example, the format of the data migration instruction is shown in Table 1 below:

[0088] Table 1

[0089]

[0090]

[0091] Among them, the data migration instruction includes three parts: Opcode, Target Descriptor and Segment Descriptor. The operation code is opcode, the target descriptor is www.LUN.. (logical unit), and the segment descriptor is source identifier and destination identifier.

[0092] For example, see Figure 4The schematic diagram of the data migration process shown in the figure, step ①, the processor sends a data migration instruction to the memory, the data migration instruction includes lun, lba1, lba2, where lun is the logical unit identifier, lba1 is the source address, and lba2 is the destination address; step ②, in the memory, the data corresponding to the logical block corresponding to lba1 is migrated to the logical block corresponding to lba2; step ③, the memory returns a data migration success notification to the processor.

[0093] In the case where the electronic device includes a processor and a memory, the processor sends a data migration instruction to the memory, and the data migration instruction includes a logical unit identifier, a source address, and a destination address. The memory receives the data migration instruction and, in response to the data migration instruction, migrates data corresponding to a first logical block to a second logical block. Then, the memory sends a data migration success notification to the processor, and the data migration success notification is used to indicate that the memory has been migrated, so that the processor can update the correspondence between the data and the logical block based on the data migration success notification.

[0094] Optionally, when data migration fails, the memory sends a data migration failure notification to the processor, or does not send a notification to the processor.

[0095] In some embodiments, the memory includes multiple physical blocks, and the data corresponding to the logical block is stored in the physical block corresponding to the logical block. In this case, the memory determines the first physical block corresponding to the first logical block and the second physical block corresponding to the second logical block in response to the data migration instruction and the preset mapping relationship, wherein the preset mapping relationship is used to characterize the mapping relationship between the logical block and the physical block; then the memory migrates the data in the first physical block to the second physical block.

[0096] In one example, the memory includes a data migration manager, for example, see Figure 5 The data migration manager shown in FIG. 1 includes a logical unit (Logical Unit Number, LUN), a preset mapping relationship (Flash Translation Layer, FTL) and multiple physical blocks (superblocks).

[0097] In addition, in some embodiments, the memory also includes a flash memory controller, and the memory migrates data in the first physical block to the second physical block, including: the first physical block sends the data in the first physical block to the memory of the flash memory controller; the flash memory controller then sends the data in the first physical block to the second physical block, that is, forwarding the data in the physical block through the memory of the flash memory controller.

[0098] In some embodiments, the destination address in the auxiliary information is empty. When performing data migration, the memory can determine the third physical block, migrate the data in the first physical block to the third physical block, and update the preset mapping relationship. The updated preset mapping relationship includes a mapping relationship between the third physical block and the third logical block corresponding to the third physical block. The third physical block is any physical block that can store data. In this case, it is not necessary to forward the data in the first physical block through the flash memory controller.

[0099] The second case: data corresponding to multiple consecutive logical blocks are migrated at one time.

[0100] For the data migration process in this case, see Figure 5 The embodiment shown.

[0101] Figure 6 is a flow chart of another data migration method according to an exemplary embodiment, which is executed by an electronic device, see Figure 6 , the method comprises the following steps:

[0102] Step S601: obtaining a data migration instruction, the data migration instruction including a logical unit identifier, a source address and auxiliary information, the auxiliary information including a destination address and N.

[0103] In the disclosed embodiment, when the processor is performing defragmentation and garbage collection (GC), if there is a section of data corresponding to a continuous logical block that needs to be migrated, the data corresponding to multiple continuous logical blocks can be migrated at one time through a data migration protocol, thereby avoiding multiple data migrations.

[0104] Wherein, N is the number of consecutive logic blocks, that is, N is the length of the logic blocks corresponding to the data to be migrated, and N is an integer greater than 1. For example, if the data corresponding to three consecutive logic blocks need to be migrated, N is 3. The source address is the address of the first logic block in the consecutive N logic blocks corresponding to the data before migration, and the destination address is the address of the first logic block in the consecutive N logic blocks corresponding to the data after migration.

[0105] In one example, the format of the data migration instruction is shown in Table 2 below:

[0106] Table 2

[0107]

[0108] The data migration instruction includes three parts: Opcode, Target Descriptor and Segment Descriptor. The operation code is opcode, the target descriptor is www.LUN.., and the segment descriptor is source identifier, destination identifier and N.

[0109] Step S602 , in response to the data migration instruction, migrate the data corresponding to the N consecutive logic blocks in the first interval to the N consecutive logic blocks in the second interval respectively.

[0110] Among them, the first logical block is the first logical block in the first interval, the second logical block is the first logical block in the second interval, the N logical blocks before data migration correspond one to one to the N logical blocks after data migration, for example, the three logical blocks before data migration are logical block 1, logical block 2 and logical block 3, and the three logical blocks after data migration are logical block 4, logical block 5 and logical block 6, then the data corresponding to logical block 1 is migrated to logical block 4, the data corresponding to logical block 2 is migrated to logical block 5, and the data corresponding to logical block 3 is migrated to logical block 6.

[0111] In the case where the electronic device includes a processor and a memory, the processor sends a data migration instruction to the memory, the data migration instruction includes a logical unit identifier, a source address and auxiliary information, the auxiliary information includes a destination address and N, the memory receives the data migration instruction, and in response to the data migration instruction, migrates the data corresponding to N consecutive logical blocks in a first interval to N consecutive logical blocks in a second interval, and then the memory sends a data migration success notification to the processor.

[0112] Optionally, when data migration fails, the memory sends a data migration failure notification to the processor, or does not send a notification to the processor.

[0113] In some embodiments, the memory includes a plurality of physical blocks, and the data corresponding to the logical block is stored in the physical block corresponding to the logical block. In this case, the memory determines the first physical block corresponding to the first logical block and the second physical block corresponding to the second logical block in response to the data migration instruction and the preset mapping relationship, wherein the preset mapping relationship is used to characterize the mapping relationship between the logical block and the physical block; then the memory migrates the data in the N consecutive physical blocks in the first physical interval to the N consecutive physical blocks in the second physical interval, wherein the first physical block is the first physical block in the first physical interval, and the second physical block is the first physical block in the second physical interval. Alternatively, the memory determines the N physical blocks corresponding to the N logical blocks in the first interval and the N physical blocks corresponding to the N logical blocks in the second interval in response to the data migration instruction and the preset mapping relationship, and then the memory migrates the data in the N physical blocks corresponding to the N logical blocks in the first interval to the N physical blocks corresponding to the N logical blocks in the second interval. Wherein, the implementation method of forwarding data between any two physical blocks refers to the implementation method of forwarding data between physical blocks in the first case above, which will not be repeated here.

[0114] For example, see Figure 7 The schematic diagram of the data migration process shown in the figure, step ①, the processor sends a data migration instruction to the memory, the data migration instruction includes lun, lba1, lba2 and 3, wherein lun is the logical unit identifier, lba1 is the source address corresponding to the first logical block of the three consecutive logical blocks before the data migration, and lba2 is the source address destination address corresponding to the first logical block of the three consecutive logical blocks after the data migration; step ②, in the memory, the data corresponding to the three consecutive logical blocks starting from the logical block corresponding to lba1 are migrated to the three consecutive logical blocks starting from the logical block corresponding to lba2; step ③, the memory returns a data migration success notification to the processor.

[0115] In the disclosed embodiment, data corresponding to a plurality of continuous logic blocks can be migrated at one time, thereby improving the efficiency of data migration, avoiding multiple data migrations, and reducing the frequency of data migration.

[0116] The third case: Migrate data corresponding to multiple discrete logical blocks at one time.

[0117] For the data migration process in this case, see Figure 8 The embodiment shown.

[0118] Figure 8 is a flow chart of another data migration method according to an exemplary embodiment, which is executed by an electronic device, see Figure 8 , the method comprises the following steps:

[0119] Step S801: obtaining a data migration instruction, where the data migration instruction includes a logical unit identifier and M group address information.

[0120] In the disclosed embodiment, when the processor is performing defragmentation and garbage collection, if the degree of fragmentation of the logical block corresponding to the data is relatively high. The logical block corresponding to the data is discontinuous and in a discrete state. By migrating the data corresponding to one logical block at a time, multiple data migrations are required. In order to improve the migration efficiency, the data corresponding to multiple discrete logical blocks are migrated in a discrete manner. In this way, the data migration instruction includes a logical unit identifier and M groups of address information, where M is an integer greater than 1. Each group of address information includes a source address and auxiliary information, and the auxiliary information includes a destination address. The source address and the destination address corresponding to each group of address information are a group.

[0121] Optionally, the data migration instruction also includes the number M of groups of address information.

[0122] In one example, the format of the data migration instruction is shown in Table 3 below:

[0123] Table 3

[0124]

[0125] The data migration instruction includes three parts: Opcode, Target Descriptor and Segment Descriptor. The operation code is opcode, the target descriptor is www.LUN.., the segment descriptor is M and M groups of source identifier and destination identifier.

[0126] Step S802 , in response to the data migration instruction, migrate the data corresponding to the logic block corresponding to the source address in each set of address information to the logic block corresponding to the destination address in the address information.

[0127] Each set of address information includes a source address and a destination address. For each set of address information, the data corresponding to the logic block corresponding to the source address in the set of address information is migrated to the logic block corresponding to the destination address in the set of address information. For example, if the data migration instruction includes two sets of address information, the source address in one set of address information corresponds to logic block 1 and the destination address corresponds to logic block 3, and the source address in the other set of address information corresponds to logic block 4 and the destination address corresponds to logic block 8, then the data corresponding to logic block 1 is migrated to logic block 3, and the data corresponding to logic block 4 is migrated to logic block 8.

[0128] In the case where the electronic device includes a processor and a memory, the processor sends a data migration instruction to the memory, and the data migration instruction includes a logical unit identifier and M groups of address information. The memory receives the data migration instruction and, in response to the data migration instruction, migrates the data corresponding to the logical block corresponding to the source address in each group of address information to the logical block corresponding to the destination address in the address information, and then the memory sends a data migration success notification to the processor.

[0129] Optionally, when data migration fails, the memory sends a data migration failure notification to the processor, or does not send a notification to the processor.

[0130] In some embodiments, the memory includes multiple physical blocks, and the data corresponding to the logical block is stored in the physical block corresponding to the logical block. In this case, the memory responds to the data migration instruction and the preset mapping relationship, determines each group of logical blocks corresponding to each group of address information, and then determines each group of physical blocks corresponding to each group of logical blocks, each group of physical blocks includes physical blocks before data migration and physical blocks after data migration, wherein the preset mapping relationship is used to characterize the mapping relationship between logical blocks and physical blocks; then for each group of physical blocks, the memory migrates the data in the physical block before data migration to the logical block after data migration. Among them, the implementation method of forwarding data between any two physical blocks refers to the implementation method of forwarding data between physical blocks in the first case above, which will not be repeated here.

[0131] For example, see Fig. 9 The schematic diagram of the data migration process shown in the figure, step ①, the processor sends a data migration instruction to the memory, the data migration instruction includes lun, lba1, lba2, lba3, lba4, wherein lun is the logical unit identifier, lba1 and lab3 are a group of address information, lba2 and lab4 are a group of address information, lba1 and lba2 are the source addresses of the logical blocks corresponding to the data migration before, lba3 and lba4 are the destination addresses of the logical blocks corresponding to the data migration after; step ②, in the memory, the data corresponding to the logical block corresponding to lba1 is migrated to the logical block corresponding to lba3, and the data corresponding to the logical block corresponding to lba2 is migrated to the logical block corresponding to lba4; step ③, the memory returns a notification of successful data migration to the processor.

[0132] In the disclosed embodiment, data corresponding to a plurality of discrete logic blocks can be migrated at one time, thereby improving the efficiency of data migration, avoiding multiple data migrations, and reducing the frequency of data migration.

[0133] It should be noted that Figure 8 The embodiment shown is only for a plurality of discrete logic blocks. In another embodiment, Figure 8The embodiment shown in the figure performs data migration on a plurality of continuous logic blocks, and the data migration method is similar to Figure 8 The same is true for the embodiment shown.

[0134] The fourth case: Migrate data corresponding to multiple discrete and continuous logical blocks at one time.

[0135] For the data migration process in this case, see Fig.10 The embodiment shown.

[0136] Fig.10 is a flow chart of another data migration method according to an exemplary embodiment, which is executed by an electronic device, see Fig.10 , the method comprises the following steps:

[0137] Step S1001: obtaining a data migration instruction, the data migration instruction including a logical unit identifier and K groups of address information, the auxiliary information in each group of the address information including a destination address and L.

[0138] In the embodiment of the present disclosure, when the processor is performing defragmentation and garbage collection, if the degree of fragmentation of the logic block corresponding to the data is relatively high, but there are also continuous logic blocks, that is, there are multiple continuous logic blocks. In this case, in order to improve the migration efficiency, the above Figure 6 and Figure 8 The embodiment shown in the figure is combined to perform data migration. In this manner, the data migration instruction includes a logical unit identifier and K groups of address information, and the auxiliary information in each group of address information includes a destination address and L, wherein K is the number of discrete groups of logical blocks, and the auxiliary information in the kth group of address information includes L, which is the number of logical blocks in the kth group of logical blocks, K is an integer greater than 1, k is a positive integer not greater than K, and L is a positive integer;

[0139] Optionally, the data migration instruction also includes the number K of groups of address information.

[0140] In one example, the format of the data migration instruction is shown in Table 4 below:

[0141] Table 4

[0142]

[0143] The data migration instruction includes three parts: Opcode, Target Descriptor and Segment Descriptor. The operation code is opcode, the target descriptor is www.LUN.., and the segment descriptor is K, K group source identifier, destination identifier and L.

[0144] Step S1002 , in response to the data migration instruction, migrate the data corresponding to the L consecutive logic blocks in the kth first interval to the L consecutive logic blocks in the kth second interval.

[0145] The kth group is any group, that is, for the logic blocks corresponding to each group of address information, step S902 is used to perform data migration. The logic block corresponding to the kth source address is the first logic block in the kth first interval, and the logic block corresponding to the kth destination address is the first logic block in the kth second interval. For a group of address information, L corresponding to the group of address information can be 1 or an integer greater than 1.

[0146] In the case where the electronic device includes a processor and a memory, the processor sends a data migration instruction to the memory, the data migration instruction includes a logical unit identifier and K groups of address information, the auxiliary information in each group of the address information includes a destination address and L, the memory receives the data migration instruction, and in response to the data migration instruction, migrates data corresponding to L consecutive logical blocks in the kth first interval to L consecutive logical blocks in the kth second interval, and then the memory sends a data migration success notification to the processor.

[0147] Optionally, when data migration fails, the memory sends a data migration failure notification to the processor, or does not send a notification to the processor.

[0148] In some embodiments, the memory includes multiple physical blocks, and the data corresponding to the logical block is stored in the physical block corresponding to the logical block. In this case, the memory responds to the data migration instruction and the preset mapping relationship, determines each group of logical blocks corresponding to each group of address information, and then determines each group of physical blocks corresponding to each group of logical blocks, each group of physical blocks includes physical blocks before data migration and physical blocks after data migration, wherein the preset mapping relationship is used to characterize the mapping relationship between logical blocks and physical blocks; then for each group of physical blocks, the memory migrates the data in the physical block before data migration to the logical block after data migration. Among them, the implementation method of forwarding data between any two physical blocks refers to the implementation method of forwarding data between physical blocks in the first case above, which will not be repeated here.

[0149] For example, see Fig.11The schematic diagram of the data migration process shown in the figure is as follows: step ①, the processor sends a data migration instruction to the memory, the data migration instruction includes lun, 2, lba1, lba2, 2, lba3, lba4, 2, wherein lun is a logical unit identifier, the first 2 means that there are 2 groups of address information, lba1 and lab3 are the first group of address information, the second 2 refers to the two consecutive logical blocks corresponding to the first group of address information, lba2 and lab4 are the second group of address information, the third 2 refers to the two consecutive logical blocks corresponding to the second group of address information, lba1 and lba2 are the source addresses of the corresponding logical blocks before data migration, and lba3 and lba4 are the destination addresses of the corresponding logical blocks after data migration; step ②, in the memory, the data corresponding to the two logical blocks starting from the logical block corresponding to lba1 are migrated to the two logical blocks starting from the logical block corresponding to lba3, and the data corresponding to the two logical blocks starting from the logical block corresponding to lba2 are migrated to the two logical blocks starting from the logical block corresponding to lba4; step ③, the memory returns a notification of successful data migration to the processor.

[0150] In the disclosed embodiment, data corresponding to a plurality of discrete and continuous logic blocks can be migrated at one time, thereby improving the efficiency of data migration, avoiding multiple data migrations, and reducing the frequency of data migration.

[0151] In the above embodiments, several situations involved in the data migration process are explained respectively. In some embodiments, other methods can be used for data migration. For example, whether it is a continuous or discrete logical block, the data migration instruction can include the source address of the logical block corresponding to the data before migration and the destination address of the logical block corresponding to the data after migration.

[0152] One point that needs to be explained is that, in the above-mentioned implementation mode, an example is taken of obtaining a data migration instruction and performing data migration in response to the data migration instruction. In another embodiment, the memory can continuously receive multiple data migration instructions. When multiple data migration instructions are continuously received, the multiple data migration instructions are added to a first-in-first-out linked list in the order in which they are received. Then, when the data migration process corresponding to a data migration instruction is completed, the next data migration instruction is obtained from the linked list until the data migration processes corresponding to all the data migration instructions in the linked list are completed.

[0153] Fig.12 is a block diagram of a data migration device according to an exemplary embodiment, which is configured in an electronic device, see Fig.12 , the device comprises:

[0154] The information acquisition module 1201 is configured to acquire a data migration instruction, where the data migration instruction includes a logical unit identifier and address information, where the logical unit identifier is used to characterize the logical unit for data migration, where the address information includes a source address and auxiliary information, where the auxiliary information includes a destination address corresponding to the source address, where the source address is an address of a first logical block in the logical unit, and the destination address is an address of a second logical block in the logical unit;

[0155] The data migration module 1202 is configured to migrate the data in the first logic block to the second logic block in response to the data migration instruction.

[0156] In some embodiments, the auxiliary information further includes N, where N is the number of the plurality of consecutive logical blocks, and N is an integer greater than 1;

[0157] The data migration module 1202 is configured to:

[0158] In response to the data migration instruction, data in N consecutive logical blocks in the first interval are respectively migrated to N consecutive logical blocks in the second interval, wherein the first logical block is the first logical block in the first interval, the second logical block is the first logical block in the second interval, and the N logical blocks before the data migration correspond one-to-one to the N logical blocks after the data migration.

[0159] In some embodiments, the data migration instruction includes M sets of address information, where M is an integer greater than 1;

[0160] The data migration module 1202 is configured to:

[0161] In response to the data migration instruction, data in the logic block corresponding to the source address in each set of address information is migrated to the logic block corresponding to the destination address in the address information.

[0162] In some embodiments, the data migration instruction includes K groups of address information, and the auxiliary information in each group of address information includes a destination address and L, wherein K is the number of discrete groups of logic blocks, L included in the auxiliary information in the kth group of address information is the number of logic blocks in the kth group of logic blocks, K is an integer greater than 1, k is a positive integer not greater than K, and L is a positive integer;

[0163] The data migration module 1202 is configured to:

[0164] In response to the data migration instruction, data in L consecutive logical blocks in the kth first interval are migrated to L consecutive logical blocks in the kth second interval, wherein the logical block corresponding to the kth source address is the first logical block in the kth first interval, and the logical block corresponding to the kth destination address is the first logical block in the kth second interval.

[0165] In some embodiments, the data migration instruction further includes an operation code, where the operation code is used to instruct to perform a data migration operation.

[0166] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0167] An embodiment of the present disclosure further provides an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to execute the data migration method in the above embodiment.

[0168] Fig.13 is a block diagram of an electronic device 1300 according to an exemplary embodiment.

[0169] Reference Fig.13 , the electronic device 1300 may include one or more of the following components: a processing component 1302 , a memory 1304 , a power component 1306 , a multimedia component 1308 , an audio component 1310 , an input / output (I / O) interface 1312 , a sensor component 1314 , and a communication component 1316 .

[0170] The processing component 1302 generally controls the overall operation of the electronic device 1300, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1302 may include one or more processors 1320 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1302 may include one or more modules to facilitate the interaction between the processing component 1302 and other components. For example, the processing component 1302 may include a multimedia module to facilitate the interaction between the multimedia component 1308 and the processing component 1302.

[0171] The memory 1304 is configured to store various types of data to support operations on the electronic device 1300. Examples of such data include instructions for any application or method operating on the electronic device 1300, contact data, phone book data, messages, pictures, videos, etc. The memory 1304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0172] The power supply component 1306 provides power to the various components of the electronic device 1300. The power supply component 1306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1300.

[0173] The multimedia component 1308 includes a screen that provides an output interface between the electronic device 1300 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1308 includes a front camera and / or a rear camera. When the electronic device 1300 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0174] The audio component 1310 is configured to output and / or input audio signals. For example, the audio component 1310 includes a microphone (MIC), and when the electronic device 1300 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1304 or sent via the communication component 1316. In some embodiments, the audio component 1310 also includes a speaker for outputting audio signals.

[0175] I / O interface 1312 provides an interface between processing component 1302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0176] The sensor assembly 1314 includes one or more sensors for providing various aspects of status assessment for the electronic device 1300. For example, the sensor assembly 1314 can detect the open / closed state of the electronic device 1300, the relative positioning of components, such as the display and keypad of the electronic device 1300, and the sensor assembly 1314 can also detect the position change of the electronic device 1300 or a component of the electronic device 1300, the presence or absence of user contact with the electronic device 1300, the orientation or acceleration / deceleration of the electronic device 1300, and the temperature change of the electronic device 1300. The sensor assembly 1314 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1314 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1314 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0177] The communication component 1316 is configured to facilitate wired or wireless communication between the electronic device 1300 and other devices. The electronic device 1300 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1316 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1316 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0178] In an exemplary embodiment, the electronic device 1300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above methods.

[0179] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1304 including instructions, and the instructions can be executed by a processor 1320 of the electronic device 1300 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0180] The embodiments of the present disclosure also provide a non-temporary computer-readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the data migration method in the above embodiments.

[0181] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed in this disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0182] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A data migration method, characterized in that: The method comprises: Acquire a data migration instruction, the data migration instruction including a logical unit identifier and address information, the logical unit identifier is used to characterize a logical unit for data migration, the address information includes a source address and auxiliary information, the auxiliary information includes a destination address corresponding to the source address, the source address is an address of a first logical block in the logical unit, and the destination address is an address of a second logical block in the logical unit; In response to the data migration instruction, data corresponding to the first logic block is migrated to the second logic block.

2. The method according to claim 1, characterized in that The auxiliary information also includes N, where N is the number of the plurality of consecutive logic blocks, and N is an integer greater than 1; The step of migrating the data corresponding to the first logic block to the second logic block in response to the data migration instruction includes: In response to the data migration instruction, data corresponding to N consecutive logical blocks in the first interval are respectively migrated to N consecutive logical blocks in the second interval, wherein the first logical block is the first logical block in the first interval, the second logical block is the first logical block in the second interval, and the N logical blocks before data migration correspond one-to-one to the N logical blocks after data migration.

3. The method according to claim 1, characterized in that The data migration instruction includes M groups of address information, where M is an integer greater than 1; The step of migrating the data corresponding to the first logic block to the second logic block in response to the data migration instruction includes: In response to the data migration instruction, data corresponding to the logic block corresponding to the source address in each set of the address information is migrated to the logic block corresponding to the destination address in the address information.

4. The method according to claim 1, characterized in that: The data migration instruction includes K groups of address information, and the auxiliary information in each group of the address information includes a destination address and L, wherein K is the number of discrete groups of logic blocks, L included in the auxiliary information in the kth group of address information is the number of logic blocks in the kth group of logic blocks, K is an integer greater than 1, k is a positive integer not greater than K, and L is a positive integer; The step of migrating the data corresponding to the first logic block to the second logic block in response to the data migration instruction includes: In response to the data migration instruction, data corresponding to L consecutive logical blocks in the kth first interval are migrated to L consecutive logical blocks in the kth second interval, wherein the logical block corresponding to the kth source address is the first logical block in the kth first interval, and the logical block corresponding to the kth destination address is the first logical block in the kth second interval.

5. The method according to any one of claims 1 to 4, characterized in that: The data migration instruction also includes an operation code, and the operation code is used to instruct to perform a data migration operation.

6. An electronic device, characterized in that: The electronic device comprises a processor and a memory, The processor is configured to send a data migration instruction to the memory, the data migration instruction including a logic unit identifier and address information, the logic unit identifier is used to represent the logic unit for data migration, the address information includes a source address and auxiliary information, the auxiliary information includes a destination address corresponding to the source address, the source address is an address of a first logic block in the logic unit, and the destination address is an address of a second logic block in the logic unit; The memory is configured to receive the data migration instruction sent by the processor; The memory is further configured to migrate the data in the first logic block to the second logic block in response to the data migration instruction.

7. The electronic device according to claim 6, characterized in that: The memory is further configured to send a data migration success notification to the processor.

8. The electronic device according to claim 6, characterized in that: The memory includes a plurality of physical blocks, and the physical blocks are flash memory media for storing data; The memory is further configured to determine, in response to the data migration instruction and a preset mapping relationship, a first physical block corresponding to the first logical block and a second physical block corresponding to the second logical block, wherein the preset mapping relationship is used to characterize a mapping relationship between the logical block and the physical block; The memory is configured to migrate data in the first physical block to the second physical block.

9. The electronic device according to claim 8, characterized in that: The memory also includes a flash memory controller; The first physical block is configured to send data in the first physical block to the memory of the flash controller; The flash memory controller is configured to send the data in the first physical block to the second physical block.

10. The electronic device according to claim 8, characterized in that: When the destination address in the auxiliary information is empty, the memory is also configured to determine a third physical block, migrate the data in the first physical block to the third physical block, and update the preset mapping relationship, wherein the updated preset mapping relationship includes a mapping relationship between the third physical block and a third logical block corresponding to the third physical block.

11. A data migration device, characterized in that: The device comprises: an information acquisition module, configured to acquire a data migration instruction, the data migration instruction including a logic unit identifier and address information, the logic unit identifier being used to characterize a logic unit for data migration, the address information including a source address and auxiliary information, the auxiliary information including a destination address corresponding to the source address, the source address being an address of a first logic block in the logic unit, and the destination address being an address of a second logic block in the logic unit; The data migration module is configured to migrate the data corresponding to the first logic block to the second logic block in response to the data migration instruction.

12. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to execute the method as claimed in any one of claims 1 to 5.

13. A non-transitory computer-readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method as claimed in any one of claims 1 to 5.

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