Composite operational circuit in integrated circuit

Abstract

The invention provides a composite operation circuit in an integrated circuit. The composite operation circuit comprises a first register set, a second register set, a third register, a multiplication / binary operation module and an addition module. The first register group is used for caching a plurality of filter coefficients or a plurality of convolution coefficients. And the second register group caches a plurality of to-be-filtered data which are input in sequence. And the third register receives and caches the input binary data to be subjected to binary convolution. The multiplication / binary operation module and the addition module perform multiplication and addition operation based on the data to be filtered and the filtering coefficient when performing filtering operation, and perform binary operation and addition operation based on the convolution coefficient and the binary data to be subjected to binary convolution when performing binary convolution operation. In this way, the filtering operation and the binary convolution operation are carried out through the time division multiplexing first register and the addition module, and the resource overhead of hardware is reduced.

Description

[Technical field]

[0001] The present invention relates to the field of hardware operation, and in particular to a composite operation circuit in an integrated circuit. [Background technology]

[0002] In existing integrated circuits, a FIR (Finite Impulse Response) filter and a binary convolution operation unit are usually designed separately, which occupies a large amount of hardware resources.

[0003] Therefore, it is urgent to propose a new technical solution to solve the above problems. [Summary of the invention]

[0004] One of the purposes of the present invention is to provide a composite operation circuit in an integrated circuit, which can not only realize filtering operation, but also realize binary convolution operation, thereby reducing hardware resource overhead.

[0005] According to one aspect of the present invention, the present invention provides a composite operation circuit in an integrated circuit, comprising: a first register group, used to cache multiple filter coefficients when performing a filtering operation, and cache multiple convolution coefficients when performing a binary convolution operation; a second register group, used to receive and shift cache multiple data to be filtered that are input in sequence when performing a filtering operation; a third register, used to receive and cache the input binary data to be binary convolved when performing a binary convolution operation; a multiplication / binary operation module and an addition module, wherein the multiplication / binary operation module and the addition module perform multiplication and addition operations based on the data to be filtered and the filter coefficients when performing a filtering operation, and perform binary operations and addition operations based on the convolution coefficients and the binary data to be binary convolved when performing a binary convolution operation.

[0006] In one embodiment, the first register group caches multiple convolution coefficients each time when performing a binary convolution operation, and the third register caches a binary data to be binary convolved each time when performing a binary convolution operation, wherein when performing a binary convolution operation, the multiple convolution coefficients in the first register group will be updated multiple times, and the binary data to be binary convolved in the third register will be updated multiple times; when performing a filtering operation, the multiplication / binary operation module multiplies each data to be filtered in the second register group by the corresponding filtering coefficient in the first register group to obtain multiple filtering product data, and when performing a binary convolution operation, the binary data to be binary convolved in the third register and each convolution coefficient in the first register group are binary operated to obtain multiple binary operation data; when performing a filtering operation, the addition module multiplies the corresponding filtering coefficient in the first register group to obtain multiple filtering product data. The multiple filtering product data obtained by the multiplication / binary operation module are added to obtain filtering result data. When performing a binary convolution operation, the previous multiple binary convolution temporary result data and the multiple binary operation data currently obtained by the multiplication / binary operation module are respectively added to obtain the current multiple binary convolution temporary result data. When performing a binary convolution operation, the convolution coefficient is updated in the first register group and the binarized data to be binary convolved is updated in the third register each time. Based on the updated convolution coefficient and the updated binarized data to be binary convolved, the current multiple binary convolution temporary result data are obtained once. After the convolution coefficient and the binarized data to be binary convolved are updated to a predetermined number of times, the multiple binary convolution temporary result data obtained for the last time are output as multiple binary convolution final result data.

[0007] Compared with the prior art, the present invention reduces hardware resource overhead by performing filtering operations and binary convolution operations through time-sharing the first register group, multiplexing the multiplication / binary operation module and / or the addition module.

Brief Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0009] Figure 1 A partial structural block diagram of a composite operation circuit in the integrated circuit of the present invention; and

[0010] Figure 2 It is another partial structural block diagram of the composite operation circuit in the integrated circuit of the present invention. [Specific implementation method]

[0011] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "coupled" and other terms indicating electrical connection should be understood in a broad sense; for example, it can be a direct electrical connection, or it can be indirectly electrically connected through an intermediate medium, and the intermediate medium can be an electronic component, a functional circuit, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0013] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0014] The present invention provides a composite operation circuit in an integrated circuit, which can not only realize filtering operation but also realize binary convolution operation, thereby reducing the resource expenditure of hardware.

[0015] Figure 1 It is a partial structural block diagram of the composite operation circuit in the integrated circuit of the present invention. Figure 2 It is another partial structural block diagram of the composite operation circuit in the integrated circuit of the present invention.

[0016] like Figure 1 and 2As shown, the composite operation circuit in the integrated circuit includes: a first register group 110, a second register group 120, a third register 130, a multiplication / binary operation module 150 and an addition module 170. The first register group 110 is used to cache multiple filter coefficients when performing a filtering operation, and cache multiple convolution coefficients when performing a binary convolution operation. The second register group 120 is used to receive and shift cache multiple data to be filtered input in sequence when performing a filtering operation. The third register 130 is used to receive and cache the input binary data to be binary convolved when performing a binary convolution operation. The multiplication / binary operation module 150 and the addition module 170 perform multiplication and addition operations based on the data to be filtered and the filter coefficients when performing a filtering operation, and perform binary operations and addition operations based on the convolution coefficients and the binary data to be binary convolved when performing a binary convolution operation. In this way, by time-sharing multiplexing the first register group, the multiplication / binary operation module and / or the addition module to perform filtering operation and binary convolution operation, the resource overhead of the hardware is reduced. That is to say, in a single integrated circuit (or chip), the composite operation circuit can work as a filter or as a binary convolution operation unit. By adopting efficient instructions, the composite operation circuit can work as a filter or as a binary convolution operation unit in time-sharing without interfering with each other.

[0017] In one embodiment, the first register group 110 caches multiple convolution coefficients each time when performing a binary convolution operation, and the third register 130 caches a binary data to be binary convolved each time when performing a binary convolution operation. When performing a binary convolution operation, the multiple convolution coefficients in the first register group 110 will be updated multiple times, and the binary data to be binary convolved in the third register 130 will be updated multiple times. When performing a filtering operation, the multiplication / binary operation module 150 multiplies each data to be filtered in the second register group 120 with the corresponding filtering coefficient in the first register group 110 to obtain multiple filtering product data, and when performing a binary convolution operation, the binary data to be binary convolved in the third register 130 and each convolution coefficient in the first register group 110 are binary operated to obtain multiple binary operation data. When performing filtering operation, the addition module 170 adds the multiple filtering product data obtained by the multiplication / binary operation module 150 to obtain filtering result data. When performing binary convolution operation, the previous multiple binary convolution temporary result data and the multiple binary operation data currently obtained by the multiplication / binary operation module are respectively added to obtain the current multiple binary convolution temporary result data. When performing binary convolution operation, the convolution coefficient in the first register group 110 and the binarized data to be binary convolved in the third register are updated each time, and the current multiple binary convolution temporary result data are obtained based on the updated convolution coefficient and the updated binarized data to be binary convolved. After the convolution coefficient is updated to a predetermined number of times, the multiple binary convolution temporary result data obtained for the last time are output as multiple binary convolution final result data.

[0018] In one embodiment, the composite operation circuit further includes: a fourth register group 160, a fifth register group 180 and a sixth register 190. The fourth register group 160 is used to cache multiple filter product data obtained by the multiplication / binary operation module 150 during filtering operation, and cache multiple binary operation data obtained by the multiplication / binary operation module 150 during binary convolution operation. When performing binary convolution operation, the addition module 170 adds the previous multiple binary convolution temporary result data cached by the fifth register group 180 to the multiple binary operation data currently obtained by the multiplication / binary operation module 150 to obtain the current multiple binary convolution temporary result data, and caches the obtained current multiple binary convolution temporary result data into the fifth register group 180. The sixth register 190 is used to cache the filter result data obtained by the addition module 170 during filtering operation.

[0019] It can be seen that the filtering operation and the binary convolution operation time-share the first register group 110, the multiplication / binary operation module 150, the addition module 170, and the fourth register group 160, which saves hardware overhead.

[0020] In one embodiment, the composite operation circuit further includes a random access memory 140. The random access memory 140 is used to cache the multiple filter coefficients into the first register group 110 when performing a filter operation, and update the multiple convolution coefficients to the first register group 110 when performing a binary convolution operation.

[0021] The first register group 110 includes a plurality of first registers 111. Each first register is used to cache one of the plurality of filter coefficients when performing filtering operation, and cache one of the plurality of convolution coefficients when performing binary convolution operation. The second register group 120 includes a plurality of second registers 121, and the plurality of second registers correspond to the plurality of first registers respectively. The plurality of second registers are arranged in sequence to form a shift register. The first second register in the shift register receives the input data to be filtered in sequence. Each time a new data to be filtered is received, each second register in the shift register shifts the data to be filtered cached therein to the next second register. The first second register in the shift register caches the new data to be filtered, and the last second register in the shift register outputs or deletes the data to be filtered cached therein. The fourth register group 160 includes a plurality of fourth registers 161, and each fourth register is used to cache a filter product data obtained by the multiplication / binary operation module when performing filtering operation, and cache a binary operation data obtained by the multiplication / binary operation module when performing binary convolution operation. The fifth register group 180 includes a plurality of fifth registers 181, each fifth register 181 being used to cache the addition module to obtain a temporary binary convolution result data when performing a binary convolution operation.

[0022] like Figure 1 In the example shown, 8 first registers 111, 8 second registers 121, 8 fourth registers 161, and 8 fifth registers 181 are shown. In other embodiments, there may be m first registers, m second registers, m fourth registers, and m fifth registers, the multiple filter coefficients are m filter coefficients, the multiple convolution coefficients are m convolution coefficients, and m is a natural number greater than or equal to 2. The filtering operation is an FIR filtering operation, and the first register, the second register, and the third register are all N-bit registers, and N is a natural number greater than or equal to 2. Preferably, the first register group and the second register group are both vector registers, which can improve the data loading speed and the operation speed.

[0023] like Figure 1 As shown, the multiplication / binary operation module 150 includes a plurality of multiplication / binary operation units 151, such as m multiplication / binary operation units ( Figure 1 m=8). Each multiplication / binary operation unit corresponds to a first register 111 and a second register 121. When performing filtering operation, each multiplication / binary operation unit multiplies the filtering coefficient cached in the corresponding first register 111 with the data to be filtered cached in the corresponding second register 121 to obtain a filtering product data. Each fourth register 161 caches a filtering product data obtained by a corresponding multiplication / binary operation unit 151. When performing binary convolution operation, each multiplication / binary operation unit 151 performs a binary operation on the convolution coefficient cached in the corresponding first register 111 and the binary data to be binary convolved cached in the third register 130 to obtain a binary operation data. Each fourth register 161 caches a binary operation data obtained by a corresponding multiplication / binary operation unit. In one embodiment, each multiplication / binary operation unit includes a multiplication unit and a binary operation unit. When performing a filtering operation, the multiplication unit of the multiplication / binary operation unit works, that is, performs a multiplication operation, and the binary operation unit of the multiplication / binary operation unit does not work. When performing a binary convolution operation, the binary operation unit of the multiplication / binary operation unit works, that is, performs a binary operation, and the multiplication unit of the multiplication / binary operation unit does not work.

[0024] like Figure 1 As shown, the adding module 170 includes a plurality of adding units 171, such as m adding units ( Figure 1 Each adding unit 171 corresponds to a multiplication / binary operation unit 151. Each adding unit is used to add a previous binary convolution temporary result data and a binary operation data currently obtained by the multiplication / binary operation unit to obtain a current binary convolution temporary result data when performing a binary convolution operation. Each fifth register 181 caches a binary convolution temporary result data obtained by a corresponding adding unit 171.

[0025] like Figure 1 As shown, part or all of the adding unit 171 is used to add multiple filtering product data obtained by each multiplication / binary operation unit to obtain filtering result data when performing filtering operation, and the sixth register 190 caches the filtering result data obtained by the adding module. Figure 1In the example shown, m=8, there are 8 adding units in total, wherein the adding unit add0 adds the 0th and 4th filter product data obtained by the multiplication / binary operation unit (Binconv / Mul0, Binconv / Mul4), the adding unit add1 adds the 1st and 5th filter product data obtained by the multiplication / binary operation unit (Binconv / Mul1, Binconv / Mul5), and the adding unit add2 adds the 1st and 5th filter product data obtained by the multiplication / binary operation unit (Binconv / Mul3, Binconv / Mul4). The said adding unit add0 adds the result of the said adding unit add1 and the result of the said adding unit add5. The said adding unit add6 adds the result of the said adding unit add4 and the result of the said adding unit add5 to obtain the final filtering result data, and finally outputs it to the sixth register 190. The said adding unit add7 is not used in the filtering operation.

[0026] When the composite operation circuit performs FIR filtering operation, that is, when used as an FIR filter, the following FIR filtering operation is performed:

[0027] Among them, x t-i is the data to be filtered cached in the past; w i is a fixed filter coefficient, y t is the filtering result data (i.e., the data after FIR filtering) output at the current time t, which is stored in the sixth register 190, and i is the position or serial number of the corresponding unit, parameter, or data, i.e. Figure 1 0-7 in the example shown in . That is, when the FIR filter is operated, the m filter coefficients w i are cached in m first registers 111 (for example, i is 0-7 respectively), and the m data to be filtered x t-i They are cached in m second registers 121 (for example, i is 0-7 respectively), the multiplication / binary operation module 150 performs the multiplication operation, and the addition module 170 performs the addition operation.

[0028] When the composite operation circuit performs a binary convolution operation, that is, when used as a binary convolution operation unit, the following binary convolution operation is performed:

[0029]

[0030]

[0031] Among them, x k The binary data to be binary convolved for the k+1th time (for example, N-bit binary data, such as N=16) is cached in the third register 130. The Binconv function is a binary operation function. The HammingWeight function is used to calculate the number of "1"s in the current binary data. For example, HammingWeight (0101) is 2, and N is The data width is is the convolution coefficient updated for the k+1th time (for example, N-bit binary data, such as N=16), stored in the corresponding first register [i], ⊙ is the exclusive OR operator, during the operation, Updated as k changes, K+1 is the predetermined number of times the convolution coefficient is updated; y i It is the temporary result data of the i-th binary convolution, stored in the fifth register [i], where [i] is the position or serial number of the corresponding unit, parameter or data.

[0032] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0033] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify and vary the above embodiments within the scope of the present invention.

Claims

1. A composite operation circuit in an integrated circuit, characterized in that: It includes: A first register group is used to cache a plurality of filter coefficients when performing a filter operation, and to cache a plurality of convolution coefficients when performing a binary convolution operation; The second register group is used to receive and shift cache a plurality of to-be-filtered data input in sequence when performing filtering operation; The third register is used to receive and cache the input binary data to be binary convolved when performing binary convolution operation; Multiplication / binary operation module; and Addition module, The multiplication / binary operation module and the addition module perform multiplication and addition operations based on the data to be filtered and the filter coefficient when performing filtering operations, and perform binary operations and addition operations based on the convolution coefficient and the binarized data to be binary convolved when performing binary convolution operations.

2. The composite operation circuit according to claim 1, characterized in that: The first register group caches a plurality of convolution coefficients each time when performing a binary convolution operation, and the third register caches a binary data to be binary convolved each time when performing a binary convolution operation, wherein when performing a binary convolution operation, the plurality of convolution coefficients in the first register group will be updated multiple times, and the binary data to be binary convolved in the third register will be updated multiple times; The multiplication / binary operation module performs a multiplication operation on each to-be-filtered data in the second register group and the corresponding filter coefficient in the first register group when performing a filtering operation, to obtain a plurality of filtering product data; and performs a binary operation on the to-be-binary-convolved binary data in the third register and each convolution coefficient in the first register group when performing a binary convolution operation, to obtain a plurality of binary operation data; When performing filtering operation, the addition module adds multiple filtering product data obtained by the multiplication / binary operation module to obtain filtering result data. When performing binary convolution operation, the previous multiple binary convolution temporary result data and the multiple binary operation data currently obtained by the multiplication / binary operation module are respectively added to obtain the current multiple binary convolution temporary result data. When performing binary convolution operation, the convolution coefficient in the first register group and the binarized data to be binary convolved in the third register are updated each time, and the current multiple binary convolution temporary result data are obtained based on the updated convolution coefficient and the updated binarized data to be binary convolved. After the convolution coefficient and the binarized data to be binary convolved are updated to a predetermined number of times, the multiple binary convolution temporary result data obtained for the last time are output as multiple binary convolution final result data.

3. The composite operation circuit according to claim 2, characterized in that: It also includes: A fourth register group, which is used to cache a plurality of filter product data obtained by the multiplication / binary operation module during filtering operation, and cache a plurality of binary operation data obtained by the multiplication / binary operation module during binary convolution operation; a fifth register group, wherein when performing a binary convolution operation, the addition module adds the previous multiple binary convolution temporary result data cached in the fifth register group and the multiple binary operation data currently obtained by the multiplication / binary operation module to obtain the current multiple binary convolution temporary result data, and caches the obtained current multiple binary convolution temporary result data into the fifth register group; The sixth register is used to cache the filtering result data obtained by the addition module when performing filtering operation.

4. The composite operation circuit according to claim 3, characterized in that: The filtering operation and the binary convolution operation time-share the first register group, the multiplication / binary operation module, the addition module, and the fourth register group.

5. The complex operation circuit according to claim 3, characterized in that: It also includes: The random access memory is used to cache the plurality of filter coefficients into the first register group when performing a filter operation, and to update the plurality of convolution coefficients to the first register group when performing a binary convolution operation.

6. The composite operation circuit according to claim 3, characterized in that: The first register group includes a plurality of first registers, each of which is used to cache one of the plurality of filter coefficients when performing a filtering operation, and to cache one of the plurality of convolution coefficients when performing a binary convolution operation; The second register group includes a plurality of second registers, each of which corresponds to a plurality of first registers. The plurality of second registers are sequentially arranged to form a shift register. The first second register in the shift register sequentially receives input data to be filtered. Each time a new data to be filtered is received, each second register in the shift register shifts the data to be filtered cached therein to the next second register. The first second register in the shift register caches the new data to be filtered, and the last second register in the shift register outputs or deletes the data to be filtered cached therein. The fourth register group includes a plurality of fourth registers, each of which is used to cache a filtering product data obtained by the multiplication / binary operation module during filtering operation, and cache a binary operation data obtained by the multiplication / binary operation module during binary convolution operation; The fifth register group includes a plurality of fifth registers, each of which is used to cache the addition module to obtain a temporary binary convolution result data when performing a binary convolution operation.

7. The composite operation circuit according to claim 6, characterized in that: The multiplication / binary operation module includes a plurality of multiplication / binary operation units, each of which corresponds to a first register and a second register. When performing a filtering operation, each multiplication / binary operation unit multiplies the filtering coefficient cached in the corresponding first register with the data to be filtered cached in the corresponding second register to obtain a filtering product data. Each fourth register caches a filtering product data obtained by a corresponding multiplication / binary operation unit. When performing a binary convolution operation, each multiplication / binary operation unit performs a binary operation on the convolution coefficient cached in the corresponding first register and the binarized data to be binary convolved cached in the third register to obtain a binary operation data. Each fourth register caches a binary operation data obtained by a corresponding multiplication / binary operation unit.

8. The complex operation circuit according to claim 7, characterized in that: The addition module includes a plurality of addition units, each of which corresponds to a multiplication / binary operation unit, and each of which is used to add a previous binary convolution temporary result data and a binary operation data currently obtained by the multiplication / binary operation unit to obtain a current binary convolution temporary result data when performing a binary convolution operation, and each fifth register caches a binary convolution temporary result data obtained by a corresponding addition unit, Part or all of the adding unit is used to add multiple filtering product data obtained by each multiplication / binary operation unit to obtain filtering result data when performing filtering operation, and the sixth register caches the filtering result data obtained by the adding module.

9. The complex operation circuit according to claim 3, characterized in that: The filtering operation is a FIR filtering operation, The first register, the second register, and the third register are all N-bit registers, where N is a natural number greater than or equal to 2. The first register group and the second register group are both vector registers.

10. The complex operation circuit according to claim 7, characterized in that: Each multiplication / binary operation unit includes a multiplication unit and a binary operation unit. When performing a filtering operation, the multiplication unit of the multiplication / binary operation unit works, and the binary operation unit of the multiplication / binary operation unit does not work. When performing a binary convolution operation, the binary operation unit of the multiplication / binary operation unit works, and the multiplication unit of the multiplication / binary operation unit does not work.

11. The complex operation circuit according to claim 10, characterized in that: Each binary operation unit performs the following binary operations: Among them, x k is the binary data to be convolved for the k+1th time. Binconv function is a binary operation function. HammingWeight function is used to calculate the number of "1" in the current binary data. N is The data width is is the convolution coefficient updated for the k+1th time, ⊙ is the same or equal operator, during the operation, It is updated as k changes, K+1 is the predetermined threshold of the number of updates of the convolution coefficient, and i is the position or serial number of the corresponding unit, parameter or data.

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