Reordering of composite condition sets for faster short circuits

Abstract

Embodiments of this disclosure relate to faster short-circuiting reordering of composite condition sets. A computing device is provided, comprising a processor configured to receive source code at a compiler. The source code may include at least one composite condition set having multiple conditions. The source code may also include a corresponding code block for each of the multiple conditions, the corresponding code block including instructions for evaluating the condition. For each of a plurality of sorts of the multiple conditions, the processor may determine that the sort satisfies one or more validity constraints. For each of the plurality of sorts satisfying one or more validity constraints, the processor may determine a corresponding estimated computational cost for the sort. The processor may reorder the multiple conditions to have a sort with the lowest estimated computational cost among the plurality of sorts satisfying one or more validity constraints.

Description

[0001] This application is a divisional application of patent application No. 201980025128.4, filed on October 10, 2020, entitled "Reordering of Composite Condition Sets for Faster Short Circuits". Technical Field

[0002] The embodiments disclosed herein relate to the field of computers. Background Technology

[0003] A compound conditional is a code structure in which two or more conditions are checked to determine whether to execute one set of instructions or another. For example, a compound conditional can be included in an "if" statement, a "for" loop, or a "while" loop. Checking a compound conditional can involve checking whether each of the two or more conditions is true. For example, a compound conditional can have the form: "if(a&&b)" or "if(a||b)".

[0004] Conditions in a composite condition set are evaluated at runtime in the order they appear in the code. Checking some conditions may be computationally more expensive than checking others. Programmers can prioritize listing the least computationally expensive conditions to avoid checking more expensive conditions when no such evaluation is needed based on the first result, thus saving processing time. However, when writing source code that includes composite condition sets, programmers may not know which conditions in the composite condition set are more expensive to check than others. Therefore, conditions may be arranged in a suboptimal order, i.e., more expensive conditions may be evaluated before less expensive ones. This can lead to wasted processing resources and slowed code execution.

[0005] Consider the following composite condition set:

[0006] If(condition1&&condition2&&condition3){

[0007] }else{

[0008] }

[0009] Each set of conditions is a Boolean predicate. Therefore, these conditions can be composed into conjunctions or disjunctions.

[0010] In the code example above, the basic code generation scheme will first evaluate the following expressions, which evaluate condition1, condition2, and condition3. Then, the generated code will perform the "&&" operation to evaluate the final single condition value, based on which the following judgment will be made: whether the IF code or the ELSE code should be executed.

[0011] Some existing compilers use conditional short-circuiting for optimization. Short-circuiting recognizes that if condition1 is false, there's no need to evaluate the expressions used to evaluate condition2 and condition3. The short-circuit then generates a jump accordingly. Short-circuiting saves the computational cost of evaluating additional condition variables. The generated code is shown below:

[0012] Compute expression that calculates condition1

[0013] If! condition1, jump to ELSE code

[0014] Compute expression that calculates condition2

[0015] If! condition2, jump to ELSE code

[0016] Compute expression that calculates condition3

[0017] If! condition3, jump to ELSE code

[0018] IF CODE

[0019] GOTO CONDITION REGION END

[0020] ELSE CODE

[0021] REGION END: ...

[0022] (Calculate the expression used to calculate condition1)

[0023] if! con If dition1 is selected, then jump to the ELSE code.

[0024] Calculate the expression used to calculate condition2.

[0025] if! con ditio n 2. Then jump to the ELSE code.

[0026] Calculate the expression used to calculate condition3.

[0027] If condition3 is true, then jump to the ELSE code.

[0028] IF code

[0029] End of conditional area

[0030] ELSE code

[0031] Zone ends:…)

[0032] However, even if the compiler can use such short-circuiting techniques, the developer may not be aware of the corresponding computational cost of different orderings. Therefore, inefficient code may be written and compiled when short-circuiting produces more efficient code. Summary of the Invention

[0033] According to one aspect of this disclosure, a computing device is provided, comprising a processor configured to receive source code at a compiler. The source code may include at least one composite set of conditions having multiple conditions. For each of the multiple conditions, the source code may further include a corresponding code block comprising instructions for evaluating the condition. For each of a plurality of sorts of the multiple conditions, the processor may further be configured to determine that the sort satisfies one or more validity constraints. For each of the plurality of sorts satisfying one or more validity constraints, the processor may further be configured to determine a corresponding estimated computational cost for that sort. The processor may also be configured to reorder the multiple conditions to have a sort with the lowest estimated computational cost among the plurality of sorts satisfying one or more validity constraints.

[0034] This summary provides a simplified overview of some concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to addressing any or all of the shortcomings pointed out in any part of this disclosure. Attached Figure Description

[0035] Figure 1 An example embodiment of a computing device according to one embodiment of the present disclosure is shown.

[0036] Figure 2 It shows according to Figure 1The embodiments include sample source code for "if" statements.

[0037] Figure 3 It shows according to Figure 1 The embodiments include example source code for a "while" loop.

[0038] Figure 4 It shows according to Figure 1 An example of computational cost estimation in an embodiment.

[0039] Figure 5 An example method that can be executed by a processor of a computing device according to an embodiment of the present disclosure is shown.

[0040] Figure 6 A schematic diagram of an example computing system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0041] To address the aforementioned challenges, a computing device is provided. Figure 1 An example embodiment of a computing device 10 is shown, which may include a volatile storage device 12, a non-volatile storage device 14, and / or a processor 16. The volatile storage device 12 and the non-volatile storage device 14 may each include a memory address configured to store data. The processor 16 may be configured to run a compiler 30 configured to receive source code 20 and translate it into assembly code 38. The translation of source code 20 into assembly code 38 when source code 20 includes at least one composite condition set 22 is described herein with reference to the systems and methods illustrated in the accompanying drawings of this disclosure.

[0042] refer to Figure 2 , Figure 1 Example source code 20 is shown in further detail. Figure 1 and Figure 2 As shown, example source code 20 includes a complex set of conditions 22 in the form of an "if" statement. Source code 20 received by compiler 30 may include at least one complex set of conditions 22. The complex set of conditions 22 may include multiple conditions 24, each of which may have a Boolean value (true or false). Source code 20 may include a corresponding code block 26 for each of the multiple conditions 24, the corresponding code block 26 including one or more instructions 28 for evaluating condition 24. When one or more instructions 28 are evaluated, code block 26 may return a Boolean value for condition 24. In some embodiments, each code block 26 may be a basic block in which no branching occurs. Alternatively, at least one code block 26 may include multiple basic blocks.

[0043] The composite condition set 22 can return a Boolean value based on the Boolean values ​​of multiple conditions 24. For example... Figure 2 As shown, source code 20 may also include a first branch code block 42, which includes one or more first branch evaluation instructions 44 configured to be executed when multiple conditions 24 are true. Figure 2 In one embodiment, the composite condition set 22 includes a logical operator 40, shown herein as the AND (&&) logical operator. However, in other embodiments, the composite condition set 22 may be expressed using another logical operator 40, such as OR, XOR, or NAND. The Boolean value of the composite condition set can be evaluated by applying the logical operator 40 to multiple conditions 24. The source code 20 may also include a second branch code block 46, which includes one or more second branch evaluation instructions 48 configured to be executed when at least one of the multiple conditions 24 is false. Figure 2 As shown, the second branch code block 46 can be the "else" branch of an "if" statement.

[0044] although Figure 1 and Figure 2 The composite condition set 22 is shown as having two conditions 24, but other numbers of conditions 24 may also be considered. In some embodiments, the composite condition set 22 may include three or more conditions 24. In such embodiments, the composite condition set 22 may also include two or more logical operators 40 that can be applied to conditions 24 to evaluate the composite condition set 22.

[0045] In addition to the compound condition set 22, the first branch code block 42, and the second branch code block 46, the source code 20 may also include other code blocks, such as... Figure 2 The ellipse shown is before the composite condition set 22 and after the second branch code block 46.

[0046] return Figure 1 The composite condition set 22 can be sent to the compiler 30. The compiler 30 can be configured to determine multiple orders 32 among the multiple conditions 24 included in the composite condition set 22. In some embodiments, the compiler 30 can determine each possible order 32 of the multiple conditions 24. In other embodiments, the compiler 30 can determine only a subset of all possible orders 32 of the conditions 24.

[0047] As a corollary of Rice's theorem, there is no algorithm that can always determine which condition 24 has the lowest computational cost for any composite condition set 22. However, the condition 24 that may have the lowest computational cost can be identified using heuristics. Such heuristics can be based on the syntactic properties of one or more instructions 28 included in the corresponding code block 26 for each condition 24.

[0048] For each of the multiple sorts 32 of condition 24, processor 16 may also be configured to determine that the sort 32 satisfies one or more legality constraints 34. Legality constraints 34 are defined herein as constraints based on one or more syntactic properties of one or more conditions 24 having a particular sort 32, such that when one or more conditions 24 do not satisfy legality constraints 34, processor 16 is configured to prevent compiler 30 from using that sort 32 to output assembly code 38. Therefore, by determining which sorts 32 satisfy one or more legality constraints 34, processor 16 can prevent errors in the assembly code 38 that may arise from reordering conditions 24. See below for reference. Figure 2 The validity constraint 34 of the example is discussed.

[0049] In an embodiment where source code 20 includes a first branch code block 42 and a second branch code block 46, the first branch code block 42 includes one or more first branch evaluation instructions 44 configured to be executed when a plurality of conditions 24 are true, and the second branch code block 46 includes one or more second branch evaluation instructions 48 configured to be executed when at least one of the plurality of conditions 24 is false. One or more legality constraints 34 include the following constraint: source code 20 includes a first branch code block 42 and a second branch code block 46. When the above legality constraints 34 are satisfied, source code 20 does not include more than one first branch code block 42 and / or more than one second branch code block 46. Additionally or alternatively, one or more legality constraints 34 may include the following constraint: the corresponding code block 26 for each condition 24 includes provisions for proceeding to a common target code block (which is located in...). Figure 2 Instruction 28 is shown as the first branch code block 42. Therefore, compiler 30 can prevent changes in the order 32 of multiple conditions 24 from affecting which code block is executed after the evaluation of the composite condition set 22.

[0050] In some embodiments, such as Figure 3As shown, source code 20 may include a portion 50 that follows the last code block 26 of the respective code blocks 26 of multiple conditions 24 and precedes a shared target code block. For example, when a compound condition set 22 is included in a "while" loop, as... Figure 3 As shown, a portion 50 of source code 20 may be at least one code block, which includes one or more instructions for incrementing variables. Other functionalities of portion 50 of source code 20 are also considered. In such an embodiment, one or more legality constraints 34 may include the constraint that a portion 50 of source code 20, following the last code block 26 of the respective code blocks 26 of the plurality of conditions 24 and preceding the common target code block, has an entry point and an exit point. In such an embodiment, the entry point may be an instruction in portion 50 of source code 20, at which processor 16 may begin execution of portion 50 of source code 20. Similarly, the exit point may be an instruction at which processor 16 ceases execution of portion 50 of source code 20.

[0051] In some embodiments, one or more legality constraints 34 may include constraints that prevent instruction 28 from calling an undefined variable. Two example scenarios where instruction 28 may call an undefined variable are discussed below. In one example, the undefined variable may be an untracked memory address. An undefined variable error may occur when instruction 28, used to dereference an untracked memory address, occurs before instruction 28 used to track the untracked memory address. In a second example, an undefined variable error may occur when instruction 28 uses the variable before another instruction 28 that defines the variable.

[0052] In some embodiments, one or more validity constraints 34 may include the constraint that no code block 26 includes instruction 28, which is a division or remainder operation, wherein the divisor may have a value of zero. By checking this validity constraint 34, the processor 16 can prevent division-by-zero errors due to reordering of condition 24.

[0053] When none of the candidate reorderings included in multiple sorting 32 satisfy each of the legality constraints 34 checked by processor 16, compiler 30 may output warning message 52, such as Figure 1 As shown. In some embodiments, warning message 52 may include an indication that the composite condition set 22 cannot be reordered to have a less computationally expensive sorting 32. Warning message 52 may include an indication of the location (e.g., line number) of the composite condition set 22 in the source code 20. In some embodiments, when compiler 30 outputs warning message 52, compiler 30 does not output assembly code 38.

[0054] For each of a plurality of sequences 32 that satisfy one or more legality constraints 34, the processor 16 may also be configured to determine a corresponding estimated computational cost 36 for that sequence 32. The corresponding estimated computational cost 36 for the sequence 32 may be determined based on predetermined static values ​​of one or more instructions 28 assigned to each code block 26. Therefore, the estimated computational cost 36 for the sequence 32 can be determined without having to collect data relating to historical computational costs of similar instructions.

[0055] refer to Figure 4 The determination of the estimated computational cost 36 according to an example embodiment is shown in further detail. Figure 4 As shown, when multiple conditions 24 have a specific order 32, in order to determine the estimated computational cost 36 of the code block 26 included in condition 24, processor 16 may refer to an estimated computational cost table 60 for each instruction 28 included in code block 26, which contains predetermined static values ​​for each instruction type in the code block. Therefore, for one or more types of operation 62, estimated computational cost table 60 may include an estimated cost score 64 associated with that operation 62. The types of operation 62 may include, for example, addition, subtraction, comparison, negation, division, remainder, AND, OR, XOR, minimum, maximum, load, store, and / or one or more other operations 62. Each type of operation 62 listed in the estimated computational cost table may have an estimated cost score 64, such as... Figure 4 The second column of the estimated computation cost table 60 is shown. In some embodiments, each operation may have an estimated integer cost and an estimated floating-point cost. When performed using integer computation, the estimated integer cost may be the estimated cost score 64 of operation 62, while when performed using floating-point computation, the estimated floating-point cost may be the estimated cost score 64 of operation 62.

[0056] Processor 16 can be configured to determine the corresponding estimated cost score 64 for each instruction 28 included in code block 26 by generally referring to the table discussed above. Additionally, when multiple conditions 24 have an ordering 32, processor 16 can determine the corresponding estimated cost score 64 for each instruction 28 of each code block 26 in this manner. Therefore, processor 16 can be configured to assign an estimated cost score 64 to each instruction 28 included in ordering 32. Based on the corresponding estimated cost score 64 for each instruction 28, processor 16 can determine the estimated computational cost 36 of the ordering. For example, the estimated computational cost 36 of ordering 32 can be determined by summing the corresponding estimated cost scores 64 assigned to each instruction 28. Alternatively, the estimated computational cost 36 can be determined using some other formula. For example, a weighting factor can be applied to at least one estimated cost score 64.

[0057] In some embodiments, processor 16 may determine the estimated computational cost 36 for each sort 32 only, rather than satisfying one or more validity constraints 34. In other embodiments, processor 16 may determine the estimated computational cost 36 of each sort 32 before checking whether each sort 32 satisfies one or more validity constraints 34. In such embodiments, processor 16 may be configured to discard any sort 32 with an estimated computational cost 36 exceeding a predetermined threshold. Filtering of estimated computational costs may occur before checking for satisfaction of one or more validity constraints 34.

[0058] Processor 16 can also be configured to determine the sort 32 with the lowest estimated computational cost 36 among a plurality of sorts 32 satisfying one or more legality constraints 34. Processor 16 can then reorder the plurality of conditions 24 to have the sort 32 with the lowest estimated computational cost 36 among the plurality of sorts 32 satisfying one or more legality constraints 34. If the sort with the lowest estimated computational cost 36 is the original sort 32 among the plurality of conditions 24, processor 16 can be configured to maintain the original sort 32. If two or more sorts 32 are bundled together to obtain the lowest estimated computational cost 36, processor 16 can select one of the two or more sorts 32 and reorder the plurality of conditions 24 to have the selected sort 32, or if the original sort 32 is included in two or more sorts 32, processor 16 maintains the original sort 32.

[0059] In an embodiment where the estimated computational cost 36 of a sort 32 is determined before checking whether a sort 32 satisfies one or more legality constraints 34, the processor 16 can be configured to rank one or more sorts 32 by the estimated computational cost 36. The processor 16 can then determine whether each sort 32 satisfies one or more legality constraints 34 in ascending order of the estimated computational cost 36 among the sorts 32. Therefore, the processor 16 can check the satisfaction of one or more legality constraints 34 by a sort 32 until the sort 32 with the lowest estimated computational cost 36 satisfying one or more legality constraints 34 is determined. The processor 16 can also be configured to reorder a plurality of conditions 24 to have sorts 32 with the lowest estimated computational cost 36 satisfying one or more legality constraints 34. For example, checking the estimated computational cost 36 of a sort 32 before checking the legality constraints 34 may be advantageous when the difference in estimated computational costs 36 between sorts 32 is expected to be large and / or when the estimated computational cost 36 of a sort 32 can be determined more quickly compared to whether a sort 32 satisfies one or more legality constraints 34.

[0060] Figure 5A flowchart is shown illustrating a method 100 executed by a processor of a computing device according to an example embodiment. The computing device may be... Figure 1 The computing device 10. At step 102, the method may include: receiving source code at a compiler. The source code may include at least one composite condition set having multiple conditions. In some embodiments, the composite condition set may include three or more conditions. The composite condition set may include two or more Boolean conditions and one or more logical operators, such as AND, OR, XOR, and / or NAND. The composite condition set may also include a corresponding code block for each of the multiple conditions, the corresponding code block including one or more instructions for evaluating the condition. In some embodiments, each code block may be a basic block. In other embodiments, at least one code block may include multiple basic blocks.

[0061] In step 104, method 100 may further include: determining, for each of a plurality of sorts of conditions, that the sort satisfies one or more legality constraints. The legality constraints are constraints based on one or more syntactic properties of one or more conditions having a particular sort, such that when one or more conditions do not satisfy the legality constraints, outputting assembly code using that sort is prohibited. As an example, one or more legality constraints may include the constraint that the corresponding code block for each condition includes instructions for proceeding to a common target code block. Therefore, unwanted branches depending on the sorting of conditions can be prevented.

[0062] As another example, one or more legality constraints may include the following constraint: the portion of the source code that follows the last code block of the respective code blocks for multiple conditions and precedes a common target code block has an entry point and an exit point. This legality constraint can prevent the processor from skipping instructions before the entry point or after the exit point because it does not want to enter and / or exit the portion of the source code that follows the last code block and precedes the common target code block.

[0063] As another example, one or more legality constraints include a constraint that no instruction calls an undefined variable. When a variable is defined in the first condition of the original order of conditions and subsequently called in the second condition, a call to an undefined variable can occur when the second condition is moved before the first condition. The aforementioned legality constraints can be checked to determine if such a reordering was performed.

[0064] As another example, one or more legality constraints may include the following constraint: no code block contains instructions for division or remainder operations, where the divisor may have a zero value.

[0065] In some embodiments, the source code may further include a first branch code block comprising one or more first branch evaluation instructions configured to be executed when multiple conditions are true. The source code may also include a second branch code block comprising one or more second branch evaluation instructions configured to be executed when at least one of the multiple conditions is false. For example, when a complex set of conditions is included in an "if" statement, the second branch code block may be the "else" branch of the "if" statement. In such embodiments, one or more validity constraints may include the constraint that the source code includes one first branch code block and one second branch code block, rather than including multiple first branch code blocks and / or multiple second branch code blocks.

[0066] At step 106, method 100 may further include: determining a corresponding estimated computational cost for each of a plurality of sorts satisfying one or more legality constraints. In some embodiments, determining the corresponding estimated computational cost for each sort may include: at step 108, assigning an estimated cost score to each instruction included in the sort. For example, the estimated cost score can be determined by reading the estimated cost score associated with the operation indicated by the instruction from an estimated computational cost table. In some embodiments, a weighting factor may be applied to the estimated cost scores of one or more instructions. At step 110, the estimated computational cost of the sort may then be determined, for example, by summing the corresponding estimated cost scores assigned to each instruction. In some embodiments, one or more other operations may be additionally or alternatively performed on the estimated cost scores to determine the estimated computational cost of the sort.

[0067] At step 112, method 100 may further include: reordering the multiple conditions to have the lowest estimated computational cost among multiple orderings that satisfy one or more legality constraints. Alternatively, method 100 may include maintaining the original ordering when the original ordering of the multiple conditions satisfies one or more legality constraints and has the lowest estimated computational cost.

[0068] Although in the systems and methods described above, the reordered at least one composite condition set includes two conditions, embodiments in which more than two conditions are reordered can also be considered. For example, the composite condition set may be of the form "if(a||b)&&(c||d)". In such an example, blocks "(a||b)" and "(c||d)" can be reordered so that the composite condition set becomes "if(c||d)&&(a||b)". Alternatively, conditions a, b, c, and d can be reordered so that the composite condition set becomes "if(b||a)&&(d||c)" in one example. In embodiments in which more than two conditions are evaluated, one or more conditions may have corresponding code blocks comprising multiple basic blocks.

[0069] The reordering of composite condition sets described above can be summarized as including the reordering of code blocks not included in the composite condition set, as shown in the example code provided below. In the example, the code blocks included in the following C++ code can be reordered:

[0070]

[0071] In the example code shown above, the computational cost of "var" is higher than that of "pred". Therefore, the execution computational cost of the example code can be reduced by reordering the code blocks in the following order: Block 5, Block 1, Block 2, Block 3, Block 4, Block 6, Block 7. Systems and methods for legality constraint checking and computational cost estimation can be applied to determine the order of code blocks that satisfy one or more legality constraints and have the lowest estimated computational cost.

[0072] To this end, a computing device can be provided, configured to perform the following methods. Initially, source code, comprising multiple code blocks, can be received at a compiler. The source code may have an initial order, which is one of multiple possible orderings. That is, the initial ordering can be reordered into one of multiple candidate reorderings. For each of the multiple orderings of the multiple code blocks, the computing device can be configured to determine that the ordering satisfies one or more legality constraints, similar to those discussed above. For each of the multiple orderings satisfying one or more legality constraints, the computing device can be configured to determine a corresponding estimated computational cost for that ordering and reorder the multiple code blocks to have the ordering with the lowest estimated computational cost among the multiple orderings satisfying one or more legality constraints. The estimated computational cost can be determined using methods similar to those described above.

[0073] Using the system and method described above, a computing device can determine which of multiple complex condition sets is most likely to require the least computational resources while also satisfying syntactic validity constraints. This approach avoids the unnecessary processing of existing systems where complex condition sets don't need to be evaluated before simpler conditions that fail to pass tests. Therefore, the system and method described above can achieve higher execution efficiency for compiled code than code compiled using previously existing methods.

[0074] In some embodiments, the methods and processes described herein may be associated with a computing system of one or more computing devices. In particular, such methods and processes may be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0075] Figure 6 A non-limiting embodiment of a computing system 200 capable of implementing one or more methods and processes described above is schematically shown. The computing system 200 is shown in a simplified form. For example, the computing system 200 may be implemented... Figure 1 The computing device 10, or alternatively, may implement some other computing system. The computing system 200 may take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), and / or other computing devices, as well as wearable computing devices (such as smartwatches and head-mounted augmented / virtual reality devices).

[0076] The computing system 200 includes a logic processor 202, volatile memory 204, and non-volatile storage device 206. The computing system 200 may optionally include a display subsystem 208, an input subsystem 210, a communication subsystem 212, and / or... Figure 6 Other components not shown.

[0077] The logic processor 202 includes one or more physical devices configured to execute instructions. For example, the logic processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform tasks, implement data types, transform the state of one or more components, achieve technical effects, or otherwise achieve desired results.

[0078] The logic processor 202 may include one or more physical processors (hardware) configured to execute software instructions. Additionally or alternatively, the logic processor 202 may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processor of the logic processor 202 may be single-core or multi-core, and the instructions executed thereon may be configured for sequential processing, parallel processing, and / or distributed processing. The various components of the logic processor 202 may optionally be distributed across two or more separate devices that may be remotely located and / or configured for coordinated processing. Various aspects of the logic processor may be virtualized and executed by remotely accessible networked computing devices configured in a cloud computing configuration. In this case, these virtualized aspects may run on different physical logic processors on various different machines.

[0079] Volatile memory 204 may include a physical device including random access memory. Volatile memory 204 is typically used by logic processor 202 to temporarily store information during the processing of software instructions. It should be understood that when power to volatile memory 204 is cut off, volatile memory 204 typically will not continue storing instructions.

[0080] The non-volatile storage device 206 includes one or more physical devices configured to store instructions executable by a logic processor to implement the methods and processes described herein. When such methods and processes are implemented, the state of the non-volatile storage device 206 can be transformed, for example, to store different data.

[0081] Non-volatile storage device 206 may include removable and / or built-in physical devices. Non-volatile storage device 206 may include optical memory (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor memory (e.g., ROM, EPROM, EEPROM, FLASH memory, etc.), and / or magnetic memory (e.g., hard disk drive, floppy disk drive, magnetic tape drive, MRAM, etc.), or other high-capacity storage device technologies. Non-volatile storage device 206 may include non-volatile devices, dynamic devices, static devices, read / write devices, read-only devices, sequential access devices, location-addressable devices, file-addressable devices, and / or content-addressable devices. It should be understood that even when the power supply to non-volatile storage device 206 is disconnected, the non-volatile storage device 206 is configured to save instructions.

[0082] Various aspects of the logic processor 202, volatile memory 204, and non-volatile storage device 206 can be integrated together into one or more hardware logic components. For example, such hardware logic components may include field-programmable gate arrays (FPGAs), programmable and application-specific integrated circuits (PASICs / ASICs), programmable standard products and application-specific standard products (PSSPs / ASSPs), system-on-a-chip (SoCs), and complex programmable logic devices (CPLDs).

[0083] The term "program" can be used to describe one aspect of a computing system 200 implemented to perform a specific function. In some cases, a program can be instantiated using portions of volatile memory 204 via a logical processor 202 that executes instructions stored in non-volatile memory 206. It should be understood that different programs can be instantiated based on the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same program can be instantiated based on different applications, services, code blocks, objects, routines, APIs, functions, etc. The term "program" encompasses single or grouped executable files, data files, libraries, drivers, scripts, database records, etc.

[0084] When included, display subsystem 208 can be used to present a visual representation of the data stored in non-volatile storage device 206. Because the methods and processes described herein change the data stored in non-volatile storage device 206, thus changing the state of non-volatile storage device 206, the state of display subsystem 208 can also be changed to visually represent the change in the underlying data. Display subsystem 208 may include one or more display devices that utilize virtually any type of technology. Such display devices may be combined with logic processor 202, volatile memory 204, and / or non-volatile storage device 206 in a shared enclosure, or such display devices may be peripheral display devices.

[0085] When included, input subsystem 210 may include or interface with one or more user input devices such as a keyboard, mouse, touchscreen, or game controller. In some embodiments, input subsystem 210 may include or interface with a selected Natural User Input (NUI) component portion. Such a component portion may be an integrated component portion or a peripheral component portion, and the transduction and / or processing of input actions may be handled on-board or off-board. Example NUI component portions may include microphones for speech recognition and / or voice recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection, gaze detection, and / or intent recognition; and an electric field sensing component portion for assessing brain activity; and / or any other suitable sensors.

[0086] When included, the communication subsystem 212 can be configured to communicatively couple the computing system 200 to one or more other computing devices. The communication subsystem 212 may include wired and / or wireless communication devices compatible with one or more different communication protocols. As a non-limiting example, the communication subsystem 212 can be configured to communicate via a wireless telephone network, or a wired or wireless local area network or wide area network. In some embodiments, the communication subsystem 212 may allow the computing system 200 to send messages to and / or receive messages from other devices via a network such as the Internet.

[0087] According to one aspect of this disclosure, a computing device is provided, comprising a processor configured to receive source code at a compiler. The source code may include at least one composite set of conditions having a plurality of conditions; and a corresponding code block for each of the plurality of conditions, the corresponding code block including one or more instructions for evaluating the condition. For each of a plurality of sorts of the plurality of conditions, the processor may also be configured to determine that the sort satisfies one or more validity constraints. For each of the plurality of sorts satisfying one or more validity constraints, the processor may also be configured to determine a corresponding estimated computational cost for that sort. The processor may also be configured to reorder the plurality of conditions to have a sort with the lowest estimated computational cost among the plurality of sorts satisfying one or more validity constraints.

[0088] According to this aspect, the source code may also include a first branch code block, which includes one or more first branch evaluation instructions configured to be executed when multiple conditions are true. The source code may also include a second branch code block, which includes one or more second branch evaluation instructions configured to be executed when at least one of multiple conditions is false.

[0089] According to this aspect, one or more legality constraints may include the following constraint: the source code includes a first branch code block and a second branch code block.

[0090] According to this aspect, one or more legality constraints may include the following constraint: the corresponding code block for each condition includes instructions for proceeding to a common target code block.

[0091] According to this aspect, one or more legality constraints may include the following constraint: the portion of the source code that follows the last code block of the corresponding code block of multiple conditions and precedes the common target code block has an entry point and an exit point.

[0092] According to this aspect, one or more legality constraints may include the following constraint: no instruction calls an undefined variable.

[0093] Based on this aspect, each code block can be a basic block.

[0094] According to this aspect, at least one code block may include multiple basic blocks.

[0095] According to this aspect, the processor can be configured to determine the corresponding estimated computational cost for each sort at least in part by: assigning an estimated cost score to each instruction included in the sort; and summing the corresponding estimated cost scores assigned to each instruction.

[0096] According to another aspect of this disclosure, a method executed by a processor of a computing device is provided. The method may include: receiving source code at a compiler. The source code may include at least one composite set of conditions having multiple conditions; and a corresponding code block for each of the multiple conditions, the corresponding code block including one or more instructions for evaluating the condition. For each of a plurality of sorts of the multiple conditions, the method may further include: determining that the sort satisfies one or more legality constraints. For each of the plurality of sorts satisfying one or more legality constraints, the method may further include: determining a corresponding estimated computational cost for that sort. The method may further include: reordering the multiple conditions to have a sort with the lowest estimated computational cost among the plurality of sorts satisfying one or more legality constraints.

[0097] According to this aspect, the source code may further include a first branch code block comprising one or more first branch evaluation instructions configured to be executed when multiple conditions are true. The source code may also include a second branch code block comprising one or more second branch evaluation instructions configured to be executed when at least one of multiple conditions is false.

[0098] According to this aspect, one or more legality constraints may include the following constraint: the source code includes a first branch code block and a second branch code block.

[0099] According to this aspect, one or more legality constraints include the following constraint: the portion of the source code that follows the last code block of the corresponding code block of multiple conditions and precedes the common target code block has an entry point and an exit point.

[0100] According to this aspect, one or more legality constraints may include the following constraint: no instruction calls an undefined variable.

[0101] Based on this aspect, each code block can be a basic block.

[0102] Based on this aspect, determining the corresponding estimated computational cost for each order includes: assigning an estimated cost score to each instruction included in the order; and summing the corresponding estimated cost scores assigned to each instruction.

[0103] According to another aspect of this disclosure, a computing device is provided, comprising a processor configured to receive source code at a compiler. The source code may include a plurality of code blocks. For each of a plurality of sorts of the plurality of code blocks, the processor may further be configured to determine that the sort satisfies one or more validity constraints. For each of the plurality of sorts satisfying one or more validity constraints, the processor may further be configured to determine a corresponding estimated computational cost for that sort. The processor may also be configured to reorder the plurality of code blocks to have a sort that has the lowest estimated computational cost among the plurality of sorts satisfying one or more validity constraints.

[0104] It should be understood that because many variations are possible, the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered limiting. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions illustrated and / or described may be performed in the illustrated and / or described order, in a different order, in parallel, or omitted. Similarly, the order of the above processes may be changed.

[0105] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations disclosed herein, as well as any and all equivalents thereof.

Claims

1. A computing device, comprising a processor, the processor being configured to: During compiler execution: The source code is received at the compiler, wherein the source code includes: At least one composite condition set having multiple conditions, said composite condition set being configured to be evaluated as part of the execution of assembly code compiled from said source code, to determine which of the multiple branch code blocks of said assembly code will be executed. Each of the plurality of conditions includes a code block comprising one or more instructions for evaluating the condition as part of the execution of the assembly code; Determine that two or more of the multiple orderings of the multiple conditions of the composite condition set satisfy one or more legality constraints, and at least one of the multiple orderings does not satisfy the one or more legality constraints, wherein each of the one or more legality constraints is an order-related constraint based on one or more syntactic properties of the instructions included in the multiple conditions, the multiple conditions having a specific ordering, the specific ordering to be determined to satisfy the order-related constraints. During the execution of the compiler, a corresponding estimated computational cost for each order is determined only for the order by assigning an estimated cost score to each instruction included in each order that satisfies the one or more legality constraints and summing the corresponding estimated cost scores assigned to each instruction, wherein the assignment includes reading the estimated cost score associated with the operation indicated by the corresponding instruction from an estimated computational cost table, the estimated computational cost table indicating the corresponding estimated cost score for multiple operations; The multiple conditions are reordered to have the following order, which has the lowest estimated computational cost among the multiple orders that satisfy the one or more legality constraints; as well as The source code, which has multiple conditions that have been reordered, is compiled into the assembly code.

2. The computing device of claim 1, wherein the source code further comprises: The first branch code block includes one or more first branch evaluation instructions, which are configured to be executed when the plurality of conditions are true; as well as The second branch code block includes one or more second branch evaluation instructions, which are configured to be executed when at least one of the plurality of conditions is false.

3. The computing device of claim 1, wherein the one or more legality constraints include the following constraint: the source code includes a first branch code block and a second branch code block.

4. The computing device of claim 1, wherein the one or more legality constraints include the constraint that the code block of each condition includes instructions for proceeding to a common target code block.

5. The computing device of claim 4, wherein the one or more legality constraints include the constraint that the source code has an entry point and an exit point in a portion following the last code block of the code block under the plurality of conditions and before the common target code block.

6. The computing device of claim 1, wherein the one or more legality constraints include the constraint that no instruction calls an undefined variable.

7. The computing device of claim 1, wherein each code block is a basic block.

8. The computing device of claim 1, wherein at least one code block comprises a plurality of basic blocks.

9. The computing device of claim 1, wherein the processor is configured to sum the corresponding estimated cost score assigned to each instruction by summing the corresponding estimated cost scores assigned to the instruction type for each instruction included in each order satisfying the one or more legality constraints.

10. The computing device of claim 9, wherein each of the plurality of instruction types is a corresponding type of operation, and wherein each type of operation has an associated estimated integer cost and an estimated floating-point cost, the estimated integer cost being an estimated cost score of the operation of that type when the operation is performed using integer computation, and the estimated floating-point cost being an estimated cost score of the operation of that type when the operation is performed using floating-point computation; and The types of operations include addition, subtraction, comparison, negation, division, remainder, AND, OR, XOR, minimum, maximum, load and / or store.

11. A method executed by a processor of a computing device, the method comprising: During compiler execution: The source code is received at the compiler, wherein the source code includes: At least one composite condition set having multiple conditions, said composite condition set being configured to be evaluated as part of the execution of assembly code compiled from said source code, to determine which of the multiple branch code blocks of said assembly code will be executed. Each of the plurality of conditions includes a code block, the code block including one or more instructions for evaluating the condition; Determine that two or more of the multiple orderings of the multiple conditions of the composite condition set satisfy one or more legality constraints, and at least one of the multiple orderings does not satisfy the one or more legality constraints, wherein each of the one or more legality constraints is an order-related constraint based on one or more syntactic properties of the instructions included in the multiple conditions, the multiple conditions having a specific ordering, the specific ordering to be determined to satisfy the order-related constraints. During the execution of the compiler, determining the corresponding estimated computational cost for each order that satisfies one or more of the legality constraints includes: assigning an estimated cost score to each instruction included in the order and summing the corresponding estimated cost scores assigned to each instruction, wherein the assignment includes reading the estimated cost score associated with the operation indicated by the corresponding instruction from an estimated computational cost table, the estimated computational cost table indicating the corresponding estimated cost score for multiple operations; The multiple conditions are reordered to have the lowest estimated computational cost among the multiple orders that satisfy the one or more validity constraints; and The source code, which has multiple conditions that have been reordered, is compiled into the assembly code.

12. The method of claim 11, wherein the source code further comprises: The first branch code block includes one or more first branch evaluation instructions, which are configured to be executed when the plurality of conditions are true; as well as The second branch code block includes one or more second branch evaluation instructions, which are configured to be executed when at least one of the plurality of conditions is false.

13. The method of claim 12, wherein the one or more legality constraints include the constraint that the source code includes a first branch code block and a second branch code block.

14. The method of claim 11, wherein the one or more legality constraints include the constraint that the code block of each condition includes instructions for proceeding to a common target code block.

15. The method of claim 14, wherein the one or more legality constraints include the constraint that the source code has an entry point and an exit point in a portion following the last code block of the code block under the plurality of conditions and before the common target code block.

16. The method of claim 11, wherein the one or more legality constraints include the constraint that no instruction calls an undefined variable.

17. The method of claim 11, wherein each code block is a basic block.

18. The method of claim 11, wherein at least one code block comprises a plurality of basic blocks.

19. A computing device, comprising a processor, the processor being configured to: During compiler execution: Source code is received at the compiler, wherein the source code includes multiple code blocks, the multiple code blocks include multiple conditions, the multiple conditions are included in a composite condition set and are configured to be evaluated as part of the execution of assembly code compiled from the source code to determine which of the multiple branch code blocks of the assembly code will be executed; Determine that two or more of the multiple orderings of the multiple conditions of the composite condition set satisfy one or more legality constraints, and at least one of the multiple orderings does not satisfy the one or more legality constraints, wherein each of the one or more legality constraints is an order-related constraint based on one or more syntactic attributes of multiple instructions included in the multiple code blocks, the multiple conditions having a specific ordering, the specific ordering to be determined to satisfy the order-related constraints. During the execution of the compiler, a corresponding estimated computational cost is determined only for instructions satisfying the order by assigning an estimated cost score to each instruction included in each order that satisfies the one or more legality constraints and summing the corresponding estimated cost scores assigned to each instruction. The assignment includes reading estimated cost scores associated with the operations indicated by the corresponding instructions from an estimated computational cost table, which indicates corresponding estimated cost scores for multiple operations. The computational cost of at least one corresponding order for each of the plurality of orders satisfying the one or more legality constraints is determined at least in part by: determining an estimated cost score assigned to the type of instruction included in each instruction in the order, wherein the type of operation includes addition, subtraction, comparison, negation, division, remainder, AND, OR, XOR, minimum, maximum, load and / or store. The plurality of code blocks including the conditions are reordered to have the following order, which has the lowest estimated computational cost of the plurality of orders that satisfy the one or more legality constraints; as well as The source code, which has multiple conditions that have been reordered, is compiled into the assembly code.

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