Time synchronization method, device, electronic device, storage medium and program product in a virtualized environment

Abstract

The present disclosure relates to a time synchronization method, apparatus, electronic device, storage medium, and program product in a virtualized environment. The virtualized environment includes a virtualized server and multiple processor cores, and the method includes: for any processor core among the multiple processor cores, the virtualized server sends a local timestamp acquisition request to the processor core and reads the first local timestamp of the virtualized server at that time; in response to receiving the first local timestamp of the processor core returned by the processor core, the virtualized server reads the second local timestamp of the virtualized server; and the virtualized server determines a timestamp calibration parameter of the processor core based on the first local timestamp of the virtualized server, the second local timestamp of the virtualized server, and the first local timestamp of the processor core.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a time synchronization method in a virtualized environment, a time synchronization device in a virtualized environment, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] In modern computing, GPUs (Graphics Processing Units) are high-performance computing chips widely used in fields such as scientific computing, graphics rendering, and machine learning. GPUs contain multiple independently running processor cores, such as the firmware (FW) processor and the GPU core. These processor cores can process large amounts of data in parallel, significantly improving computing efficiency.

[0003] With the continuous development of virtualization technology, GPU virtualization has become a key technology in cloud computing and data centers. In a virtualized environment, GPU resources are abstracted and allocated to multiple virtual machines (VMs) through virtualization technology. Each VM has its own virtual CPU (vCPU), which together with the host CPU form a complex heterogeneous system. This system design allows multiple users to share the same physical hardware resources, improving resource utilization and flexibility.

[0004] However, because each processor core (including the CPU, the firmware processor on the GPU, and the GPU core) runs at a different clock frequency, their time bases are independent of each other. This independence makes time synchronization a challenge when communicating and collaborating across processor cores. For example, in distributed computing tasks, programs running on different processor cores need to be time synchronized to ensure data consistency and accuracy. Furthermore, time-based statistical analysis, logging, and other functions also require precise time synchronization to ensure their effectiveness. Summary of the Invention

[0005] The present disclosure provides a technical solution for time synchronization in a virtualized environment.

[0006] According to one aspect of the present disclosure, a time synchronization method in a virtualized environment is provided, wherein the virtualized environment includes a virtualized server and multiple processor cores, and the method includes:

[0007] For any processor core among the multiple processor cores, the virtualization server sends a local timestamp acquisition request to the processor core, and reads a first local timestamp of the virtualization server at this time;

[0008] In response to receiving the first local timestamp of the processor core returned by the processor core, the virtualization server reads a second local timestamp of the virtualization server;

[0009] The virtualization server determines a calibration parameter of the timestamp of the processor core according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core.

[0010] In a possible implementation, after determining the calibration parameter of the timestamp of the processor core, the method further includes:

[0011] In response to receiving the data to be synchronized from the processor core, the virtualization server calibrates the local timestamp of the processor core carried in the data to be synchronized according to the calibration parameters of the timestamp of the processor core to obtain calibrated data corresponding to the data to be synchronized.

[0012] In a possible implementation, the virtualization server determines, according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core, a calibration parameter of the timestamp of the processor core, including:

[0013] The virtualization server compensates the first local timestamp of the processor core according to the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core;

[0014] The virtualization server determines a calibration parameter of the timestamp of the processor core according to one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server and the second local timestamp of the processor core.

[0015] In a possible implementation, the virtualization server compensates the first local timestamp of the processor core according to the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core, including:

[0016] The virtualization server determines, based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, a total time between sending the local timestamp acquisition request and receiving a response from the processor core;

[0017] determining a one-way communication delay based on the total time;

[0018] A second local timestamp of the processor core is determined based on the first local timestamp of the processor core and the one-way communication delay.

[0019] In one possible implementation, the virtualization server determines, based on one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, and the second local timestamp of the processor core, a calibration parameter of the timestamp of the processor core, including:

[0020] A calibration parameter of the timestamp of the processor core is determined according to a difference between the second local timestamp of the virtualization server and the second local timestamp of the processor core generated by the virtualization server.

[0021] In a possible implementation, the method further includes:

[0022] In response to the local timestamp acquisition request, the processor core reads a local timestamp register to obtain a first local timestamp of the processor core.

[0023] In a possible implementation, the virtualization server re-determines the calibration parameters of the timestamp of the processor core at a preset frequency.

[0024] In one possible implementation, the multiple processor cores include at least some of the following types: a GPU core, a firmware processor in a GPU, and a virtual CPU.

[0025] According to one aspect of the present disclosure, a time synchronization device in a virtualized environment is provided, wherein the virtualized environment includes a virtualized server and multiple processor cores, and the device includes:

[0026] a sending module, configured to, for any processor core among the plurality of processor cores, cause the virtualization server to send a local timestamp acquisition request to the processor core, and read a first local timestamp of the virtualization server at that time;

[0027] a first reading module, configured for the virtualization server to read a second local timestamp of the virtualization server in response to receiving the first local timestamp of the processor core returned by the processor core;

[0028] A determination module is configured to determine, by the virtualization server, a calibration parameter of the timestamp of the processor core according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core.

[0029] In a possible implementation, the apparatus further includes:

[0030] A calibration module is used for the virtualization server to calibrate the local timestamp of the processor core carried in the data to be synchronized in response to receiving the data to be synchronized from the processor core, according to the calibration parameters of the timestamp of the processor core, to obtain the calibrated data corresponding to the data to be synchronized.

[0031] In a possible implementation, the determining module is configured to:

[0032] The virtualization server compensates the first local timestamp of the processor core according to the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core;

[0033] The virtualization server determines a calibration parameter of the timestamp of the processor core according to one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server and the second local timestamp of the processor core.

[0034] In a possible implementation, the determining module is configured to:

[0035] The virtualization server determines, based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, a total time between sending the local timestamp acquisition request and receiving a response from the processor core;

[0036] determining a one-way communication delay based on the total time;

[0037] A second local timestamp of the processor core is determined based on the first local timestamp of the processor core and the one-way communication delay.

[0038] In a possible implementation, the determining module is configured to:

[0039] A calibration parameter of the timestamp of the processor core is determined according to a difference between the second local timestamp of the virtualization server and the second local timestamp of the processor core generated by the virtualization server.

[0040] In a possible implementation, the apparatus further includes:

[0041] The second reading module is configured to read the local timestamp register of the processor core in response to the local timestamp acquisition request to obtain a first local timestamp of the processor core.

[0042] In a possible implementation, the virtualization server re-determines the calibration parameters of the timestamp of the processor core at a preset frequency.

[0043] In one possible implementation, the multiple processor cores include at least some of the following types: a GPU core, a firmware processor in a GPU, and a virtual CPU.

[0044] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0045] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0046] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0047] In an embodiment of the present disclosure, the virtualization environment includes a virtualization server and multiple processor cores. For any processor core among the multiple processor cores, the virtualization server sends a local timestamp acquisition request to the processor core and reads the first local timestamp of the virtualization server at this time. In response to receiving the first local timestamp of the processor core returned by the processor core, the virtualization server reads the second local timestamp of the virtualization server. The virtualization server determines the calibration parameters of the timestamp of the processor core based on the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core. Thus, in the virtualization environment, time synchronization is performed based on the local timestamps of each processor core, so that time synchronization between different processor cores can be achieved while maintaining high performance. The embodiment of the present disclosure can support synchronization between multiple systems with different clock frequencies, can adapt to complex heterogeneous system environments, and has little impact on existing systems.

[0048] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0049] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0051] Figure 1 A flowchart of a time synchronization method in a virtualized environment provided by an embodiment of the present disclosure is shown.

[0052] Figure 2 A schematic diagram illustrating a time synchronization method in a virtualized environment provided by an embodiment of the present disclosure is shown.

[0053] Figure 3 A block diagram of a time synchronization device in a virtualized environment provided by an embodiment of the present disclosure is shown.

[0054] Figure 4 A block diagram of an electronic device 1900 provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0055] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0056] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0057] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0058] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0059] In the prior art, in pursuit of performance and efficiency, each processor core's local clock source is typically used to obtain time. While this approach is simple, it lacks an efficient mechanism for synchronizing time between different processor cores. This leads to issues with cross-processor core time statistics, logging, and other operations, making comparison and calibration impossible. These issues not only impact system performance but can also cause data inconsistencies and errors, impacting the stability and reliability of the entire system.

[0060] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a time synchronization in a virtualized environment, wherein the virtualized environment includes a virtualized server and multiple processor cores, wherein the virtualized server sends a local timestamp acquisition request to any processor core among the multiple processor cores, and reads the first local timestamp of the virtualized server at this time, and the virtualized server responds to receiving the first local timestamp of the processor core returned by the processor core, reads the second local timestamp of the virtualized server, and the virtualized server determines the calibration parameters of the timestamp of the processor core based on the first local timestamp of the virtualized server, the second local timestamp of the virtualized server, and the first local timestamp of the processor core, thereby performing time synchronization based on the local timestamps of each processor core in the virtualized environment, thereby achieving time synchronization between different processor cores while maintaining high performance. The embodiment of the present disclosure can support synchronization between multiple systems with different clock frequencies, can adapt to complex heterogeneous system environments, and has little impact on existing systems.

[0061] The time synchronization method in a virtualized environment provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0062] Figure 1A flowchart of a time synchronization method in a virtualized environment provided by an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the time synchronization method in the virtualized environment may be a time synchronization device in the virtualized environment. For example, the time synchronization method in the virtualized environment may be executed by a terminal device or a server or other electronic device. Among them, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the time synchronization method in the virtualized environment may be implemented by a processor calling computer-readable instructions stored in a memory. In an embodiment of the present disclosure, the virtualized environment includes a virtualized server and multiple processor cores. As Figure 1 As shown, the time synchronization method in a virtualized environment includes steps S11 to S13.

[0063] In step S11 , for any processor core among the multiple processor cores, the virtualization server sends a local timestamp acquisition request to the processor core, and reads a first local timestamp of the virtualization server at that time.

[0064] In step S12 , in response to receiving the first local timestamp of the processor core returned by the processor core, the virtualization server reads a second local timestamp of the virtualization server.

[0065] In step S13 , the virtualization server determines a calibration parameter of the timestamp of the processor core according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core.

[0066] In an embodiment of the present disclosure, a virtualization environment may include a virtualization server and multiple processor cores.

[0067] A virtualization server, also known as a virtual machine monitor (VMM), hypervisor, or hypervisor, is a software layer that creates an abstraction between physical hardware and virtual machines. It manages physical resources such as the CPU (Central Processing Unit), GPU (Graphics Processing Unit), memory, storage, and network interfaces, allocating them to virtual machines. It also handles the creation, scheduling, and management of virtual machines.

[0068] A processor core may be any unit responsible for performing computing tasks or executing program instructions. In the embodiment of the present disclosure, the processor core for time synchronization via the virtualized server may include a physical processor core or a virtual processor core.

[0069] Among them, a physical processor core can refer to a processor core that actually exists in physical hardware. A physical processor core can be part of a CPU or other processor (such as a GPU) and has independent computing capabilities. A physical processor core can directly execute instructions of a computer program, process data, and perform various computing tasks. In the absence of virtualization technology, an operating system can run directly on a physical processor core and directly access and control hardware resources. For example, a physical processor core can include a physical CPU core, a physical GPU core, a firmware (FW) processor in a GPU, and so on.

[0070] A virtual processor core (VPC) represents a logical processor core abstracted from a physical processor core through virtualization technology. It is a concept in a virtualized environment. For example, a VPC can include a virtual CPU, a virtual GPU, and so on. Each VPC core (e.g., a VPC) can be designed to have similar characteristics to a physical processor core, allowing a virtual machine (VM) to believe it is running directly on the physical hardware. VPCs are part of a virtualization platform that allows multiple VMs to share the same physical hardware resources, with each VM having one or more VPC cores to perform tasks.

[0071] In one possible implementation, the multiple processor cores include at least some of the following types: a GPU core, a firmware processor in a GPU, and a virtual CPU.

[0072] A GPU core refers to the core of a GPU, which can be used for graphics rendering and parallel computing tasks. A firmware processor can be a microprocessor embedded in a hardware device, which can be used to execute firmware programs and control low-level operations of the device. A virtual CPU (vCPU) is a virtualization technology that emulates the functionality of a physical CPU in a virtualized environment. A virtual CPU allows a virtual machine (VM) to execute instructions and process tasks as if it were a real physical CPU. Each VM can be assigned one or more virtual CPUs, which share the CPU resources of the physical server.

[0073] As an example of this implementation, time synchronization can be performed on GPU cores in a virtualized environment. In a virtualized environment, multiple virtual machines may share the same physical GPU resources. Time synchronization between GPU cores ensures that they can properly collaborate and synchronize data when performing parallel computing tasks. Furthermore, time synchronization helps optimize the allocation and scheduling of GPU resources, improving computing performance and responsiveness. Furthermore, by time synchronizing GPU cores in a virtualized environment, it is possible to ensure that applications running in different virtual machines maintain consistency when accessing shared data.

[0074] As an example of this implementation, time synchronization can be performed on the firmware processor of a GPU in a virtualized environment. The firmware processor is typically responsible for managing the GPU's low-level operations and hardware status. Time synchronization ensures that the firmware processor can accurately track and manage hardware events. Furthermore, synchronized timestamps can help monitor and record the GPU's operating status, facilitating performance analysis and troubleshooting. Furthermore, the firmware processor needs to schedule and manage the execution of tasks by the GPU core, and time synchronization facilitates accurate task scheduling and instruction execution.

[0075] As an example of this implementation, time synchronization can be performed on virtual CPUs in a virtualized environment. Each virtual machine in a virtualized environment may have its own virtual CPU. Time synchronization enables the virtual CPU to effectively manage and execute multiple tasks, improving the operating efficiency of the virtual machine. The virtual CPU needs to coordinate with other computing resources such as the physical CPU and GPU, and time synchronization is key to achieving this coordination. Furthermore, the virtualization platform can allocate resources based on virtual CPU time information, ensuring fairness and efficiency across different virtual machines.

[0076] Time synchronization is crucial to the stability, performance, and reliability of the entire virtualized environment. It ensures that operations between different computing resources proceed in an orderly manner, supporting the efficient operation of complex computing tasks and multi-user environments. Time synchronization can reduce data errors and system problems caused by time inconsistencies, thereby improving overall system efficiency and user satisfaction.

[0077] In one possible implementation, the virtualization server and the processor core may communicate via a PCI (Peripheral Component Interconnect) bus. For example, the virtualization server and the processor core may communicate via a PCIe (Peripheral Component Interconnect Express) bus.

[0078] In the embodiment of the present disclosure, each processor core is centered on the virtualization server and synchronizes time with the virtualization server. The virtualization server provides a unified time base, ensuring that all connected processor cores, including physical processor cores and virtual processor cores, can be synchronized to a common time source, thereby maintaining time consistency. The centralized time synchronization mechanism centered on the virtualization server simplifies the time management task, because all time calibration and synchronization activities are performed through the virtualization server and do not need to be performed separately on each processor core. In addition, centralized synchronization reduces the need for time negotiation between individual processor cores, thereby reducing communication overhead and processing delays, and improving the performance of the overall system. In a complex heterogeneous system containing multiple types of processor cores, the time synchronization mechanism centered on the virtualization server can adapt to the characteristics and requirements of different cores to achieve effective time synchronization.

[0079] In a possible implementation, the virtualization server re-determines the calibration parameters of the timestamp of the processor core at a preset frequency.

[0080] The preset frequency may represent the time interval for the virtualization server to recalculate and update the calibration parameters. The preset frequency may be fixed or dynamically adjusted.

[0081] In this implementation, time synchronization can be performed periodically between processor cores. Since changes in the system operating environment (such as temperature changes, power supply fluctuations, etc.) may affect clock accuracy, calibration parameters need to be periodically recalculated to maintain time synchronization accuracy.

[0082] By regularly synchronizing with the central time source provided by the virtualization server, we can reduce the accumulation of errors caused by local clock frequency differences or time drift among processor cores, thereby improving the accuracy of time synchronization. This implementation ensures that processor cores across the entire virtualized environment maintain consistent and accurate time, even during long-term operations and under various system changes. This is crucial for maintaining system stability and reliability, as well as for data synchronization and collaboration across processor cores.

[0083] In an embodiment of the present disclosure, when time calibration is performed on any processor core among a plurality of processor cores, the virtualization server sends a local timestamp acquisition request to the processor core and reads the first local timestamp of the virtualization server at this time. That is, the virtualization server can read the local timestamp while sending the local timestamp acquisition request to the processor core to obtain the first local timestamp of the virtualization server. The first local timestamp of the virtualization server can represent the local timestamp read by the virtualization server when the virtualization server sends the local timestamp acquisition request to the processor core. The first local timestamp of the virtualization server can be used to represent the moment when the local timestamp acquisition request is sent out. In one example, the first local timestamp of the virtualization server can be represented by tsc1.

[0084] A timestamp is a record of a specific point in time, usually an incremental count starting from a specific starting point. In computer systems, timestamps are used to mark the time when an event occurred and are very important for logging, performance monitoring, synchronization operations, and more.

[0085] In an embodiment of the present disclosure, a processor core may read the first local timestamp of the processor core in response to a local timestamp acquisition request from a virtualization server. The first local timestamp of the processor core may represent the local timestamp read by the processor core in response to the local timestamp acquisition request from the virtualization server. That is, the first local timestamp of the processor core may refer to the timestamp recorded by the processor core when the processor core receives the local timestamp acquisition request from the virtualization server. The first local timestamp of the processor core may represent the local time of the processor core when the request is received. In one example, when the processor core is a firmware processor, the first local timestamp of the processor core may be represented by fwtsc1.

[0086] In a possible implementation, the method further includes: the processor core reading a local timestamp register in response to the local timestamp acquisition request to obtain a first local timestamp of the processor core.

[0087] In this implementation, the local timestamp register can provide a high-resolution time counter that increments as the processor core executes instructions, thereby recording the passage of time. In one example, the local timestamp register can be a 64-bit or higher-bit-width counter that operates at a fixed frequency. The local timestamp register can increment at a fixed frequency and can restart from zero after the corresponding processor core is reset.

[0088] When the time of an event needs to be recorded, the processor core can read the current value of the local timestamp register, which serves as the timestamp of the event. Because the local timestamp register is tightly integrated with the processor core, it can provide very precise time measurement, for example, with sub-microsecond resolution.

[0089] Each processor core can have its own local timestamp register, allowing it to independently track time without being affected by other processor cores. For example, in x86 processors, the TSC (Time Stamp Counter) is a widely used local timestamp register for CPUs. In GPUs, similar functionality may be implemented by dedicated timer registers, such as "gputimer" in NVIDIA GPUs. Local timestamp registers are typically designed to be less affected by external factors (such as temperature changes), thereby maintaining time stability.

[0090] In this implementation, the processor core uses its own local timestamp register to obtain the timestamp, that is, the timestamp acquisition operation is completed locally and does not require data exchange through the PCI bus, so the impact on the PCI bandwidth is very small.

[0091] In an embodiment of the present disclosure, the virtualization server may read the second local timestamp of the virtualization server in response to receiving the first local timestamp of the processor core returned by the processor core. The second local timestamp of the virtualization server may represent the local timestamp read by the virtualization server in response to receiving the first local timestamp of the processor core returned by the processor core. That is, the second local timestamp of the virtualization server may refer to the timestamp recorded again by the virtualization server after receiving the timestamp response returned by the processor core. The second timestamp of the virtualization server may represent the moment when the response is received. In one example, the second local timestamp of the virtualization server may be represented by tsc2.

[0092] In an embodiment of the present disclosure, the virtualization server may determine a timestamp calibration parameter for the processor core based on the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core. In an embodiment of the present disclosure, the timestamp calibration parameter for any processor core may refer to a parameter required to adjust and correct the local timestamp of the processor core to align it with a unified or standard time base in the virtualization environment.

[0093] In one possible implementation, the virtualization server determines the calibration parameters of the timestamp of the processor core based on the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core, including: the virtualization server compensates the first local timestamp of the processor core based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core; the virtualization server determines the calibration parameters of the timestamp of the processor core based on one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, and the second local timestamp of the processor core.

[0094] Due to communication delay, namely the time between when the virtualization server sends a request to the processor core and when the processor core returns a response, the virtualization server needs to compensate the processor core's first local timestamp to obtain a more accurate time representation. In this implementation, the virtualization server can compensate the processor core's first local timestamp based on the virtualization server's first local timestamp and the virtualization server's second local timestamp to obtain the processor core's second local timestamp. The processor core's second local timestamp can represent the result of the compensation operation. The processor core's second local timestamp is adjusted to compensate for the communication delay between when the virtualization server sends the request and when the processor core receives the response.

[0095] After obtaining the second local timestamp of the processor core, the virtualization server may determine a timestamp calibration parameter of the processor core according to the first local timestamp of the virtualization server and / or the second local timestamp of the virtualization server and the second local timestamp of the processor core.

[0096] In one possible implementation, the virtualization server compensates the first local timestamp of the processor core based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core, including: the virtualization server determines the total time between sending the local timestamp acquisition request and receiving the response of the processor core based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server; determines the one-way communication delay based on the total time; and determines the second local timestamp of the processor core based on the first local timestamp of the processor core and the one-way communication delay.

[0097] For example, the difference between the second local timestamp tsc2 of the virtualized server and the first local timestamp tsc1 of the virtualized server can be calculated to obtain the total time between sending the local timestamp acquisition request and receiving the response of the processor core, that is, Δtsc=tsc2-tsc1.

[0098] Based on the total time Δtsc, the one-way communication delay can be calculated. For example, Δtsc can be divided by 2 (assuming that the round-trip communication delay is roughly the same) to get the one-way communication delay Δtsc single =Δtsc / 2. For another example, the total time Δtsc and historical data can be combined to determine one-way communication delay. For example, historical data can be analyzed to identify patterns and trends in communication delay, such as by calculating the total time average, median, or percentile in the historical data. Based on historical data, a predictive model can be built to estimate one-way communication delay. For example, a simple arithmetic mean model or a more complex machine learning model such as linear regression, decision tree, or neural network can be used.

[0099] The first local timestamp fwtsc1 of the processor core and the one-way communication delay Δtsc can be used to determine the communication delay. single , determine the second local timestamp fwtsc2 of the processor core. For example, fwtsc2 = fwtsc1 - Δtsc single .

[0100] In this way, the second local timestamp fwtsc2 of the processor core represents the local timestamp of the processor core after compensating for the communication delay.

[0101] In this implementation, the virtualization server determines the total time between sending the local timestamp acquisition request and receiving the response of the processor core based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, determines the one-way communication delay based on the total time, and determines the second local timestamp of the processor core based on the first local timestamp of the processor core and the one-way communication delay, thereby effectively compensating the root timestamp of the processor core, thereby achieving more accurate time synchronization in a virtualized environment.

[0102] In one possible implementation, the virtualization server determines the calibration parameters of the timestamp of the processor core based on one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, and the second local timestamp of the processor core, including: determining the calibration parameters of the timestamp of the processor core based on the difference between the second local timestamp of the virtualization server and the second local timestamp of the processor core calculated by the virtualization server.

[0103] In this implementation, the virtualization server may determine the timestamp calibration parameter fwpara of the processor core based on the second local timestamp tsc2 of the virtualization server and the second local timestamp ftsc2 of the processor core, for example, fwpara=tsc2-fwtsc2.

[0104] In another possible implementation, the virtualization server may calculate the calibration parameter based on the second local timestamp tsc2 of the virtualization server, the second local timestamp fwtsc2 of the processor core, and the historical value fwpara of the calibration parameter of the timestamp of the processor core. history , determines the latest value of the processor core's timestamp calibration parameter fwpara new For example, fwpara new =k(tsc2-fwtsc2)+(1-k)fwpara history Where k is an adjustment coefficient between 0 and 1, which is used to balance the influence of the current time difference and the historical calibration parameters.

[0105] In another possible implementation, the virtualization server may determine the timestamp calibration parameter fwpara of the processor core based on the first local timestamp tsc1 of the virtualization server and the second local timestamp fwtsc2 of the processor core, for example, fwpara=fwtsc2-tsc1.

[0106] In another possible implementation, the virtualization server may virtualize the first local timestamp tsc1 of the server, the second local timestamp fwtsc2 of the processor core, and the historical value fwpara of the calibration parameter of the timestamp of the processor core. history , determines the latest value of the processor core's timestamp calibration parameter fwpara new For example, fwpara new =k(fwtsc2-tsc1)+(1-k)fwpara history .

[0107] In the disclosed embodiment, the virtualization server may record the calibration parameters of each processor and update the timestamps in events according to these calibration parameters to ensure the time consistency of the entire system.

[0108] In one possible implementation, after determining the calibration parameters of the timestamp of the processor core, the method further includes: the virtualization server, in response to receiving the data to be synchronized from the processor core, calibrates the local timestamp of the processor core carried in the data to be synchronized according to the calibration parameters of the timestamp of the processor core, to obtain calibrated data corresponding to the data to be synchronized.

[0109] In this implementation, when a processor core needs to obtain the current time timestamp, it can directly read the local timestamp instead of obtaining it from other processor cores or external sources. This approach reduces dependence on external time sources and reduces communication overhead.

[0110] In this implementation, each processor core uses its local timestamp to record the timestamp of the event when it executes a task or an event occurs. This means that each processor core independently marks the moment when the event occurs.

[0111] In this implementation, the data to be synchronized can represent data generated by the processor core when executing a task in a virtualized environment. The data to be synchronized can represent data that has not yet completed time calibration and synchronization processing. The data to be synchronized is sent to the virtualization server for further time calibration and synchronization processing. The virtualization server adjusts the local timestamp carried in the data to be synchronized based on the calibration parameters of the processor core's timestamp to compensate for time differences caused by factors such as clock frequency and communication delays. The calibrated timestamp will be aligned with the unified time base of the virtualization server, converting the original data to be synchronized into calibrated data. After calibration, the data to be synchronized can be used for synchronization between different components in the system to ensure that all related events and operations are recorded and processed in the correct time sequence.

[0112] The time synchronization method in a virtualized environment provided by the embodiments of the present disclosure can be applied to technical fields such as GPU, vGPU, virtualization, and heterogeneous systems, and is not limited here.

[0113] The following describes a specific application scenario to illustrate the time synchronization method in a virtualized environment provided by an embodiment of the present disclosure. Figure 2A schematic diagram of a time synchronization method in a virtualized environment provided by an embodiment of the present disclosure is shown. In this application scenario, the virtualized environment includes a virtualized server and multiple processor cores, wherein the multiple processor cores include firmware servers FW0, FW1, ..., FWn on a GPU. The virtualized server reads a local timestamp from the CPU TSC. Firmware server FW0 reads a local timestamp from GPU timer 0, firmware server FW1 reads a local timestamp from GPU timer 1, ..., and firmware server FWn reads a local timestamp from GPU timer n. The firmware server and the virtualized server communicate via PCIe.

[0114] For example, when performing time calibration on any firmware server, the virtualization server driver reads the first local timestamp tsc1 of the virtualization server and sends a local timestamp acquisition request to the firmware server. In response to the local timestamp acquisition request, the firmware server reads the local timestamp register, obtains the first local timestamp fwtsc1 of the firmware server, and returns the first local timestamp fwtsc1 of the firmware server to the virtualization server. In response to receiving the first local timestamp fwtsc1 of the firmware processor returned by the firmware processor, the virtualization server driver reads the second local timestamp tsc2 of the virtualization server. Based on the first local timestamp tsc1 and the second local timestamp tsc2 of the virtualization server, the virtualization server driver compensates the first local timestamp fwtsc1 of the firmware processor to obtain the second local timestamp fwtsc2 of the firmware processor. Based on the first local timestamp tsc1 and / or the second local timestamp tsc2 of the virtualization server, and the second local timestamp fwtsc2 of the firmware processor, the virtualization server driver calculates a timestamp calibration parameter fwpara for the firmware processor.

[0115] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0116] In addition, the present disclosure also provides a time synchronization device, an electronic device, a computer-readable storage medium, and a computer program product in a virtualized environment. The above can all be used to implement the time synchronization method in any virtualized environment provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0117] Figure 3 FIG2 is a block diagram of a time synchronization device in a virtualized environment provided by an embodiment of the present disclosure. The virtualized environment includes a virtualized server and multiple processor cores, such as Figure 3 As shown, the time synchronization device in the virtualized environment includes:

[0118] The sending module 31 is configured to send, by the virtualization server, a local timestamp acquisition request to any processor core among the plurality of processor cores, and read a first local timestamp of the virtualization server at that time;

[0119] A first reading module 32 is configured for the virtualization server to read a second local timestamp of the virtualization server in response to receiving the first local timestamp of the processor core returned by the processor core;

[0120] The determination module 33 is configured to determine, by the virtualization server, a calibration parameter of the timestamp of the processor core according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core.

[0121] In a possible implementation, the apparatus further includes:

[0122] A calibration module is used for the virtualization server to calibrate the local timestamp of the processor core carried in the data to be synchronized in response to receiving the data to be synchronized from the processor core, according to the calibration parameters of the timestamp of the processor core, to obtain the calibrated data corresponding to the data to be synchronized.

[0123] In a possible implementation, the determining module 33 is configured to:

[0124] The virtualization server compensates the first local timestamp of the processor core according to the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core;

[0125] The virtualization server determines a calibration parameter of the timestamp of the processor core according to one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server and the second local timestamp of the processor core.

[0126] In a possible implementation, the determining module 33 is configured to:

[0127] The virtualization server determines, based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, a total time between sending the local timestamp acquisition request and receiving a response from the processor core;

[0128] determining a one-way communication delay based on the total time;

[0129] A second local timestamp of the processor core is determined based on the first local timestamp of the processor core and the one-way communication delay.

[0130] In a possible implementation, the determining module 33 is configured to:

[0131] A calibration parameter of the timestamp of the processor core is determined according to a difference between the second local timestamp of the virtualization server and the second local timestamp of the processor core generated by the virtualization server.

[0132] In a possible implementation, the apparatus further includes:

[0133] The second reading module is configured to read the local timestamp register of the processor core in response to the local timestamp acquisition request to obtain a first local timestamp of the processor core.

[0134] In a possible implementation, the virtualization server re-determines the calibration parameters of the timestamp of the processor core at a preset frequency.

[0135] In one possible implementation, the multiple processor cores include at least some of the following types: a GPU core, a firmware processor in a GPU, and a virtual CPU.

[0136] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0137] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above method. The computer-readable storage medium may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium.

[0138] The embodiment of the present disclosure further provides a computer program, comprising a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0139] An embodiment of the present disclosure further provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0140] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0141] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0142] Figure 4 FIG. 1 is a block diagram of an electronic device 1900 provided by an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a terminal or a server. Figure 4 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0143] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (MacOS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0144] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0145] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0146] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0147] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0148] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0149] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0150] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0151] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0152] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0153] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0154] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0155] If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained the individual's separate consent before processing the sensitive personal information, and at the same time meet the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0156] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A time synchronization method in a virtualized environment, characterized in that: The virtualized environment includes a virtualized server and multiple processor cores, and the method includes: For any processor core among the multiple processor cores, the virtualization server sends a local timestamp acquisition request to the processor core, and reads a first local timestamp of the virtualization server at this time; In response to receiving the first local timestamp of the processor core returned by the processor core, the virtualization server reads a second local timestamp of the virtualization server; The virtualization server determines, based on the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core, a calibration parameter for the timestamp of the processor core, wherein the parameter used to determine the calibration parameter includes the second local timestamp of the processor core, and the method for determining the second local timestamp of the processor core includes: The virtualization server determines, based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, a total time between sending the local timestamp acquisition request and receiving a response from the processor core; determining a one-way communication delay based on the total time; A second local timestamp of the processor core is determined based on the first local timestamp of the processor core and the one-way communication delay.

2. The method according to claim 1, characterized in that After determining the calibration parameters of the timestamp of the processor core, the method further includes: In response to receiving the data to be synchronized from the processor core, the virtualization server calibrates the local timestamp of the processor core carried in the data to be synchronized according to the calibration parameters of the timestamp of the processor core to obtain calibrated data corresponding to the data to be synchronized.

3. The method according to claim 1, characterized in that The virtualization server determines, according to the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core, a calibration parameter of the timestamp of the processor core, including: The virtualization server compensates the first local timestamp of the processor core according to the first local timestamp of the virtualization server and the second local timestamp of the virtualization server to obtain the second local timestamp of the processor core; The virtualization server determines a calibration parameter of the timestamp of the processor core according to one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server and the second local timestamp of the processor core.

4. The method according to claim 3, characterized in that The virtualization server determines, according to one or both of the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, and the second local timestamp of the processor core, a calibration parameter of the timestamp of the processor core, including: A calibration parameter of the timestamp of the processor core is determined according to a difference between the second local timestamp of the virtualization server and the second local timestamp of the processor core generated by the virtualization server.

5. The method according to claim 1, wherein The method further comprises: In response to the local timestamp acquisition request, the processor core reads a local timestamp register to obtain a first local timestamp of the processor core.

6. The method according to claim 1, characterized in that The virtualization server re-determines the calibration parameters of the timestamp of the processor core at a preset frequency.

7. The method according to claim 1, characterized in that The plurality of processor cores include at least some of the following types: a GPU core, a firmware processor in a GPU, and a virtual CPU.

8. A time synchronization device in a virtualized environment, characterized in that: The virtualization environment includes a virtualization server and multiple processor cores, and the device includes: a sending module, configured to, for any processor core among the plurality of processor cores, cause the virtualization server to send a local timestamp acquisition request to the processor core, and read a first local timestamp of the virtualization server at that time; a first reading module, configured for the virtualization server to read a second local timestamp of the virtualization server in response to receiving the first local timestamp of the processor core returned by the processor core; a determination module, configured to, by the virtualization server, determine a calibration parameter for the timestamp of the processor core based on the first local timestamp of the virtualization server, the second local timestamp of the virtualization server, and the first local timestamp of the processor core, wherein the parameter used to determine the calibration parameter includes the second local timestamp of the processor core, and the method for determining the second local timestamp of the processor core includes: The virtualization server determines, based on the first local timestamp of the virtualization server and the second local timestamp of the virtualization server, a total time between sending the local timestamp acquisition request and receiving a response from the processor core; determining a one-way communication delay based on the total time; A second local timestamp of the processor core is determined based on the first local timestamp of the processor core and the one-way communication delay.

9. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, characterized in that: When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the method according to any one of claims 1 to 7.

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