Critical data processing systems, methods, apparatus, media, and program product

Abstract

This invention relates to the field of data storage technology, and discloses a critical data processing system, method, device, medium, and program product. The critical data processing system includes: a power-down monitoring module, a power-down processing module, a critical data extraction module, a hardware acceleration module, volatile memory, and a storage disk. Based on different monitoring results from the power-down monitoring module and the state of the critical data recording switch, the critical data extraction module and the power-down data processing module package the corresponding data to be recorded or protected and move it to a specific address in the volatile memory. Then, the hardware acceleration module reads the recorded or protected data from the corresponding address in the volatile memory. This critical data processing system has a high transmission rate and sufficient storage space, enabling it to perform both power-down critical data protection and critical data recording functions. During operation, it can automatically switch from critical data recording to power-down critical data protection mode according to the usage scenario.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, specifically to a key data processing system, method, device, medium, and program product. Background Technology

[0002] Recording critical data during system operation offers significant benefits for maintaining system stability, optimizing performance, troubleshooting, and future decision-making. However, existing solutions may impact system performance during data recording, such as insufficient data bandwidth and storage space. Furthermore, backup power supplies have limited lifespan during power outages. For systems requiring large amounts of data protection, the standard data transfer rates in existing power-down protection schemes are insufficient, potentially leading to data loss as external receiving tools cannot promptly write the recorded data to the hard drive after receiving it from the capture chip. This ultimately affects system analysis.

[0003] Therefore, there is an urgent need for a critical data recording and protection system with high transmission rate and sufficient storage space, capable of realizing both critical data protection and critical data recording functions during power failure. Summary of the Invention

[0004] In view of this, this application provides a critical data processing system, method, device, medium and program product that can realize two functions: power failure critical data protection and critical data recording. During operation, it can automatically switch from critical data recording to power failure critical data protection working state according to the usage scenario. The technical solution is as follows.

[0005] In a first aspect, the present invention provides a critical data processing system, which includes: a power failure monitoring module, a power failure processing module, a critical data extraction module, a hardware acceleration module, a volatile memory, and a storage disk.

[0006] The power failure monitoring module is used to monitor the power supply voltage and the status of the data recording switch. When the power supply voltage is less than the preset voltage, a data protection command is generated; when the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, a data recording command is generated.

[0007] The key data extraction module is used to acquire the data to be recorded when a data recording instruction is received; to package the data to be recorded into a recording data packet and store it in the first target storage block of the volatile memory; and to generate a first command and send it to the hardware acceleration module.

[0008] The power-down processing module is used to acquire the data to be protected when a data protection instruction is received; the data to be protected contains an end tag, which is used to indicate whether the data to be protected is complete; the data to be protected is packaged into a protection data packet and stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module.

[0009] The hardware acceleration module is configured to read the record data packet from the first target storage block of the volatile memory via the storage disk when the first command is received; and to read the protection data packet from the second target storage block of the volatile memory via the storage disk when the second command is received.

[0010] The key data processing system provided by this invention has the following advantages:

[0011] The critical data processing system of this invention includes two functions: critical data recording and critical data protection during power failure. A power failure monitoring module monitors the power supply voltage and the data recording switch status in real time, determining whether to activate the critical data recording function or the power failure data protection function based on the monitoring results and the data recording switch status. When the power supply voltage is greater than or equal to a preset threshold voltage, it indicates that the system is operating normally. If the data recording switch is on at this time, the critical data extraction module records the critical data. The critical data extraction module obtains critical data from the upstream sub-unit module, packages it into a data recording packet, stores the data recording packet in the first storage block of the volatile memory, and sends a first command to the hardware acceleration module to read the data recording packet from the first storage block of the volatile memory and move the data recording packet to the storage disk, completing the recording of the critical data. When the power supply voltage is less than the preset threshold voltage, it indicates that the system has lost power, requiring the critical data recording process to be stopped and the critical data protection process to be activated, with the power failure handling module protecting the critical data. The power-down processing module retrieves the data to be protected, tagged with an end label, from the upstream sub-unit module and packages it into a data protection packet. The end label indicates whether the data is continuous and complete; only continuous and complete critical data is protected. The data protection packet is stored in the second storage block of the volatile memory, and a second command is sent to the hardware acceleration module to read the data recording packet from the second storage block and move it to the storage disk, thus completing the protection of the critical data. This critical data processing system features high transmission rate and ample storage space. During normal operation, it records critical data to the storage disk and quickly moves it to the storage disk during power failure. It can achieve both power-down critical data protection and critical data recording functions, and can automatically switch from critical data recording to power-down critical data protection based on power supply voltage monitoring during operation.

[0012] In an optional implementation, the hardware acceleration module is further configured to: upon receiving the first command, determine whether the first target storage block of the volatile memory has been released; if the first target storage block of the volatile memory has not been released, send a masking command to the key data extraction module, causing the key data extraction module to stop storing the record data packet in the first target storage block of the volatile memory.

[0013] In the data recording function of the key data processing system of the present invention, when key data is recorded, the key data extraction module sends the storage block ID for data recording to the hardware acceleration module. The hardware acceleration module determines whether the storage block for key data recording is available based on the received storage block ID information. If it is not available, it will stop writing key data into the volatile memory.

[0014] In one optional implementation, the power failure monitoring module is further configured to: switch to a backup power supply when the power supply voltage is lower than a preset voltage.

[0015] In one optional implementation, the critical data processing system further includes: an arbitration module, used to arbitrate a data recording instruction when a data recording instruction is received, and generate a first arbitration result; the first arbitration result is used to instruct the critical data extraction module to obtain the data to be recorded from the corresponding upstream sub-unit module to generate a recording data packet.

[0016] In one alternative implementation, the arbitration module is further configured to:

[0017] When a data protection instruction is received, the data protection request in the data protection instruction is arbitrated, and a second arbitration result is generated based on the end tag. The second arbitration result is used to instruct the power failure processing module to obtain continuous data to be protected from the corresponding upstream sub-unit module to generate a protection data packet.

[0018] The key data processing system of the present invention also includes an arbitration module, which is used to generate a corresponding arbitration result according to a data recording instruction or a data protection instruction, so that the key data extraction module or the power failure processing module can obtain the corresponding data from the upstream sub-unit module according to the arbitration result to generate the corresponding data packet.

[0019] Secondly, the present invention provides a key data processing method, applied to the aforementioned key data processing system, the method comprising:

[0020] The system acquires the power supply voltage and the data recording switch status; when the power supply voltage is not less than a preset voltage and the data recording switch is in the on state, it acquires the recording data packet; it stores the recording data packet in the first target storage block of the volatile memory; and it reads the recording data packet from the first target storage block of the volatile memory via a storage disk.

[0021] In one optional implementation, the key data processing method further includes:

[0022] When the power supply voltage is lower than the preset power supply, acquire the protection data packet; store the protection data packet in the second target storage block of the volatile memory; and read the protection data packet from the second target storage block of the volatile memory via the storage disk.

[0023] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the key data processing method described in the first aspect or any corresponding embodiment thereof.

[0024] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the key data processing method described in the first aspect or any corresponding embodiment thereof.

[0025] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the key data processing method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of the key data processing system provided in the embodiments of the present invention.

[0028] Figure 2 This is a flowchart illustrating the key data recording method provided in an embodiment of the present invention.

[0029] Figure 3 This is a flowchart illustrating the key data protection method provided in the embodiments of the present invention.

[0030] Figure 4This is a schematic diagram of the NVMe command processing flow provided in an embodiment of the present invention.

[0031] Figure 5 This is a logical block diagram illustrating a key data recording process according to an exemplary embodiment.

[0032] Figure 6 This is a logical block diagram illustrating a critical data protection process according to an exemplary embodiment.

[0033] Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] It should be understood that the term "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.

[0036] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0037] In the embodiments of this application, "predefined" can be achieved by pre-storing corresponding codes, tables or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method.

[0038] First, let me introduce the terminology used in this application.

[0039] NVMe: Non-volatile memory express, a host controller interface specification for non-volatile memory; SQ: Submission Queue; CQ: Completion Queue; DDR: Double Data Rate, synchronous dynamic random access memory; AXI: Advanced Extensible Interface, an on-chip bus proposed by ARM for high performance, high bandwidth, and low latency; EEPROM: Electrically Erasable Programmable read-only memory; RAM: Random Access Memory. sq_cmd: command word; cq_reply: response word; record_pkt: record data packet; protect_data: protect data; sq_entry: entry; cq_entry: entry; sq_doorbell: doorbell; cq_doorbell: doorbell.

[0040] Recording critical data during system operation offers significant benefits for maintaining system stability, optimizing performance, troubleshooting, and future decision-making. However, data recording can negatively impact system performance. In applications requiring high performance, a balance must be struck between data recording and system performance. Therefore, an efficient data recording method is needed to meet the demands of recording large volumes of data. Examples of existing data recording methods include: using on-chip memory such as SRAM to record on-chip data; sending data to be recorded to a remote server or storage device via a network interface; and using Coresight technology for data recording.

[0041] These existing critical data logging methods, if the amount of data to be logged is too large, can lead to the phenomenon of new data overwriting old data after the RAM is full, resulting in the loss of a large amount of logged data. Sending logged data to a remote end via a network interface is only available to systems that support network interfaces. The Coresight architecture's data bandwidth is limited by the sampling frequency of the external receiving tool. In scenarios where multiple CPU cores are logging data simultaneously, since each core may generate data that needs to be logged in every clock cycle during operation, and the data path ultimately needs to merge and summarize all data sources into one data stream before outputting it off-chip, there is a high possibility of insufficient bandwidth causing backpressure on some data links. Moreover, if the amount of data to be logged is too large, the phenomenon of new data overwriting old data after the RAM is full can lead to the loss of a large amount of logged data.

[0042] Furthermore, chip power-down protection plays a crucial role in ensuring data security, stable system operation, and system recoverability. Therefore, it is necessary to design reasonable protection logic to ensure that necessary data can be protected during power loss. Examples of existing power-down protection methods include: providing a stable power supply to the chip system through an uninterruptible power supply to prevent data loss; using EEPROM or other non-volatile memory in the chip or system to store important data; and using specialized power-down protection chips.

[0043] Because the backup power supply can only sustain operation for a limited time during a power outage, this method places high demands on data transmission rates. For systems requiring protection of large amounts of data during power outages, existing power-loss protection methods are insufficient. In analyzing complex multi-core systems, the high rate of data generation within the chip may allow for normal output from the chip and reception by external tools, but the relatively slow write speed to the hard drive can prevent timely data loss, ultimately impacting system analysis.

[0044] To address the shortcomings of existing critical data recording and power-loss protection methods, a critical data protection and recording method based on the NVMe protocol is introduced. NVMe is a host controller interface for PCIe-based solid-state drives (SSDs), offering significant advantages in performance, power consumption, compatibility, and management efficiency. NVMe is specifically designed for non-volatile storage media such as NAND and flash memory, meeting the demands of high-speed storage. NVMe's advantage lies in its ability to utilize parallel data paths, resulting in improved performance acceleration. It enables existing and new applications to function more efficiently. Furthermore, NVMe's advantages include low latency, low power consumption, and high compatibility.

[0045] Therefore, this invention provides a critical data processing system capable of performing two functions: power-down critical data protection and critical data recording. During normal system operation, critical data is recorded to a storage disk; during power failure, critical data is quickly transferred to the storage disk; and during operation, the system automatically switches from critical data recording to power-down critical data protection based on power supply voltage monitoring. The framework structure diagram of this critical data processing system is shown below. Figure 1 As shown, the term "module" as used below can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0046] The critical data processing system includes: a power failure monitoring module, a power failure processing module, a critical data extraction module, a hardware acceleration module, volatile memory, and a storage disk.

[0047] The power failure monitoring module is used to monitor the power supply voltage and the status of the data recording switch. When the power supply voltage is less than a preset voltage, a data protection command is generated; when the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, a data recording command is generated.

[0048] Optionally, when the power failure monitoring module detects that the power supply voltage is lower than the preset voltage, it switches to the backup power supply to ensure that the data protection process can be completed smoothly.

[0049] Optionally, the critical data processing system also includes an arbitration module, used to arbitrate upon receiving a data recording instruction or a data protection instruction, generating an arbitration result so that the critical data extraction module or the power failure processing module can obtain the corresponding data from the upstream sub-unit module based on the arbitration result. Specifically, arbitration is performed on the data recording instruction issued by the power failure monitoring module, enabling the critical data recording module to obtain critical data from the corresponding upstream sub-unit module to generate a data recording packet based on the arbitration result of the recorded data; or arbitration is performed on the protection data according to the data protection instruction, enabling the power failure processing module to obtain continuous data to be protected from the corresponding upstream sub-unit module to generate a complete protection data packet based on the arbitration result of the protection data.

[0050] The key data extraction module is used to acquire the data to be recorded when a data recording instruction is received; to package the data to be recorded into a recording data packet and store it in the first target storage block of the volatile memory; and to generate a first command and send it to the hardware acceleration module.

[0051] Specifically, the data recording packet includes the key data to be recorded, a timestamp, and packet header information. The first command contains the ID information of the first target storage block, and the hardware acceleration module will determine whether the first target storage block is available based on this ID information.

[0052] The power-down processing module is used to acquire the data to be protected when a data protection command is received; the data to be protected contains an end tag, which is used to indicate whether the data to be protected is complete; the data to be protected is packaged into a protection data packet and stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module.

[0053] Specifically, the data protection package includes the key data to be protected, timestamps, and tag information. The tag information serves as a data end marker. When the power failure processing module obtains the data to be protected from the upstream sub-unit module, it uses this tag information as a basis to ensure that the obtained data to be protected is continuous and complete, thereby generating a complete protection data package.

[0054] The hardware acceleration module is used to read record data packets from the first target storage block of the volatile memory via the storage disk when a first command is received; and to read protection data packets from the second target storage block of the volatile memory via the storage disk when a second command is received.

[0055] Optionally, the hardware acceleration module is further configured to: upon receiving the first command, determine whether the first target storage block of the volatile memory has been released; if the first target storage block of the volatile memory has not been released, send a masking command to the critical data extraction module, causing the critical data extraction module to stop storing the recorded data packet into the first target storage block of the volatile memory. Specifically, the critical data extraction module sends the storage block ID for data recording to the hardware acceleration module. The hardware acceleration module determines whether the storage block for critical data recording is available based on the received storage block ID information. If it is unavailable, it stops writing critical data into the volatile memory.

[0056] The hardware acceleration module can be an NVMe hardware acceleration module, and the storage disk can be an NVMe disk. In this case, the first command is an NVMe command for recording data, and the second command is an NVMe command for protecting data. When the NVMe hardware acceleration module receives an NVMe command, it generates an NVMe command frame according to the NVMe protocol requirements, manages it according to the NVMe disk's submission queue requirements, delivers a submission doorbell to the NVMe disk, notifies the NVMe disk to read data packets from the corresponding location in the volatile memory, parses the completion entry returned by the disk, delivers the completion doorbell, and generates a response as required, sending it to the corresponding upstream module.

[0057] It should be noted that the NVMe hardware acceleration module and NVMe disk based on the NVMe protocol described above are one application scenario of the solution involved in the embodiments of this application. The solution involved in the embodiments of this application can also be executed through other protocols that support the various functions involved in the embodiments of this application. Data transmission can be performed using hardware acceleration modules and storage disks based on various interface protocols. For example, data transmission can be performed using AHCI hardware acceleration modules based on the AHCI (Advanced Host Controller Interface) protocol and SATA storage devices; data transmission can also be performed using SCSI (Small Computer System Interface) protocol with various types and specifications of hard drives, including traditional mechanical hard drives and solid-state drives. However, the SATA interface protocol is suitable for low-performance mechanical hard drives, but as the performance of SSDs has gradually increased, the traditional standard is no longer applicable, thus becoming a major bottleneck limiting SSDs. In addition, NVMe offers nearly 6 times the read and write performance compared to AHCI / SATA, and 2 to 3 times the read and write performance compared to AHCI / PCIe SSDs.

[0058] Therefore, using NVMe hardware acceleration modules and NVMe disks based on the NVMe protocol can better record and protect critical data.

[0059] The critical data processing system of this invention includes two functions: critical data recording and critical data protection during power failure. A power failure monitoring module monitors the power supply voltage and the data recording switch status in real time, determining whether to activate the critical data recording function or the power failure data protection function based on the monitoring results and the data recording switch status. When the power supply voltage is greater than or equal to a preset threshold voltage, it indicates that the system is operating normally. If the data recording switch is on at this time, the critical data extraction module records the critical data. The critical data extraction module obtains critical data from the upstream sub-unit module, packages it into a data recording packet, stores the data recording packet in the first storage block of the volatile memory, and sends a first command to the hardware acceleration module to read the data recording packet from the first storage block of the volatile memory and move the data recording packet to the storage disk, completing the recording of the critical data. When the power supply voltage is less than the preset threshold voltage, it indicates that the system has lost power, requiring the critical data recording process to be stopped and the critical data protection process to be activated, with the power failure handling module protecting the critical data. The power-down processing module retrieves the data to be protected, tagged with an end label, from the upstream sub-unit module and packages it into a data protection packet. The end label indicates whether the data is continuous and complete; only continuous and complete critical data is protected. The data protection packet is stored in the second storage block of the volatile memory, and a second command is sent to the hardware acceleration module to read the data recording packet from the second storage block and move it to the storage disk, thus completing the protection of the critical data. This critical data processing system features high transmission rate and ample storage space. During normal operation, it records critical data to the storage disk and quickly moves it to the storage disk during power failure. It can achieve both power-down critical data protection and critical data recording functions, and can automatically switch from critical data recording to power-down critical data protection based on power supply voltage monitoring during operation.

[0060] The key data processing system in this embodiment is presented in the form of functional units. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0061] Based on the above, this embodiment also proposes a key data processing method, which is applied to the above-mentioned key data processing system. The method includes a key data recording method and a key data protection method.

[0062] The process of key data recording methods is as follows: Figure 2 As shown, it includes the following steps.

[0063] S201. Obtain the power supply voltage and data recording switch status. When the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, obtain the recording data packet.

[0064] Specifically, in step S201, when the power supply voltage is not less than the preset voltage, it indicates that the system is operating normally, and the critical data recording process is initiated. A data recording instruction is sent to the upstream sub-unit module and the critical data extraction module, enabling the critical data extraction module to acquire the critical data to be recorded and assemble it into a data recording package.

[0065] S202, Store the recorded data packet into the first target storage block of the volatile memory.

[0066] Specifically, in step S202, the key data extraction module stores the acquired data record packet into a specific data storage block of the volatile memory, and generates a first command containing the ID of the data storage block and sends it to the NVMe hardware acceleration module, so that the hardware acceleration module can determine whether the data storage block is available. The first command is an NVMe command for recording data.

[0067] S203. Read the record data packet from the first target storage block of the volatile memory through the storage disk.

[0068] Specifically, in step S203, the hardware acceleration module moves the data record packet from a specific data storage block of the volatile memory to the storage disk according to the received first command.

[0069] The process of critical data protection methods is as follows: Figure 3 As shown, it includes the following steps.

[0070] S301. Obtain the power supply voltage and compare it with a preset voltage. When the power supply voltage is less than the preset voltage, obtain the protection data packet.

[0071] Specifically, in step 3201, when the power supply voltage is lower than the preset voltage, it indicates a system power failure, and the critical data protection process is initiated. A data protection command is sent to the upstream sub-unit module and the power failure handling module, enabling the power failure handling module to acquire the critical data to be protected and assemble it into a data protection package. It should be noted that when acquiring the critical data to be protected, an end tag is used to determine whether the acquired data is continuous and complete, ensuring that a complete data protection package is obtained.

[0072] S302. Store the protection data packet in the second target storage block of the volatile memory.

[0073] Specifically, in step S302, the power-down processing module stores the acquired data protection packet into a specific data storage block of the volatile memory and sends a second command to the hardware acceleration module. The second command is an NVMe command for protecting the data.

[0074] S303. Read the protection data packet from the second target storage block of the volatile memory via the storage disk.

[0075] Specifically, in step S303, the hardware acceleration module moves the data record packet from a specific data storage block of the volatile memory to the storage disk according to the received second command.

[0076] In summary, the key data recording method and key data protection method provided in this embodiment are applied to the above-mentioned key data processing system. Different functions are selected according to the real-time monitored power supply voltage. Key data is recorded to the storage disk during normal operation and key data is quickly moved to the storage disk when power is lost.

[0077] The following example will illustrate the key data processing system and method based on the key data processing system and method provided in the above embodiments.

[0078] Combination Figure 1 The critical data processing system shown in this example has the following framework: the upstream is a sub-unit that needs to record or protect critical data, and the main processing modules are an arbitration module, a power failure monitoring module, a power failure handling module, a critical data extraction module, and a hardware acceleration module (taking the NVMe hardware acceleration module as an example); the downstream consists of volatile memory (DDR in this example) and storage disks (NVMe disks as an example).

[0079] The NVMe hardware acceleration module, based on the NVMe command processing flow, constructs the provided command word as a `sq_entry` as required. It manages the `sq_entry` according to the SQ queue requirements of the NVMe device, delivers `sq_doorbell` messages, parses `cq_entry` messages, delivers `cq_doorbell` messages, and returns a response as required. `Sq_proc` is the processing module for SQ services, and `cq_proc` is the processing module for CQ services. Specifically, the NVMe command processing flow is as follows: Figure 4As shown, the process includes the following steps: the host writes a command to the submission queue (SQ); the host updates the doorbell pointer of the SQ tail pointer and notifies the controller; the controller receives the notification and retrieves the command; the controller executes the command; after execution, the execution result completion queue entry (CQE) is written to the completion queue (CQ), and the CQ tail pointer is modified; the controller sends an interrupt notification that the command execution is complete; after receiving the interrupt, the host checks the command completion status; the host processes the command execution result and updates the doorbell pointer of the CQ head pointer.

[0080] Key data recording process such as Figure 5 As shown, it includes the following steps.

[0081] In response to the data recording command issued by the power failure monitoring module, the system sends critical data recording requests to the sub-units and the critical data extraction module. The sub-units write to their internal cache according to a predetermined packet format; for example, two caches can be prepared and written using a ping-pong method. After caching the complete data packet, the sub-unit initiates a critical data recording arbitration request. The arbitration module arbitrates the critical data recording requests from each sub-unit and generates an arbitration result. Based on the arbitration result, the critical data extraction module reads the data to be recorded from the corresponding sub-unit, assembles the data into packets, and adds timestamps and header information. The recorded data packets are then written to the storage block corresponding to the valid ID in the DDR. When the key data extraction module writes the data record packet to the storage block, it constructs a command word and sends it to the NVMe hardware acceleration module. This command word carries the ID information of the DDR record data storage block. The sq_proc in the NVMe hardware acceleration module generates a sq_entry based on the command word. The sq_entry retains the DDR record data storage block ID information. The sq_proc in the NVMe hardware acceleration module writes the sq_entry to the DDR. The sq_proc in the NVMe hardware acceleration module generates a sq_doorbell and sends it to the NVMe disk. The NVMe disk retrieves the recorded data from the corresponding location in the DDR based on the sq_doorbell.

[0082] It should be noted that the critical data cache of DDR supports block storage. The cache storing record data in DDR is divided into multiple storage blocks of the same size according to different IDs. The validity of the data storage block is determined by the NVMe hardware acceleration module. Specifically, the cq_proc in the NVMe hardware acceleration module receives the cq_entry returned by the disk and can parse the record data storage block ID information of DDR from the cq_entry. The cq_proc in the NVMe hardware acceleration module generates a cq_reply based on the cq_entry and sends it to the critical data extraction module. The cq_proc in the NVMe hardware acceleration module generates a cq_doorbell and sends it to the NVMe disk. The critical data extraction module obtains the released DDR storage block ID information based on the cq_reply and can determine whether the ID corresponding to the DDR storage block is available when generating the command word. If all the cache IDs storing record data in DDR have not been released, the write signal of the critical data extraction module to DDR is blocked after the data record packet is generated. Only when there is a usable record data cache block in DDR will the complete data record packet be written.

[0083] Critical data protection processes such as Figure 6 As shown, it includes the following steps.

[0084] In response to the data protection command issued by the power failure monitoring module, the backup power supply is activated, and the system sends critical data protection requests to the sub-units and the power failure handling module. Upon receiving the critical data protection request, the sub-unit stops initiating critical data recording arbitration requests; it caches the data to be protected, waiting for the first arbitration enable (i.e., when a power failure protection request is detected) to initiate a power failure protection arbitration request. The arbitration module arbitrates the power failure protection requests from each sub-unit. After the first arbitration result is generated, the arbitration enable is pulled low. The arbitration enable needs to be activated again based on the protection data end flag read from the sub-unit in the next step to ensure the continuity and integrity of the sub-unit's power failure protection data. The power failure handling module obtains the arbitration result, reads the power failure protection data inside the sub-unit, and assembles it into packets, adding timestamps and tag information. The tag information serves as the data end flag to determine whether a complete data packet to be protected has been received. After packet assembly, the data protection packet is written to a specific address in the DDR, and a command word is constructed and sent to the NVMe hardware acceleration module. In the NVMe hardware acceleration module, sq_proc generates sq_entry based on the command word; sq_proc writes sq_entry to DDR; sq_proc generates sq_doorbell and sends it to the NVMe disk; the NVMe disk retrieves power-loss protection data from the corresponding location in DDR based on sq_doorbell; cq_proc receives and parses cq_entry; cq_proc generates cq_doorbell and sends it to the NVMe disk; the NVMe hardware acceleration module generates a power-loss protection end flag.

[0085] In summary, the critical data recording and protection methods provided in this example, based on the aforementioned critical data processing system and methods, select different functions according to the real-time monitored power supply voltage and data recording switch status. During normal operation, critical data is recorded to the NVMe disk, and in the event of a power outage, the critical data is quickly moved to the NVMe disk. Leveraging the low latency and high bandwidth data transmission advantages of the NVMe protocol, the rapid migration of critical data to the disk for protection during power outages effectively improves power-loss protection efficiency. Simultaneously, in scenarios requiring continuous recording of critical data, data can be written to the corresponding hard disk space in a timely manner, solving the problem of low data transfer rates in ordinary systems. Furthermore, migrating the data to the NVMe disk allows for the storage of more critical data. The system supports automatic switching from critical data recording to power-loss critical data protection during operation, depending on the usage scenario.

[0086] This invention also provides a computer device having the above-described features. Figure 1 The key data processing system is shown. Please refer to [link / reference]. Figure 7 , Figure 7This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0087] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0088] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0089] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0090] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0091] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0092] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0093] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0094] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A key data processing system, characterized in that, The system includes: a power failure monitoring module, a power failure handling module, a key data extraction module, a hardware acceleration module, a volatile memory, and a storage disk; The power failure monitoring module is used to monitor the power supply voltage and the status of the data recording switch. When the power supply voltage is less than a preset voltage, a data protection command is generated; when the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, a data recording command is generated. The key data extraction module is used to obtain the data to be recorded when a data recording instruction is received; to package the data to be recorded into a recording data packet and store it in the first target storage block of the volatile memory; and to generate a first command and send it to the hardware acceleration module. The power-down processing module is used to acquire the data to be protected when a data protection instruction is received; the data to be protected contains an end tag, which is used to indicate whether the data to be protected is complete; the data to be protected is packaged into a protection data packet and stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module. The hardware acceleration module is configured to read the record data packet from the first target storage block of the volatile memory via the storage disk when the first command is received; and to read the protection data packet from the second target storage block of the volatile memory via the storage disk when the second command is received.

2. The key data processing system according to claim 1, characterized in that, The hardware acceleration module is also used for: When the first command is received, it is determined whether the first target memory block of the volatile memory has been released; If the first target storage block of the volatile memory is not released, a masking command is sent to the key data extraction module, causing the key data extraction module to stop storing the record data packet in the first target storage block of the volatile memory.

3. The key data processing system according to claim 1, characterized in that, The power failure monitoring module is also used for: When the power supply voltage is lower than the preset voltage, switch to the backup power supply.

4. The key data processing system according to claim 1, characterized in that, The system also includes: An arbitration module is used to arbitrate the data recording instruction when it is received, and generate a first arbitration result; the first arbitration result is used to instruct the key data extraction module to obtain the data to be recorded from the corresponding upstream sub-unit module to generate the recording data packet.

5. The key data processing system according to claim 4, characterized in that, The arbitration module is also used for: When the data protection instruction is received, the data protection request in the data protection instruction is arbitrated, and a second arbitration result is generated based on the end tag; The second arbitration result is used to instruct the power failure processing module to obtain continuous data to be protected from the corresponding upstream sub-unit module to generate the protection data packet.

6. A key data processing method, characterized in that, The method, applied to a critical data processing system as described in any one of claims 1 to 5, comprises: Acquire power supply voltage and record switch status; When the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, the data recording data packet is acquired; The recorded data packet is stored in the first target storage block of the volatile memory; The record data packet is read from the first target storage block of the volatile memory via the storage disk.

7. The key data processing method according to claim 6, characterized in that, The method further includes: When the power supply voltage is lower than the preset power supply, a protection data packet is acquired; The protection data packet is stored in the second target memory block of the volatile memory; The protection data packet is read from the second target storage block of the volatile memory via the storage disk.

8. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the key data processing method of any one of claims 6 to 7 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the key data processing method according to any one of claims 6 to 7.

10. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the key data processing method according to any one of claims 6 to 7.

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