Cross-clock domain data latching system and method

Abstract

The application relates to a cross-clock domain data latching system, comprising a first clock domain module configured to generate a first signal that conforms to a first clock domain clock frequency and represents a first clock domain data update; the latch module is coupled to the first clock domain module, comprises one or more latches and is configured to receive data from the first clock domain module and latch the data; and the second clock domain module is coupled to the latch module and is configured to generate a second signal which conforms to a second clock domain clock frequency and represents that the data in the latch module is about to be read, and the second clock domain clock frequency is higher than the first clock domain clock frequency. The invention further relates to electronic equipment. The invention further relates to a cross-clock-domain data latching method. According to the method and the device, the occurrence probability and the negative influence of the metastable state are reduced aiming at a cross-clock-domain scene.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a cross-clock domain data latching system and method. Background Art

[0002] In modern integrated circuit (IC) design, especially in highly integrated system-on-chip (SoC) design, clock domain crossing (CDC) is a critical and complex issue. With the increasing complexity of chip functions and the diversification of clock networks, cross-clock domain interfaces are increasing. How to effectively process these asynchronous signals becomes the key to ensuring system stability and reliability.

[0003] When a signal crosses from one clock domain to another, if it is not handled properly, it is very easy to generate a metastable state. Metastable state means that the output of a circuit element is in an uncertain state, which may be between a high level and a low level, and is manifested as the level of the output signal fluctuating around an intermediate value. This uncertain output will cause the subsequent logic circuit to receive an erroneous signal and cause serious failures in the system. Therefore, avoiding the generation of metastable states is very important in cross-clock domain data processing.

[0004] Although the occurrence of metastable state cannot be completely avoided, its probability and negative impact can be reduced through reasonable design methods.

[0005] According to the prior art, a multi-stage synchronizer can be used to reduce the impact of metastable states. By setting multiple triggers in series in the user clock domain, data from the master clock domain is received. However, this method has certain defects in the case where the user clock is much faster than the master clock, such as in the application scenario where the user clock frequency is greater than twice the master clock frequency. Strategies such as synchronizers, handshakes, or first-in-first-out (FIFO) cannot meet the requirements, because when the user issues a read command, the above strategies cause the user to read incomplete or erroneous data due to the slow master clock and large synchronization logic delay.

[0006] Therefore, a reliable method is needed to implement data latching from the master clock domain to the user clock domain. Summary of the invention

[0007] In view of the technical problems existing in the prior art, the present application proposes a cross-clock domain data latching system, comprising: a first clock domain module, configured to generate a first signal representing a first clock domain data update that conforms to a clock frequency of the first clock domain; a latch module, coupled to the first clock domain module, comprising one or more latches, configured to receive data from the first clock domain module and latch it; a second clock domain module, coupled to the latch module, configured to generate a second signal representing data to be read from the latch module that conforms to a clock frequency of the second clock domain, wherein the clock frequency of the second clock domain is higher than that of the first clock domain. clock frequency; wherein the first clock domain module at least includes a first latch signal generating unit, coupled to the second clock domain module, configured to receive the first signal and the second signal and generate a first latch signal based on the first signal and the second signal; a buffer unit, coupled to the first latch signal generating unit, when the first latch signal is valid, configured to widen the first latch signal to generate a second latch signal and provide it to the latch module, the latch module is configured to update its latched data to the current first clock domain data, wherein the pulse width of the second latch signal is greater than or equal to the minimum latch pulse width of the latch module.

[0008] In particular, in the cross-clock domain data latching system proposed in the present application, when the first latching signal fails, the output of the buffer unit fails, and the latching module is configured not to update the latched data.

[0009] In particular, the cross-clock domain data latching system proposed in the present application, wherein the first latch signal generating unit includes at least a NOT gate, whose input end is configured to receive the second signal; and an AND gate, whose first input end is coupled to the output end of the NOT gate, whose second input end is configured to receive the first signal, and whose output end is coupled to the buffer unit.

[0010] In particular, the present application proposes a cross-clock domain data latching system, wherein the buffer unit includes at least one buffer sub-unit; wherein the buffer sub-unit includes: a first buffer, whose input end is coupled to the first latch signal generating unit and is configured to receive the first latch signal; or a gate, whose first input end is coupled to the output end of the first buffer, whose second input end is coupled to the input end of the first buffer, and whose output end is coupled to the output end of the buffer unit.

[0011] In particular, the cross-clock domain data latching system proposed in the present application, wherein the buffer unit also includes a filtering subunit, which is coupled between the first latch signal generating unit and the first buffer subunit, and is configured to filter out the first latch signal that is smaller than a preset pulse width.

[0012] In particular, in the cross-clock domain data latching system proposed in the present application, the preset pulse width adopted by the filtering subunit is at least related to the maximum latch pulse width of each latch in the latch module.

[0013] In particular, in the cross-clock domain data latch system proposed in the present application, the preset pulse width is also related to the driving pulse width and number of the first buffer.

[0014] In particular, in the cross-clock domain data latching system proposed in the present application, the filtering subunit is a second buffer, and its driving pulse width is greater than the driving pulse width of the first buffer.

[0015] The present application also proposes an electronic device, comprising the above-mentioned cross-clock domain data latching system.

[0016] The present application also proposes a cross-clock domain data latching method, including: when a first signal representing the update of first clock domain data is valid and a second signal representing the latched data to be read is invalid, a first latch signal is generated based on the first signal and the second signal, and the first latch signal is widened to generate a second latch signal that meets the latch pulse width, and the latched data is updated using the current first clock domain data.

[0017] In particular, the cross-clock domain data latching method proposed in the present application further includes: when the first signal is valid and the second signal is also valid, the latched data is not updated.

[0018] In particular, the cross-clock domain data latching method proposed in the present application further includes filtering the first latch signal first, and then widening the filtered signal to obtain the second latch signal.

[0019] This application targets cross-clock domain scenarios, ensuring that data remains stable when users read, while reducing the probability and negative impact of metastable states. In particular, in application scenarios where the user clock frequency is greater than twice the master clock frequency, this application can quickly complete the latching of the latest data after the signal representing the master clock domain data update is generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1 is a schematic diagram of a cross-clock domain data latching system according to an embodiment of the present application; Figure 2 is a timing diagram of working signals of a cross-clock domain data latch system according to an embodiment of the present application; Figure 3 is a timing diagram of working signals of a cross-clock domain data latch system according to an embodiment of the present application; Figure 4 is a timing diagram of working signals of a cross-clock domain data latch system according to an embodiment of the present application; Figure 5 It is a flow chart of a cross-clock domain data latching method according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0023] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0024] In the following detailed description, a high level is valid and a low level is invalid. Based on the present application, merely defining the change of the signal valid or invalid state in the opposite way also falls within the protection scope of the present application.

[0025] Figure 1 is a schematic diagram of a cross-clock domain data latching system according to an embodiment of the present application.

[0026] According to one embodiment, the cross-clock domain data latch system may include a main clock domain module 10 and a user clock domain module 11 , and a latch module 12 coupled therebetween.

[0027] According to one embodiment, the master clock domain module 10 may include a first latch signal generating unit 101 .

[0028] According to one embodiment, the first latch signal generating unit 101 may be configured to receive update_main. Update_main is a signal representing data update of the main clock domain module 10. According to one embodiment, the signal width of update_main may be at least one main clock cycle.

[0029] According to an embodiment, the first latch signal generating unit 101 may also be configured to receive read_user. read_user is a signal indicating that data in the latch module is about to be read, indicating that the user will read data in the latch module 12 in the next user clock cycle. read_user may maintain a high level during the user reading data.

[0030] According to one embodiment, the first latch signal generating unit 101 may include at least one NOT gate 1011 and one AND gate 1012. The NOT gate 1011 is configured to receive read_user, and its output terminal is electrically connected to the first input terminal of the AND gate 1012. The second input terminal of the AND gate 1012 is configured to receive update_main. The output terminal of the AND gate 1012 is configured to output latch_en_temp. According to one embodiment, when update_main is valid and read_user is invalid, latch_en_temp is valid. When the user is reading, read_user is valid. At this time, regardless of whether update_main is valid, the output signal latch_en_temp is invalid, and the data is not updated, ensuring that the data is stable when the user reads.

[0031] According to one embodiment, the master clock domain module 10 may further include a buffer unit 102. According to one embodiment, the buffer unit 102 may be configured to widen latch_en_temp to obtain latch_en. The reason for widening latch_en_temp is to ensure that latch_en meets the minimum pulse width requirement of the latch module 12. If the minimum pulse width requirement of the latch module 12 is not met, data may not be properly latched.

[0032] According to an embodiment, the buffer unit 102 may include a plurality of buffer subunits 1021. Each buffer subunit 1021 can delay the received signal for a certain time. Therefore, latch_en_temp is delayed step by step by the plurality of buffer subunits 1021, and the obtained latch_en is equivalent to latch_en_temp being widened, and the total width of the widening is the sum of the delay times of the buffer subunits.

[0033] According to one embodiment, each buffer subunit 1021 may include at least one buffer 10211, whose input terminal is configured to receive latch_en_temp or buffered latch_en_temp, and whose output terminal is coupled to a first input terminal of an OR gate 10212. Another input terminal of the OR gate 10212 is configured to receive latch_en_temp or buffered latch_en_temp.

[0034] According to another embodiment, latch_en_temp with a pulse width that is too small still cannot meet the minimum pulse width requirement of the latch module after being widened. To avoid this situation, the buffer unit 102 can also be configured to filter latch_en_temp that still does not meet the minimum pulse width requirement of the latch module 12 after being widened. Because there are some slight differences between the minimum latch pulse widths of different latches in the latch module 12, the input signal latch_en_temp is filtered to ensure that the pulse width of latch_en after its widening must be greater than a certain length to ensure that all latches work at the same time, otherwise it will cause some latches to work and some latches to not work, resulting in latched data errors. Therefore, optionally, according to one embodiment, the buffer unit 102 can also include a filtering subunit 1022, whose input end is configured to receive the first latch signal latch_en_temp, and whose output end is coupled to the input end of the first buffer subunit 1021. According to one embodiment, the filtering subunit 1022 may include a buffer having a larger specification than the buffer in the buffer subunit, so that a signal with a pulse width too small cannot enter the buffer subunit 1021 .

[0035] According to one embodiment, the OR gate 10231 in the last buffer sub-unit has a stronger driving capability than the OR gates in other buffer sub-units, and can drive the latch module 12 .

[0036] According to one embodiment, the number of buffer sub-units in the buffer unit 102 is determined according to the delay parameters of the buffer sub-units and the minimum latch signal pulse width of the latch module 12 .

[0037] Assume that the minimum pulse width requirement of the latch module 12 is t l The minimum driving pulse width of the filter subunit 1022 is t f , that is, the pulse width of latch_en_temp must be at least t f Only then can it pass through the filtering subunit 1022. The pulse delay of each buffer subunit is t b , the number of buffer subunits is n. In order for the second latch signal latch_en to meet the minimum pulse width requirement of the latch module 12, it should satisfy: t f +nt b ≥t l , that is, n≥(t l -t f ) / t b .

[0038] Optionally, according to an embodiment, to avoid deviation, an additional width of 20% is usually reserved, so the number n of buffer sub-units finally used should satisfy n≥1.2 (t l -t f ) / t b .

[0039] Optionally, the above formula can also be used to calculate t f The range of t f ≥t l -nt b / 1.2.

[0040] According to one embodiment, the period of the driving signal of the user clock domain may be 30ns. After the first latch signal latch_en_temp with a pulse width of 0.3ns is widened by 24 buffer subunits 1021, the pulse width of the generated second latch signal latch_en is 1.5ns (0.3+0.05×24=1.5). After a rising edge or falling edge of the user clock domain module driving signal is generated, read_user can ensure that the latest data can be latched before the next rising edge or falling edge of the user clock domain module driving signal arrives, because the pulse width of the second latch signal latch_en is less than half of the period of the user clock domain module driving signal.

[0041] Optionally, according to an embodiment, the number of buffer subunits may be greater than the minimum number limit. In subsequent operations, the number of buffer subunits actually used may be adjusted by adding switches or the like.

[0042] Figures 2 to 4 It is a timing diagram of working signals of a cross-clock domain data latch system according to an embodiment of the present application.

[0043] According to one embodiment, the cross-clock domain data latching system may involve a signal main_clk. Main_clk is a driving signal of a main clock domain module.

[0044] According to one embodiment, the cross-clock domain data latching system may further involve a signal update_main. Update_main is a signal representing the main clock domain data update.

[0045] According to one embodiment, the cross-clock domain data latching system may further involve a signal user_clk. User_clk is a driving signal of a user clock domain module.

[0046] According to one embodiment, the cross-clock domain data latching system may further involve a signal read_user. Read_user is a signal indicating that data in the latch module is to be read.

[0047] According to one embodiment, the cross-clock domain data latching system may further involve a first latch signal latch_en_temp. Latch_en_temp is a first latch signal generated by a first latch signal generating unit.

[0048] According to one embodiment, the cross-clock domain data latching system may further involve a second latch signal latch_en. Latch_en is a second latch signal obtained by extending the first latch signal latch_en_temp through a buffer unit.

[0049] According to one embodiment, the cross-clock domain data latching system may also involve data main_data. Main_data is data in the main clock domain module.

[0050] According to one embodiment, the cross-clock domain data latching system may also involve data user_data. User_data is data read by the user clock domain module.

[0051] According to one embodiment, Figure 2 As shown, at time t1, update_main jumps to valid, and at time t2 after t1, read_user jumps to valid. After read_user jumps to valid, user_clk jumps to valid. For example, the next rising edge t3 will trigger the user to read the data. That is, the data in the main clock domain has been updated, and before the user starts to read the data in the latch module, this time can be fully utilized to make the latch module latch the updated data in the main clock domain. For example, in the time period from t1 to t2, update_main is valid, read_user is invalid, and after the operation of the first latch signal generating unit, latch_en_temp is valid. Latch_en_temp is filtered and widened by the buffer unit to generate latch_en. The pulse width of this signal is greater than or equal to the minimum pulse width for the latch module to work normally, so that the latest data DATA_B is latched into the latch module before the user reads the data.

[0052] Alternatively, according to one embodiment, when the filtering subunit is not used, the rising edge of latch_en is aligned with the rising edge of latch_en_temp.

[0053] According to one embodiment, the number of buffer sub-units in the buffer unit is determined according to the delay parameters of the buffer sub-units and the minimum latch signal pulse width of the latch module.

[0054] Assume that the minimum pulse width requirement of the latch module is t l The minimum driving pulse width of the filter subunit is t f , that is, the pulse width of latch_en_temp must be at least t f The pulse delay of each buffer subunit is t b , the number of buffer subunits is n. In order for the second latch signal latch_en to meet the minimum pulse width requirement of the latch module, it should meet the following requirements: t f +nt b ≥t l , that is, n≥(t l -t f ) / t b .

[0055] Optionally, according to an embodiment, to avoid deviation, an additional width of 20% is usually reserved, so the number n of buffer sub-units finally used should satisfy n≥1.2 (t l -t f ) / t b .

[0056] Optionally, the above formula can also be used to calculate t f The range of t f ≥t l -nt b / 1.2 .

[0057] According to one embodiment, Figure 3 As shown, at time t4, update_main jumps to valid, and at time t5 before time t4, read_user jumps to valid, and at time t4, read_user is still valid. It can be considered that the user is reading data or will read data soon, so it is necessary to keep the data stable to prevent the user from reading wrong data. Specifically, after the operation of the first latch signal generating unit, it is obtained that latch_en_temp is invalid and cannot be widened, latch_en is invalid, although the data in the main clock domain has been updated to DATA_B, the data in the latch will not be updated, ensuring that the data remains stable when the user reads.

[0058] According to one embodiment, Figure 4As shown, at time t5, update_main jumps to valid, and at time t6 after time t5, read_user jumps to valid. In the time period from t5 to t6, update_main is valid, read_user is invalid, and after the operation of the first latch signal generating unit, latch_en_temp is valid. However, at this time, the pulse width of latch_en_temp does not meet the minimum pulse width requirement of the filtering subunit in the buffer unit, so it fails to pass the filtering subunit, latch_en is still invalid, and the data is not updated.

[0059] The reasons for filtering latch_en_temp are as follows: First, latch_en_temp with a pulse width that is too small still cannot meet the minimum pulse width requirement of the latch module after being widened. Second, there are some subtle differences between the minimum latch pulse widths of different latches in the latch module. The input signal latch_en_temp needs to be filtered to ensure that the pulse width of latch_en after widening must be greater than a certain length to ensure that all latches work at the same time, otherwise some latches will work and some will not work, resulting in latched data errors.

[0060] Figure 5 It is a flow chart of a cross-clock domain data latching method according to an embodiment of the present application.

[0061] Step 501: receive update_main and read_user, and generate latch_en_temp. update_main is a signal representing the update of data in the main clock domain, and its width can be at least one main clock cycle. read_user is a signal representing the data in the latch module to be read.

[0062] Step 502: Determine whether latch_en_temp is valid.

[0063] Step 503: When latch_en_temp is invalid, the data is not updated.

[0064] Step 504: When latch_en_temp is valid, determine whether the pulse width of latch_en_temp meets the minimum pulse width requirement.

[0065] Step 505: When the pulse width of latch_en_temp does not meet the minimum pulse width requirement, latch_en_temp is ignored.

[0066] Step 506: The data is not updated.

[0067] Step 507: When the pulse width of latch_en_temp meets the minimum pulse width requirement, latch_en_temp is widened to generate latch_en.

[0068] Step 508: Latch the main clock domain data based on latch_en, waiting for the user to read.

[0069] The cross-clock domain data latching system and method proposed in the present application can reliably implement cross-clock domain data latching, ensuring that the data will not change when the user reads it at any time, thereby avoiding the occurrence of metastable conditions.

[0070] This application targets cross-clock domain scenarios, ensuring that data remains stable when users read, while reducing the probability and negative impact of metastable states. In particular, in application scenarios where the user clock frequency is greater than twice the master clock frequency, this application can quickly complete the latching of the latest data after the signal representing the master clock domain data update is generated.

[0071] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A cross-clock domain data latch system, characterized in that: include: A first clock domain module configured to generate a first signal representing a first clock domain data update that complies with a first clock domain clock frequency; A latch module, coupled to the first clock domain module, comprising one or more latches, configured to receive data from the first clock domain module and latch the data; A second clock domain module, coupled to the latch module, configured to generate a second signal that corresponds to a second clock domain clock frequency and represents that data in the latch module is to be read, wherein the second clock domain clock frequency is higher than the first clock domain clock frequency; Wherein, the first clock domain module at least includes: a first latch signal generating unit, coupled to the second clock domain module, configured to receive the first signal and the second signal and generate a first latch signal based on the first signal and the second signal; A buffer unit is coupled to the first latch signal generating unit. When the first latch signal is valid, the buffer unit is configured to widen the first latch signal to generate a second latch signal and provide it to the latch module. The latch module is configured to update its latched data to the current first clock domain data, wherein the pulse width of the second latch signal is greater than or equal to the minimum latch pulse width of the latch module.

2. The cross-clock domain data latch system according to claim 1, characterized in that: When the first latch signal is invalid, the buffer unit output is invalid, and the latch module is configured not to update the latched data.

3. The cross-clock domain data latch system according to claim 1, characterized in that: The first latch signal generating unit at least includes: a NOT gate, whose input terminal is configured to receive the second signal; An AND gate has a first input terminal coupled to the output terminal of the NOT gate, a second input terminal configured to receive the first signal, and an output terminal coupled to the buffer unit.

4. The cross-clock domain data latching system according to claim 1, characterized in that: The buffer unit includes at least one buffer subunit; The buffer subunit comprises: a first buffer, an input terminal of which is coupled to the first latch signal generating unit and configured to receive the first latch signal; An OR gate has a first input terminal coupled to the output terminal of the first buffer, a second input terminal coupled to the input terminal of the first buffer, and an output terminal coupled to the output terminal of the buffer unit.

5. The cross-clock domain data latching system according to claim 4 is characterized in that: The buffer unit further includes a filtering subunit coupled between the first latch signal generating unit and the first buffer subunit and configured to filter out the first latch signal having a pulse width smaller than a preset pulse width.

6. The cross-clock domain data latching system according to claim 5, characterized in that: The preset pulse width used by the filtering subunit is at least related to the maximum latch pulse width of each latch in the latch module.

7. The cross-clock domain data latching system according to claim 6 is characterized in that: The preset pulse width is also related to the driving pulse width and number of the first buffer.

8. The cross-clock domain data latching system according to claim 6, characterized in that: The filtering subunit is a second buffer, and a driving pulse width thereof is greater than a driving pulse width of the first buffer.

9. An electronic device, characterized in that: The invention comprises a cross-clock domain data latching system as described in any one of claims 1-8.

10. A method for latching data across clock domains, characterized in that: include: When the first signal representing the update of the first clock domain data is valid and the second signal representing the latched data to be read is invalid, a first latch signal is generated based on the first signal and the second signal, and the first latch signal is widened to generate a second latch signal that meets the latch pulse width, and the latched data is updated using the current first clock domain data.

11. The cross-clock domain data latching method according to claim 10, characterized in that: The method further includes not updating latched data when the first signal is valid and the second signal is also valid.

12. The cross-clock domain data latching method according to claim 10, characterized in that: The method further includes filtering the first lock signal and then stretching the filtered signal to obtain the second latch signal.

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