Pixel unit, display panel and display device

Abstract

The invention provides a pixel unit, a display panel and a display device. The pixel unit comprises a pixel electrode, a first switch tube and a second switch tube. The first connection end of the first switch tube is used for receiving data voltage, and the second connection end is electrically connected to the pixel electrode. The first connecting end of the second switch tube is used for receiving data voltage, and the second connecting end is electrically connected to the pixel electrode. The pixel units are displayed according to preset periods, and each preset period comprises X first-class frame periods and Y second-class frame periods. The first switch tube is switched on in a partial period of each first type of frame period and is switched off in each second type of frame period. And the second switch tube is kept switched off in each first type of frame period and is switched on in a part of time period of each second type of frame period. According to the pixel unit, the first data voltage hopping quantity generated by the first switching tube and the second data voltage hopping quantity generated by the second switching tube are at least partially counteracted, and the problem of head shaking lines can be relieved or even completely eliminated.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel unit, a display panel and a display device. Background Art

[0002] When the LCD (Liquid Crystal Display) panel is displaying, the pixel driving circuit in the display panel will turn on the switch tube for charging the pixel unit through the scan line input conduction voltage, and the data line will give the data voltage to the first end of the pixel capacitor Clc and the storage capacitor Cst through the turned-on switch tube. At the same time, the common voltage of the common voltage end is directly input to the second end of the pixel capacitor Clc and the storage capacitor Cst, so that the pixel capacitor Clc and the storage capacitor Cst are charged according to the data voltage and the common voltage, thereby changing the deflection degree of the liquid crystal.

[0003] However, due to the parasitic capacitance of the switch tube in the pixel unit itself, when the voltage on the scan line jumps from the on-voltage to the off-voltage (also called the cut-off voltage), the data voltage written to the first end of the pixel capacitor Clc and the storage capacitor Cst will be pulled down due to the coupling of the parasitic capacitance to produce a voltage drop, resulting in different brightness of the pixel unit at different polarities. When the user shakes his head to observe the display screen, it is easy to lose frames and produce shaking head wrinkles, affecting the display effect of the screen and the user's experience. Summary of the invention

[0004] In view of this, the main purpose of the present application is to propose a pixel unit, a display panel and a display device, aiming to solve the problem that existing LCD panels are prone to head shake wrinkles.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a pixel unit, which includes a pixel electrode, a first switch tube and a second switch tube. The first switch tube includes a first connection end, a second connection end and a control end, the first connection end of the first switch tube is used to receive a data voltage, and the second connection end of the first switch tube is electrically connected to the pixel electrode; the second switch tube includes a first connection end, a second connection end and a control end, the first connection end of the second switch tube is used to receive a data voltage, and the second connection end of the second switch tube is electrically connected to the pixel electrode; the pixel unit is displayed according to a preset period, each of the preset periods includes X first-type frame periods and Y second-type frame periods, X≥1, Y≥1; the control end of the first switch tube receives a first turn-on voltage in a partial period of each first-type frame period, so that the first switch tube is turned on and transmits the received data voltage to the pixel electrode, and the control end of the first switch tube continues to receive a first turn-off voltage in each second-type frame period, so that the first switch tube is turned on in each second-type frame period. The control end of the second switch tube keeps receiving the second turn-off voltage in each of the first-type frame periods, so that the second switch tube keeps turning off in each of the first-type frame periods, and the control end of the second switch tube receives the second turn-on voltage in a partial period of each of the second-type frame periods, so that the second switch tube is turned on and transmits the received data voltage to the pixel electrode; wherein the first switch tube is a high-level turn-on switch tube, the second switch tube is a low-level turn-on switch tube, the first turn-on voltage and the second turn-off voltage are both high-level voltages, and the second turn-on voltage and the first turn-off voltage are both low-level voltages; or, the first switch tube is a low-level turn-on switch tube, the second switch tube is a high-level turn-on switch tube, the first turn-on voltage and the second turn-off voltage are both low-level voltages, and the second turn-on voltage and the first turn-off voltage are both high-level voltages.

[0006] The pixel unit provided in the present application sets a first switch tube and a second switch tube which are both electrically connected to the pixel electrode, sets the first on-voltage of the first switch tube and the second off-voltage of the second switch tube to be the same level, sets the first off-voltage of the first switch tube and the second on-voltage of the second switch tube to be the same level, and allows the first switch tube to work in a first frame period and remain in an off state in a second frame period, and allows the second switch tube to work in a second frame period and remain in an off state in the first frame period, so that the first data voltage jump amount generated by the parasitic capacitance of the first switch tube and the second data voltage jump amount generated by the parasitic capacitance of the second switch tube can be at least partially offset, which can alleviate or even completely eliminate the shaking head wrinkle problem.

[0007] In some embodiments, in each of the preset periods, the number X of the first type of frame periods is equal to the number Y of the second type of frame periods.

[0008] In some embodiments, in each of the preset periods, the number X of the first type of frame periods and the number Y of the second type of frame periods are even numbers.

[0009] In some embodiments, in each of the preset periods, X first-type frame periods are arranged continuously, and Y second-type frame periods are arranged continuously.

[0010] In some embodiments, the first switch tube and the second switch tube are respectively located on opposite sides of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are respectively electrically connected to different data lines.

[0011] In some embodiments, the first switch tube and the second switch tube are both located at the same side of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are electrically connected to the same data line.

[0012] In some embodiments, the first switch tube is one of an N-type transistor and a P-type transistor, and the second switch tube is the other of the N-type transistor and the P-type transistor.

[0013] In some embodiments, a capacitance value of a parasitic capacitor between the gate and the source of the first switch tube is equal to a capacitance value of a parasitic capacitor between the gate and the source of the second switch tube.

[0014] The second aspect of the present application also provides a display panel, which includes N rows of pixel units, N first scan lines, and N second scan lines. The pixel units are the pixel units described in the first aspect above; the N first scan lines are electrically connected to the N rows of pixel units one by one, and each of the first scan lines is electrically connected to the control end of the first switch tube in the corresponding row of pixel units; the N first scan lines are used to output a first turn-on voltage to the control end of the first switch tube in the N rows of pixel units in each of the first-type frame periods in accordance with a preset timing, so as to control the first switch tube in the N rows of pixel units to be turned on row by row, and to keep outputting a first turn-off voltage to the control end of the first switch tube in the N rows of pixel units in each of the second-type frame periods, so as to control the first switch tube in the N rows of pixel units to be turned on in the second The N second scan lines are electrically connected to the N rows of pixel units one by one, and each of the second scan lines is electrically connected to the control end of the second switch tube in the corresponding row of pixel units; the N second scan lines are used to output a second turn-off voltage to the control end of the second switch tube in the N rows of pixel units in each of the first frame periods to control the second switch tubes in the N rows of pixel units to remain turned off in the first frame periods, and in each of the second frame periods, output a second turn-on voltage to the control end of the second switch tube in the N rows of pixel units in sequence according to a preset timing to control the second switch tubes in the N rows of pixel units to be turned on row by row.

[0015] A third aspect of the present application further provides a display device, which includes a row driving module and the display panel described in the second aspect, wherein the row driving module is electrically connected to the display panel.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0018] Figure 2 for Figure 1 A driving voltage waveform diagram of a pixel unit in;

[0019] Figure 3 Schematic diagram of the mechanism of head shake lines;

[0020] Figure 4 A schematic diagram of a first structure of a display device provided in an embodiment of the present application;

[0021] Figure 5 A second structural schematic diagram of a display device provided in an embodiment of the present application;

[0022] Figure 6 for Figure 4-5 A driving voltage waveform diagram of a pixel unit in;

[0023] Figure 7 for Figure 4-5 A timing diagram of a scanning signal of a first row of pixel units in a display device in a preset period;

[0024] Figure 8 for Figure 4-5 The diagram is a schematic diagram of the brightness of each frame of the display device when it is working.

[0025] The following are the descriptions of the reference numerals:

[0026] Display device 1

[0027] Display panel 100

[0028] Row driver module 200

[0029] Pixel unit P, P'

[0030] Switch tube 11

[0031] Pixel electrode 12

[0032] The first switch tube T1

[0033] The second switch tube T2

[0034] The first scanning line Scan

[0035] The second scanning line Scan'

[0036] Liquid crystal capacitance Clc

[0037] Storage capacitor Cst

[0038] Parasitic capacitance Cgs

[0039] Common electrode Vcom

[0040] Scan Line 101

[0041] Data line 102

[0042] Data voltage Vd

[0043] Pixel voltage Vs, Vs'

[0044] Scan signal Vg

[0045] Data voltage jump value ΔV

[0046] The first data voltage jump amount ΔV1

[0047] The second data voltage jump amount ΔV2

[0048] High level voltage Vgh

[0049] Low level voltage Vgl

[0050] The first frame period Fram1

[0051] The second frame period Fram2

[0052] The third frame period Fram3

[0053] The fourth frame period Fram4

[0054] The fifth frame period Fram5

[0055] The sixth frame cycle Fram6

[0056] The seventh frame cycle Fram7

[0057] The eighth frame cycle Fram8

[0058] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In addition, the terms "first", "second", etc. in the specification of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0061] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0062] Compared with traditional CRT (Cathode Ray Tube) TVs and plasma TVs, a major advantage of LCD TVs is that they save power. LCD consumes only half the power of CRTs of the same size, and is much lower than plasma. Compared with traditional CRTs, LCDs are also better in terms of environmental protection. This is because there are no high-voltage components inside LCD monitors like CRTs, so there will not be excessive radioactive rays caused by high voltage. The display area of ​​the LCD monitor itself does not radiate at all, only a small amount of electromagnetic waves from the drive circuit. As long as the shell is strictly sealed, EMI (Electromagnetic Interference, electromagnetic interference), so its radiation index is generally lower than that of CRT; and LCD has a large visible area. LCD controls the state of liquid crystal molecules through electrodes on the display screen to achieve display purposes. Even if the screen is enlarged, its volume will not increase proportionally (only the size is increased without increasing the thickness, so many products provide wall-mounting function, which allows users to save more space), and it is much lighter in weight than traditional displays with the same display area. The weight of LCD TV is about 1 / 3 of that of traditional TV, so LCD is also called cold display or environmentally friendly display. Currently, LCD is developing towards higher resolution, higher display quality and larger size.

[0063] See also Figure 1 , Figure 1 Schematic diagram of the structure of the display panel provided in the embodiment of the present application. TFT (Thin Film Transistor) type LCD is usually driven by Line-by-Line (progressive scanning), such as Figure 1As shown, the scanning signal of the n-1th scanning line 101 is Gn-1, the scanning signal of the nth scanning line 101 is Gn, and the scanning signal of the n+1th scanning line 101 is Gn+1. When the scanning signal of the nth scanning line 101 is a conduction voltage (for example, 25V), the switch tube 11 in the nth pixel unit P' is turned on, and the data line 102 writes the data voltage into the pixel unit P' of this row through the turned-on switch tube 11. Specifically, each pixel unit P' includes a switch tube 11, a liquid crystal capacitor Clc, and a storage capacitor Cst, wherein one end of the storage capacitor Cst and the liquid crystal capacitor is a pixel electrode 12 and the other end is a common electrode Vcom. In the present application, the voltage of the common electrode Vcom is referred to as a common voltage, also recorded as Vcom. Because the charging and discharging of liquid crystal is a capacitor structure, if it is driven by a DC (direct current) circuit, it will cause electrons to stay at the positive electrode / holes at the negative electrode for a long time, then residual charge will inevitably be generated at both ends of the capacitor, which will be reflected in the display screen as a residual image. In order to avoid this phenomenon, DC is generally changed to AC (alternating current). Liquid crystal works by relying on different voltages, different rotations, and different light transmittances at both ends. Specifically, the greater the voltage between the pixel electrode 12 and the common electrode Vcom, the higher the brightness of the pixel unit P'. Figure 1 As shown, when the scan signal of the n-th row scan line 101 is the on-voltage, the 1st column data line 102 provides a data voltage V1+ charged to the pixel unit P' located in the 1st column and the n-th row, the 2nd column data line 102 provides a data voltage V2- charged to the pixel unit P' located in the 2nd column and the n-th row, and the 3rd column data line 102 provides a data voltage V3+ charged to the pixel unit P' located in the 3rd column and the n-th row, wherein "±" represents the polarity of the data voltage, which is the voltage level of the data voltage compared to the common electrode Vcom, that is, if it is higher than the common electrode Vcom, the polarity is "+", and if it is lower than it, the polarity is "-". In this way, by charging each pixel unit P' with a data voltage of opposite polarity in adjacent frames, the afterimage in the picture can be eliminated.

[0064] Please also read Figure 2-3 , Figure 2 for Figure 1 A driving voltage waveform diagram of a pixel unit in; Figure 3 The following is a schematic diagram of the mechanism of head shake wrinkles. When the display panel is driven by AC, head shake wrinkles are likely to appear. Head shake wrinkles are alternating light and dark stripes that can only be observed by the user of the display panel when shaking the head. The mechanism of their generation is:

[0065] Since there is a parasitic capacitance Cgs between the gate and the source of the switch tube 11, when the scanning signal of the n-th scanning line 101 is finished, the scanning signal of the n-th scanning line 101 changes from the on voltage to the off voltage, and the pixel voltage Vs on the pixel electrode 12 is affected by the coupling effect of the parasitic capacitance Cgs and generates a data voltage jump amount ΔV. Figure 2 As shown, assuming that the on-voltage is a high level (e.g., 25V) and the off-voltage is a low level (e.g., -5V), when the polarity of the pixel voltage Vs received by the pixel unit P' is positive, the data voltage jump amount ΔV will pull down the pixel voltage Vs, thereby reducing the difference between the pixel voltage Vs and the common voltage Vcom, thereby making the display brightness of the pixel unit P' darker, and when the polarity of the pixel voltage Vs received by the pixel unit P' is negative, the data voltage jump amount ΔV will further pull down the pixel voltage Vs, thereby increasing the difference between the pixel voltage Vs and the common voltage Vcom, thereby making the display brightness of the pixel unit P' brighter. Since the brightness seen by the human eye when observing the picture is the average brightness level of multiple consecutive frames, under normal circumstances, the brightness difference between each pixel unit P' in the positive polarity frame and the negative polarity frame will be balanced. However, when the human eye shakes, it will probabilistically miss some frames. If the missed frames are mostly of a certain polarity, the brightness difference between the positive polarity frames and the negative polarity frames will change, resulting in head shaking wrinkles.

[0066] Specifically, Figure 3 As shown, when displaying the first frame period Fram1, the third frame period Fram3, the fifth frame period Fram5 and the seventh frame period Fram7, the data voltage applied to the pixel electrode is greater than the common voltage Vcom, and the difference between the two is the first difference. When displaying the second frame period Fram2, the fourth frame period Fram4, the sixth frame period Fram6 and the eighth frame period Fram8, the data voltage applied to the pixel electrode is less than the common voltage Vcom, and the difference between the two is the second difference, and the first difference is less than the second difference, that is, the brightness of the second frame period Fram2, the fourth frame period Fram4, the sixth frame period Fram6 and the eighth frame period Fram8 is greater than the brightness of the first frame period Fram1, the third frame period Fram3, the fifth frame period Fram5 and the seventh frame period Fram7. At this time, if the user shakes his head and misses the fourth frame period Fram4-the sixth frame period Fram6, then the user's eyes cannot observe the third frame image F3 and the seventh frame image F7 for good averaging. In this case, the user will observe the shaking head wrinkle phenomenon.

[0067] Please also read Figures 4 to 8 , Figure 4 A schematic diagram of a first structure of a display device provided in an embodiment of the present application; Figure 5 A second structural schematic diagram of a display device provided in an embodiment of the present application; Figure 6 for Figure 4-5 A driving voltage waveform diagram of a pixel unit in; Figure 7 for Figure 4-5 A timing diagram of a scanning signal of a first row of pixel units in a display device in a preset period; Figure 8 for Figure 4-5 The brightness diagram of each frame of the display device when it is working is shown. In order to solve the problem that the existing LCD panel is prone to head shaking, the present application provides a pixel unit P, which includes a pixel electrode 12, a first switch tube T1 and a second switch tube T2.

[0068] The first switch tube T1 includes a first connection end, a second connection end and a control end. The first connection end of the first switch tube T1 is used to receive a data voltage, and the second connection end of the first switch tube T1 is electrically connected to the pixel electrode 12 .

[0069] The second switch tube T2 includes a first connection end, a second connection end and a control end. The first connection end of the second switch tube T2 is used to receive a data voltage, and the second connection end of the second switch tube T2 is electrically connected to the pixel electrode 12 .

[0070] The pixel unit P is displayed according to a preset period, and each of the preset periods includes X first-type frame periods and Y second-type frame periods, where X≥1 and Y≥1. The control end of the first switch tube T1 receives a first on-voltage in a partial period of each first-type frame period, so that the first switch tube T1 is turned on and transmits the received data voltage to the pixel electrode 12. The control end of the first switch tube T1 continues to receive a first off-voltage in each second-type frame period, so that the first switch tube T1 remains off in each second-type frame period. The control end of the second switch tube T2 continues to receive a second off-voltage in each first-type frame period, so that the second switch tube T2 remains off in each first-type frame period. The control end of the second switch tube T2 receives a second on-voltage in a partial period of each second-type frame period, so that the second switch tube T2 is turned on and transmits the received data voltage to the pixel electrode 12.

[0071] Among them, the first switch tube T1 is a switch tube that is turned on at a high level, the second switch tube T2 is a switch tube that is turned on at a low level, the first turn-on voltage and the second turn-off voltage are both high-level voltages, and the second turn-on voltage and the first turn-off voltage are both low-level voltages; or, the first switch tube T1 is a switch tube that is turned on at a low level, the second switch tube T2 is a switch tube that is turned on at a high level, the first turn-on voltage and the second turn-off voltage are both low-level voltages, and the second turn-on voltage and the first turn-off voltage are both high-level voltages.

[0072] The first switch tube T1 and the second switch tube T2 include but are not limited to thin film transistors (TFT), triodes, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. When the first switch tube T1 and the second switch tube T2 are thin film transistors, the first switch tube T1 is one of an N-type transistor and a P-type transistor, and the second switch tube T2 is the other of an N-type transistor and a P-type transistor.

[0073] For example, Figure 6 As shown, it is assumed that the first switch tube T1 is an N-type TFT, the second switch tube T2 is a P-type TFT, the parasitic capacitance between the gate and the source of the first switch tube T1 is Cgs1, the parasitic capacitance between the gate and the source of the second switch tube T2 is Cgs2, the first on-voltage and the second off-voltage are high-level voltages Vgh, the first off-voltage and the second on-voltage are low-level voltages Vgl, and Vgh>Vcom>Vgl. In each of the preset cycles, the number X of the first type of frame cycles and the number Y of the second type of frame cycles are both 2, such as Figure 8 As shown, in the first preset cycle, the first frame cycle Fram1 and the second frame cycle Fram2 are both the first type of frame cycles, the third frame cycle Fram3 and the fourth frame cycle Fram4 are both the second type of frame cycles, and in the second preset cycle, the fifth frame cycle Fram5 and the sixth frame cycle Fram6 are both the first type of frame cycles, and the seventh frame cycle Fram7 and the eighth frame cycle Fram8 are both the second type of frame cycles.

[0074] Then, in the first type of frame period, when the scanning signal Vg received by the control end of the first switch tube T1 changes from the first on-voltage to the first off-voltage, the parasitic capacitor Cgs1 generates a first data voltage jump amount ΔV1 for the pixel voltage Vs on the pixel electrode 12 in the pixel unit P, wherein the relationship between the first data voltage jump amount ΔV1 and the liquid crystal capacitor Clc of the pixel unit P, the storage capacitor Cst and the parasitic capacitor Cgs1 between the gate and the source of the first switch tube T1 is:

[0075] ΔV1=(Vgh-Vgl)*Cgs1 / (Cgs1+Cst+Clc)

[0076] When the polarity of the data voltage Vd received by the first connection end of the first switch tube T1 is positive, the first data voltage jump amount ΔV1 will pull down the pixel voltage Vs on the pixel electrode 12, thereby reducing the difference between the pixel voltage Vs and the common voltage Vcom, and further making the display brightness of the pixel unit P darker; when the polarity of the data voltage Vd received by the first connection end of the first switch tube T1 is negative, the first data voltage jump amount ΔV1 will further pull down the pixel voltage Vs on the pixel electrode 12, thereby increasing the difference between the pixel voltage Vs and the common voltage Vcom, and further making the display brightness of the pixel unit P brighter.

[0077] In the second type of frame period, when the scanning signal Vg received by the control end of the second switch tube T2 changes from the second on-voltage to the second off-voltage, the parasitic capacitor Cgs2 generates a second data voltage jump amount ΔV2 for the pixel voltage Vs on the pixel electrode 12 in the pixel unit P, wherein the relationship between the second data voltage jump amount ΔV2 and the liquid crystal capacitor Clc of the pixel unit P, the storage capacitor Cst, and the parasitic capacitor Cgs2 between the gate and the source of the second switch tube T2 is:

[0078] ΔV2=(Vgl-Vgh)*Cgs2 / (Cgs2+Cst+Clc)

[0079] When the polarity of the data voltage Vd received by the first connection end of the second switch tube T2 is positive, the second data voltage jump amount ΔV2 will further increase the pixel voltage Vs' on the pixel electrode 12, thereby increasing the difference between the pixel voltage Vs and the common voltage Vcom, thereby making the display brightness of the pixel unit P brighter; when the polarity of the pixel voltage Vs received by the first connection end of the second switch tube T2 is negative, the second data voltage jump amount ΔV2 will increase the pixel voltage Vs on the pixel electrode 12, thereby decreasing the difference between the pixel voltage Vs and the common voltage Vcom, thereby making the display brightness of the pixel unit P darker.

[0080] like Figure 8 As shown, since the first data voltage jump amount ΔV1>0 and the second data voltage jump amount ΔV2<0, in one cycle, the first data voltage jump amount ΔV1 and the second data voltage jump amount ΔV2 can at least partially offset each other. Thus, when the user's eyes shake and miss some frames, the difference between the brightness of the pixel unit P in the positive polarity frame and the brightness in the negative polarity frame will be reduced, thereby alleviating or even completely eliminating the head shake wrinkle problem.

[0081] The pixel unit P provided in the present application sets a first switch tube T1 and a second switch tube T2 which are both electrically connected to the pixel electrode 12, sets the first on-voltage of the first switch tube T1 and the second off-voltage of the second switch tube T2 to be the same level, sets the first off-voltage of the first switch tube T1 and the second on-voltage of the second switch tube T2 to be the same level, and allows the first switch tube T1 to work in a first frame period and remain in an off state in a second frame period, and allows the second switch tube T2 to work in a second frame period and remain in an off state in the first frame period, so that the first data voltage jump amount ΔV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump amount ΔV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 can be at least partially offset, which can alleviate or even completely eliminate the shaking head wrinkle problem.

[0082] In some embodiments, in each of the preset periods, the number X of the first type of frame periods is equal to the number Y of the second type of frame periods.

[0083] Thus, in each of the preset cycles, the offsetting portion of the first data voltage jump amount ΔV1 and the second data voltage jump amount ΔV2 is greater, and the effect of alleviating the shaking head wrinkles is better.

[0084] In some implementations, the pixel unit P is driven in a frame inversion manner, that is, the polarity of the data voltage Vd received by the pixel unit P in any two adjacent frame periods is opposite. In each of the preset periods, the number X of the first type of frame periods and the number Y of the second type of frame periods are even numbers.

[0085] In this way, in each of the preset cycles, the number of first-type frame cycles with positive polarity is equal to the number of first-type frame cycles with negative polarity, and the number of second-type frame cycles with positive polarity is also equal to the number of second-type frame cycles with negative polarity. The offsetting part of the first data voltage jump amount ΔV1 and the second data voltage jump amount ΔV2 is greater, and the effect of alleviating shake head wrinkles is better.

[0086] In some embodiments, in each of the preset periods, X first-type frame periods are arranged continuously, and Y second-type frame periods are arranged continuously.

[0087] In this way, frequent switching of the working states of the first switch tube T1 and the second switch tube T2 can be avoided, the control logic can be simplified, and the loss can be reduced.

[0088] like Figure 4 As shown, in some embodiments, the first switch tube T1 and the second switch tube T2 are respectively located on opposite sides of the pixel electrode 12, and the first connection end of the first switch tube T1 and the first connection end of the second switch tube T2 are respectively electrically connected to different data lines 102.

[0089] like Figure 5 As shown, in some embodiments, the first switch tube T1 and the second switch tube T2 are both located on the same side of the pixel electrode 12 , and the first connection end of the first switch tube T1 and the first connection end of the second switch tube T2 are electrically connected to the same data line 102 .

[0090] In some embodiments, a capacitance value of a parasitic capacitor Cgs1 between the gate and the source of the first switch tube T1 is equal to a capacitance value of a parasitic capacitor Cgs2 between the gate and the source of the second switch tube T2 .

[0091] In this way, it can be ensured that the first data voltage jump amount ΔV1 and the second data voltage jump amount ΔV2 are completely offset, thereby completely eliminating the shaking head wrinkle problem.

[0092] Please refer again Figure 4-5 Based on the same inventive concept, the present application also provides a display panel 100, wherein the display panel 100 includes N rows of pixel units P, N first scan lines Scan, and N second scan lines Scan'.

[0093] Wherein, the pixel unit P is the pixel unit P described in any of the above embodiments.

[0094] The N first scan lines Scan are electrically connected to the N rows of pixel units P in a one-to-one correspondence, and each of the first scan lines Scan is electrically connected to the control end of the first switch tube T1 in the corresponding row of pixel units P. The N first scan lines Scan are used to output a first on-voltage to the control end of the first switch tube T1 in the N rows of pixel units P in sequence according to a preset timing in each of the first-type frame periods, so as to control the first switch tubes T1 in the N rows of pixel units P to be turned on row by row, and to keep outputting a first off-voltage to the control end of the first switch tube T1 in the N rows of pixel units P in each of the second-type frame periods, so as to control the first switch tubes T1 in the N rows of pixel units P to remain off in each of the second-type frame periods.

[0095] The N second scan lines Scan' are electrically connected to the N rows of pixel units P in a one-to-one correspondence, and each of the second scan lines Scan' is electrically connected to the control end of the second switch tube T2 in the corresponding row of pixel units P. The N second scan lines Scan' are used to keep outputting a second turn-off voltage to the control end of the second switch tube T2 in the N rows of pixel units P in each of the first-type frame periods, so as to control the second switch tubes T2 in the N rows of pixel units P to remain turned off in each of the first-type frame periods, and to output a second turn-on voltage to the control end of the second switch tube T2 in the N rows of pixel units P in sequence according to a preset timing in each of the second-type frame periods, so as to control the second switch tubes T2 in the N rows of pixel units P to be turned on row by row.

[0096] The display panel 100 provided in the present application, by setting a first switch tube T1 and a second switch tube T2 electrically connected to the pixel electrode 12 in the pixel unit P, setting the first on-voltage of the first switch tube T1 and the second off-voltage of the second switch tube T2 to be the same level, the first off-voltage of the first switch tube T1 and the second on-voltage of the second switch tube T2 to be the same level, and allowing the first switch tube T1 to work in a first-type frame period and remain in an off state in a second-type frame period, and allowing the second switch tube T2 to work in a second-type frame period and remain in an off state in the first-type frame period, so that the first data voltage jump amount ΔV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump amount ΔV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 can be at least partially offset, which can alleviate or even completely eliminate the shaking head wrinkle problem.

[0097] Based on the same inventive concept, the present application further provides a display device 1 , which includes a row driving module 200 and the above-mentioned display panel 100 , wherein the row driving module 200 is electrically connected to the display panel 100 .

[0098] The row driver module 200 is used to provide a first on-voltage or a first off-voltage to each first scan line Scan, and to provide a second on-voltage or a second off-voltage to each second scan line Scan'. In some embodiments, the row driver module 200 may include a GOA (Gate Driven on Array), which may be disposed in the display panel 100.

[0099] The display device 1 provided in the present application, by setting a first switch tube T1 and a second switch tube T2 electrically connected to the pixel electrode 12 in the pixel unit P, setting the first on-voltage of the first switch tube T1 and the second off-voltage of the second switch tube T2 to be the same level, the first off-voltage of the first switch tube T1 and the second on-voltage of the second switch tube T2 to be the same level, and allowing the first switch tube T1 to work in a first-type frame period and remain in an off state in a second-type frame period, and allowing the second switch tube T2 to work in a second-type frame period and remain in an off state in the first-type frame period, so that the first data voltage jump amount ΔV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump amount ΔV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 can be at least partially offset, which can alleviate or even completely eliminate the shaking head wrinkle problem.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A pixel unit, characterized in that: The pixel unit comprises: Pixel electrode; A first switch tube, comprising a first connection end, a second connection end and a control end, wherein the first connection end of the first switch tube is used to receive a data voltage, and the second connection end of the first switch tube is electrically connected to the pixel electrode; and A second switch tube, comprising a first connection end, a second connection end and a control end, wherein the first connection end of the second switch tube is used to receive a data voltage, and the second connection end of the second switch tube is electrically connected to the pixel electrode; The pixel unit is displayed according to a preset cycle, each of the preset cycles includes X first-type frame cycles and Y second-type frame cycles, X≥1, Y≥1; the control end of the first switch tube receives a first on-voltage in a partial period of each first-type frame cycle, so that the first switch tube is turned on and transmits the received data voltage to the pixel electrode, and the control end of the first switch tube continues to receive a first off-voltage in each second-type frame cycle, so that the first switch tube remains off in each second-type frame cycle; the control end of the second switch tube continues to receive a second off-voltage in each first-type frame cycle, so that the second switch tube remains off in each first-type frame cycle, and the control end of the second switch tube receives a second on-voltage in a partial period of each second-type frame cycle, so that the second switch tube is turned on and transmits the received data voltage to the pixel electrode; Among them, the first switch tube is a switch tube that is turned on at a high level, the second switch tube is a switch tube that is turned on at a low level, the first turn-on voltage and the second turn-off voltage are both high-level voltages, and the second turn-on voltage and the first turn-off voltage are both low-level voltages; or, the first switch tube is a switch tube that is turned on at a low level, the second switch tube is a switch tube that is turned on at a high level, the first turn-on voltage and the second turn-off voltage are both low-level voltages, and the second turn-on voltage and the first turn-off voltage are both high-level voltages.

2. The pixel unit according to claim 1, characterized in that: In each of the preset periods, the number X of the first type of frame periods is equal to the number Y of the second type of frame periods.

3. The pixel unit according to claim 2, characterized in that: In each of the preset periods, the number X of the first-type frame periods and the number Y of the second-type frame periods are even numbers.

4. The pixel unit according to claim 3, characterized in that: In each of the preset periods, X first-type frame periods are arranged continuously, and Y second-type frame periods are arranged continuously.

5. The pixel unit according to claim 1, characterized in that: The first switch tube and the second switch tube are respectively located at two opposite sides of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are respectively electrically connected to different data lines.

6. The pixel unit according to claim 1, characterized in that: The first switch tube and the second switch tube are both located at the same side of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are electrically connected to the same data line.

7. The pixel unit according to claim 1, characterized in that: The first switch tube is one of an N-type transistor and a P-type transistor, and the second switch tube is the other of the N-type transistor and the P-type transistor.

8. The pixel unit according to claim 7, characterized in that: The capacitance value of the parasitic capacitor between the gate and the source of the first switch tube is equal to the capacitance value of the parasitic capacitor between the gate and the source of the second switch tube.

9. A display panel, characterized in that: The display panel comprises: N rows of pixel units, wherein the pixel units are the pixel units according to any one of claims 1 to 8; N first scan lines are electrically connected to the N rows of pixel units in a one-to-one correspondence, and each of the first scan lines is electrically connected to the control end of the first switch tube in the corresponding row of pixel units; the N first scan lines are used to output a first on-voltage to the control end of the first switch tube in the N rows of pixel units in sequence according to a preset timing in each of the first-type frame periods, so as to control the first switch tubes in the N rows of pixel units to be turned on row by row, and to keep outputting a first off-voltage to the control end of the first switch tube in the N rows of pixel units in each of the second-type frame periods, so as to control the first switch tubes in the N rows of pixel units to remain off during the second-type frame periods; and N second scan lines are electrically connected to the N rows of pixel units in a one-to-one correspondence, and each of the second scan lines is electrically connected to the control end of the second switch tube in the corresponding row of pixel units; the N second scan lines are used to keep outputting a second turn-off voltage to the control end of the second switch tube in the N rows of pixel units in each of the first-type frame periods, so as to control the second switch tubes in the N rows of pixel units to remain turned off during the first-type frame periods, and in each of the second-type frame periods, output a second turn-on voltage to the control end of the second switch tube in the N rows of pixel units in sequence according to a preset timing, so as to control the second switch tubes in the N rows of pixel units to be turned on row by row.

10. A display device, characterized in that: The display device comprises: A row driver module; and The display panel as claimed in claim 9, wherein the row driving module is electrically connected to the display panel.

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