Pixel unit, display panel and display device

Abstract

The application provides a pixel unit, a display panel and a display device. The pixel unit comprises a pixel electrode, a first switch tube and a second switch tube. A first connection end of the first switch tube is used for receiving a data voltage, and a second connection end is electrically connected to the pixel electrode. A first connection end of the second switch tube is used for receiving the data voltage, and a second connection end is electrically connected to the pixel electrode. The pixel unit displays according to a preset period, each preset period comprises X first type frame periods and Y second type frame periods. The first switch tube is turned on in part of each first type frame period and is kept off in each second type frame period. The second switch tube is kept off in each first type frame period and is turned on in part of each second type frame period. The pixel unit makes a first data voltage jump variable generated by the first switch tube and a second data voltage jump variable generated by the second switch tube at least partially offset, so that the problem of wobble lines can be alleviated or even completely eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel unit, a display panel and a display device. BACKGROUND

[0002] When the LCD (Liquid Crystal Display) panel displays, the pixel driving circuit in the display panel inputs the on voltage through the scanning line to turn on the switch tube for charging the pixel unit, the data line inputs the data voltage to the first end of the pixel capacitor Clc and the storage capacitor Cst through the on switch tube, and the common voltage of the common voltage end is directly input to the second end of the pixel capacitor Clc and the storage capacitor Cst, so that the pixel capacitor Clc and the storage capacitor Cst are charged according to the data voltage and the common voltage, thereby changing the deflection degree of the liquid crystal.

[0003] However, since the switch tube in the pixel unit itself has a parasitic capacitance, when the voltage on the scanning line jumps from the on voltage to the off voltage (also known as the cutoff voltage), the data voltage written to the first end of the pixel capacitor Clc and the storage capacitor Cst will be pulled down due to the coupling effect of the parasitic capacitance, thereby causing the brightness of the pixel unit to differ at different polarities, and when the user observes the display screen by shaking his head, the frame is easily lost and the head shake lines appear, which affects the display effect of the screen and the user experience. SUMMARY

[0004] Therefore, the main purpose of the present application is to provide a pixel unit, a display panel and a display device, which aims to solve the problem that the existing LCD panel is prone to head shake lines.

[0005] To achieve the above object, the first aspect of the present application provides a pixel unit, which comprises a pixel electrode, a first switch tube and a second switch tube. The first switch tube comprises a first connection end, a second connection end and a control end, the first connection end of the first switch tube is used for receiving a data voltage, and the second connection end of the first switch tube is electrically connected to the pixel electrode; the second switch tube comprises a first connection end, a second connection end and a control end, the first connection end of the second switch tube is used for receiving a data voltage, and the second connection end of the second switch tube is electrically connected to the pixel electrode; the pixel unit displays according to a preset period, each of the preset periods comprises X first type frame periods and Y second type frame periods, X≥1, Y≥1; the control end of the first switch tube receives a first conduction voltage in part of each of the first type frame periods, so that the first switch tube is turned on and transmits the received data voltage to the pixel electrode, and the control end of the first switch tube keeps receiving a first turn-off voltage in each of the second type frame periods, so that the first switch tube keeps turned off in each of the second type frame periods; the control end of the second switch tube keeps receiving a second turn-off voltage in each of the first type frame periods, so that the second switch tube keeps turned off in each of the first type frame periods, and the control end of the second switch tube receives a second conduction voltage in part of each of the second type frame periods, so that the second switch tube is turned on and transmits the received data voltage to the pixel electrode; wherein the first switch tube is a high-level conduction switch tube, the second switch tube is a low-level conduction switch tube, the first conduction voltage and the second turn-off voltage are high-level voltages, and the second conduction voltage and the first turn-off voltage are low-level voltages; or, the first switch tube is a low-level conduction switch tube, the second switch tube is a high-level conduction switch tube, the first conduction voltage and the second turn-off voltage are low-level voltages, and the second conduction voltage and the first turn-off voltage are high-level voltages.

[0006] The pixel unit provided by the present application can at least partially offset the first data voltage jump value generated by the parasitic capacitance of the first switch tube and the second data voltage jump value generated by the parasitic capacitance of the second switch tube by setting the first switch tube and the second switch tube which are both electrically connected to the pixel electrode, setting the first conduction voltage of the first switch tube and the second turn-off voltage of the second switch tube to be the same level, setting the first turn-off voltage of the first switch tube and the second conduction voltage of the second switch tube to be the same level, and making the first switch tube work in the first type frame period and keep turned off in the second type frame period, and making the second switch tube work in the second type frame period and keep turned off in the first type frame period, so as to alleviate or even completely eliminate the wobble line problem.

[0007] In some embodiments, in each of the preset periods, the number X of the first type of frame periods is equal to the number Y of the second type of frame periods.

[0008] In some embodiments, in each of the preset periods, the number X of the first type of frame periods and the number Y of the second type of frame periods are even numbers.

[0009] In some embodiments, in each of the preset periods, the X first type of frame periods are arranged continuously, and the Y second type of frame periods are arranged continuously.

[0010] In some embodiments, the first switch tube and the second switch tube are respectively located on opposite sides of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are respectively electrically connected to different data lines.

[0011] In some embodiments, the first switch tube and the second switch tube are both located on the same side of the pixel electrode, and the first connection end of the first switch tube and the first connection end of the second switch tube are electrically connected to the same data line.

[0012] In some embodiments, the first switch tube is one of an N-type transistor and a P-type transistor, and the second switch tube is the other one of the N-type transistor and the P-type transistor.

[0013] In some embodiments, the parasitic capacitance between the gate and the source of the first switch tube has a capacitance value equal to that of the parasitic capacitance between the gate and the source of the second switch tube.

[0014] The second aspect of the present application also provides a display panel, comprising N rows of pixel units, N first scan lines and N second scan lines. The pixel unit is the pixel unit of the first aspect described above; the N first scan lines are electrically connected to the N rows of pixel units one by one, and the control end of the first switch tube in each corresponding row of pixel units is electrically connected to each first scan line; the N first scan lines are used for outputting a first conduction voltage to the control end of the first switch tube in the N rows of pixel units in a preset time sequence in each first type frame period, so as to control the first switch tube in the N rows of pixel units to be turned on row by row, and a first turn-off voltage is kept to be output to the control end of the first switch tube in the N rows of pixel units in each second type frame period, so as to control the first switch tube in the N rows of pixel units to keep off in the second type frame period; the N second scan lines are electrically connected to the N rows of pixel units one by one, and the control end of the second switch tube in each corresponding row of pixel units is electrically connected to each second scan line; the N second scan lines are used for keeping a second turn-off voltage to be output to the control end of the second switch tube in the N rows of pixel units in each first type frame period, so as to control the second switch tube in the N rows of pixel units to keep off in the first type frame period, and a second conduction voltage is output to the control end of the second switch tube in the N rows of pixel units in a preset time sequence in each second type frame period, so as to control the second switch tube in the N rows of pixel units to be turned on row by row.

[0015] The third aspect of the present application also provides a display device, comprising a row driving module and the display panel of the second aspect described above, and the row driving module is electrically connected to the display panel.

[0016] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The structural schematic diagram of the display panel provided by the embodiment of the present application;

[0018] Figure 2 The driving voltage waveform diagram of the pixel unit in Figure 1

[0019] Figure 3 The schematic diagram of the generation mechanism of the shaking head pattern;

[0020] Figure 4 The first structural schematic diagram of the display device provided by the embodiment of the present application;

[0021] Figure 5 The second structural schematic diagram of the display device provided by the embodiment of the present application;​

[0022] Figure 6 For Figures 4-5 the driving voltage waveform diagram of the pixel unit in the display device shown in FIG. 1;

[0023] Figure 7 For Figures 4-5 the timing diagram of the scanning signal of the first row of pixel units in the display device shown in FIG. 1 in a preset period;

[0024] Figure 8 For Figures 4-5 the luminance schematic diagram of each frame picture of the display device shown in FIG. 1 when working.

[0025] The following is the description of the reference signs:

[0026] Display device 1

[0027] Display panel 100

[0028] Row driving module 200

[0029] Pixel unit P, P'

[0030] Switching tube 11

[0031] Pixel electrode 12

[0032] First switching tube T1

[0033] Second switching tube T2

[0034] First scanning line Scan

[0035] Second scanning line Scan'

[0036] Liquid crystal capacitor Clc

[0037] Storage capacitor Cst

[0038] Parasitic capacitor Cgs

[0039] Common electrode Vcom

[0040] Scanning line 101

[0041] Data line 102

[0042] Data voltage Vd

[0043] Pixel voltage Vs, Vs'

[0044] Scanning signal Vg

[0045] Data voltage jump ΔV

[0046] First data voltage jump ΔV1

[0047] Second data voltage jump amount ΔV2

[0048] High-level voltage Vgh

[0049] Low-level voltage Vgl

[0050] First frame period Fram1

[0051] Second frame period Fram2

[0052] Third frame period Fram3

[0053] Fourth frame period Fram4

[0054] Fifth frame period Fram5

[0055] Sixth frame period Fram6

[0056] Seventh frame period Fram7

[0057] Eighth frame period Fram8

[0058] The following detailed description will further describe the present application with reference to the above drawings. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0060] In addition, the terms "first", "second", and the like in the description of the present application are used to distinguish similar objects, and do not necessarily indicate a particular order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0061] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0062] A big advantage of liquid crystal television compared with traditional CRT (Cathode Ray Tube) television and plasma television is power saving. Liquid crystal has only half of the power consumption of CRT of the same size, and is much lower than plasma. Compared with traditional CRT, liquid crystal is also better in environmental protection. This is because there is no high-voltage component inside the liquid crystal display, so it is not prone to excessive radiation caused by high voltage. The display area of the liquid crystal display itself has no radiation. Only a small amount of electromagnetic waves comes from the driving circuit. As long as the shell is strictly sealed, EMI (Electromagnetic Interference) can be reduced, so the radiation index is generally lower than that of CRT. In addition, the liquid crystal display has a large visible area. The liquid crystal display controls the state of liquid crystal molecules through electrodes on the display screen to achieve the purpose of display. Even if the screen is enlarged, the volume will not increase in proportion (only the size increases, not the thickness, so many products provide a wall hanging function, which can save space for users). Moreover, the weight of the liquid crystal display is much lighter than that of the traditional display of the same display area. The weight of the liquid crystal television is about 1 / 3 of that of the traditional television. Therefore, the liquid crystal display is also called a cold display or an environmentally friendly display. At present, LCD is developing towards higher resolution, higher display quality and larger size.

[0063] Please refer to Figure 1 , Figure 1 The structural diagram of the display panel provided by the embodiment of the present application is shown. The TFT (Thin Film Transistor, i.e. thin film transistor) type LCD usually adopts a Line-by-Line (line-by-line scanning) driving mode, as shown in Figure 1As shown, the scanning signal of the n-1th row scanning line 101 is Gn-1, the scanning signal of the n th row scanning line 101 is Gn, and the scanning signal of the n+1th row scanning line 101 is Gn+1. When the scanning signal of the n th row scanning line 101 is the on voltage (for example, 25V), the switch tube 11 in the n th row pixel unit P' is opened, and the data line 102 writes the data voltage into the row pixel unit P' through the on switch tube 11. Specifically, each pixel unit P' includes a switch tube 11, a liquid crystal capacitor Clc, and a storage capacitor Cst, wherein one end of the storage capacitor Cst and the liquid crystal capacitor is the pixel electrode 12 and the other end is the common electrode Vcom. In this application, the voltage of the common electrode Vcom is called the common voltage, also denoted as Vcom. Because the liquid crystal charging and discharging is a capacitor architecture, if a DC (direct current) circuit is used for driving, the electrons will stay in the positive electrode and the holes will stay in the negative electrode for a long time, and the residual charge will inevitably be generated at both ends of the capacitor, which will cause the display screen to have a residual image. In order to avoid this phenomenon, DC is generally changed to AC (alternating current), and the liquid crystal works by relying on the difference in voltage between the two ends, the difference in rotation, and the difference in light transmittance. Specifically, the greater the voltage between the pixel electrode 12 and the common electrode Vcom, the higher the brightness of the pixel unit P'. Figure 1 As shown, when the scanning signal of the n th row scanning line 101 is the on voltage, the data voltage provided by the 1st column data line 102 to the pixel unit P' located in the 1st column and the n th row is V1+, the data voltage provided by the 2nd column data line 102 to the pixel unit P' located in the 2nd column and the n th row is V2-, and the data voltage provided by the 3rd column data line 102 to the pixel unit P' located in the 3rd column and the n th row is V3+. Here, "+" and "-" represent the polarity of the data voltage, which is the voltage of the data voltage relative to the common electrode Vcom, that is, if the data voltage is higher than the common electrode Vcom, the polarity is "+", and if the data voltage is lower than the common electrode Vcom, the polarity is "-". In this way, by charging each pixel unit P' with opposite polarity data voltage in adjacent frames, the residual image in the picture can be eliminated.

[0064] Please refer to Figures 2-3 , Figure 2 for the driving voltage waveform diagram of the pixel unit in Figure 1 . Figure 3 is a schematic diagram of the generation mechanism of the wobble pattern. When the display panel is driven in an alternating current mode, a wobble pattern is likely to appear. The wobble pattern is a kind of stripe pattern with alternating light and dark that can only be observed by the user of the display panel when the user shakes his head. The generation mechanism is as follows:

[0065] Since there is a parasitic capacitance Cgs between the gate and the source of the switch tube 11, when the scanning of the nth row scanning line 101 ends, the scanning signal of the nth row scanning line 101 changes from the on voltage to the off voltage, and the pixel voltage Vs on the pixel electrode 12 will be affected by the coupling of the parasitic capacitance Cgs to generate a data voltage jump ΔV. As shown in Figure 2 , assuming that the on voltage is high (for example, 25V) and the off voltage is low (for example, -5V), when the polarity of the pixel voltage Vs received by the pixel unit P' is positive, the data voltage jump ΔV will lower the pixel voltage Vs, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes smaller, and in turn, the display brightness of the pixel unit P' becomes darker, and when the polarity of the pixel voltage Vs received by the pixel unit P' is negative, the data voltage jump ΔV will further lower the pixel voltage Vs, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes larger, and in turn, the display brightness of the pixel unit P' becomes brighter. Since the brightness observed by the human eye when observing the picture is the average brightness level of continuous multiple frames, under normal circumstances, the brightness difference between the positive polarity frame and the negative polarity frame of each pixel unit P' will be balanced out. However, when the human eye is shaking, some frames will be missed by probability, and if the missed frames are more in one polarity, the brightness difference between the positive polarity frame and the negative polarity frame will be changed, and thus the wobble lines appear.

[0066] Specifically, as shown in Figure 3 , when the first frame period Fram1, the third frame period Fram3, the fifth frame period Fram5 and the seventh frame period Fram7 are displayed, the data voltage applied on the pixel electrode is greater than the common voltage Vcom, and the difference between the two is the first difference, when the second frame period Fram2, the fourth frame period Fram4, the sixth frame period Fram6 and the eighth frame period Fram8 are displayed, the data voltage applied on the pixel electrode is less than the common voltage Vcom, and the difference between the two is the second difference, and the first difference is less than the second difference, that is, the brightness of the second frame period Fram2, the fourth frame period Fram4, the sixth frame period Fram6 and the eighth frame period Fram8 is greater than the brightness of the first frame period Fram1, the third frame period Fram3, the fifth frame period Fram5 and the seventh frame period Fram7. At this time, if the user shakes his head and misses the fourth frame period Fram4 to the sixth frame period Fram6, the eyes of the user cannot observe the third frame image F3 and the seventh frame image F7 well, and in this case, the user will observe the wobble lines.

[0067] Please refer to Figures 4-8 , Figure 4 , the first structure schematic diagram of the display device provided by the embodiment of the present application;Figure 5 A second structural schematic diagram of a display device provided by an embodiment of the present application; Figure 6 A driving voltage waveform diagram of a pixel unit in the display device shown in Figures 4-5 A driving voltage waveform diagram of a pixel unit in the display device shown in Figure 7 A timing diagram of a scan signal of a first row of pixel units in the display device shown in Figures 4-5 A timing diagram of a scan signal of a first row of pixel units in the display device shown in Figure 8 A timing diagram of a scan signal of a first row of pixel units in the display device shown in Figures 4-5 A luminance schematic diagram of each frame of the display device shown in operation. In order to solve the problem that the existing LCD panel is prone to wobble lines, the present application provides a pixel unit P, which comprises a pixel electrode 12, a first switch tube T1 and a second switch tube T2.

[0068] The first switch tube T1 comprises a first connection end, a second connection end and a control end, the first connection end of the first switch tube T1 is configured to receive a data voltage, and the second connection end of the first switch tube T1 is electrically connected to the pixel electrode 12.

[0069] The second switch tube T2 comprises a first connection end, a second connection end and a control end, the first connection end of the second switch tube T2 is configured to receive a data voltage, and the second connection end of the second switch tube T2 is electrically connected to the pixel electrode 12.

[0070] The pixel unit P displays according to a preset period, each of the preset periods comprises X first type frame periods and Y second type frame periods, X≥1, Y≥1. The control end of the first switch tube T1 receives a first conduction voltage in part of each of the first type frame periods, so that the first switch tube T1 is turned on and transmits the received data voltage to the pixel electrode 12, and the control end of the first switch tube T1 receives a first turn-off voltage in each of the second type frame periods, so that the first switch tube T1 is turned off in each of the second type frame periods. The control end of the second switch tube T2 receives a second turn-off voltage in each of the first type frame periods, so that the second switch tube T2 is turned off in each of the first type frame periods, and the control end of the second switch tube T2 receives a second conduction voltage in part of each of the second type frame periods, so that the second switch tube T2 is turned on and transmits the received data voltage to the pixel electrode 12.

[0071] The first switch tube T1 is a switch tube that is turned on at a high level, the second switch tube T2 is a switch tube that is turned on at a low level, the first turn-on voltage and the second turn-off voltage are both high-level voltages, and the second turn-on voltage and the first turn-off voltage are both low-level voltages; or, the first switch tube T1 is a switch tube that is turned on at a low level, the second switch tube T2 is a switch tube that is turned on at a high level, the first turn-on voltage and the second turn-off voltage are both low-level voltages, and the second turn-on voltage and the first turn-off voltage are both high-level voltages.

[0072] The first switch transistor T1 and the second switch transistor T2 include, but are not limited to, thin film transistors (TFTs), triodes, MOSFETs (metal oxide semiconductor field effect transistors), and the like. When the first switch transistor T1 and the second switch transistor T2 are thin film transistors, the first switch transistor T1 is one of an N-type transistor and a P-type transistor, and the second switch transistor T2 is the other of the N-type transistor and the P-type transistor.

[0073] For example, Figure 6 As shown, it is assumed that the first switch transistor T1 is an N-type TFT, the second switch transistor T2 is a P-type TFT, the parasitic capacitance between the gate and source of the first switch transistor T1 is Cgs1, the parasitic capacitance between the gate and source of the second switch transistor T2 is Cgs2, the first on-voltage and the second off-voltage are a high-level voltage Vgh, the first off-voltage and the second on-voltage are a low-level voltage Vgl, and Vgh>Vcom>Vgl. In each of the preset periods, the number X of the first-type frame periods and the number Y of the second-type frame periods are both 2, as shown in FIG. Figure 8 As shown, in the first preset period, the first frame period Fram1 and the second frame period Fram2 are both the first type of frame periods, the third frame period Fram3 and the fourth frame period Fram4 are both the second type of frame periods, and in the second preset period, the fifth frame period Fram5 and the sixth frame period Fram6 are both the first type of frame periods, and the seventh frame period Fram7 and the eighth frame period Fram8 are both the second type of frame periods.

[0074] So, in the first type of frame period, when the control end of the first switch tube T1 receives a scanning signal Vg changing from a first on-voltage to a first off-voltage, the parasitic capacitance Cgs1 will generate a first data voltage jump ΔV1 on the pixel voltage Vs on the pixel electrode 12 in the pixel unit P, wherein the first data voltage jump ΔV1 has a relationship with the liquid crystal capacitance Clc, the storage capacitance Cst and the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 as follows:

[0075] ΔV1 = (Vgh-Vgl) * Cgs1 / (Cgs1 + Cst + Clc)

[0076] When the polarity of the data voltage Vd received by the first connection end of the first switch tube T1 is positive, the first data voltage jump ΔV1 will pull down the pixel voltage Vs on the pixel electrode 12, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes smaller, and then the display brightness of the pixel unit P becomes dark; when the polarity of the data voltage Vd received by the first connection end of the first switch tube T1 is negative, the first data voltage jump ΔV1 will further pull down the pixel voltage Vs on the pixel electrode 12, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes larger, and then the display brightness of the pixel unit P becomes bright.

[0077] In the second type of frame period, when the control end of the second switch tube T2 receives a scanning signal Vg changing from a second on-voltage to a second off-voltage, the parasitic capacitance Cgs2 will generate a second data voltage jump ΔV2 on the pixel voltage Vs on the pixel electrode 12 in the pixel unit P, wherein the second data voltage jump ΔV2 has a relationship with the liquid crystal capacitance Clc, the storage capacitance Cst and the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 as follows:

[0078] ΔV2 = (Vgl-Vgh) * Cgs2 / (Cgs2 + Cst + Clc)

[0079] When the first connection end of the second switch tube T2 receives a data voltage Vd with a positive polarity, the second data voltage jump variable AV2 further pulls up the pixel voltage Vs' on the pixel electrode 12, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes larger, and in turn, the display brightness of the pixel unit P is biased to be brighter; when the first connection end of the second switch tube T2 receives a pixel voltage Vs with a negative polarity, the second data voltage jump variable AV2 pulls up the pixel voltage Vs on the pixel electrode 12, so that the difference between the pixel voltage Vs and the common voltage Vcom becomes smaller, and in turn, the display brightness of the pixel unit P is biased to be dimmer.

[0080] As shown in FIG. 1, because the first data voltage jump variable AV1>0 and the second data voltage jump variable AV2<0, in one period, the first data voltage jump variable AV1 and the second data voltage jump variable AV2 can at least partially offset each other, so that when the user's eyes shake and miss some frames, the difference between the brightness of the pixel unit P in the positive polarity frame and the brightness in the negative polarity frame will be reduced, and in turn, the problem of wobble lines can be alleviated or even completely eliminated. Figure 8

[0081] The pixel unit P provided in the present application can at least partially offset the first data voltage jump variable AV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump variable AV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 by setting the first switch tube T1 and the second switch tube T2 which are both electrically connected with the pixel electrode 12, setting the same level of the first turn-on voltage of the first switch tube T1 and the second turn-off voltage of the second switch tube T2 and the same level of the first turn-off voltage of the first switch tube T1 and the second turn-on voltage of the second switch tube T2, and letting the first switch tube T1 work in the first type of frame period and remain in the turn-off state in the second type of frame period, and letting the second switch tube T2 work in the second type of frame period and remain in the turn-off state in the first type of frame period, so that the problem of wobble lines can be alleviated or even completely eliminated.

[0082] In some embodiments, in each of the preset periods, the number X of the first type of frame period is equal to the number Y of the second type of frame period.

[0083] In this way, in each of the preset periods, the offset part of the first data voltage jump variable AV1 and the second data voltage jump variable AV2 is larger, and the effect of alleviating the wobble lines is better.

[0084] ​In some embodiments, the pixel units P are driven in a frame inversion manner, i.e., the pixel units P receive data voltages Vd with opposite polarities in any two adjacent frame periods. In each preset period, the number X of the first type of frame periods and the number Y of the second type of frame periods are even numbers.

[0085] Thus, in each preset period, the number of the first type of frame periods with positive polarity is equal to the number of the first type of frame periods with negative polarity, and the number of the second type of frame periods with positive polarity is equal to the number of the second type of frame periods with negative polarity. The offset parts of the first data voltage jump ΔV1 and the second data voltage jump ΔV2 are more, and the effect of alleviating the wobble lines is better.

[0086] In some embodiments, in each preset period, the X first type of frame periods are arranged continuously, and the Y second type of frame periods are arranged continuously.

[0087] Thus, the working state of the first switch tube T1 and the second switch tube T2 can be avoided from frequently switching, the control logic can be simplified, and the loss can be reduced.

[0088] As shown in Figure 4 some embodiments, the first switch tube T1 and the second switch tube T2 are located at opposite sides of the pixel electrode 12 respectively, and the first connection end of the first switch tube T1 and the first connection end of the second switch tube T2 are electrically connected to different data lines 102 respectively.

[0089] As shown in Figure 5 some embodiments, the first switch tube T1 and the second switch tube T2 are located at the same side of the pixel electrode 12, and the first connection end of the first switch tube T1 and the first connection end of the second switch tube T2 are electrically connected to the same data line 102.

[0090] In some embodiments, the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 has the same capacitance value as the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2.

[0091] Thus, it can be ensured that the first data voltage jump ΔV1 and the second data voltage jump ΔV2 are completely offset, so that the wobble line problem can be completely eliminated.

[0092] Please refer to Figures 4-5 again, based on the same inventive concept, the present application also provides a display panel 100, which comprises N rows of pixel units P, N first scan lines Scan, and N second scan lines Scan'.

[0093] The pixel unit P is the pixel unit P described in any of the above embodiments.

[0094] The N first scan lines Scan are in one-to-one correspondence with the N rows of pixel units P and are electrically connected thereto. Each first scan line Scan is electrically connected to the control end of the first switch tube T1 in the corresponding row of pixel units P. The N first scan lines Scan are configured to output a first conduction voltage to the control end of the first switch tube T1 in the N rows of pixel units P in a preset time sequence in each first type frame period, so as to control the first switch tube T1 in the N rows of pixel units P to be turned on row by row, and output a first turn-off voltage to the control end of the first switch tube T1 in the N rows of pixel units P in each second type frame period, so as to control the first switch tube T1 in the N rows of pixel units P to be kept off in each second type frame period.

[0095] The N second scan lines Scan' are in one-to-one correspondence with the N rows of pixel units P and are electrically connected thereto. Each second scan line Scan' is electrically connected to the control end of the second switch tube T2 in the corresponding row of pixel units P. The N second scan lines Scan' are configured to output a second turn-off voltage to the control end of the second switch tube T2 in the N rows of pixel units P in each first type frame period, so as to control the second switch tube T2 in the N rows of pixel units P to be kept off in each first type frame period, and output a second conduction voltage to the control end of the second switch tube T2 in the N rows of pixel units P in a preset time sequence in each second type frame period, so as to control the second switch tube T2 in the N rows of pixel units P to be turned on row by row.

[0096] The display panel 100 provided in the present application can at least partially offset the first data voltage jump ΔV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump ΔV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 by setting the first conduction voltage of the first switch tube T1 and the second turn-off voltage of the second switch tube T2 to be the same, setting the first turn-off voltage of the first switch tube T1 and the second conduction voltage of the second switch tube T2 to be the same, and making the first switch tube T1 work in the first type frame period and keep off in the second type frame period, and making the second switch tube T2 work in the second type frame period and keep off in the first type frame period, so as to alleviate or even completely eliminate the shaking line problem.

[0097] Based on the same inventive concept, the application further provides a display device 1 comprising a row driving module 200 and the display panel 100 described above, wherein the row driving module 200 is electrically connected with the display panel 100.

[0098] The row driving module 200 is configured to provide a first turn-on voltage or a first turn-off voltage to each first scan line Scan, and provide a second turn-on voltage or a second turn-off voltage to each second scan line Scan'.

[0099] The display device 1 provided by the application can at least partially offset the first data voltage jump ΔV1 generated by the parasitic capacitance Cgs1 between the gate and the source of the first switch tube T1 and the second data voltage jump ΔV2 generated by the parasitic capacitance Cgs2 between the gate and the source of the second switch tube T2 by setting the first turn-on voltage of the first switch tube T1 and the second turn-off voltage of the second switch tube T2 to be the same, setting the first turn-off voltage of the first switch tube T1 and the second turn-on voltage of the second switch tube T2 to be the same, and setting the first switch tube T1 to work in the first type of frame period and remain in the turn-off state in the second type of frame period, and setting the second switch tube T2 to work in the second type of frame period and remain in the turn-off state in the first type of frame period, so as to alleviate or even completely eliminate the shaking stripe problem.

[0100] Although the embodiments of the application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the application, and the scope of the application is defined by the claims and their equivalents.

Claims

1. A pixel unit, characterized in that: The pixel unit includes: pixel electrode; a first switching transistor, comprising a first connecting end, a second connecting end, and a control end, wherein the first connecting end of the first switching transistor is used to receive a data voltage, and the second connecting end of the first switching transistor is electrically connected to the pixel electrode; and a second switching tube, comprising a first connecting end, a second connecting end, and a control end, wherein the first connecting end of the second switching tube is used to receive a data voltage, and the second connecting end of the second switching tube is electrically connected to the pixel electrode; The pixel unit displays according to a preset period, each of the preset periods including X first-type frame periods and Y second-type frame periods, where X≥1 and Y≥1; the control terminal of the first switch tube receives a first on-voltage during a portion of each first-type frame period, so that the first switch tube is turned on and transmits the received data voltage to the pixel electrode; the control terminal of the first switch tube continues to receive a first off-voltage during each second-type frame period, so that the first switch tube remains off during each second-type frame period; the control terminal of the second switch tube continues to receive a second off-voltage during each first-type frame period, so that the second switch tube remains off during each first-type frame period; the control terminal of the second switch tube receives a second on-voltage during a portion of each second-type frame period, so that the second switch tube is turned on and transmits the received data voltage to the pixel electrode; In which, the first switching tube is a high-level conduction switching tube, the second switching tube is a low-level conduction switching tube, the first conduction voltage and the second turn-off voltage are both high-level voltages, and the second conduction voltage and the first turn-off voltage are both low-level voltages; or, the first switching tube is a low-level conduction switching tube, the second switching tube is a high-level conduction switching tube, the first conduction voltage and the second turn-off voltage are both low-level voltages, and the second conduction voltage and the first turn-off voltage are both high-level voltages.

2. The pixel unit according to claim 1, wherein: In each of the preset periods, the number X of the first-type frame periods is equal to the number Y of the second-type frame periods.

3. The pixel unit according to claim 2, wherein: In each of the preset periods, the number X of the first-type frame periods and the number Y of the second-type frame periods are even numbers.

4. The pixel unit according to claim 3, wherein: In each of the preset periods, X first-type frame periods are arranged continuously, and Y second-type frame periods are arranged continuously.

5. The pixel unit according to claim 1, wherein: The first switching tube and the second switching tube are respectively located on two opposite sides of the pixel electrode, and the first connection end of the first switching tube and the first connection end of the second switching tube are respectively electrically connected to different data lines.

6. The pixel unit according to claim 1, wherein: The first switching tube and the second switching tube are both located on the same side of the pixel electrode, and the first connection end of the first switching tube and the first connection end of the second switching tube are electrically connected to the same data line.

7. The pixel unit according to claim 1, wherein: The first switch tube is one of an N-type transistor and a P-type transistor, and the second switch tube is the other of the N-type transistor and the P-type transistor.

8. The pixel unit according to claim 7, wherein: The capacitance value of the parasitic capacitor between the gate and the source of the first switching tube is equal to the capacitance value of the parasitic capacitor between the gate and the source of the second switching tube.

9. A display panel, characterized in that: The display panel includes: N rows of pixel units, each of which is a pixel unit according to any one of claims 1 to 8; N first scan lines are electrically connected to the N rows of pixel units in a one-to-one correspondence, and each of the first scan lines is electrically connected to the control terminal of the first switch tube in the corresponding row of pixel units; the N first scan lines are used to output a first on-voltage to the control terminals of the first switch tubes in the N rows of pixel units in sequence according to a preset timing during each first-type frame period, so as to control the first switch tubes in the N rows of pixel units to be turned on row by row, and to keep outputting a first off-voltage to the control terminals of the first switch tubes in the N rows of pixel units during each second-type frame period, so as to control the first switch tubes in the N rows of pixel units to remain turned off during the second-type frame period; and N second scan lines are electrically connected to the N rows of pixel units in a one-to-one correspondence, and each of the second scan lines is electrically connected to the control end of the second switch tube in the corresponding row of pixel units; the N second scan lines are used to maintain outputting a second turn-off voltage to the control end of the second switch tube in the N rows of pixel units during each of the first-type frame periods, so as to control the second switch tubes in the N rows of pixel units to remain turned off during the first-type frame periods, and to output a second turn-on voltage to the control end of the second switch tube in the N rows of pixel units in sequence according to a preset timing during each of the second-type frame periods, so as to control the second switch tubes in the N rows of pixel units to be turned on row by row.

10. A display device, characterized in that: The display device includes: row driver module; and The display panel according to claim 9, wherein the row driver module is electrically connected to the display panel.

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