GOA unit, driving method and gate driving circuit

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a GOA unit, a driving method and a gate drive circuit. The GOA unit includes a pull-up module and an output module. The output module includes: a first transistor, a second transistor, a switching circuit and a pull-down circuit. The switching circuit is used to control the driving output end to output gate drive signals of different waveforms under the action of a first control signal; the pull-down circuit is used to lower the potential of the second connection end of the switching circuit and the second end of the second transistor under the action of the second control signal; wherein the phases of the first control signal and the second control signal are opposite; the switching circuit and the pull-down circuit in the present application respectively control the second transistor to output gate drive signals of different waveforms under the action of the first control signal and the second control signal input externally, so that the gate drive signals of different waveforms are compatible with the requirements of pre-charging in multiple inversion modes.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and particularly relates to a GOA unit, a driving method, and a gate driving circuit. Background Art

[0002] GOA (Gate Driver on Array) technology integrates the TFT (Thin Film Transistor) in the GOA drive circuit onto the array substrate, thereby eliminating the gate driver integrated circuit part originally set outside the array substrate, reducing product costs in terms of both material costs and process steps.

[0003] The GOA driving circuit includes multiple cascaded GOA units. Each GOA unit is usually provided with a pull-up module and an output module. The pull-up module is used to generate a Q-point voltage, and the output module is used to generate a stage transmission signal and a gate drive signal under the action of the Q-point voltage.

[0004] Currently, in order to improve the panel charging rate, the gate drive signal output by the GOA unit has an interlaced pre-charging effect, that is, the gate of the n-2 or n-1 row is turned on for charging at the same time as the n row, so that the n row has a longer charging time; however, the gate drive signal output by the current GOA unit can only meet the column inversion and plane inversion driving modes, and is not compatible with the point inversion and row inversion modes.

[0005] Therefore, how to achieve pre-charging compatible with multiple inversion modes is an urgent problem to be solved. Summary of the Invention

[0006] The present application provides a GOA unit, a driving method and a gate driving circuit to solve the problem in the related art that the output signal of the GOA unit is not compatible with pre-charging of multiple inversion modes.

[0007] In the first aspect, the present application provides a GOA unit, which includes a pull-up module for generating a Q-point voltage, and an output module for generating a stage transmission signal and a gate drive signal, the output module including: a first transistor, the control end of the first transistor is connected to the output end of the pull-up module, the second end of the first transistor is connected to the clock signal end, and the second end of the first transistor is used as the first-stage transmission output end for outputting the first-stage transmission signal; a second transistor, the first end of the second transistor is connected to the clock signal end, and the second end of the second transistor is used as the driving output end for outputting the gate drive signal; a switching circuit, the switching circuit including an input end, a first connection end, and a second connection end for receiving a first control signal, the first connection end of the switching circuit A connection end is connected to the control end of the first transistor, and the second connection end of the switching circuit is connected to the control end of the second transistor. The switching circuit is used to control the driving output end to output a gate driving signal of a different waveform under the action of a first control signal; a pull-down circuit, the pull-down circuit includes a first input end, a first connection end, and a second connection end for receiving a second control signal, the first connection end of the pull-down circuit is connected to the second connection end of the switching circuit, and the second connection end of the pull-down circuit is connected to the second end of the second transistor; the pull-down circuit is used to pull down the potential of the second connection end of the switching circuit and the second end of the second transistor under the action of the second control signal; wherein the phases of the first control signal and the second control signal are opposite.

[0008] Optionally, the gate drive signal output by the nth-level GOA unit includes a first pre-charge period, a second pre-charge period and a normal charging period; wherein, the first pre-charge period corresponds to the normal charging period of the n-2th level, and the second pre-charge period corresponds to the normal charging period of the n-1th level; when the first control signal is a continuous high level, the first pre-charge period, the second pre-charge period and the normal charging period are all high levels; when the first control signal is a square wave signal, the first pre-charge period and the normal charging period are high levels, and the second pre-charge period is a low level.

[0009] Optionally, the switching circuit includes: a third transistor, the control end of the third transistor serves as the input end of the switching circuit, the first end of the third transistor is connected to the control end of the first transistor, and the second end of the third transistor is connected to the control end of the second transistor.

[0010] Optionally, the pull-down circuit includes: a fourth transistor, the control end of the fourth transistor serving as the first input end of the pull-down circuit, the first end of the fourth transistor being connected to the second connection end of the switching circuit, and the second end of the fourth transistor being grounded; and a fifth transistor, the control end of the fifth transistor being connected to the control end of the fourth transistor, the first end of the fifth transistor being connected to the second end of the second transistor, and the second end of the fifth transistor being grounded.

[0011] Optionally, the pull-down circuit also includes: a sixth transistor, the control end of the sixth transistor serving as the second input end of the pull-down circuit, connected to the driving output end of the next-level GOA unit, the first end of the sixth transistor connected to the second end of the fourth transistor, and the second end of the sixth transistor grounded; a seventh transistor, the control end of the seventh transistor connected to the control end of the sixth transistor, the first end of the seventh transistor connected to the second end of the fifth transistor, and the second end of the seventh transistor grounded.

[0012] Optionally, the output module also includes: a flip circuit, the flip circuit including a first input end for receiving a high-level signal, a second input end for receiving a second control signal, and an output end, the output end of the flip circuit is connected to the input end of the switching circuit, and the flip circuit is used to generate a first control signal with an opposite phase according to the second control signal.

[0013] Optionally, the flipping circuit includes: an eighth transistor, the control end of the eighth transistor is connected to the high-level signal output end, and the first end of the eighth transistor is connected to the control end of the eighth transistor; a ninth transistor, the control end of the ninth transistor is connected to the second control signal output end, the first end of the ninth transistor is connected to the second end of the eighth transistor, and the second end of the ninth transistor is grounded; a tenth transistor, the control end of the tenth transistor is connected to the first end of the ninth transistor, the first end of the tenth transistor is connected to the first end of the eighth transistor, and the second end of the tenth transistor is connected to the input end of the switching circuit; an eleventh transistor, the control end of the eleventh transistor is connected to the control end of the ninth transistor, the first end of the eleventh transistor is connected to the second end of the tenth transistor, and the second end of the eleventh transistor is grounded.

[0014] Optionally, the output module also includes: a twelfth transistor, the control end of the twelfth transistor is connected to the control end of the first transistor, the first end of the twelfth transistor is connected to the clock signal end, and the second end of the twelfth transistor is used as the second-level transmission output end for outputting the second-level transmission signal; a bootstrap capacitor, the first end of the bootstrap capacitor is connected to the control end of the twelfth transistor, and the second end of the bootstrap capacitor is connected to the second end of the twelfth transistor.

[0015] In the second aspect, the present application provides a driving method applied to a GOA unit, the driving method comprising: obtaining a current polarity inversion mode of a display panel; outputting a corresponding first control signal and a second control signal according to the current polarity inversion mode; and the GOA unit outputting a gate drive signal of a corresponding waveform under the action of the first control signal and the second control signal.

[0016] In the second aspect, the present application provides a gate drive circuit, which includes: a signal control module, the input end of the signal control module is connected to the timing controller, and is used to output corresponding first control signals and second control signals according to the polarity inversion mode output by the timing controller; a plurality of cascaded GOA units, each GOA unit is connected to the output end of the signal control module, and is used to output gate drive signals of corresponding waveforms under the action of the first control signal and the second control signal.

[0017] The technical solution provided by this application has at least the following beneficial effects:

[0018] The switching circuit and the pull-down circuit in the present application respectively control the second transistor to output gate drive signals of different waveforms under the action of the first control signal and the second control signal input externally, so that the gate drive signals of different waveforms can meet the driving modes of column inversion, surface inversion, dot inversion and row inversion, and achieve compatibility with the pre-charging requirements of multiple inversion modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 Shown is a structural schematic diagram of a gate drive circuit provided in an embodiment of the present application.

[0021] Figure 2 FIG. 1 is a circuit diagram of a GOA unit in related art.

[0022] Figure 3 FIG2 is a waveform diagram of a gate drive signal provided in an embodiment of the present application.

[0023] Figure 4 Shown is a circuit diagram of the first GOA unit provided in an embodiment of the present application.

[0024] Figure 5 FIG. 1 is a waveform diagram of another gate driving signal provided in an embodiment of the present application.

[0025] Figure 6 Shown is a circuit diagram of the second GOA unit provided in an embodiment of the present application.

[0026] Figure 7 FIG. 1 is a waveform diagram of another gate driving signal provided in an embodiment of the present application.

[0027] Figure 8 FIG. 1 is a circuit diagram of a third GOA unit provided in an embodiment of the present application.

[0028] Figure 9 FIG. 1 is a circuit diagram of a fourth GOA unit provided in an embodiment of the present application.

[0029] Figure 10 The figure shows a flow chart of a driving method provided in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] 100, GOA unit; 110, switching circuit; 120, pull-down circuit; 130, flip circuit;

[0032] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; C1, bootstrap capacitor. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0034] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0035] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0036] like Figure 1 As shown, the GOA unit of the present application mainly includes a pull-up module, a pull-down module, an output module, a reset module and a noise reduction module. The pull-up module and the pull-down module output Q-point voltage. The pull-up module and the pull-down module need to obtain multiple transmission signals from the upper and lower GOA units. The Q-point voltage is the turn-on voltage of the output module, so that the output module outputs a gate drive signal to provide a turn-on voltage for the display area. The reset module is used to avoid the influence between frames, and the noise reduction module reduces the noise of each important signal. Among them, Gn-3 represents the output of the n-3th level GOA unit. The gate driving signal of the n-3th level GOA unit is represented by Fn-3, and the level transmission signal output by the n+4th level GOA unit is represented by Fn+4; the node N1 represents the first pull-up input terminal, the node N2 represents the second pull-up input terminal, the node N3 represents the pull-down input terminal, the node N4 represents the driving output terminal, the node N5 represents the driving level transmission terminal, the node N6 represents the level transmission output terminal, the node N7 represents the clock control terminal, the node N8 represents the reset input terminal, the node N9 represents the noise reduction trigger terminal, and the node Qn represents the voltage control terminal. In one embodiment, the circuit structure of the output module is as follows: Figure 2 As shown, T1 and T2 output Fn and Gn signals respectively, wherein Gn provides a turn-on voltage and level transmission requirements for the display area, while the Fn signal is only used for level transmission.

[0037] Figure 3 The figure shows the waveform output of the GOA unit at the n-2, n-1 and n levels. Figure 3As shown, the waveform phases of adjacent levels differ by 1H, while the output waveform width of each level is more than 1H. There is overlap between adjacent Gouts. The Gout width is divided into t1, t2, and t3 from right to left with one H as the smallest unit. Therefore, the t3 period is the normal charging time of the nth row, and the redundant t1 and t2 are the pre-charging time of the nth row. During the t1 and t2 periods, the data of the n-2 and n-1th rows can be pre-charged into the pixels of the Nth row. When the polarity inversion mode of the data is column inversion or plane inversion, the polarity of the N-2 and N-1th rows is the same as that of the nth row. Therefore, the data pre-charged into the pixels of the nth row can give a certain increase in the internal potential of the pixels. Therefore, when the data of the nth row arrives, the target potential can be quickly charged.

[0038] It can be seen that the above-mentioned pre-charging method can greatly improve the panel charging rate, but the above-mentioned method only has an improving effect on the column inversion and plane inversion modes. When point inversion or row inversion is adopted, it will have a certain negative impact on the charging rate. For example, when the polarities of the n-2, n-1 and n rows are positive-negative-positive or negative-positive-negative respectively, before the target potential charging is completed in the t3 period, the data voltage with opposite polarity of the n-1 row will be charged in advance at t2 time. Therefore, this method is not compatible with the point inversion, row inversion and other modes; therefore, in order to meet the compatibility pre-charging in the multi-inversion mode, the present application provides a GOA unit, which specifically includes the following embodiments:

[0039] The GOA unit 100 provided in this application includes a pull-up module for generating a Q-point voltage, and an output module for generating a level transfer signal and a gate drive signal; Figure 4 As shown, the output module includes a first transistor T1, a second transistor T2, a switching circuit 110 and a pull-down circuit 120; the control end of the first transistor T1 is connected to the output end of the pull-up module, the second end of the first transistor T1 is connected to the clock signal end, and the second end of the first transistor T1 is used as the first-level transmission output end for outputting the first-level transmission signal; the first end of the second transistor T2 is connected to the clock signal end, and the second end of the second transistor T2 is used as the driving output end for outputting the gate driving signal; the switching circuit 110 includes an input end for receiving a first control signal A, a first connecting end, and a second connecting end. The first connecting end of the switching circuit 110 is connected to the control end of the first transistor T1, and the second connecting end of the switching circuit 110 is connected to the control end of the second transistor T2. The switching circuit 110 is used to control the driving output end to output gate driving signals of different waveforms under the action of the first control signal A.

[0040] In this embodiment, the pull-down circuit 120 includes a first input terminal, a first connection terminal, and a second connection terminal for receiving a second control signal B. The first connection terminal of the pull-down circuit 120 is connected to the second connection terminal of the switching circuit 110, and the second connection terminal of the pull-down circuit 120 is connected to the second terminal of the second transistor T2. The pull-down circuit 120 is used to lower the potential of the second connection terminal of the switching circuit 110 and the second terminal of the second transistor T2 under the action of the second control signal B. The first control signal A and the second control signal B have opposite phases.

[0041] It should be noted that the gate drive signal output by the n-th level GOA unit 100 includes a first pre-charge period, a second pre-charge period and a normal charging period; wherein the first pre-charge period corresponds to the normal charging period of the n-2th level, and the second pre-charge period corresponds to the normal charging period of the n-1th level; Figure 3 As shown, t1 is the first pre-charge period, t2 is the second pre-charge period, and t3 is the normal charging period; when the first control signal A is always at a high level, the first pre-charge period, the second pre-charge period, and the normal charging period are all at a high level. At this time, the output waveform of the gate drive signal can meet the column inversion and plane inversion driving modes, that is, Figure 3 The output waveform is shown.

[0042] In one embodiment, when the first control signal A is a square wave signal, the first pre-charge period and the normal charging period are high level, and the second pre-charge period is low level. At this time, the output waveform of the gate drive signal can meet the driving mode of dot inversion and row inversion, that is, Figure 5 The output waveform is shown.

[0043] from Figure 3 and Figure 5 It can be seen from the waveform diagram of FIG. 1 that in this embodiment, the output waveform of the first control signal A is the same as the output waveform of the gate drive signal.

[0044] Continue to refer Figure 4 As shown, when the Q-point voltage output by the pull-up module is at a high level, the first transistor T1 is turned on, so that the first-stage transmission end outputs a first-stage transmission signal for stage transmission; wherein the output waveform of the first-stage transmission signal is the same as the waveform of the clock signal.

[0045] It should be noted that when the first control signal A is at a low level, although the third transistor T3 is in a closed state, the charge at the Qe point cannot be released and is still at a high potential to turn on the second transistor T2, so that the gate drive signal still outputs a high level; in order to prevent the problem of charge backflow, this embodiment uses the pull-down circuit 120 to pull down the control end of the second transistor T2 when the first control signal A is at a low level, thereby immediately disconnecting the second transistor T2; at the same time, the second end of the second transistor T2 is pulled down by the pull-down circuit 120 so that the drive output end outputs a low-level signal, thereby improving the stability of the drive signal.

[0046] It can be seen from this that the switching circuit 110 and the pull-down circuit 120 in the present application respectively control the second transistor T2 to output gate drive signals of different waveforms under the action of the first control signal A and the second control signal B input externally, so that the gate drive signals of different waveforms can meet the driving modes of column inversion, surface inversion, dot inversion and row inversion, and achieve compatibility with the pre-charging requirements of multiple inversion modes.

[0047] In one embodiment, the switching circuit 110 includes: a third transistor T3, the control end of the third transistor T3 serves as the input end of the switching circuit 110, the first end of the third transistor T3 is connected to the control end of the first transistor T1, and the second end of the third transistor T3 is connected to the control end of the second transistor T2.

[0048] It should be noted that if Figure 4 As shown, when the first control signal A is high, the third transistor T3 is turned on, and the output waveform of the gate drive signal is the same as the clock signal CK, which can meet the column inversion and plane inversion driving modes; ... Figure 5 When the square wave signal is shown, the output waveform of the gate drive signal is the same as the first control signal A, that is, the potentials in adjacent time periods are opposite, which can meet the driving modes of dot inversion and row inversion.

[0049] In one embodiment, if Figure 4 As shown, the pull-down circuit 120 includes: a fourth transistor T4 and a fifth transistor T5; the control end of the fourth transistor T4 serves as the first input end of the pull-down circuit 120, the first end of the fourth transistor T4 is connected to the second connection end of the switching circuit 110, and the second end of the fourth transistor T4 is grounded; the control end of the fifth transistor T5 is connected to the control end of the fourth transistor T4, the first end of the fifth transistor T5 is connected to the second end of the second transistor T2, and the second end of the fifth transistor T5 is grounded.

[0050] It should be noted that if Figure 5As shown, when the row inversion or dot inversion driving mode needs to be met, the first control signal A and the second control signal B are square wave signals with opposite phases. When the first control signal A is at a low level, the second control signal B is at a high level, and the fourth transistor T4 and the fifth transistor T5 are turned on at the same time, so that the fourth transistor T4 pulls down the control end of the second transistor T2, and the fifth transistor T5 pulls down the second end of the second transistor T2, so that the second transistor T2 outputs a low-level signal; in addition, when the first control signal A is at a high level, the second control signal B is low, and the fourth transistor T4 and the fifth transistor T5 are turned off at the same time, so that the second transistor T2 outputs the same potential as the CK signal.

[0051] Optionally, in Figure 5 In the b4 period, since the second control signal B is at a high level and the first control signal A is at a low level, the second transistor T2 is turned off and the fifth transistor T5 is turned on, and the Gn signal releases the charge to the ground through the fifth transistor T5; however, the second transistor T2 is a driving transistor in the driving plane, and its size and voltage are relatively large, and the fifth transistor T5 is only a switch with a small size, so that the Gn voltage is released slowly through the fifth transistor T5, so that it appears at the falling edge of Gn. Figure 5 The tailing phenomenon shown in the figure can cause the pixel to be mischarged.

[0052] In another embodiment, Figure 6 As shown, in order to solve the tailing problem of the gate drive signal on the falling edge, the pull-down circuit 120 of this embodiment further includes: a sixth transistor T6 and a seventh transistor T7; the control end of the sixth transistor T6 serves as the second input end of the pull-down circuit 120, and is connected to the driving output end of the next-stage GOA unit 100, the first end of the sixth transistor T6 is connected to the second end of the fourth transistor T4, and the second end of the sixth transistor T6 is grounded; the control end of the seventh transistor T7 is connected to the control end of the sixth transistor T6, the first end of the seventh transistor T7 is connected to the second end of the fifth transistor T5, and the second end of the seventh transistor T7 is grounded.

[0053] The specific working principle of the pull-down circuit 120 in this embodiment is as follows: Figure 7 As shown, during the b4 period, the second control signal B is at a high level, and the fourth transistor T4 and the fifth transistor T5 are turned on; however, at this time, Gn-1 is at a low level, which turns off the sixth transistor T6 and the seventh transistor T7. Therefore, during the b4 period, the gate voltage of the second transistor T2 is still Qen. It can be seen that the role of the sixth transistor T6 and the seventh transistor T7 is not to pull down the gate of the second transistor T2 during the b4 period, so that the second transistor T2 is turned on during the b4 period. Since the CK signal is at a low level at this time, the Gn voltage is immediately released through the CK terminal, improving the tailing phenomenon of the Gn falling edge. Figure 5 and Figure 7 By comparison, the difference between the two figures is that the right shoulder signal of Qen and the falling edge of Gn in the t3 period are different.

[0054] In one embodiment, the output module also includes: a flip circuit 130, the flip circuit 130 includes a first input end for receiving a high-level signal, a second input end for receiving a second control signal B, and an output end, the output end of the flip circuit 130 is connected to the input end of the switching circuit 110, and the flip circuit 130 is used to generate a first control signal A with an opposite phase according to the second control signal B.

[0055] It should be noted that since the first control signal A and the second control signal B have opposite phases, in order to reduce the input of external signals, this embodiment uses the flip circuit 130 to invert the second control signal B to obtain the first control signal A.

[0056] Specifically, if Figure 8 and Figure 9 As shown, the flip circuit 130 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; the control end of the eighth transistor T8 is connected to the high-level signal output end, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the second control signal B output end, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is grounded; the control end of the tenth transistor T10 is connected to the first end of the ninth transistor T9, the first end of the tenth transistor T10 is connected to the first end of the eighth transistor T8, and the second end of the tenth transistor T10 is connected to the input end of the switching circuit 110; the control end of the eleventh transistor T11 is connected to the control end of the ninth transistor T9, the first end of the eleventh transistor T11 is connected to the second end of the tenth transistor T10, and the second end of the eleventh transistor T11 is grounded.

[0057] The specific working principle of the flip circuit 130 of this embodiment is as follows: since the control terminal of the eighth transistor T8 is connected to a continuous high level, the eighth transistor T8 is always in the on state, outputting a high level to the control terminal of the tenth transistor T10, so that the tenth transistor T10 also continuously outputs a high level; at the same time, if the second control signal B output by the external chip is a low level, the ninth transistor T9 and the eleventh transistor T11 are both in the off state, and the output signal of the flip circuit 130 at this time is the high level output by the tenth transistor T10; if the second control signal B output by the external chip is a high level, the ninth transistor T9 and the tenth transistor T10 are both in the on state, thereby pulling down the output potential of the tenth transistor T10, so that the tenth transistor T10 outputs a low level, thereby realizing the flip function of the second control signal B.

[0058] In one embodiment, the output module further includes: a twelfth transistor T12 and a bootstrap capacitor C1, the control end of the twelfth transistor T12 is connected to the control end of the first transistor T1, the first end of the twelfth transistor is connected to the clock signal end, and the second end of the twelfth transistor T12 is used as the second-level transmission output end for outputting the second-level transmission signal; the first end of the bootstrap capacitor C1 is connected to the control end of the twelfth transistor T12, and the second end of the bootstrap capacitor C1 is connected to the second end of the twelfth transistor T12.

[0059] like Figure 4 、 Figure 6 、 Figure 8 and Figure 9 As shown, the first transistor and the twelfth transistor both use Qn as the gate and CK as the drain, so the generated Fn and Gtn waveforms can be used for stage transmission. Providing redundant stage transmission terminals can simplify the cascade routing between GOA units.

[0060] In another embodiment, the present application provides a driving method, such as Figure 10 As shown, the driving method applies the GOA unit shown in the above embodiment, and specifically includes the following steps:

[0061] Step S101: obtaining the current polarity inversion mode of the display panel;

[0062] Step S102: outputting a first control signal and a second control signal corresponding to the current polarity inversion mode;

[0063] Step S103, the GOA unit under the action of the first control signal and the second control signal, outputs a gate drive signal corresponding to the waveform.

[0064] It should be noted that, since the GOA unit of this embodiment is compatible with multiple modes of polarity inversion, it is necessary to obtain the current polarity inversion mode of the display panel through external devices such as a timing controller when performing GOA driving, where the current polarity inversion mode includes but is not limited to point inversion, row inversion, column inversion or surface inversion; then, the corresponding first control signal and second control signal are selected and output according to the current polarity inversion mode, so that the GOA unit outputs the corresponding gate drive signal; the specific working principle is the same as that of the GOA unit in the above embodiment, and will not be repeated here.

[0065] In another embodiment, the present application provides a gate drive circuit, which includes: a signal control module and the GOA unit of the above embodiment; wherein the input end of the signal control module is connected to the timing controller, and is used to output the corresponding first control signal and second control signal according to the polarity inversion mode output by the timing controller; each GOA unit is connected to the output end of the signal control module, and is used to output a gate drive signal of a corresponding waveform under the action of the first control signal and the second control signal.

[0066] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0067] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0068] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A GOA unit, characterized in that: The GOA unit includes a pull-up module for generating a Q-point voltage, and an output module for generating a stage transmission signal and a gate drive signal, wherein the output module includes: a first transistor, wherein the control end of the first transistor is connected to the output end of the pull-up module, the second end of the first transistor is connected to the clock signal end, and the second end of the first transistor is used as the first-stage transmission output end for outputting the first-stage transmission signal; a second transistor, wherein a first terminal of the second transistor is connected to the clock signal terminal, and a second terminal of the second transistor is used as a driving output terminal for outputting a gate driving signal; a switching circuit, the switching circuit comprising an input terminal for receiving a first control signal, a first connection terminal, and a second connection terminal, the first connection terminal of the switching circuit being connected to the control terminal of the first transistor, the second connection terminal of the switching circuit being connected to the control terminal of the second transistor, the switching circuit being configured to control the drive output terminal to output gate drive signals of different waveforms under the action of the first control signal; a pull-down circuit, the pull-down circuit comprising a first input terminal for receiving a second control signal, a first connection terminal, and a second connection terminal, the first connection terminal of the pull-down circuit being connected to the second connection terminal of the switching circuit, and the second connection terminal of the pull-down circuit being connected to the second terminal of the second transistor; the pull-down circuit being configured to pull down the potential of the second connection terminal of the switching circuit and the second terminal of the second transistor under the action of the second control signal; The first control signal and the second control signal have opposite phases.

2. The GOA unit according to claim 1, characterized in that The gate drive signal output by the n-th level GOA unit includes a first pre-charge period, a second pre-charge period and a normal charging period; wherein the first pre-charge period corresponds to the normal charging period of the n-2-th level, and the second pre-charge period corresponds to the normal charging period of the n-1-th level; When the first control signal is at a continuously high level, the first pre-charging period, the second pre-charging period and the normal charging period are all at a high level; When the first control signal is a square wave signal, the first pre-charge period and the normal charge period are at a high level, and the second pre-charge period is at a low level.

3. The GOA unit according to claim 1, characterized in that The switching circuit includes: A third transistor, wherein the control end of the third transistor serves as the input end of the switching circuit, the first end of the third transistor is connected to the control end of the first transistor, and the second end of the third transistor is connected to the control end of the second transistor.

4. The GOA unit according to claim 1, characterized in that The pull-down circuit comprises: a fourth transistor, wherein a control terminal of the fourth transistor serves as a first input terminal of the pull-down circuit, a first terminal of the fourth transistor is connected to the second connection terminal of the switching circuit, and a second terminal of the fourth transistor is grounded; a fifth transistor, wherein a control end of the fifth transistor is connected to the control end of the fourth transistor, a first end of the fifth transistor is connected to the second end of the second transistor, and a second end of the fifth transistor is grounded.

5. The GOA unit according to claim 4, characterized in that The pull-down circuit further includes: a sixth transistor, wherein the control end of the sixth transistor serves as the second input end of the pull-down circuit and is connected to the driving output end of the next-stage GOA unit, the first end of the sixth transistor is connected to the second end of the fourth transistor, and the second end of the sixth transistor is grounded; a seventh transistor, wherein a control end of the seventh transistor is connected to the control end of the sixth transistor, a first end of the seventh transistor is connected to the second end of the fifth transistor, and a second end of the seventh transistor is grounded.

6. The GOA unit according to claim 1, characterized in that The output module also includes: A flip circuit, the flip circuit comprising a first input end for receiving a high-level signal, a second input end for receiving a second control signal, and an output end, the output end of the flip circuit being connected to the input end of the switching circuit, the flip circuit being used to generate a first control signal with an opposite phase according to the second control signal.

7. The GOA unit according to claim 6, characterized in that The flip circuit includes: an eighth transistor, wherein the control terminal of the eighth transistor is connected to the high-level signal output terminal, and the first terminal of the eighth transistor is connected to the control terminal of the eighth transistor; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the second control signal output terminal, a first terminal of the ninth transistor is connected to the second terminal of the eighth transistor, and a second terminal of the ninth transistor is grounded; a tenth transistor, wherein a control terminal of the tenth transistor is connected to the first terminal of the ninth transistor, a first terminal of the tenth transistor is connected to the first terminal of the eighth transistor, and a second terminal of the tenth transistor is connected to the input terminal of the switching circuit; an eleventh transistor, wherein the control end of the eleventh transistor is connected to the control end of the ninth transistor, the first end of the eleventh transistor is connected to the second end of the tenth transistor, and the second end of the eleventh transistor is grounded.

8. The GOA unit according to any one of claims 1 to 7, characterized in that: The output module also includes: a twelfth transistor, wherein the control terminal of the twelfth transistor is connected to the control terminal of the first transistor, the first terminal of the twelfth transistor is connected to the clock signal terminal, and the second terminal of the twelfth transistor is used as a second-stage transmission output terminal for outputting a second-stage transmission signal; A bootstrap capacitor, wherein a first end of the bootstrap capacitor is connected to the control end of the twelfth transistor, and a second end of the bootstrap capacitor is connected to the second end of the twelfth transistor.

9. A driving method, characterized in that: Applied to the GOA unit according to any one of claims 1 to 8, the driving method includes: Get the current polarity inversion mode of the display panel; Outputting corresponding first control signals and second control signals according to the current polarity inversion mode; Under the effects of the first control signal and the second control signal, the GOA unit outputs a gate driving signal with a corresponding waveform.

10. A gate drive circuit, characterized in that: The gate drive circuit includes: a signal control module, wherein an input end of the signal control module is connected to the timing controller and is configured to output a corresponding first control signal and a second control signal according to a polarity inversion mode output by the timing controller; A plurality of cascaded GOA units according to any one of claims 1 to 8, each GOA unit being connected to the output end of the signal control module, and configured to output a gate drive signal of a corresponding waveform under the action of the first control signal and the second control signal.

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