Driving circuit, display panel and driving method

Abstract

The application provides a driving circuit, a display panel and a driving method. The driving circuit comprises a controller and a plurality of first scan lines and second scan lines extending along a second direction. The controller is electrically connected with the second scan lines. The controller is configured to: in the case that any two adjacent first row pixel units and M second row pixel units therebetween transmit a first scan signal on any first scan line to start the corresponding first row pixel unit to display a first gray scale value N1, the controller is further configured to input a second scan signal to the second scan line, the second scan signal is used to start the second row pixel unit to display a second gray scale value N2; N2=i*N1 / (M+1). In the application, by assigning the second row pixel unit with an interpolation gray scale value based on the gray scale value of the first row pixel unit, a smoother image transition can be achieved, and in particular when displaying a high-contrast image, the jagged edges are reduced, and the image quality in the HSR display mode is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit, a display panel and a driving method. BACKGROUND

[0002] Nowadays, the refresh rate pursued by the display industry is getting higher and higher, and the way of improving the refresh rate of the television display screen through frequency doubling technology is also becoming more and more common, such as HSR (Hardware Super Resolution) technology.

[0003] HSR is a technology for displaying high refresh rate by adjusting the timing of low refresh rate driving, such as 4K*2K UHD 60Hz display through 4K*1K UHD 120Hz display by adjusting the timing, such as 4K*2K UHD 120Hz display through 4K*1K UHD 240Hz display by adjusting the timing. Because the total amount of data displayed is the same, the specifications of the driving components are the same, and only the refresh rate is doubled by adjusting the timing, but part of the resolution is also sacrificed.

[0004] At present, in order to improve the picture display definition under HSR technology, the long-bright display screen adjusts the Gn (scanning data) phase to charge a part of the gray scale voltage of the previous odd row pixel to the even row pixel, and then charges a part of the gray scale voltage of the next odd row pixel, neutralizes the gray scale of the even row pixel, thereby realizing the blurring processing of the position with large contrast difference, so that the image boundary is smoother. However, in the direct display screen with PWM (Pulse-Width Modulation) dimming, there is no charging process, and the gray scale is realized by controlling the light and dark time length, and the display data cannot be increased, so the adjustment of the Gn phase to realize the intermediate value of the adjacent two odd row pixels displayed by the even row pixel cannot be applied to the direct display screen with PWM dimming. That is, when the PWM dimming direct display screen realizes HSR, the position with large contrast difference of the display screen is prone to have jagged edges, which reduces the overall quality of the image. SUMMARY

[0005] The present application provides a driving circuit, a display panel and a driving method which are beneficial to improve the image quality under HSR technology.

[0006] In a first aspect, the embodiments of the present application provide a driving circuit applied to a display panel, the display panel comprising a plurality of pixel units arranged periodically along a first direction and a second direction, in the second direction, a plurality of rows of pixel units comprise a first row of pixel units and a second row of pixel units, and M rows of the second row of pixel units are arranged between each adjacent two first rows of pixel units; the driving circuit comprises:

[0007] a plurality of first scan lines and second scan lines extending in a second direction, each of the first scan lines being electrically connected to a corresponding one of the first rows of pixel units, and each of the second scan lines being electrically connected to a corresponding one of the second rows of pixel units;

[0008] a controller electrically connected to the second scan lines, the controller being configured to, in a case that any one of the first scan lines transmits a first scan signal to activate the corresponding first row of pixel units to display a first gray scale value N1, input a second scan signal to the second scan lines, the second scan signal being used to activate the second rows of pixel units to display a second gray scale value N2, N2 = i * N1 / (M + 1), where M is a positive integer, and i is a number of the second rows of pixel units, the number of the second rows of pixel units being increased along a direction close to the activated first row of pixel units.

[0009] wherein M is a positive integer, and i is a number of the second rows of pixel units, the number of the second rows of pixel units being increased along a direction close to the activated first row of pixel units.

[0010] According to the first aspect, in a possible implementation, the first scan lines and the second scan lines are arranged alternately, the first rows of pixel units are odd rows of pixel units, and the second rows of pixel units are even rows of pixel units.

[0011] According to the first aspect, in a possible implementation, the controller comprises a plurality of control units, each of the second scan lines is electrically connected to a corresponding one of the control units, each of the control units comprises first and second switch transistors arranged in parallel, input ends of the first and second switch transistors are electrically connected to a third scan line, output ends of the first and second switch transistors are electrically connected to a corresponding one of the second scan lines, a control end of the first switch transistor is electrically connected to one of the first scan lines adjacent to the corresponding one of the second scan lines, and a control end of the second switch transistor is electrically connected to another one of the first scan lines adjacent to the corresponding one of the second scan lines.

[0012] According to the first aspect, in a possible implementation, the driving circuit further comprises a switching unit, the first scan lines and the second scan lines are electrically connected to a scan driver, the switching unit is configured to control the driving circuit to switch between a first mode and a second mode, in a case that the driving circuit is in the first mode, the scan driver transmits a first scan signal to the first scan lines row by row to activate the odd rows of pixel units and two of the even rows of pixel units adjacent to the odd rows of pixel units, and in a case that the driving circuit is in the second mode, the scan driver transmits a third scan signal to the first scan lines and the second scan lines row by row to activate the pixel units row by row.

[0013] According to the first aspect, in a possible implementation, the second scan signal is provided with a third switch transistor, the third switch transistor is located between the connection point of the scan driver and the control unit, and the control end of the third switch transistor is electrically connected with the switching unit.

[0014] According to the first aspect, in a possible implementation, the control unit is provided with a fourth switch transistor, the fourth switch transistor is located between the input end of the first switch transistor and a third scan line, and the control end of the fourth switch transistor is electrically connected with the switching unit.

[0015] According to the first aspect, in a possible implementation, the switching unit includes a first control line and a second control line, each of the third switch transistors is connected to the first control line, and each of the fourth switch transistors is connected to the second control line; the first control line is used to output a low level, and the second control line is used to output a high level to control the driving circuit to switch to the first mode; the first control line is used to output a high level, and the second control line is used to output a low level to control the driving circuit to switch to the second mode.

[0016] The second aspect, the application further provides a display panel, the display panel includes a plurality of pixel units arranged in an array and the driving circuit of the first aspect, and pixel units in the same row are connected to the same scan line.

[0017] The third aspect, the application further provides a driving method, the driving method is applied to the driving circuit of the first aspect, and the driving method includes:

[0018] obtaining first image data corresponding to the first row of pixel units according to original image data, the first image data including time sequence information and a target gray scale value N;

[0019] in the case that the display mode of the display panel is HSR, inputting a first scan signal to the first scan line to start the first row of pixel units to display a first gray scale value N1 according to the time sequence information in a preset time period;

[0020] in the case that any first row of pixel units displays the first gray scale value N1, inputting a second scan signal to the second scan line to start the second row of pixel units to display a second gray scale value N2, N2 = i * N1 / (M + 1) in any two adjacent first row of pixel units and M rows of second row of pixel units therebetween.

[0021] Wherein, M is a positive integer, i is the number of the second row of pixel units, the index of the second row of pixel units increases along the direction close to the activated first row of pixel units, and i is a positive integer.

[0022] According to a third aspect, in a possible implementation, the driving method further includes:

[0023] Dividing the original image data into odd frame image data and even frame image data;

[0024] In a first frame display period, starting the first row of pixel units with the odd frame image data as the first image data;

[0025] In a second frame display period, starting the first row of pixel units with the even frame image data as the first image data;

[0026] Wherein, the first frame display period and the second frame display period are two adjacent frame display periods.

[0027] The driving circuit, the display panel and the driving method provided in the application can realize smoother image transition by assigning the second row of pixel units with the interpolation gray scale value based on the gray scale value of the first row of pixel units, especially when displaying high-contrast images. Not only the delicacy of the image is improved, but also the image quality in HSR display mode is improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0029] Figure 1 is a circuit schematic diagram of the driving circuit and the pixel unit in an embodiment of the present application;

[0030] Figure 2 is a circuit schematic diagram of the driving circuit and the pixel unit in another embodiment of the present application;

[0031] Figure 3 is Figure 2 is a signal timing diagram in the embodiment shown in the figure;

[0032] Figure 4 is a flowchart of the driving method in an embodiment of the present application.

[0033] Reference signs:

[0034] 10 - pixel unit; 10a - first row of pixel units; 10b - second row of pixel units; 20 - control unit; 30 - switching unit; 40 - scan driver; X1 - first control line; X2 - second control line; V+ - third scan line; T1 - first switching transistor; T2 - second switching transistor; T3 - third switching transistor; T4 - fourth switching transistor; G1 - first scan line; G2 - second scan line; OE - enable signal. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0036] It should be noted that when a component is referred to as being "fixed" to another component, it can be directly on the other component or there can be an intervening component. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or there can be an intervening component.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The use of the terms "and / or" includes a combination of one or more of the associated listed items.

[0038] Some embodiments of the present application will be described in detail with reference to the drawings. The following embodiments and features of the embodiments can be combined with each other in the case of no conflict.

[0039] The present application provides a display panel, such as Figure 1 As shown, the display panel includes a plurality of pixel units 10 arranged in an array and a driving circuit of the first aspect, the pixel units 10 in the same row are connected to the same scan line. The driving circuit has a first mode and a second mode. In the case of the first mode, the driving circuit enables the pixel units 10 in adjacent rows to work cooperatively by a specific signal processing algorithm and circuit design, thereby improving the refresh rate of the display panel and realizing the HSR display mode. In the case of the second mode, the display panel works in the traditional line-by-line scanning mode. In this mode, the pixel units 10 in each row are activated in turn and display the picture row by row in the order from top to bottom or from left to right.

[0040] The display panel has a plurality of pixel units 10 arranged in an array, which are responsible for generating and displaying images. Each pixel unit 10 usually contains three sub-pixels of red (R), green (G) and blue (B) or other color combinations to present rich colors. The pixel units 10 in the same row are connected by the same scan line, which enables the driving circuit to control all the pixel units 10 in a row at the same time. The function of the scan line is to sequentially activate each row of pixel units during the display process to form a complete image on the screen.

[0041] In an embodiment, the pixel units 10 are arranged in a periodic array along a first direction and a second direction, forming a standard display matrix. In the second direction, the pixel units 10 are divided into two types of rows: first row pixel units 10a and second row pixel units 10b. M rows of second row pixel units 10b are inserted between every two adjacent first row pixel units 10a, and M is a positive integer. By controlling the gray levels of the first row pixel units 10a and the second row pixel units 10b, a smoother image transition can be achieved. The first direction is the row direction, and the second direction is the column direction.

[0042] The driving circuit includes a controller and a plurality of first scan lines G1 and second scan lines G2 extending in the second direction.

[0043] The number of first scan lines G1 is consistent with the number of rows of first row pixel units 10a, and each row of first row pixel units 10a is connected to a corresponding first scan line. Each row of first row pixel units 10a receives a scan signal through an independent first scan line G1.

[0044] The number of second scan lines G2 is consistent with the number of rows of second row pixel units 10b, and each row of second row pixel units 10b is connected to a corresponding second scan line. Each row of second row pixel units 10b receives a scan signal through an independent second scan line G2.

[0045] Each second scan line G2 is electrically connected to a control unit 20. These control units 20 send corresponding scan signals to the corresponding second scan lines G2 according to the signal state of the first scan lines G1.

[0046] For the convenience of illustration, in this application, one display unit is composed of two first row pixel units 10a and M second row pixel units 10b between them. In the case of the second mode, when any first scan line G1 transmits a first scan signal to start the corresponding first row pixel unit 10a to display the first gray scale value N1, the controller in the adjacent M second row pixel units 10b receives a certain form of trigger signal. The trigger signal can be directly from the first scan line G1 or generated by other logic circuits. The controller calculates the second gray scale value N2 to be displayed according to the number i of the second row pixel unit 10b to be started. The calculation formula is N2 = i * N1 / (M + 1). The number i of the second row pixel unit 10b increases along the direction close to the started first row pixel unit 10a, and i is a positive integer; M is the number of inserted second row pixel units 10b. The control unit 20 then sends a second scan signal to the second scan line G2 to start the second row pixel unit 10b to display the calculated gray scale value N2. Thus, when displaying high-contrast images, the gray scale value of the second row pixel unit 10b can be adjusted to reduce the sawtooth effect and improve the fineness of the image.

[0047] For example, the two adjacent first row pixel units 10a can be provided with 3 second row pixel units 10b, forming a unit group composed of 5 pixel units; represented by 2n+1 to 2n+5 rows, where n is a natural number, representing the position of the unit group in the overall pixel array. In the second mode, when any first scan line G1, such as the first scan line G1 connected to the 2n+1 row pixel unit, transmits a first scan signal to start the 2n+1 row pixel unit to display the first gray scale value N1, the controller receives a trigger signal and inputs a second scan signal to the second scan line G2 corresponding to the 2n+2 row pixel unit, the 2n+3 row pixel unit and the 2n+4 row pixel unit.

[0048] When the 2n+1 row displays the first gray scale value N1, taking the 2n+1 row pixel unit as the reference, the 2n+2 row pixel unit displays the gray scale value N21 = 3*N1 / 4, the 2n+3 row pixel unit displays the gray scale value N22 = N1 / 2, and the 2n+4 row pixel unit displays the gray scale value N23 = N1 / 4.

[0049] When the 2n+5 row displays the first gray scale value N1', taking the 2n+5 row pixel unit as the reference, the 2n+2 row pixel unit displays the gray scale value N21' = N1' / 4, the 2n+3 row pixel unit displays the gray scale value N22' = N1' / 2, and the 2n+4 row pixel unit displays the gray scale value N23' = 3*N1' / 4.

[0050] In one display cycle, 2n+1 rows display the first gray scale value N1, 2n+2 rows of pixel units display the gray scale value N2=N21+N21'=3N1 / 4+N1' / 4, 2n+3 rows of pixel units display the gray scale value N3=N22+N22'=N1 / 2+N1' / 2, 2n+4 rows of pixel units display the gray scale value N4=N23+N23'=N1 / 4+3*N1' / 4, and 2n+5 rows display the first gray scale value N1'.

[0051] Wherein the 2n+5 rows of pixel units also serve as the start of the next display unit, that is, any first row of pixel units 10a is activated, and the plurality of second pixel units 10 adjacent to both sides thereof are also activated. Thus, the adjacent 3 rows of second row pixel units 10b, i.e., the 2n+2 rows of pixel units, the 2n+3 rows of pixel units, and the 2n+4 rows of pixel units, realize the gradual transition from the 2n+1 rows of pixel units to the 2n+5 rows of pixel units, and by assigning the second row pixel units 10b with the interpolated gray scale value based on the gray scale value of the first row pixel units 10a, a smoother image transition can be realized, especially when displaying high-contrast images. Not only does this improve the delicacy of the image, but it also improves the image quality in the HSR display mode.

[0052] In other embodiments, the number of second row pixel units 10b inserted between the two adjacent first row pixel units 10a can be 1 row, 2 rows, 4 rows, 5 rows, or even more, which is not limited in the present application.

[0053] In the above embodiment one example, as shown in Figure 2 and Figure 3 The first scan line G1 and the second scan line G2 are alternately arranged, the first row of pixel units 10a are odd rows of pixel units, and the second row of pixel units 10b are even rows of pixel units. That is, the first scan line G1 scans the odd rows of pixel units, and the second scan line G2 scans the even rows of pixel units. In order to reduce the sawtooth effect in high-contrast pictures, as shown in Figure 2As shown, in the 5 rows of pixel units (2n+1 row of pixel units to 2n+5 row of pixel units) arranged in series, the corresponding scanning lines are represented by G2n+1 to G2n+5, when the 2n+3 row (odd row) pixel unit 10 displays the gray scale value N1, its adjacent even row pixel units (2n+2 row of pixel units and 2n+4 row of pixel units) can display a certain interpolation result of N1, for example, N1 / 2, respectively. Thus, in one display unit, 2n+1 row of pixel units to 2n+3 row of pixel units, 2n+1 row of pixel units starts, 2n+2 row of pixel units starts, and the timing is consistent, the brightness of 2n+2 row of pixel units is half of the brightness of 2n+1 row of pixel units; 2n+3 row of pixel units starts, 2n+2 row of pixel units starts, and the timing is consistent, the brightness of 2n+2 row of pixel units is half of the brightness of 2n+3 row of pixel units; the gray scale value is the integral of brightness and time, that is, the gray scale value of 2n+1 row of pixel units is N1, the gray scale value of 2n+3 row of pixel units is N1', and the gray scale value of 2n+2 row of pixel units is (N1+N1') / 2. It can be understood that 2n+3 row of pixel units also serves as the start of the next display unit, that is, the gray scale value of 2n+4 row of pixel units is the intermediate gray scale value of the gray scale values of 2n+3 row of pixel units and 2n+5 row of pixel units, so that for any two adjacent odd row pixel units and the even row pixel unit therebetween, the even row pixel unit can display the intermediate gray scale value of the two odd row pixel units.

[0054] wherein, Figure 3 OE is an enable signal, the enable signal OE is usually transmitted to the driving chip of the display panel together with the data signal and the control signal. When the enable signal OE is high, the driving chip will receive and process the data signal, so as to control whether the pixel unit 10 on the display panel is lit or not.

[0055] Thus, in the PWM dimming direct display screen, the scanning signal Gn and the driving signal Sn have constant voltage, different gray scales are realized by adjusting the light and dark time length, and the brightness is constant when it is light, and it is black when it is dark. In the present application, Sn is not changed, the display panel realizes smoother image transition in the HSR display mode by adjusting the voltage of the scanning signal corresponding to the second row of pixel units 10b, and the picture quality is improved.

[0056] In an embodiment, the controller comprises a plurality of control units 20, each second scan line G2 is electrically connected with a corresponding control unit 20. The control unit 20 comprises a first switch transistor T1 and a second switch transistor T2 arranged in parallel, the input ends of the first switch transistor T1 and the second switch transistor T2 are electrically connected with the third scan line V+, the output ends of the first switch transistor T1 and the second switch transistor T2 are electrically connected with the corresponding second scan line G2; the control end of the first switch transistor T1 is electrically connected with one of the first scan lines G1 adjacent to the second scan line G2, and the control end of the second switch transistor T2 is electrically connected with the other first scan line G1 adjacent to the second scan line G2. The output ends of the first switch transistor T1 and the second switch transistor T2 are both electrically connected with the corresponding second scan line G2, since the two switch transistors are in parallel, that is, the first switch transistor T1 and the second switch transistor T2, so that when any one of the switch transistors is turned on, the second scan line G2 is in communication with the third scan line V+ to receive the second scan signal.

[0057] The control end of the first switch transistor T1 is electrically connected with the previous first scan line G1, and the control end of the second switch transistor T2 is electrically connected with the next first scan line G1. Thus, when the previous first scan line G1 outputs the first scan signal to the first row of pixel units 10a, the first switch transistor T1 is turned on, and when the next first scan line G1 outputs the first scan signal to the first row of pixel units 10a, the second switch transistor T2 is turned on. This design allows the two switch transistors to independently control the activation of the second scan line G2 according to different signals of the first scan lines G1.

[0058] And the third scan line V+ can input a constant voltage, and the specific voltage value is determined according to the gray scale value to be displayed. Since the first scan signal is a square wave signal, the two switch transistors are turned on when the voltage is high and are turned off when the voltage is low, so that the timing of the second scan signal is consistent with the timing of the first scan signal.

[0059] The driving circuit further comprises a switching unit 30, the first scan line G1 and the second scan line G2 are both electrically connected with a scan driver 40, and the switching unit 30 is configured to control the driving circuit to switch between a first mode and a second mode.

[0060] In the first mode, the scan driver 40 transmits the first scan signal to the first scan line G1 row by row to start the odd row of pixel units and the two even rows of pixel units adjacent to the odd row of pixel units; the display panel realizes the HSR display mode, which activates the adjacent odd and even rows of pixel units at the same time, and uses interpolation or other techniques to smooth the transition, thereby reducing the sawtooth feeling in high-contrast pictures and improving the display effect.

[0061] In the case of the second mode, the scan driver 40 transmits the third scan signal to the first scan line G1 and the second scan line G2 row by row to activate the pixel units 10 row by row. The second mode is suitable for standard display requirements, directly activating all pixel units 10 row by row through independent scan lines (the first scan line G1 and the second scan line G2), such as daily video playing, text display, etc., in which row-by-row scanning is sufficient to meet the requirements of display quality.

[0062] One end of the first scan line G1 and the second scan line G2 can be connected to the scan driver 40, which activates the first scan line G1 and the second scan line G2 row by row, thereby realizing the second mode. The switching unit 30 can connect the second scan line G2 to the control unit 20, thereby realizing the first mode. The switching unit 30 allows flexible switching between the two modes according to the current display requirements or optimization targets. This increases the flexibility and adaptability of the driving circuit, enabling it to cope with different application scenarios and display requirements.

[0063] The second scan signal is provided with a third switch transistor T3, which is located between the connection point of the scan driver 40 and the control unit 20, and the control end of the third switch transistor T3 is electrically connected to the switching unit 30. The switching unit 30 can directly control the switching state of the third switch transistor T3. When the driving circuit needs to switch to different working modes (such as the first mode or the second mode), the switching unit 30 will send a control signal to the third switch transistor T3. If the third switch transistor T3 is closed (i.e. not conducting), the scan driver 40 cannot send the third scan signal to the control unit 20; if the third switch transistor T3 is open (i.e. conducting), the scan driver 40 can normally send the third scan signal to the control unit 20, thereby allowing the second row of pixel units 10b to be activated by the third scan signal.

[0064] The control unit 20 is provided with a fourth switch transistor T4, which is located between the input end of the first switch transistor T1 and the third scan line V+, and the control end of the fourth switch transistor T4 is electrically connected to the switching unit 30. The switching unit 30 can also control the switching state of the fourth switch transistor T4. When the driving circuit is in a mode that does not require the control unit 20 to work (such as the second mode), the switching unit 30 can close the fourth switch transistor T4, thereby blocking the third scan line V+ from transmitting the scan signal to the second scan line G2. In the mode that requires the control unit 20 to work (such as the first mode), the switching unit 30 will open the fourth switch transistor T4, allowing the signal of the third scan line V+ to be normally transmitted to the input ends of the first switch transistor T1 and the second switch transistor T2.

[0065] In other embodiments, a fourth switch transistor T4 can also be arranged between the control terminals of the first switch transistor T1 and the second switch transistor T2 and the first scan line G1, so that the signal flow on the first scan line G1 can be controlled more directly. This helps to reduce signal interference and false triggering, and improves the stability and reliability of the circuit. The present application does not limit this.

[0066] The switching unit 30 includes a first control line X1 and a second control line X2, each third switch transistor T3 is connected to the first control line X1, and each fourth switch transistor T4 is connected to the second control line X2.

[0067] Specifically, the first control line X1 outputs a high level, and the second control line X2 outputs a low level to control the driving circuit to switch to the first mode; because the first control line X1 outputs a high level, the third switch transistor T3 is activated (turned on). This means that the second scan line G2 is turned on between the scan driver 40, allowing the scan driver 40 to send the third scan signal to the second scan line G2. Because the second control line X2 outputs a low level, the fourth switch transistor T4 is closed (not conductive). This disconnects the input terminals of the first switch transistor T1 and the second switch transistor T2 from the third scan signal. Thus, in the first mode, all pixel units 10 are scanned row by row by the scan driver 40.

[0068] The first control line X1 outputs a low level, and the second control line X2 outputs a high level to control the driving circuit to switch to the second mode. Because the first control line X1 outputs a low level, the third switch transistor T3 is closed (not conductive). This blocks the circuit path related to the second scan line G2 from the scan driver 40, preventing the scan driver 40 from sending the third scan signal to the second scan line G2. Because the second control line X2 outputs a high level, the fourth switch transistor T4 is activated (turned on). The input terminals of the first switch transistor T1 and the second switch transistor T2 are turned on with the third scan signal, which allows the conductive disconnect of the first switch transistor T1 and the second switch transistor T2 to be controlled by the signal flow of the first scan line G1. Thus, in the second mode, the scan driver 40 outputs the first scan signal to the first scan line G1, thereby controlling the odd row pixel units to be activated row by row, and when any one of the odd row pixel units is activated, the third scan line V+ outputs the second scan signal to the second scan line G2, thereby controlling the two even row pixel units adjacent to the activated odd row pixel units.

[0069] In addition, the present application also provides a driving method, which is applied to the driving circuit described above, as shown in Figure 4 The driving method includes:

[0070] Step S10, obtaining first image data corresponding to the first row of pixel units according to the original image data, the first image data including timing information and a target gray scale value N;

[0071] In this step, the system first extracts the first image data related to the first row of pixel units according to the original image data. These data include timing information and a target gray scale value N, the timing information is used to determine when to send a scanning signal to the scanning line, and the target gray scale value N specifies the brightness level that the pixel unit should display.

[0072] Step S20, in the case that the display mode of the display panel is HSR, according to the timing information, inputting a first scanning signal to the first scanning line in a preset time period to start the corresponding first row of pixel units to display a first gray scale value N1;

[0073] When the display panel is in the HSR display mode, the system will input a first scanning signal to the first scanning line in a preset time period according to the timing information obtained in step S10. This signal is used to start the corresponding first row of pixel units and make them display the first gray scale value N1. It should be noted that although there may be errors in actual application, the first gray scale value N1 displayed by the first row of pixel units remains consistent with the target gray scale value N.

[0074] Step S30, in the case that any of the first row of pixel units displays the first gray scale value N1, the control unit inputs a second scanning signal to the second scanning line to start the second row of pixel units to display a second gray scale value N2, among any two adjacent first row of pixel units and M rows of second row of pixel units therebetween;

[0075] Wherein, M is a positive integer, N2=i*N1 / (M+1); i is the number of the second row of pixel units, the label of the second row of pixel units increases along the direction close to the started first row of pixel units, i is a positive integer.

[0076] According to the given formula N2=i*N1 / (M+1), the gray scale value that each second row of pixel units should display can be calculated. Taking the case that two adjacent first row of pixel units can be provided with 3 second row of pixel units, forming a unit group consisting of 5 rows of pixel units (represented by 2n+1 to 2n+5 rows, where n is a natural number representing the position of the unit group in the overall pixel array) as an example. In the second mode (corresponding to the HSR display mode of the display panel), when any first scanning line (for example, the one connecting the 2n+1 row of first row of pixel units) transmits a first scanning signal to start the corresponding first row of pixel units to display a first gray scale value N1, the control units in the adjacent 3 rows of second row of pixel units (2n+2 row, 2n+3 row, 2n+4 row) will receive a trigger signal.

[0077] When the first gray scale value N1 is displayed in the 2n+1 row, based on the 2n+1 row pixel unit, the gray scale value N21=3*N1 / 4 displayed by the 2n+2 row pixel unit, the gray scale value N22=N1 / 2 displayed by the 2n+3 row pixel unit, and the gray scale value N23=N1 / 4 displayed by the 2n+4 row pixel unit.

[0078] When the first gray scale value N1' is displayed in the 2n+5 row, based on the 2n+5 row pixel unit, the gray scale value N21'=N1' / 4 displayed by the 2n+2 row pixel unit, the gray scale value N22'=N1' / 2 displayed by the 2n+3 row pixel unit, and the gray scale value N23'=3*N1' / 4 displayed by the 2n+4 row pixel unit.

[0079] In one display period, the first gray scale value N1 is displayed in the 2n+1 row, the gray scale value N2=N21+N21'=3N1 / 4+N1' / 4 displayed by the 2n+2 row pixel unit, the gray scale value N3=N22+N22'=N1 / 2+N1' / 2 displayed by the 2n+3 row pixel unit, the gray scale value N4=N23+N23'=N1 / 4+3*N1' / 4 displayed by the 2n+4 row pixel unit, and the first gray scale value N1' is displayed in the 2n+5 row.

[0080] Wherein the 2n+5 row pixel unit also serves as the start of the next display unit, that is, any first row pixel unit is started, and the plurality of second pixel units adjacent to both sides thereof are also started. Thus, the adjacent three rows of second row pixel units (2n+2 row, 2n+3 row, 2n+4 row) realize the gradual transition from the 2n+1 row pixel unit to the 2n+5 row pixel unit, that is, by assigning the second row pixel unit with an interpolation gray scale value based on the gray scale value of the first row pixel unit, a smoother image transition can be realized, especially when displaying a high-contrast image. Not only the delicacy of the image is improved, but also the image quality in the HSR display mode is improved.

[0081] Taking the first row pixel unit as the odd row pixel unit and the second row pixel unit as the even row pixel unit as an example for description.

[0082] The driving method comprises: dividing the original image data into odd frame image data and even frame image data; starting the first row pixel unit with the odd frame image data as the first image data in a first frame display period; starting the first row pixel unit with the even frame image data as the first image data in a second frame display period; wherein the first frame display period and the second frame display period are adjacent two frame display periods.

[0083] The time sequence information and the target gray scale value N related to the first row of pixel units are extracted from the original image data. The data are divided into odd frames and even frames in time sequence, and each frame contains a part of image data. Specifically, the image data corresponding to the odd row of pixel units is odd frame image data, and the image data corresponding to the even row of pixel units is even frame image data.

[0084] In the first frame display period, the first scanning signal is input to the first scanning line according to the odd frame image data, and the first row of pixel units is started to display the first gray scale value N1. In the second frame display period, the above process is repeated using the even frame image data to update or maintain the display state of the first row of pixel units.

[0085] By dividing the original image data into odd frames and even frames, the refresh rate of the display panel is improved without increasing the amount of additional data.

[0086] In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like refer to the orientation or positional relationship based on the drawings described, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0087] The above disclosure is only one preferred embodiment of the present application, and of course cannot limit the scope of the present application. Those skilled in the art can understand that the implementation of all or part of the above-mentioned embodiments, and the equivalent changes made according to the claims of the present application, still belong to the scope covered by the present application.

Claims

1. A driving circuit applied to a display panel, characterized in that, The display panel comprises a plurality of pixel units arranged in a periodic array along a first direction and a second direction, in the second direction, a plurality of rows of pixel units comprise a first row of pixel units and a second row of pixel units, and M rows of the second row of pixel units are arranged between every two adjacent first rows of pixel units; the driving circuit comprises: a plurality of first scan lines and second scan lines extending along the second direction, each row of the first row of pixel units being connected to a corresponding first scan line, each row of the second row of pixel units being connected to a corresponding second scan line, the first scan lines and the second scan lines being arranged alternately, the first row of pixel units being odd rows of pixel units, and the second row of pixel units being even rows of pixel units; a controller electrically connected to the second scan lines, the controller being configured to, in any two adjacent rows of the first row of pixel units and M rows of the second row of pixel units, in the case that a first scan signal is transmitted on any first scan line to start the corresponding first row of pixel units to display a first gray scale value N1, the controller is further configured to input a second scan signal to the second scan line, the second scan signal being used to start the second row of pixel units to display a second gray scale value N2, N2 = i*N1 / (M+1); wherein M is a positive integer, i is the number of the second row of pixel units, the label of the second row of pixel units increases in the direction close to the started first row of pixel units, and i is a positive integer; the driving circuit further comprises a switching unit, the first scan lines and the second scan lines are electrically connected to a scan driver, and the switching unit is configured to control the driving circuit to switch between a first mode and a second mode; in the case of the first mode of the driving circuit, the scan driver transmits a first scan signal to the first scan lines row by row to start the odd rows of pixel units and two adjacent even rows of pixel units of the odd rows of pixel units; in the case of the second mode of the driving circuit, the scan driver transmits a third scan signal to the first scan lines and the second scan lines row by row to start the pixel units row by row.

2. The drive circuit according to claim 1, characterized in that, the controller comprises a plurality of control units, each second scan line being electrically connected to a corresponding control unit, the control unit comprising a first switch transistor and a second switch transistor arranged in parallel, the input ends of the first switch transistor and the second switch transistor being electrically connected to a third scan line, and the output ends of the first switch transistor and the second switch transistor being electrically connected to a corresponding second scan line; the control end of the first switch transistor is electrically connected to one of the first scan lines adjacent to the second scan line, and the control end of the second switch transistor is electrically connected to another of the first scan lines adjacent to the second scan line.

3. The drive circuit according to claim 2, characterized in that, a third switch transistor is arranged on the second scan signal, the third switch transistor being located between the connection point of the scan driver and the control unit, and the control end of the third switch transistor being electrically connected to the switching unit.

4. The drive circuit according to claim 3, characterized in that, The control unit is provided with a fourth switch transistor, which is located between the input end of the first switch transistor and the third scan line, and the control end of the fourth switch transistor is electrically connected with the switching unit.

5. The drive circuit according to claim 4, characterized in that, The switching unit comprises a first control line and a second control line, each of the third switch transistors is connected to the first control line, and each of the fourth switch transistors is connected to the second control line. The first control line is used to output a low level, and the second control line is used to output a high level to control the driving circuit to switch to the first mode; the first control line is used to output a high level, and the second control line is used to output a low level to control the driving circuit to switch to the second mode.

6. A display panel, characterized by, The display panel comprises a plurality of pixel units arranged in an array and the driving circuit according to any one of claims 1 to 5, and pixel units in the same row are connected to the same scan line.

7. A driving method, comprising: The driving method is applied to the driving circuit according to any one of claims 1 to 5, and the driving method comprises: obtaining first image data corresponding to the first row of pixel units according to original image data, the first image data comprising timing information and a target gray scale value N; in the case that the display mode of the display panel is HSR, inputting a first scan signal to the first scan line at a preset time period according to the timing information to start the corresponding first row of pixel units to display a first gray scale value N1; in the case that any first row of pixel units in any two adjacent rows of the first row of pixel units and M rows of the second row of pixel units display the first gray scale value N1, inputting a second scan signal to the second scan line to start the second row of pixel units to display a second gray scale value N2, N2 = i*N1 / (M+1); wherein M is a positive integer, i is the number of the second row of pixel units, the number of the second row of pixel units increases along the direction close to the started first row of pixel units, and i is a positive integer.

8. The driving method according to claim 7, wherein The driving method further comprises: dividing the original image data into odd frame image data and even frame image data; in a first frame display period, starting the first row of pixel units with the odd frame image data as the first image data; in a second frame display period, starting the first row of pixel units with the even frame image data as the first image data; wherein the first frame display period and the second frame display period are two adjacent frame display periods.

Images