Pixel and display device including same

Abstract

The invention provides a pixel and a display device including the same. A pixel according to an aspect of the present invention includes: a first transistor outputting a driving current corresponding to a magnitude of a data voltage at an output terminal; a second transistor connected between a gate of the first transistor and a data line; a third transistor connected between the first transistor and the second transistor; a fourth transistor connected between the first transistor and a driving voltage line; the light emitting diode is connected with the first transistor; a first capacitor connected between a gate of the first transistor and the third transistor; and a second capacitor connected between the third transistor and the driving voltage line.

Description

Technical Field

[0001] The invention relates to a pixel for internal compensation of a display and a display device comprising the pixel. Background Art

[0002] The display device may include pixels, each of which may include a capacitor, a light emitting element, and a transistor driving the light emitting element. Summary of the invention

[0003] The present invention provides a display device that improves image quality by compensating for a threshold voltage of a driving transistor constituting a pixel circuit.

[0004] The problems to be solved by the present disclosure are not limited to the problems mentioned above, and ordinary technicians can clearly understand other technical problems not mentioned from the following records.

[0005] According to a preferred embodiment of the present invention, a pixel may include: a first transistor, which outputs a driving current corresponding to the size of a data voltage to an output terminal; a second transistor, which is connected between a gate of the first transistor and a data line; a third transistor, which is connected between the first transistor and the second transistor; a fourth transistor, which is connected between the first transistor and a driving voltage line; a light emitting diode, which is connected to the first transistor; a first capacitor, which is connected between the gate of the first transistor and the third transistor; and a second capacitor, which is connected between the third transistor and the driving voltage line.

[0006] In one embodiment, the pixel may further include: a fifth transistor connected between the first electrode of the light emitting diode and the second electrode of the light emitting diode.

[0007] In one embodiment, the pixel operates in a non-luminous interval and a luminous interval during a frame interval, and the non-luminous interval may include: a write interval, in which the third transistor, the fourth transistor and the fifth transistor are turned off, and the second transistor is turned on, thereby applying a data signal from the data line to the gate of the first transistor; and a first interval, and before the write interval, the second transistor, the third transistor and the fifth transistor are turned on, and the fourth transistor is turned off, thereby applying an initialization voltage from the data line to the gate of the first transistor.

[0008] In one embodiment, during the light emitting interval, the second transistor, the third transistor, and the fifth transistor may be turned off, and the fourth transistor may be turned on.

[0009] In one embodiment, the light emitting interval may include: a second interval, and after the writing interval, the third transistor is turned on.

[0010] In one embodiment, the pixel may further include a third capacitor connected between the driving voltage line and a first node, wherein the first node may be a node where the first transistor and the third transistor are connected.

[0011] In one embodiment, the pixel may further include: a fourth capacitor connected between the gate of the second transistor and a second node, wherein the second node may be a node where the first capacitor and the second capacitor are connected.

[0012] In one embodiment, the voltage supplied to the initialization voltage line may be a voltage supplied to the second electrode of the light emitting diode.

[0013] In one embodiment, the voltage supplied to the initialization voltage line may be a voltage different from a voltage supplied to the second electrode of the light emitting diode.

[0014] In one embodiment, the non-luminescent interval may further include: a third interval, after the writing interval and before the second interval, the second transistor, the third transistor and the fourth transistor are turned off.

[0015] In one embodiment, in the third interval, the timing at which the first gate signal transitions from the gate-off voltage to the gate-on voltage may be earlier than the timing at which the second gate signal transitions from the gate-on voltage to the gate-off voltage.

[0016] In one embodiment, the third interval may be shorter than the first interval and the second interval.

[0017] According to a preferred embodiment of the present invention, a display device may include: a plurality of pixels; a gate driving circuit for supplying gate signals to the pixels; and a data driving circuit for supplying data signals to the pixels, wherein each of the plurality of pixels may include: a first transistor for supplying a driving current corresponding to the magnitude of a data voltage to an output terminal; a second transistor including a gate connected to a first gate line and connected between the gate of the first transistor and a data line; a third transistor including a gate connected to a second gate line and connected between the first transistor and the second transistor; a fourth transistor including a gate connected to a third gate line and connected between the first transistor and a driving voltage line; a light emitting diode connected to the first transistor; a first capacitor connected between the gate of the first transistor and the third transistor; and a second capacitor connected between the third transistor and the driving voltage line.

[0018] In one embodiment, each of the plurality of pixels may further include: a fifth transistor including a gate connected to the first gate line and connected between the first electrode of the light emitting diode and the second electrode of the light emitting diode.

[0019] In one embodiment, in a first interval of a frame interval, the gate driving circuit may supply a first gate signal to the first gate line to turn on the second transistor and the fifth transistor, and supply a second gate signal to the second gate line to turn on the third transistor, and in a write interval of the frame interval, the gate driving circuit may supply the first gate signal to the first gate line to turn on the second transistor, in the first interval, the data driving circuit supplies an initialization voltage to the data line, and in the write interval, the data driving circuit supplies a data signal to the data line.

[0020] In one embodiment, during the light emitting period of the frame period, the gate driving circuit may supply a third gate signal to the third gate line to turn on the fourth transistor.

[0021] In one embodiment, the light emitting interval may include: a second interval, after the writing interval, the third transistor is turned on, wherein in the second interval, the gate driving circuit supplies a second gate signal to the second gate line to turn on the third transistor.

[0022] In one embodiment, each of the pixels may further include: a third capacitor connected between the driving voltage line and a first node, wherein the first node may be a node where the first transistor and the third transistor are connected.

[0023] In one embodiment, each of the pixels may further include: a fourth capacitor connected between the first gate line and a second node, wherein the second node may be a node where the first capacitor and the second capacitor are connected.

[0024] In one embodiment, the frame interval may further include: a third interval, after the writing interval and before the second interval, the second transistor, the third transistor and the fourth transistor are turned off.

[0025] According to the above technical solution of the present disclosure, a display device can be provided which improves image quality by compensating for the threshold voltage of a driving transistor constituting a pixel circuit.

[0026] According to the above technical solution of the present disclosure, the circuit driving speed can be improved and the display panel can be displayed at a high resolution by appropriately configuring the number of transistors and capacitors in the pixel circuit.

[0027] The effects of the present disclosure are not limited to the above-mentioned effects, and those skilled in the art can clearly understand other effects not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. 1 is a diagram schematically showing a display device according to an embodiment of the present invention.

[0029] Figure 2 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0030] Figure 3 is a diagram showing driving signals of a pixel circuit according to an embodiment of the present invention.

[0031] Figure 4a and Figure 4b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram showing the driving of the circuit in the first interval.

[0032] Figure 5a and Figure 5b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram showing driving of the circuit in the writing interval is shown.

[0033] Figure 6a and Figure 6b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram showing driving of the circuit in the third interval.

[0034] Figure 7 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0035] Figure 8 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0036] Figure 9a and Figure 9b It is used to illustrate an embodiment of the present invention. Figure 8 A diagram showing the driving of the circuit in the first interval.

[0037] Fig.10a and Fig.10b It is used to illustrate an embodiment of the present invention. Figure 8 A diagram showing driving of the circuit in the writing interval is shown.

[0038] Fig.11a and Fig.11b It is used to illustrate an embodiment of the present invention. Figure 8A diagram showing driving of the circuit in the fourth interval.

[0039] Fig.12a and Figure 12b It is used to illustrate an embodiment of the present invention. Figure 8 A diagram showing driving of the circuit in the third interval.

[0040] Fig.13 FIG. 1 is a diagram showing an embodiment of the present invention. Figure 3 The diagram shows a case where the driving signal has a skew rate.

[0041] Fig.14 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0042] Fig.15 is a diagram showing driving signals of a pixel circuit according to an embodiment of the present invention.

[0043] Description of Reference Numerals PX: Pixel PC: Pixel Circuit ED: Light Emitting Diode T1~T5: Transistor C1, C2: capacitors DL: Data Line GL1~GL3: Gate lines ELVDD: driving voltage line VIL: Initialization voltage line N1, N2, G: nodes DETAILED DESCRIPTION

[0044] The present invention can be subjected to various transformations and has various embodiments, so specific embodiments will be illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods for achieving them will become clear with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0045] In the following embodiments, terms such as “first” and “second” are used to distinguish one component from other components and are not used in a limiting sense.

[0046] In the following embodiments, unless the context clearly means otherwise, an expression in the singular includes an expression in the plural.

[0047] In the following embodiments, the terms such as “including” or “having” refer to the presence of the features or constituent elements described in the specification, and do not preclude the possibility of adding one or more other features or constituent elements.

[0048] In this specification, "A and / or B" means A, B, or both A and B. In addition, in this specification, "at least one of A and B" means A, B, or both A and B.

[0049] In the following embodiments, when it is mentioned that X and Y are connected, it can include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Among them, X and Y can be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the drawings or detailed descriptions, and also includes connection relationships other than the connection relationships shown in the drawings or detailed descriptions.

[0050] For example, the case where X and Y are electrically connected may include the case where one or more elements (eg, switches, transistors, capacitors, inductors, resistors, diodes, etc.) capable of electrically connecting X and Y are connected between X and Y.

[0051] In the following embodiments, "ON" used in association with the state of an element may refer to the activated state of the element, and "OFF" may refer to the inactivated state of the element. "ON" used in association with a signal received by an element may refer to a signal that activates the element, and "OFF" may refer to a signal that deactivates the element. An element may be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low level voltage, and an N-channel transistor (N-type transistor) is activated by a high level voltage. Therefore, the "ON" voltage for a P-type transistor and an N-type transistor should be understood as opposite (low to high) voltage levels.

[0052] In the following embodiments, the x direction, y direction, and z direction are not limited to directions along the three axes on the vertical coordinate system, and can be interpreted as including the broad meaning thereof. For example, the x direction, y direction, and z direction can be perpendicular to each other, but can also refer to different directions that are not perpendicular to each other.

[0053] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals and repeated description thereof will be omitted.

[0054] Figure 1 FIG. 1 is a diagram schematically showing a display device according to an embodiment of the present invention.

[0055] Reference Figure 1 The display device 1 may include a pixel portion 11 , a gate driving circuit 12 , a data driving circuit 13 and a controller 14 .

[0056] A plurality of pixels PX and signal lines capable of applying electric signals to the plurality of pixels PX may be arranged in the pixel portion 11. The pixel portion 11 may be a display region that displays an image.

[0057] A plurality of pixels PX may be repeatedly arranged in a first direction (x direction, row direction) and a second direction (y direction, column direction). A plurality of pixels PX may be arranged in a plurality of forms such as stripe arrangement, diamond arrangement, mosaic arrangement, etc. and realize an image. Each of the plurality of pixels PX may include a light emitting diode as a display element, and the light emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. Hereinafter, a pixel circuit according to an embodiment of the present invention will be referred to Figure 2 This will be described later.

[0058] The signal lines capable of applying electrical signals to the plurality of pixels PX may include a plurality of gate lines GL extending along a first direction and a plurality of data lines DL extending along a second direction. The plurality of gate lines GL may be arranged spaced apart along the second direction and may transmit gate signals GS to the pixels PX. The plurality of data lines DL may be arranged spaced apart along the first direction and may transmit data signals DS to the pixels PX. Each of the plurality of pixels PX may be connected to at least one corresponding gate line of the plurality of gate lines GL and a corresponding data line of the plurality of data lines DL. Figure 1 In the figure, for the sake of convenience, a case where one gate line is connected to the pixel PX is shown, but each pixel PX may be connected to a plurality of gate lines according to the number of transistors constituting the pixel circuit.

[0059] The gate driving circuit 12 may be connected to a plurality of gate lines GL, and generate a gate signal corresponding to a control signal GCS from the controller 14, and sequentially supply the generated gate signal to the gate lines GL. The gate lines GL may be connected to the gates of transistors included in the pixels PX. The gate signal may be a gate control signal that controls the turning on and off of the transistors whose gates are connected to the gate lines GL. The gate signal may be a square wave signal including an on-voltage that enables the transistors to be turned on and an off-voltage that enables the transistors to be turned off.

[0060] The data driving circuit 13 may be connected to the plurality of data lines DL and supply data signals DS to the data lines DL corresponding to control signals DCS from the controller 14. The data driving circuit 13 may receive a gamma voltage GV corresponding to each gray level and image data DAT2 from the controller 14 and may generate data signals DS corresponding to the gray levels.

[0061] The controller 14 may generate a gate control signal GCS and a data control signal DCS based on a signal input from the outside. The controller 14 may supply the gate control signal GCS to the gate driving circuit 12 , and may supply the data control signal DCS to the data driving circuit 13 .

[0062] The controller 14 may convert input image data DAT1 input from the outside (e.g., a graphics processor) to generate image data DAT2. For example, the controller 14 may convert the input image data DAT1 in RGB format into image data DAT2 in a format that conforms to the pixel arrangement of the pixel unit 11. The controller 14 may be equipped with a storage unit in which a gamma voltage corresponding to a grayscale and correction data are recorded.

[0063] exist Figure 1 1 and 2 show a case where the data driving circuit 13 and the controller 14 are implemented independently of each other, but the present invention is not limited thereto. For example, the data driving circuit 13 and the controller 14 may be implemented as one IC (eg, a driver integrated circuit).

[0064] The display device 1 according to an embodiment of the present invention may be an organic light emitting display device, an inorganic light emitting display device (Inorganic Light Emitting Display or inorganic EL display device), a quantum dot light emitting display device (Quantum dot Light Emitting Display) or other display devices.

[0065] The display device 1 can be used not only for mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, portable electronic devices such as UMPCs (UltraMobile PCs), but also for TVs, laptops, monitors, billboards, IoT (Internet of Things) devices, and other products. In addition, the display device 1 according to an embodiment can be used for wearable devices such as smart watches, watch phones, glasses-type displays, and head mounted displays (HMDs). In addition, the display device 1 according to an embodiment can be used as a dashboard of a car, a center information display (CID) arranged on a center fascia or dashboard of a car, a room mirror display that replaces a side mirror of a car, and a display arranged on the back of a front seat as an entertainment device for a rear seat of a car.

[0066] Figure 2 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention. Figure 3 is shown for illustration Figure 2 A diagram of a signal showing the operation of a pixel. Figure 2 The pixel PX shown may be Figure 1 An embodiment of a pixel PX is shown.

[0067] Reference Figure 2, the pixel PX may include a light emitting diode ED as a display element (light emitting element) and a pixel circuit PC connected to the light emitting diode ED. In one embodiment, the light emitting diode ED may be an organic light emitting diode (OLED). The pixel PX may emit light such as red, green, blue or white through the light emitting diode ED. The pixel circuit PC may include a first transistor T1 to a fifth transistor T5 and a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor T2 to the fifth transistor T5 may be a switching transistor that transmits a signal. The first terminal (first electrode) of each of the first transistor T1 to the fifth transistor T5 may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, in the case where the first terminal is a source, the second terminal may be a drain. The node where the first transistor T1 is connected to the third transistor T3 may be defined as a first node N1, and the node where the first capacitor C1 is connected to the second capacitor C2 may be defined as a second node N2. In addition, the node connected to the gate of the first transistor T1 may be defined as a third node G.

[0068] In one embodiment, if Figure 2 As shown, the plurality of transistors included in the pixel circuit PC may be P-type silicon thin film transistors. In another embodiment, the plurality of transistors included in the pixel circuit PC may be N-type oxide thin film transistors. In another embodiment, a portion of the plurality of transistors included in the pixel circuit PC may be N-type oxide thin film transistors, and another portion may be P-type silicon thin film transistors.

[0069] The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO: Low Temperature Polycrystalline Oxide) thin film transistor containing oxide in the active pattern (semiconductor layer). However, this is only exemplary, and the N-type transistor is not limited thereto. For example, the active pattern (semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon (poly silicon)) or an organic semiconductor, etc. The silicon thin film transistor may be a low temperature polycrystalline silicon (LTPS: Low Temperature Poly-Silicon) thin film transistor containing amorphous silicon (amorphous silicon), polycrystalline silicon (polysilicon), etc. in the active pattern (semiconductor layer).

[0070] The pixel PX may be connected to a first gate line GL1 transmitting a first gate signal, a second gate line GL2 transmitting a second gate signal, and a third gate line GL3 transmitting a third gate signal. In one embodiment, the third gate signal may be referred to as a light emitting control signal, and the third gate line GL3 may be referred to as a light emitting control line. In addition, the pixel PX may be connected to a first gate line GL1 transmitting a first driving voltage VDD (refer to Fig.14 ), an initialization voltage line VIL for transmitting an initialization voltage, and a data line DL for transmitting a data signal. In one embodiment, the data line DL may be connected to a reference voltage line for transmitting a reference voltage to transmit the reference voltage.

[0071] The first driving voltage VDD (refer to Fig.14 ) may be higher than the second driving voltage VSS (refer to Fig.14 ). The voltage level of the reference voltage may be lower than the first driving voltage VDD (reference voltage). Fig.14 ) voltage level.

[0072] The first transistor T1 may be connected between the fourth transistor T4 and the light emitting diode ED. The first transistor T1 may include a gate, a first terminal connected to the first node N1, and a second terminal. The first terminal of the first transistor T1 may be connected to the driving voltage line ELVDD via the fourth transistor T4, and the second terminal may be connected to the pixel electrode of the light emitting diode ED. The first transistor T1 may receive a data signal through the data line DL according to the switching operation of the second transistor T2, thereby controlling the current amount of the driving current flowing to the light emitting diode ED.

[0073] The second transistor T2 may be connected between the gate of the first transistor T1 and the data line DL. The second transistor T2 may include a gate connected to the first gate line GL1, a first terminal connected to the data line DL, and a second terminal connected to the third node G. The second transistor T2 may be turned on by a first gate signal transmitted to the first gate line GL1, thereby electrically connecting the data line DL to the third node G, and transmitting the data signal transmitted to the data line DL to the third node G connected to the gate of the first transistor T1. In one embodiment, when the data line DL is connected to the reference voltage line, the second transistor T2 may also be turned on by the first gate signal, thereby transmitting the reference voltage to the third node G connected to the gate of the first transistor T1.

[0074] The third transistor T3 may be connected between the first terminal of the first transistor T1 and the first capacitor C1. The third transistor T3 may include a gate connected to the second gate line GL2, a first terminal connected to the first node N1, and a second terminal connected to the first capacitor C1. In one embodiment, the third transistor T3 may be turned on by a second gate signal transmitted to the second gate line GL2, thereby connecting the first node N1 to the second node N2.

[0075] The fourth transistor T4 may be connected between the driving voltage line ELVDD and the first terminal of the first transistor T1. The fourth transistor T4 may include a gate connected to the third control line GL3, a first terminal connected to the driving voltage line ELVDD, and a second terminal connected to the first node N1. The fourth transistor T4 may be turned on or off according to a control signal transmitted to the third gate line GL3.

[0076] The fifth transistor T5 may be connected between the second terminal of the first transistor T1 and an initialization voltage line VIL for supplying an initialization voltage. In one embodiment, the initialization voltage line VIL may receive a second driving voltage VSS (refer to Fig.14 ). The fifth transistor T5 may include a gate connected to the first gate line GL1, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the initialization voltage line VIL. The fifth transistor T5 may be turned on or off by a first gate signal transmitted to the first gate line GL1.

[0077] The first capacitor C1 may be connected between the second terminal of the third transistor T3 and the gate of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the third node G, and the second electrode may be connected to the second node N2. The first capacitor C1, as a storage capacitor, may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal.

[0078] The second capacitor C2 may be connected between the driving voltage line ELVDD and the third transistor T3. A first electrode of the second capacitor C2 may be connected to the driving voltage line ELVDD, and a second electrode may be connected to the second node N2. The capacitance of the first capacitor C1 may be greater than that of the second capacitor C2.

[0079] The light emitting diode ED may be connected to the first transistor T1. The light emitting diode ED may include a pixel electrode (anode) connected to the second terminal of the first transistor T1 and an opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive a second driving voltage VSS (refer to Fig.14 ). The counter electrode may be a common electrode shared by a plurality of pixels PX.

[0080] The pixel PX can display an image in each frame interval. Figure 3 , a frame interval may include a non-light-emitting interval in which the pixel PX does not emit light and a light-emitting interval EP in which the pixel PX emits light. The non-light-emitting interval may include a first interval P1 and a second interval P2, and the light-emitting interval EP may include a third interval P3.

[0081] Each of the first gate signal G1, the second gate signal G2, and the third gate signal G3 may have a high level voltage during a portion of the interval, and may have a low level voltage during a portion of the interval. The high level voltage of the first gate signal G1, the second gate signal G2, and the third gate signal G3 may be a cut-off voltage that turns off the transistor, and the low level voltage may be a turn-on voltage that turns on the transistor.

[0082] Figure 4a and Figure 4b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram showing the driving of the circuit in the first interval.

[0083] The first interval P1 may be an initialization interval for initializing the gate electrode of the first transistor T1 and the pixel electrode of the light emitting diode ED and a compensation interval for compensating for a threshold voltage of the first transistor T1. The first interval P1 may be approximately one horizontal period (1H).

[0084] Reference Figure 4a and Figure 4b In the first interval P1, a first gate signal G1 of a gate-on voltage may be supplied to the first gate line GL1, and a second gate signal G2 of a gate-on voltage may be supplied to the second gate line GL2. A third gate signal G3 of a gate-off voltage may be supplied to the third gate line GL3. A reference voltage Vref may be supplied to the data line DL. The reference voltage Vref may be an initialization voltage for initializing the gate of the first transistor T1.

[0085] The second transistor T2 and the fifth transistor T5 can be turned on by the first gate signal G1, and the third transistor T3 can be turned on by the second gate signal G2. The reference voltage Vref can be transmitted to the third node G (i.e., the gate of the first transistor T1) through the turned-on second transistor T2, and the second driving voltage VSS (reference Fig.14) can be transmitted to the pixel electrode of the light emitting diode ED through the turned-on fifth transistor T5, and the first transistor T1 can be turned on. If the voltage between the first terminal of the first transistor T1 and the second node N2 reaches the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. And, the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be charged to the first capacitor C1. In the first interval P1, the voltage of the third node G can be initialized to the reference voltage Vref, the voltage of the second node N2 can be initialized to Vref-Vth, and the pixel electrode of the light emitting diode ED can be initialized to the second driving voltage VSS (reference voltage VSS). Fig.14 ).

[0086] Figure 5a and Figure 5b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram of driving the circuit in the second interval is shown.

[0087] The second interval P2 may be a writing interval in which the data signal DATA is transmitted to the gate of the first transistor T1. The second interval P2 may be approximately one horizontal period (1H).

[0088] Reference Figure 5a and Figure 5b In the second interval P2, the first gate signal G1 of the gate-on voltage may be supplied to the first gate line GL1, the second gate signal G2 of the gate-off voltage may be supplied to the second gate line GL2, and the third gate signal G3 of the gate-off voltage may be supplied to the third gate line GL3. The data signal DATA may be supplied to the data line DL.

[0089] The second transistor T2 and the fifth transistor T5 may be turned on by the first gate signal G1. At this time, the third transistor T3 and the fourth transistor T4 may be turned off by the second gate signal G2 and the third gate signal G3 of the gate-off voltage. The second transistor T2 may transmit the data voltage (Vdata) corresponding to the data signal DATA from the data line DL to the third node G (i.e., the gate of the first transistor T1). Thus, the voltage of the third node G may be changed from the reference voltage Vref to the data voltage (Vdata). At this time, the voltage (Vn2) of the second node N2 may also be changed corresponding to the voltage change amount (Vdata-Vref) of the third node G. The voltage (Vn2) of the second node N2 may be a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacity ratio (α=C1 / (C1+C2)) of the first capacitor C1 and the second capacitor C2. Thus, in the second interval P2, the voltage (Vn2) of the second node N2 may be as shown in the following formula (1), and the data voltage (Vdata) corresponding to the data signal DATA of the first transistor T1 may be charged to the first capacitor C1.

[0090] Vn2(P2)=Vref-Vth+α×(Vdata-Vref)=Vref-Vth+{(C1 / (C1+C2)}×(Vdata-Vref)……(1) Figure 6a and Figure 6b It is used to illustrate an embodiment of the present invention. Figure 2 A diagram showing driving of the circuit in the third interval.

[0091] The light emitting interval EP may be a period during which the light emitting diode ED emits light. The light emitting interval EP may include a third interval P3. The third interval P3 may be approximately one horizontal period (1H).

[0092] Reference Figure 6a and Figure 6b In the third interval P3, the second gate signal G2 of the gate-on voltage may be supplied to the second gate line GL2, and the third gate signal G3 of the gate-on voltage may be supplied to the third gate line GL3. The first gate signal G1 of the gate-off voltage may be supplied to the first gate line GL1. In this case, the third gate signal G3 may be a light emitting control signal.

[0093] The second transistor T2 and the fifth transistor T5 can be turned off by the first gate signal G1. The third transistor T3 and the fourth transistor T4 can be turned on by the second gate signal G2 and the third gate signal G3. Thus, the first driving voltage VDD (refer to Fig.14) may be supplied to the first terminal of the first transistor T1, so that the first transistor T1 may be turned on. Since the third transistor T3 and the fourth transistor T4 are turned on, in the third interval P3, the voltage (Vn2) of the second node N2 may be changed to the first driving voltage VDD (refer to Fig.14 ). The voltage (Vg) of the third node G is a value obtained by adding the voltage change of the second node N2 in the third interval P3 and the second interval P2 (Vn2 (P3) - Vn2 (P2)) to the voltage (Vg (P2)) of the third node G in the second interval P2. If equation (1) is substituted into equation (2), it can be expressed as shown in the following equation (3).

[0094] Vg=Vg(P2)+Vn2(P3)-Vn2(P2) Vg=Vdata+VDD-Vn2(P2)……(2) Vg=Vdata+VDD-Vref+Vth-[{C1 / (C1+C2)}×Vdata+{C1 / (C1+C2)}×Vref]……(3) After the third interval P3, the second gate signal G2 of the gate-off voltage may be supplied to turn off the third transistor T3, and the voltage (Vn2) of the second node N2 may be maintained at the first driving voltage VDD (refer to Fig.14 ).

[0095] The first transistor T1 may output a driving current (Id∝(Vgs-Vth)) corresponding to a voltage stored in the first capacitor C1 (i.e., a voltage (Vgs-Vth) obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a gate-source voltage of the first transistor T1 (a voltage difference between the gate of the first transistor T1 and the first node N1) (Vgs=Vdata-Vref+Vth-α×(Vdata-Vref)) 2 ), the light emitting diode ED can emit light with a brightness corresponding to the magnitude of the driving current (Id) which is independent of the threshold voltage (Vth) of the first transistor T1.

[0096] Figure 7 is a diagram showing a pixel circuit of a pixel included in a display device according to an embodiment of the present invention.

[0097] Figure 7 The pixel circuit of the pixel shown can be in Figure 21. An embodiment of adding a third capacitor C3 to the pixel circuit of the pixel shown in FIG. The third capacitor C3 may be connected between the driving voltage line ELVDD and the third transistor T3. A first electrode of the third capacitor C3 may be connected to the driving voltage line ELVDD, and a second electrode may be connected to the first node N1. The capacitance of the first capacitor C1 may be greater than the capacitance of the third capacitor C3.

[0098] according to Figure 7 The pixel circuit of the pixel shown can adjust the voltages of the first node N1 and the second node N2 in the second interval P2 and the third interval P3, and can adjust the range of Vdata. For example, in the second interval P2, the voltage of the second node N2 can be changed to a voltage (Vref-Vth+β×(Vdata-Vref)) that varies according to the capacity ratio (β=C1 / (C1+C2+C3)) of the first capacitor C1, the second capacitor C2, and the third capacitor C3, and in the third interval P3, the voltage (Vg) of the third node G can be expressed as "Vg=Vdata+VDD-Vref+Vth-[{C1 / (C1+C2+C3)}×Vdata+{C1 / (C1+C2+C3)}×Vref])".

[0099] Figure 8 is a diagram showing a pixel circuit of a pixel included in a display device according to an embodiment of the present invention.

[0100] Figure 8 The pixel circuit of the pixel shown can be in Figure 2 An example of adding a third capacitor C3 to the pixel circuit of the pixel shown. Figure 8 The third capacitor C3 may be connected between the gate of the second transistor T2 and the second node N2. The first electrode of the third capacitor C3 may be connected to the first gate line GL1 connected to the gate of the second transistor T2, and the second electrode may be connected to the second terminal of the third transistor T3, the first capacitor C1, and the second capacitor C2. The capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2, and the capacitance of the second capacitor C2 may be greater than the capacitance of the third capacitor C3.

[0101] In this manual, for the Figure 7 The third capacitor C3 shown distinguishes, Figure 8 The third capacitor shown may also be denoted as fourth capacitor C4.

[0102] exist Figure 8 The pixel circuit of the pixel shown in the figure operates in one frame interval, and the fourth interval P4 can be added to Figure 3 The fourth interval P4 may be located between the second interval P2 and the third interval P3.

[0103] Figure 9a and Figure 9b It is used to illustrate the present invention according to an embodiment Figure 8 A diagram showing the driving of the circuit in the first interval.

[0104] The first interval P1 may be an initialization interval for initializing the gate electrode of the first transistor T1 and the pixel electrode of the light emitting diode ED and a compensation interval for compensating for a threshold voltage of the first transistor T1. The first interval P1 may be approximately one horizontal period (1H).

[0105] Reference Figure 9a and Figure 9b In the first interval P1, a first gate signal G1 of a gate-on voltage may be supplied to the first gate line GL1, a second gate signal G2 of a gate-on voltage may be supplied to the second gate line GL2, a third gate signal G3 of a gate-off voltage may be supplied to the third gate line GL3, and a reference voltage Vref may be supplied to the data line DL.

[0106] The second transistor T2 and the fifth transistor T5 may be turned on by the first gate signal G1, and the third transistor T3 may be turned on by the second gate signal G2. The gate of the third node G (i.e., the first transistor T1) may be initialized to the reference voltage Vref by the turned-on second transistor T2. The first node N1 (i.e., the pixel electrode of the light emitting diode ED) may be initialized to the initialization voltage by the turned-on third transistor T3. In the first interval P1, the voltage of the third node G may be Vref, the voltage of the second node N2 may become Vref-Vth, and the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be charged to the first capacitor C1.

[0107] Fig.10a and Fig.10b It is used to illustrate an embodiment of the present invention. Figure 8 A diagram of driving the circuit in the second interval is shown.

[0108] The second interval P2 may be a writing interval in which the data signal DATA is transmitted to the gate of the first transistor T1. The second interval P2 may be approximately one horizontal period (1H).

[0109] Reference Fig.10a and Fig.10b, in the second interval P2, the first gate signal G1 of the gate-on voltage may be supplied to the first gate line GL1, so that the second transistor T2 and the fifth transistor T5 may be turned on. At this time, the third transistor T3 and the fourth transistor T4 may be turned off by the second gate signal G2 and the third gate signal G3 of the gate-off voltage. The second transistor T2 may transmit the data voltage (Vdata) corresponding to the data signal DATA from the data line DL to the third node G (ie, the gate of the first transistor T1). Thus, the voltage of the third node G may be changed from the reference voltage Vref to the data voltage (Vdata). At this time, the voltage (Vn2) of the second node N2 may also be changed corresponding to the voltage change amount (Vdata-Vref) of the third node G. The voltage (Vn2) of the second node N2 may be changed to a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacity ratio (α=C1 / (C1+C2+C3)) of the first capacitor C1, the second capacitor C2, and the third capacitor C3. Thus, in the writing period P2 , the voltage ( Vn2 ) of the second node N2 is as shown in the following equation (4), and the data voltage (Vdata) corresponding to the data signal DATA of the first transistor T1 can be charged to the first capacitor C1 .

[0110] Vn2(P2)=Vref-Vth+α×(Vdata-Vref)=Vref-Vth+{(C1 / (C1+C2+C3)}×(Vdata-Vref)……(4) Fig.11a and Fig.11b It is used to illustrate an embodiment of the present invention. Figure 8 A diagram showing driving of the circuit in the fourth interval.

[0111] Reference Fig.11a and Fig.11b In the fourth interval P4, the first gate signal G1 of the gate-off voltage may be supplied to the first gate line GL1, the second gate signal G2 of the gate-off voltage may be supplied to the second gate line GL2, and the third gate signal G3 of the gate-off voltage may be supplied to the third gate line GL3.

[0112] The first transistor T1 to the fifth transistor T5 may be turned off by the first gate signal G1, the second gate signal G2, and the third gate signal G3 of the gate-off voltage. As the first gate signal G1 transitions from the gate-on voltage (G1_Vgh) to the gate-off voltage (G1_Vgl), the voltage of the first electrode of the third capacitor C3 connected to the first gate line GL1 may change by an amount corresponding to the voltage change amount (G1_Vgh-G1_Vgl) of the first gate signal G1, and the voltage (Vn2) of the second node N2 connected to the second electrode of the third capacitor C3 may change corresponding to the voltage change amount of the first gate signal G1.

[0113] In this case, in the fourth interval P4 , the voltage of the gate of the first transistor T1 may be the data voltage (Vdata), and the voltage (Vn2) of the second node N2 may be as shown in the following equation (5).

[0114] Vn2(P4)=Vn2(P2)+(amount of change in the voltage (Vn2) of the second node N2 between the second section P2 and the fourth section P4) Vn2(P4)=Vref-Vth+{C1 / (C1+C2+C3)}×(Vdata-Vref)+{C3 / (C1+C2+C3)}×(G1_Vgh-G1_Vg1)……(5) Fig.12a and Figure 12b FIG. 1 is a diagram showing an embodiment of the present invention. Figure 8 A view of the drive in the third interval of the circuit is shown.

[0115] Reference Fig.12a and Figure 12b In the third interval P3, the second gate signal G2 of the gate-on voltage may be supplied to the second gate line GL2, the third gate signal G3 of the gate-on voltage may be supplied to the third gate line GL3, and the first gate signal G1 of the gate-off voltage may be supplied to the first gate line GL1.

[0116] The second transistor T2 and the fifth transistor T5 can be turned off by the first gate signal G1. The third transistor T3 and the fourth transistor T4 can be turned on by the second gate signal G2 and the third gate signal G3. Thus, the first driving voltage VDD (refer to Fig.14 ) may be supplied to the first terminal of the first transistor T1, so that the first transistor T1 may be turned on. As the third transistor T3 and the fourth transistor T4 are turned on, in the third interval P3, the voltage (Vn2) of the second node N2 may be changed to the first driving voltage VDD (refer to Fig.14 ). The voltage (Vg) at the third node G may be expressed as follows:

[0117] Vg=Vg(P4)+Vn2(P3)-Vn2(P4) Vg=Vdata+VDD-Formula (5) Vg=Vdata+VDD-Vref+Vth-{C1 / (C1+C2+C3)}×(Vdata-Vref)-{C3 / (C1+C2+C3)}×(G1_Vgh-G1_Vg1)……(6) pass Figure 8 In the pixel shown in FIG. 1 , the gate voltage of the first transistor T1 reflects both the data voltage (Vdata) and the voltage according to the first gate signal G1 , thereby increasing the range of the data voltage. Figure 8 The data voltage generated by the pixel shown can be compared with the Figure 2 The pixel shown produces a data voltage increase of approximately 3V.

[0118] Fig.13 is a diagram showing gate signals according to an embodiment of the present invention.

[0119] Reference Fig.13 The first gate signal G1, the second gate signal G2, and the third gate signal G3 supplied by the gate driving circuit 12 may be signals whose rising edge and falling edge gradually change. The first gate signal G1, the second gate signal G2, and the third gate signal G3 may have a gradually rising rising edge and a gradually falling falling edge.

[0120] The gate drive circuit 12 can adjust the period of maintaining the gate on voltage by adjusting the rising slope and falling slope of the first gate signal G1, the second gate signal G2 and the third gate signal G3. The on time and off time of the transistor can be further finely adjusted by finely adjusting the first gate signal G1, the second gate signal G2 and the third gate signal G3. For example, Fig.13 As shown, the fourth interval P4 can be realized by adjusting the rising slope and falling slope of the first gate signal G1, the second gate signal G2, and the third gate signal G3. In this case, the fourth interval P4 can be shorter than the first interval P1, the second interval P2, and the third interval P3. For example, the fourth interval P4 can be shorter than about one horizontal period (1H). In the fourth interval P4, the timing of the first gate signal G1 transitioning from the gate-off voltage to the gate-on voltage can be earlier than the timing of the second gate signal G2 transitioning from the gate-on voltage to the gate-off voltage.

[0121] Fig.14 is a diagram showing an equivalent circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0122] Fig.14 The pixel circuit of the pixel shown is Figure 2 The difference of the pixel circuit of the pixel shown is that the initialization voltage line VIL connected with the fifth transistor T5 receives an initialization voltage (Vint) different from the second driving voltage VSS. The fifth transistor T5 may include a first terminal connected to the second terminal of the first transistor T1, a second terminal connected to the initialization voltage line VIL supplied with the initialization voltage (Vint), and a gate connected to the first gate line GL1. The initialization voltage (Vint) supplied to the initialization voltage line VIL may be a voltage lower than the second driving voltage VSS.

[0123] By supplying the initialization voltage from the fifth transistor T5 , the light emitting diode ED may be discharged, and the pixel electrode of the light emitting diode ED may be initialized to the initialization voltage (Vint).

[0124] Fig.15 is a diagram showing signals for driving a pixel circuit according to an embodiment of the present invention.

[0125] Reference Fig.15 According to an embodiment of the present invention, even if the second gate signal G2 is supplied as the gate-off voltage before the first interval P1 and after the third interval P3, the Figure 2 Although not shown, even if the second gate signal G2 is supplied as the gate-off voltage before the first interval P1 and after the third interval P3, the pixel circuit with the third capacitor C3 added Figure 8 The pixel circuit of the pixel shown may also perform Figure 9a and Figures 9b to 12a to Figure 12b The driver described in .

[0126] The steps of the method or algorithm described in connection with the embodiments of the present invention may be directly implemented by hardware, or may be implemented by a software module executed by hardware, or may be implemented by a combination thereof. The software module may reside in a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a hard disk, a removable hard disk, a read-only compact disk (CD-ROM), or any form of computer-readable recording medium known in the technical field to which the present invention belongs.

[0127] The embodiments of the present invention are described above with reference to the accompanying drawings, but those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing its technical ideas or essential features. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and are not restrictive.

Claims

1. A pixel comprising: A first transistor outputs a driving current corresponding to the magnitude of the data voltage; a second transistor connected between the gate of the first transistor and the data line; a third transistor connected between the first transistor and the second transistor; a fourth transistor connected between the first transistor and a driving voltage line; a light emitting diode connected to the first transistor; A first capacitor connected between the gate of the first transistor and the third transistor; as well as The second capacitor is connected between the third transistor and the driving voltage line.

2. The pixel according to claim 1, further comprising: The fifth transistor is connected between the first electrode of the light emitting diode and the initialization voltage line.

3. The pixel according to claim 2, wherein: The pixel operates in a non-luminous interval and a luminous interval during a frame interval, The non-luminous interval includes: In a writing interval, the third transistor, the fourth transistor, and the fifth transistor are turned off, and the second transistor is turned on, so that a data signal is applied from the data line to the gate of the first transistor; and In a first interval, before the writing interval, the second transistor, the third transistor, and the fifth transistor are turned on, and the fourth transistor is turned off, so that an initialization voltage is applied from the data line to the gate of the first transistor.

4. The pixel according to claim 3, wherein: In the light emitting interval, the second transistor, the third transistor, and the fifth transistor are turned off, and the fourth transistor is turned on.

5. The pixel according to claim 4, wherein: The light emitting interval includes: In the second interval, after the writing interval, the third transistor is turned on.

6. The pixel according to claim 5, further comprising: a third capacitor connected between the driving voltage line and the first node, The first node is a node where the first transistor and the third transistor are connected.

7. The pixel according to claim 5, further comprising: a fourth capacitor connected between the gate of the second transistor and the second node, The second node is a node where the first capacitor and the second capacitor are connected.

8. The pixel according to claim 2, wherein: The voltage supplied to the initialization voltage line is a voltage supplied to the second electrode of the light emitting diode.

9. The pixel according to claim 2, wherein: A voltage supplied to the initialization voltage line is a voltage different from a voltage supplied to the second electrode of the light emitting diode.

10. The pixel according to claim 7, wherein: The non-luminous interval also includes: In a third section, after the writing section and before the second section, the second transistor, the third transistor, and the fourth transistor are turned off.

11. The pixel according to claim 10, wherein: In the third interval, a timing at which the first gate signal transitions from the gate-off voltage to the gate-on voltage is earlier than a timing at which the second gate signal transitions from the gate-on voltage to the gate-off voltage.

12. The pixel according to claim 10, wherein: The third interval is shorter than the first interval and the second interval.

13. A display device, comprising: Multiple pixels; A gate driving circuit supplies a gate signal to the pixel; as well as a data driving circuit for supplying a data signal to the pixel; Wherein, each of the plurality of pixels comprises: A first transistor outputs a driving current corresponding to the magnitude of the data voltage; a second transistor including a gate connected to the first gate line and connected between the gate of the first transistor and the data line; a third transistor including a gate connected to the second gate line and connected between the first transistor and the second transistor; a fourth transistor, comprising a gate connected to the third gate line, and connected between the first transistor and the driving voltage line; a light emitting diode connected to the first transistor; A first capacitor connected between the gate of the first transistor and the third transistor; and The second capacitor is connected between the third transistor and the driving voltage line.

14. The display device according to claim 13, wherein: Each of the plurality of pixels further comprises: The fifth transistor includes a gate connected to the first gate line and is connected between the first electrode of the light emitting diode and an initialization voltage line.

15. The display device according to claim 14, wherein: In a first interval of a frame interval, the gate driving circuit supplies a first gate signal to the first gate line to turn on the second transistor and the fifth transistor, and supplies a second gate signal to the second gate line to turn on the third transistor, and In a writing period of the frame period, the gate driving circuit supplies the first gate signal to the first gate line to turn on the second transistor. In the first interval, the data driving circuit supplies an initialization voltage to the data line, and In the writing section, the data driving circuit supplies a data signal to the data line.

16. The display device according to claim 15, wherein: During a light emitting period of the frame period, the gate driving circuit supplies a third gate signal to the third gate line to turn on the fourth transistor.

17. The display device according to claim 16, wherein: The light emitting interval includes: In the second interval, after the writing interval, the third transistor is turned on, In the second interval, the gate driving circuit supplies a second gate signal to the second gate line to turn on the third transistor.

18. The display device according to claim 17, wherein: Each of the pixels further comprises: a third capacitor connected between the driving voltage line and the first node, The first node is a node where the first transistor and the third transistor are connected.

19. The display device according to claim 17, wherein: Each of the pixels further comprises: a fourth capacitor connected between the first gate line and the second node, The second node is a node where the first capacitor and the second capacitor are connected.

20. The display device according to claim 19, wherein: The frame interval also includes: In a third section, after the writing section and before the second section, the second transistor, the third transistor, and the fourth transistor are turned off.

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