Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a shift register, the shift register comprising a plurality of shift register units; the shift register unit comprising an input module, an output module and a voltage stabilizing module; the input module is configured to write voltages to a first node and a second node based on at least an input signal and a first clock signal; the output module is connected to the first node and the second node respectively; the output module is configured to output a high level signal based on the voltage of the first node, and is also configured to output a low level signal based on the voltage of the second node; the voltage stabilizing module is connected to the first node; during at least part of the period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and a first voltage signal. The present application can ensure that the shift register unit stably outputs a high level enable signal, thereby improving the product performance reliability.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Indium gallium zinc oxide (IGZO) is a material used in the channel layer of next-generation thin-film transistors (TFTs), a type of metal oxide display panel technology. IGZO transistors offer high mobility and low leakage, significantly reducing display image sticking and reducing costs. Currently, pixel circuits fabricated entirely using TFTs are a technological trend, leading to the urgent need to develop a suitable shift drive circuit. Summary of the Invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a display panel and a display device, so as to provide a shift driving circuit capable of stably outputting a scanning signal, thereby improving product yield.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, the display panel includes a shift register, the shift register includes a plurality of shift register units; the shift register unit includes an input module, an output module and a voltage stabilizing module;

[0005] The input module is configured to write voltages to the first node and the second node respectively based on at least an input signal and a first clock signal, and the output module is connected to the first node and the second node respectively; the output module is configured to output a high-level signal based on the voltage of the first node, and is further configured to output a low-level signal based on the voltage of the second node;

[0006] The voltage stabilizing module is connected to at least the first node; during at least a portion of the time when the first node is at a high potential, the voltage stabilizing module is configured to raise the potential of the first node based on the voltage of the first node and the first voltage signal.

[0007] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0008] The display panel and display device provided by embodiments of the present invention have the following beneficial effects: the display panel is provided with a plurality of cascaded shift register units, each transistor in the shift register unit is an n-type transistor, and a voltage stabilizing module is added to the shift register unit. The voltage stabilizing module can raise the potential of the first node during at least a portion of the time period when the first node is at a high potential, so that the first node is stably maintained at a high potential, thereby ensuring that the shift register unit stably outputs a high-level signal. The shift register unit can then stably provide a high-level enable signal to the n-type transistor in the pixel circuit, ensuring stable operation of the pixel circuit and improving product performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a pixel circuit in related art;

[0011] Figure 2 Schematic diagram of a shift register unit in related art;

[0012] Figure 3 for Figure 2 A timing diagram of the shift register unit in the embodiment;

[0013] Figure 4 A simplified schematic diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0015] Figure 6 A timing diagram provided by an embodiment of the present invention;

[0016] Figure 7 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0017] Figure 8 Another timing diagram provided by an embodiment of the present invention;

[0018] Figure 9 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0019] Figure 10 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0020] Figure 11 Another shift register unit diagram provided for the embodiment of the present application;

[0021] Figure 12 Another timing diagram provided for the embodiment of the present application;

[0022] Figure 13 Another timing diagram provided for the embodiment of the present application;

[0023] Figure 14 Another shift register unit diagram provided for the embodiment of the present application;

[0024] Figure 15 Another shift register unit diagram provided for the embodiment of the present application;

[0025] Figure 16 Another shift register unit diagram provided for the embodiment of the present application;

[0026] Figure 17 Another timing diagram provided for the embodiment of the present application;

[0027] Figure 18 A shift register unit cascade diagram provided for the embodiment of the present application;

[0028] Figure 19 Another shift register unit diagram provided for the embodiment of the present application;

[0029] Figure 20 A shift register unit cascade diagram provided for the embodiment of the present application;

[0030] Figure 21 Another shift register unit diagram provided for the embodiment of the present application;

[0031] Figure 22 Another timing diagram provided for the embodiment of the present application;

[0032] Figure 23 Another shift register unit diagram provided for the embodiment of the present application;

[0033] Figure 24 Another timing diagram provided for the embodiment of the present application;

[0034] Figure 25 Another shift register unit diagram provided for the embodiment of the present application;

[0035] Figure 26 Another shift register unit diagram provided for the embodiment of the present application;

[0036] Figure 27 A display device diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all of the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0038] The terms used in the embodiments of the present application are only for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0039] Figure 1 Fig. 1 is a schematic diagram of a pixel circuit in the prior art. Figure 1 As shown in Fig. 1, the pixel circuit includes a driving transistor DT, a data writing transistor T1, a gate reset transistor T2, a light emitting control transistor T3, an electrode reset transistor T4 and a storage capacitor C1. The driving transistor DT is a double-gate structure including a top gate and a bottom gate. The top gate of the driving transistor DT is connected to the data writing transistor T1, the gate reset transistor T2 and one plate of the storage capacitor C1, and the bottom gate of the driving transistor DT is connected to the other plate of the storage capacitor C1. The pixel circuit also needs a first power signal ELVDD, a reset signal Vref, a constant voltage signal Vini, a data signal Data, a light emitting control signal EM1, a scanning signal G1, a scanning signal G2 and a scanning signal G3. The pixel circuit is connected to a first electrode of a light emitting device OLED (Organic Light-Emitting Diode), and a second electrode of the light emitting device OLED is connected to a second power signal ELVSS. Coled represents a parasitic capacitance of the light emitting device OLED itself. The active layer of each transistor in the pixel circuit includes a metal oxide, and the transistor is an n-type transistor. The control signals required by the pixel circuit, such as the light emitting control signal EM1, the scanning signal G1, the scanning signal G2 and the scanning signal G3, have high-level enable levels, so a shift register unit capable of providing high-level enable levels is needed.

[0040] Figure 2 Fig. 2 is a schematic diagram of a shift register unit in the prior art. Figure 2As shown, the shift register unit includes an input module 01 and an output module 02. Output module 02 includes a first output transistor T1', a second output transistor T2', a second capacitor C2, and a third capacitor C3. The output end of input module 01 is connected to node N1 and node NB1. The control end of the first output transistor T1' is connected to node N2, which is connected to node N1 via a switch transistor T3'. The control end of the second output transistor T2' is connected to node NB1. The first end of the first output transistor T1' receives a high-level signal VGH, and the second end is connected to the output end OUT of the shift register unit. The first end of the second output transistor T2' receives a low-level signal VGL, and the second end is connected to the output end OUT of the shift register unit. The control end of the switch transistor T3' receives the high-level signal VGH. The first output transistor T1', the second output transistor T2', and the switch transistor T3' are all n-type transistors. Under the control of the input signal STV and the clock signal CK', the input module 01 writes signals to node N1 and node NB1, respectively.

[0041] Figure 3 for Figure 2 A timing diagram of the shift register unit in an embodiment. Figure 3 The potential changes at each node are shown in FIG. Figure 3 As shown, during the period when the node N2 is at a high level, the first output transistor T1' is turned on and provides a high level signal VGH to the output terminal OUT, and the output terminal OUT outputs a high level signal; during the period when the node NB1 is at a high level, the second output transistor T2' is turned on and provides a low level signal VGL to the output terminal OUT, and the output terminal OUT outputs a low level signal. Due to the small threshold voltage range of the n-type transistor, during the period when the node N2 is written to a high level, the node N2 will leak to the node N1 through the switch transistor T3', causing the potential of the node N2 to decrease (as shown in FIG. Figure 3 The potential change of the node N2 affects the on-state of the first output transistor T1', thereby affecting the output capability of the high-level signal. When the high-level signal is used as an enable signal, it affects the operation of the pixel circuit, resulting in abnormal display.

[0042] To address the problems of related technologies, embodiments of the present invention provide a display panel in which a voltage stabilizing module is provided within a shift register unit. This voltage stabilizing module stabilizes the potential at the control terminal of an output module, enabling the output module to stably output a high-level enable signal. In applications, the shift register unit outputs a stable high-level enable signal to drive the n-type transistor in the pixel circuit.

[0043] Figure 4 A simplified schematic diagram of a display panel provided by an embodiment of the present invention. Figure 4As shown in the figure, the display panel includes a plurality of pixel circuits 10 arranged in an array, and the pixel circuits 10 are arranged into pixel circuit rows 10H in the horizontal direction. A plurality of shift register units 20 are cascaded to form a shift register 2, and the output terminals of the shift register units 20 are connected to each pixel circuit 10 in the pixel circuit row 10H through a scan line 30. The pixel circuit 10 includes at least one n-type transistor, and the output terminal of the shift register unit 20 outputs a high-level enable signal to drive the n-type transistor in the pixel circuit 10. Figure 4 In some embodiments, the shift register unit 20 is arranged on one side of the pixel circuit row 10H, and in other embodiments, the shift register unit 20 is arranged on both sides of the pixel circuit row 10H.

[0044] Figure 5 A shift register unit provided by an embodiment of the present application is shown in the figure. Figure 5 As shown in the figure, the shift register unit includes an input module 21, an output module 22, and a voltage stabilizing module 23. The input module 21 is configured to write voltages to a first node Q1 and a second node Q2 based on at least an input signal STV and a first clock signal CK1, and the output module 22 is connected to the first node Q1 and the second node Q2. The output module 22 is configured to output a high-level signal based on the voltage of the first node Q1, and is also configured to output a low-level signal based on the voltage of the second node Q2. Optionally, the output module 22 includes a third output tube M3 and a fourth output tube M4, the third output tube M3 provides a high-level signal VGH to an output terminal OUT under the control of the high level of the first node Q1, and the fourth output tube M4 provides a low-level signal VGL to the output terminal OUT under the control of the high level of the second node Q2. The high-level signal output by the output terminal OUT serves as an enable signal for driving the n-type transistor in the pixel circuit.

[0045] The voltage stabilizing module 23 is connected to at least the first node Q1, and during at least part of the period when the first node Q1 is at a high potential, the voltage stabilizing module 23 is configured to pull the potential of the first node Q1 high based on the voltage of the first node Q1 and a first voltage signal VG1. The first voltage signal VG1 is a high-level signal during at least part of the period.

[0046] An embodiment of the present application provides a display panel, and a voltage stabilizing module 23 is added to the shift register unit 20. The voltage stabilizing module 23 can pull the potential of the first node Q1 high during at least part of the period when the first node Q1 is at a high potential, so that the first node Q1 is stably maintained at a high potential, and the shift register unit 20 can stably output a high-level signal. The shift register unit 20 can stably provide a high-level enable signal to the n-type transistor in the pixel circuit 10, so as to ensure stable operation of the pixel circuit 10 and improve the performance reliability of the product.

[0047] In some embodiments, at least the transistor connected to the first node Q1 in the output module 22 is an n-type transistor. The n-type transistor is turned on under high-level control and turned off under low-level control. In this embodiment of the present invention, the voltage stabilizing module 23 is configured to maintain a stable high voltage during periods when the first node Q1 is at a high voltage. This ensures that the n-type transistors in the output module 22 remain stably turned on, thereby allowing the shift register unit 20 to stably output a high-level signal. Optionally, all transistors in the output module 22 are n-type transistors.

[0048] In some embodiments, all transistors in the shift register unit 20 are n-type transistors. This configuration allows the active layers of each transistor to be made of the same material, simplifying the display panel's film manufacturing process and reducing manufacturing costs. Furthermore, when at least some transistors in the pixel circuit of the display panel are made of n-type transistors, the shift register unit 20 can also match the pixel circuit's manufacturing process, simplifying the display panel's manufacturing process.

[0049] In the embodiment of the present invention, the active layer of the n-type transistor in the shift register unit 20 includes indium gallium zinc oxide. Indium gallium zinc oxide transistors have the advantages of high mobility and low leakage, which can improve the circuit performance reliability of the shift register unit 20.

[0050] In some embodiments, Figure 6 A timing diagram provided by an embodiment of the present invention can be used to drive Figure 5 The shift register unit 20 is provided. Figure 6 As shown, the operation of the shift register unit 20 includes a first period t1 and a second period t2; at least in the first period t1 and the second period t2, the first node Q1 is at a high potential. In the first period t1, the voltage of the first node Q1 is V1; in the second period t2, the voltage of the first node Q1 is V2, and V2>V1. Figure 6 The timing diagram shows that the potential of the first node Q1 in the second period t2 is higher than that in the first period t1. In this embodiment, the voltage stabilizing module 23 pulls the potential of the first node Q1 higher in the second period t2, so that the first node Q1 can be stably maintained at a high potential. This ensures that the shift register unit 20 stably outputs a high-level signal. The shift register unit 20 can then provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10, ensuring stable operation of the pixel circuit 10 and improving product performance and reliability.

[0051] In some embodiments, the operation of the shift register unit 20 includes m first time periods t1 and m second time periods t2, where m is an integer and m≥1; in time sequence, the first time periods t1 and the second time periods t2 are arranged alternately, and the first first time period t1 is earlier than the first second time period t2. Figure 6In this embodiment, m=2 is used as an example. It is understood that the number m is related to the duration that the first node Q1 maintains a high level. The larger the m, the longer the first node Q1 maintains a high level. The potential writing of the first node Q1 is controlled by the input module 21. That is, the duration that the first node Q1 maintains a high level is related to the high level duration of the input signal STV. The longer the first node Q1 maintains a high level, the longer the shift register unit 20 outputs a high level. In this embodiment of the present invention, the number m is set based on the duration of the high level enable level required in the application.

[0052] In some embodiments, during a first period t1, the input module 21 writes a high voltage to the first node Q1 based on the high voltage signal of the first clock signal CK1. Under control of the first node Q1, the voltage stabilizing module 23 writes a low voltage signal of the first voltage signal VG1 to a third node Q3 within the voltage stabilizing module 23. During a second period t2, the voltage stabilizing module 23 writes a high voltage signal of the first voltage signal VG1 to the third node Q3 under control of the first node Q1. Based on the potential change of the third node Q3, the potential of the first node Q1 is pulled high. This embodiment provides a third node Q3 within the voltage stabilizing module 23. During the first period t1, a low voltage is written to the third node Q3. During the second period t2, a high voltage is written to the third node Q3. The potential change of the third node Q3 is used to pull the potential of the first node Q1 high. Even if leakage current from the first node Q1 to other nodes occurs, this leakage current can be compensated, ensuring that the first node Q1 maintains a relatively stable high voltage, allowing the output transistor controlled by it to be stably turned on, thereby ensuring that the shift register unit 20 stably outputs a high voltage signal. The shift register unit 20 can provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10, thereby ensuring stable operation of the pixel circuit 10 and improving product performance reliability.

[0053] In some embodiments, Figure 7 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, the voltage stabilization module 23 includes a first transistor T1, a second transistor T2, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first node Q1, the control terminal of the second transistor T2 is connected to the second node Q2, the first terminal of the first transistor T1 receives a first voltage signal VG1, the second terminal of the first transistor T1 and the second terminal of the second transistor T2 are connected to the third node Q3, and the first terminal of the second transistor T2 receives a second voltage signal VG2. One plate of the first capacitor C1 is connected to the first node Q1, and the other plate is connected to the third node Q3. In addition, the shift register unit 20 also includes a protection transistor M5, the control terminal of the protection transistor M5 receives a high-level signal VGH, the protection transistor M5 is connected between an output terminal of the input module 21 and the first node Q1, and the protection transistor M5 and the output terminal of the input module 21 are connected to a fifth node Q5.

[0054] Combine Figure 6 As shown in the timing diagram, during the first time period t1, the voltage stabilization module 23 writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the first node Q1. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on and write the low-level signal of the first voltage signal VG1 to the third node Q3. During this time period, the third node Q3 is at a low potential, and the plate of the first capacitor C1 connected to the first node Q1 is at a high potential, while the plate connected to the third node Q3 is at a low potential.

[0055] During the second period t2, the voltage stabilization module 23, under the control of the high potential of the first node Q1, writes the high-level signal of the first voltage signal VG1 to the third node Q3. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on, writing the high-level signal of the first voltage signal VG1 to the third node Q3, causing the third node Q3 to have a high potential. The potential of the third node Q3 jumps from a low level to a high level, and the potential of the first node Q1 is pulled up due to the coupling effect of the first capacitor C1.

[0056] In this embodiment, the voltage stabilizing module 23 operates under the control of the potential of the first node Q1. It utilizes the coupling effect of the first capacitor C1 to raise the potential of the first node Q1, so that the potential of the first node Q1 after being raised in the second period t2 is higher than the potential in the first period t1. This can compensate for the leakage current from the first node Q1 to the fifth node Q5 through the protection transistor M5, ensuring that the first node Q1 is stably maintained at a high potential. This, in turn, allows the output transistor controlled by the first node Q1 to be stably turned on, ensuring that the output end of the shift register unit 20 outputs a stable high-level enable signal.

[0057] In some embodiments, as Figure 6As shown, the operation of the shift register unit 20 also includes a reset period t30; during the reset period t30, the first node Q1 is at a low potential and the second node Q2 is at a high potential. During the reset period t30, the voltage stabilizing module 23 writes the low potential of the second voltage signal VG2 to the third node Q3 based on the control of the second node Q2. In this way, the third node Q3 can be reset. Specifically, combined with Figure 7 From the perspective of FIG. 1 , when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on and write the second voltage signal VG2 to the third node Q3 to reset the third node Q3. Optionally, the second voltage signal VG2 is a low level signal VGL.

[0058] Figure 7 The structure of the output module 22 is also shown. The output module 22 includes a third output transistor M3, a fourth output transistor M4, a capacitor C01, and a capacitor C02. The control end of the third output transistor M3 is connected to the first node Q1, a first end receives a high-level signal VGH, and a second end is connected to the output end OUT of the output module 22. The control end of the fourth output transistor M4 is connected to the second node Q2, a first end receives a low-level signal VGL, and a second end is connected to the output end OUT of the output module 22. When the first node Q1 is at a high level, the first node Q1 controls the third output transistor M3 to turn on, and the shift register unit outputs a high-level signal. When the second node Q2 is at a high level, the second node Q2 controls the fourth output transistor M4 to turn on, and the shift register unit outputs a low-level signal.

[0059] In some embodiments, the first voltage signal VG1 is the second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 can be a pair of clock signals with the same period. In the first time period t1, the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level; in the second time period t2, the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level. The first clock signal CK1 and the second clock signal CK2 jointly drive the cascaded multiple shift register units 20. In the embodiment of the present invention, setting the first voltage signal VG1 as the second clock signal CK2 can simplify the types of signals required to drive the shift register unit 20, and is also beneficial to reducing the wiring of the display panel and narrowing the border.

[0060] In other embodiments, Figure 8 Another timing diagram provided by the embodiment of the present invention can be used to drive the shift register unit 20 provided by the embodiment of the present invention. Figure 8As shown, the operation of the shift register unit 20 includes a first period t1 and a second period t2; at least in the first period t1 and the second period t2, the first node Q1 is at a high potential. In the first period t1, the voltage of the first node Q1 is V1; in the second period t2, the voltage of the first node Q1 is V2, and V2>V1. In terms of time sequence, the first period t1 is earlier than the second period t2; the length of the first period t1 is t01, and the length of the second period t2 is t02, and t02>t01. That is, the duration of the first period t1 is shorter than the duration of the second period t2, and the potential of the first node Q1 is at a higher potential for a longer time after being pulled up. The high potential of the first node Q1 controls the output module 22 to output a high-level enable signal. The longer the time that the first node Q1 is at a higher potential, the better the stability of the high-level signal output by the shift register unit.

[0061] In some embodiments, in the first time period t1, the input module 21 writes a high potential to the first node Q1 based on the high-level signal of the first clock signal CK1, and the voltage stabilizing module 23 writes the high level of the input signal STV to the fourth node Q4 in the voltage stabilizing module 23 under the control of the high-level signal of the first clock signal CK1, and writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4.

[0062] The second period t2 includes a first sub-segment t21 and a second sub-segment t22. In the first sub-segment t21, the voltage stabilizing module 23 writes a high-level signal of the first voltage signal VG1 to the third node Q3 under the control of the fourth node Q4, and pulls up the potential of the fourth node Q4 based on the potential change of the third node Q3, so that the voltage of the fourth node Q4 is V3. There is unidirectional conduction between the fourth node Q4 and the first node Q1, and the voltage of the fourth node Q4 is written to the first node Q1. In the second sub-segment t22, the voltage stabilizing module 23 writes a low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4. The voltage stabilizing module 23 writes the voltage of the input signal STV to the fourth node Q4 under the control of the high level of the first clock signal CK1, so that the voltage of the fourth node Q4 is V4. V4 <V3,由于第四节点Q4和第一节点Q1之间单向导电,则第一节点Q1不会向第四节点Q4漏电,使得第一节点Q1能够维持在高电位。由 Figure 8 It can be seen from the timing that in the second period t2, the first node Q1 is maintained at a relatively higher potential, and although the fourth node Q4 is maintained at a high potential, its high potential fluctuates.

[0063] In this embodiment, a third node Q3 and a fourth node Q4 are provided in the voltage stabilizing module 23. A low level is written to the third node Q3 during the first period t1. During the first sub-segment t21 of the second period t2, a high level is written to the third node Q3. The potential change of the third node Q3 is used to increase the potential of the fourth node Q4. The high potential of the fourth node Q4 is then used to increase the potential of the first node Q1. Furthermore, during the second sub-segment t21, the potential of the fourth node Q4 is lowered, and the path between the fourth node Q4 and the first node Q1 is cut off. This ensures that the first node Q1 remains stable at a relatively high potential after the first sub-segment t21, thereby enabling the output transistor controlled by the first node Q1 to be stably turned on, ensuring that the output end of the shift register unit 20 outputs a stable high-level enable signal.

[0064] In some embodiments, Figure 9 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 9 As shown, the voltage stabilization module 23 includes a first transistor T1, a second transistor T2, a first capacitor C1, a third transistor T3, and a sub-input module 231. The control terminal of the first transistor T1 is connected to the first node Q1 through the third transistor T3, and the control terminal of the second transistor T2 is connected to the second node Q2. The first terminal of the first transistor T1 receives a first voltage signal VG1, the second terminal of the first transistor T1 and the second terminal of the second transistor T2 are connected to the third node Q3, and the first terminal of the second transistor T2 receives a second voltage signal VG2. The first voltage signal VG1 can be the second clock signal CK2, and the second voltage signal VG2 can be the low-level signal VGL. The control terminal of the first transistor T1, one plate of the first capacitor C1, and the control terminal of the third transistor T3 are connected to a fourth node Q4. The first terminal of the third transistor T3 is connected to the fourth node Q4, and the second terminal of the third transistor T3 is connected to the first node Q1. The output terminal of the sub-input module 231 is connected to the fourth node Q4. The sub-input module 231 is configured to write a voltage to the fourth node Q4 based on the input signal STV and the first clock signal CK1.

[0065] Combine Figure 8From the timing diagram, in the first time period t1, the sub-input module 231 writes the high level of the input signal STV into the fourth node Q4 in the voltage stabilizing module 23 under the control of the first clock signal CK1. The high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the low level signal of the first voltage signal VG1 into the third node Q3. In the first sub-segment t21 of the second time period t2, the high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the high level signal of the first voltage signal VG1 into the third node Q3. The third node Q3 jumps from a low potential to a high potential. Due to the coupling effect of the first capacitor C1, the potential of the fourth node Q4 is pulled up. The high potential of the fourth node Q4 controls the third transistor T3 to turn on and write the high potential of the fourth node Q4 into the first node Q1, thereby pulling up the potential of the first node Q1. In addition, Figure 9 In this embodiment, the control terminal and the first terminal of the third transistor T3 are both connected to the fourth node Q4. The third transistor T3 forms a diode-like structure, resulting in unidirectional conduction. During the second sub-segment t21, a low-level signal of the first voltage signal VG1 is written to the third node Q3 under the control of the high potential of the fourth node Q4, and the voltage stabilization module 23 writes a high-level signal of the input signal STV to the fourth node Q4 under the control of the high-level signal of the first clock signal CK1. During this period, the potential of the fourth node Q4 is lower than that in the first sub-segment t21. However, because the third transistor T3 forms a diode-like structure, it can prevent the first node Q1 from discharging to the fourth node Q4, thereby improving the stability of the high potential of the first node Q1. Therefore, the first node Q1 can still maintain a relatively high potential in the second sub-segment t22.

[0066] in addition, Figure 9 In this embodiment, the operation of the shift register unit 20 also includes a reset period t30. During the reset period t30, the first node Q1 is at a low potential and the second node Q2 is at a high potential. During the reset period t30, the voltage stabilization module 23 writes the low potential of the second voltage signal VG2 to the third node Q3 based on the control of the second node Q2. Specifically, during the period when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on, writing the second voltage signal VG2 to the third node Q3, thereby resetting the third node Q3.

[0067] In some embodiments, Figure 10 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 10As shown, the sub-input module 231 includes a fourth transistor T4 and a fifth transistor T5. The control terminal of the fourth transistor T4 receives the first clock signal CK1, the first terminal receives the input signal STV, and the second terminal is connected to the sixth node Q6. The control terminal of the fifth transistor T5 receives the third voltage signal VG3, the first terminal is connected to the sixth node Q6, and the second terminal is connected to the fourth node Q4. The third voltage signal VG3 is a high-level signal VGH. During a first period t1, the fourth transistor T4 is turned on under the control of the high level of the first clock signal CK1, writing the high level of the input signal STV to the sixth node Q6. The fifth transistor T5 is turned on under the control of the third voltage signal VG3, writing the high level of the sixth node Q6 to the fourth node Q4. During the first sub-segment t21 of the second period t2, the first clock signal CK1 is low, and the fourth transistor T4 is turned off. This blocks the path for the sub-input module 231 to write signals to the fourth node Q4, causing the fourth node Q4 to maintain a high level. In the second sub-segment t22 of the second period t2, the first clock signal CK1 is at a high level, the fourth transistor T4 is turned on, and the sub-input module 231 writes the signal provided by the input signal STV into the fourth node Q4.

[0068] In some embodiments, as Figure 10 As shown, the voltage stabilizing module 23 further includes a sixth transistor T6, wherein the control terminal of the sixth transistor T6 is connected to the sixth node Q6, the first terminal receives the second voltage signal VG2, and the second terminal is connected to the second node Q2. During the first period t1 and the second period t2 when the first node Q1 is at a high potential, the sixth node Q6 is at a high potential. The high potential of the sixth node Q6 controls the sixth transistor T6 to turn on and write the low level of the second voltage signal VG2 to the second node Q2, so that the second node Q2 is well maintained at a low level.

[0069] In other embodiments, Figure 11 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown. Figure 12 Another timing diagram provided by an embodiment of the present invention is: Figure 12 The signal timing provided can be used to drive Figure 11 Provided shift register unit. Figure 11 As shown, the voltage stabilization module 23 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 receives the first clock signal CK1. The first terminal of the seventh transistor T7 and an output terminal of the input module 21 are connected to the fifth node Q5. The second terminal of the seventh transistor T7 is connected to the first node Q1. The control terminal of the eighth transistor T8 is connected to the first node Q1. The first terminal of the eighth transistor T8 receives the first voltage signal VG1, which is the input signal STV or the first high-level signal VGH. The second terminal of the eighth transistor T8 is connected to the fifth node Q5.

[0070] Combine Figure 12 From the timing diagram, the operation of the shift register unit 20 includes a first period t1 and a second period t2; in the first period t1 and the second period t2, the first node Q1 is at a high potential.

[0071] During a first period t1, the first clock signal CK1 is a high-level signal, and the first voltage signal VG1 is a high-level signal. The voltage stabilizing module 23, under the control of the potential of the first node Q1, writes the high-level signal of the first voltage signal VG1 into the fifth node Q5. Furthermore, under the control of the high-level signal of the first clock signal CK1, the high-level potential of the fifth node Q5 is written into the first node Q1. Specifically, the high-level potential of the first node Q1 controls the eighth transistor T8 to turn on, writing the high-level signal VGH (or the high-level signal of the input signal STV) into the fifth node Q5. The high-level signal of the first clock signal CK1 controls the seventh transistor T7 to turn on, writing the high-level potential of the fifth node Q5 into the first node Q5. During this period, both the first node Q1 and the fifth node Q5 are at a high potential.

[0072] During the second period t2, the first clock signal CK1 is a low-level signal and the first voltage signal VG1 is a high-level signal. The voltage stabilizing module 23, under the control of the potential of the first node Q1, writes the high-level signal of the first voltage signal VG1 to the fifth node Q5. Furthermore, under the control of the low-level signal of the first clock signal CK1, the path between the fifth node Q5 and the first node Q1 is cut off. Specifically, the high potential of the first node Q1 controls the eighth transistor T8 to turn on, writing the high-level signal VGH (or the high-level signal of the input signal STV) to the fifth node Q5. At this time, the first clock signal CK1 is a low-level signal, and the seventh transistor T7 is turned off. During this period, both the first node Q1 and the fifth node Q5 are at a high potential, and the path between the two nodes is cut off, which enables the first node Q1 to maintain a high potential, preventing the first node Q1 from leaking to other nodes and affecting the output of the high-level signal of the shift register unit.

[0073] In some embodiments, as Figure 7 As shown, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based at least on the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the output signal of the first submodule 211. In this embodiment, the first submodule 211, the second submodule 212, and the third submodule 213 cooperate to write signals to the first node Q1 and the second node Q2.

[0074] Figure 7The shift register unit 20 shown in FIG. 1 further includes a protection transistor M5. An output terminal of the input module 21 is connected to the fifth node Q5, and the protection transistor M5 is connected between the fifth node Q5 and the first node Q1. The first submodule 211 is configured to write a voltage to the fifth node Q5 based on the input signal STV and the first clock signal CK1, thereby writing a voltage to the first node Q1 via the protection transistor M5.

[0075] In one embodiment, if Figure 7 As shown, the second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The control terminal of the ninth transistor T9 receives the input signal STV, and the first terminal of the ninth transistor T9 receives the second voltage signal VG2, which can be a low-level signal VGL. The second terminal of the ninth transistor T9 and the control terminal of the tenth transistor T10 are connected to a seventh node Q7. The first terminal of the tenth transistor T10 receives the first clock signal CK1, and the second terminal is connected to the second node Q2. One plate of the second capacitor C2 receives the first clock signal CK1, and the other plate is connected to the seventh node Q7.

[0076] The first submodule 211 includes an eighteenth transistor T18, wherein the control terminal of the eighteenth transistor T18 receives the first clock signal CK1, the first terminal receives the input signal STV, and the second terminal is connected to the first node Q1. The third submodule 213 includes a nineteenth transistor T19, wherein the control terminal of the nineteenth transistor T19 is connected to the output terminal of the first submodule 211 (i.e., connected to the fifth node Q5), the first terminal receives the second voltage signal VG2, and the second terminal is connected to the second node Q2.

[0077] Figure 13 Another timing diagram provided by the embodiment of the present invention can be used to drive Figure 7 The shift register unit provided in the embodiment. The operation of the input module 21 can be combined with Figure 7 and Figure 13 From a perspective of FIG. 1 , the operation of the shift register unit 20 includes a first period t1 , a second period t2 and a third period t3 which are sequentially arranged in time.

[0078] During the first period t1, the input module 21 is turned on by the high level of the first clock signal CK1 and the high level of the input signal STV. The high level of the input signal STV is written to the first node Q1, and the low level of the second voltage signal VG2 is written to the second node Q2 and the seventh node Q7. Specifically, the high level of the first clock signal CK1 controls the turning on of the eighteenth transistor T18 in the first submodule 211, which writes the high level of the input signal STV to the fifth node Q5. The high level of the fifth node Q5 is then written to the first node Q1 via the protection transistor M5. The high level of the fifth node Q5 controls the turning on of the nineteenth transistor T19 in the third submodule 213, which writes the low level of the second voltage signal VG2 to the second node Q2. Furthermore, the high level of the input signal STV controls the turning on of the ninth transistor T9 in the second submodule 212, which writes the low level of the second voltage signal VG2 to the seventh node Q7. During this period, the fifth node Q5 and the first node Q1 are at a high potential, while the second node Q2 and the seventh node Q7 are at a low potential.

[0079] During the second period t2, the input module 21 is turned off under the control of the low-level signal of the first clock signal CK1. The first node Q1 maintains a high potential, while the second node Q2 and the seventh node Q7 maintain a low potential. Specifically, the low-level signal of the first clock signal CK1 controls the eighteenth transistor T18 to turn off, and the fifth node Q5 maintains a high potential. The high level of the fifth node Q5 controls the nineteenth transistor T19 in the third submodule 213 to turn on, and the second node Q2 maintains a low potential. The high level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn on, and the seventh node Q7 maintains a low potential. As can be seen from the above description of the voltage stabilizing module 23, during this period, the voltage stabilizing module 23 maintains the first node Q1 at a high potential.

[0080] During the third period t3, the input module 21 is turned on under the control of the high level of the first clock signal CK1, writing the low level of the input signal STV to the first node Q1. Based on the high level of the first clock signal CK1, the potential of the seventh node Q7 is pulled high, and the high level of the first clock signal CK1 is written to the second node Q2. Specifically, the high level of the first clock signal CK1 controls the turning on of the eighteenth transistor T18 in the first submodule 211, writing the low level of the input signal STV to the fifth node Q5. The low level of the fifth node Q5 is then written to the first node Q1 via the protection transistor M5, causing the first node Q1 to be at a low level. Furthermore, the low level of the input signal STV controls the turning off of the ninth transistor T9 in the second submodule 212. During this period, the first clock signal CK1 transitions from a low level to a high level. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled high, and the seventh node Q7 is at a high level. The high level of the seventh node Q7 controls the turning on of the tenth transistor T10 in the second submodule 212, writing the high level of the first clock signal CK1 to the second node Q2. During this period, the first node Q1 is at a low potential, and the second node Q2 is at a high potential.

[0081] in addition, Figure 11 The structure of the input module 21 shown in the embodiment and Figure 7 The structure of the input module 21 is the same as that of the Figure 11 The working process of the input module 21 illustrated in the embodiment can be understood with reference to the above description, and will not be described in detail here.

[0082] In other embodiments, Figure 10 As shown, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based on at least the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0083] The second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The ninth transistor T9 includes a first sub-transistor T91 and a second sub-transistor T92. The control terminal of the first sub-transistor T91 and the control terminal of the second sub-transistor T92 receive an input signal STV. The first terminal of the first sub-transistor T91 receives a second voltage signal VG2. The second terminal of the first sub-transistor T91 and the first terminal of the second sub-transistor T92 are connected to an eighth node Q8, and the second terminal of the second sub-transistor T92 is connected to a seventh node Q7. The control terminal of the tenth transistor T10 is connected to the seventh node Q7, the first terminal receives a first clock signal CK1, and the second terminal is connected to the second node Q2. One plate of the second capacitor C2 receives the first clock signal CK1, and the other plate is connected to the seventh node Q7. The second submodule 212 also includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the seventh node Q7, the first terminal receives a third voltage signal VG3, and the second terminal is connected to the eighth node Q8. The second voltage signal VG2 can be a low-level signal VGL, and the third voltage signal VG3 can be a high-level signal VGH. Figure 10 It is also shown in FIG. 1 that the first submodule 211 includes an eighteenth transistor T18 and the third submodule 213 includes a nineteenth transistor T19 .

[0084] In another embodiment, Figure 14 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 14 As shown, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 includes an eighteenth transistor T18, the third submodule 213 includes a nineteenth transistor T19, and the second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. Figure 14 and Figure 10 The difference of the input module 21 in the embodiment is that, Figure 14 In the embodiment, a first terminal of the eleventh transistor T11 receives the first clock signal CK1 , and a control terminal of the eleventh transistor T11 is connected to the second terminal of the tenth transistor T10 .

[0085] In another embodiment, Figure 15 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown. Figure 15 and Figure 14 The difference is that Figure 15 In the embodiment, the first terminal of the eleventh transistor T11 receives the third voltage signal VG3 , and the control terminal of the eleventh transistor T11 is connected to the seventh node Q7 .

[0086] above Figure 10 、 Figure 14 、 Figure 15The working process of the input module 21 in the embodiment can be combined with the above Figure 13 The working process of the second submodule 212 is as follows: Figure 10 Taking the embodiment as an example, during the first period t1, the input signal STV is high, turning on the first and second sub-transistors T91 and T92. Low levels are written to the eighth and seventh nodes Q8 and Q7, and the low level at the seventh node Q7 turns off the eleventh transistor T11. During the second period t2, the eighth and seventh nodes Q8 and Q7 remain low. During the third period t3, the input signal STV is low, turning off the first and second sub-transistors T91 and T92. The first clock signal CK1 transitions from low to high. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled high. The high potential at the seventh node Q7 turns on the eleventh transistor T11, writing the high level of the third voltage signal VG3 to the eighth node Q8. During this period, both the eighth and seventh nodes Q8 and Q7 are high, and the first and second sub-transistors T91 and T92 are turned off. This prevents leakage from the seventh node Q7 when the ninth transistor T9 is negatively biased. This ensures that the tenth transistor T10 is in a stably turned-on state, so that the high-level signal provided by the first clock signal CK1 is stably written into the second node Q2, and the second node Q2 is at a stable high potential.

[0087] In some embodiments, as Figure 9 and Figure 10 As shown, the shift register unit further includes an anti-leakage module 24, which is connected between the second node Q2 and the output module 22. The anti-leakage module 24 is configured to be closed under the control of the first clock signal CK1. Figure 10 For example, combined with Figure 13 According to the timing diagram, during the third period t3, the first clock signal CK1 is at a high level, and a high potential is written to the second node Q2. The leakage prevention module 24 is turned on and writes the high level of the second node Q2 to the control terminal of the fourth output transistor M4 in the output module 22, thereby causing the shift register unit to output the low level provided by the low-level signal VGL. The third period t3 is the period during which the high-level signal is written to the control terminal of the fourth output transistor M4. During the fourth period t4, the first clock signal CK1 is at a low level, and the leakage prevention module 24 is turned off. This closes the leakage path from the control terminal of the fourth output transistor M4, thereby stabilizing the potential at the output terminal of the fourth output transistor M4 and enabling the shift register unit to stably output a low-level signal.

[0088] like Figure 10As shown, the leakage prevention module 24 includes a twelfth transistor T12, the control end of the twelfth transistor T12 receives the first clock signal CK1, the first end is connected to the second node Q2, and the second end is connected to a control end of the output module 22, specifically, the second end is connected to the control end of the fourth output tube M4.

[0089] In some embodiments, Figure 16 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 16 As shown, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1. The second submodule 212 is configured to write a voltage to the second node Q2 based on at least the output signal of the first submodule 211, the first clock signal CK1, and the second clock signal CK2. The third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0090] like Figure 16 As shown, the second submodule 212 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and a third capacitor C3. The control terminal of the thirteenth transistor T13 is connected to the output terminal of the first submodule 211, a first terminal receives the second voltage signal VG2, and a second terminal is connected to the second terminal of the fourteenth transistor T14. Optionally, the second voltage signal VG2 is a low-level signal VGL. The control terminal of the fourteenth transistor T14 receives the first clock signal CK1, and the control terminal of the fifteenth transistor T15 receives the third voltage signal VG3. Optionally, the third voltage signal VG3 is a high-level signal VGH. The first terminal of the fourteenth transistor T14 receives the third voltage signal VG3, and the second terminal is connected to the first terminal of the fifteenth transistor T15. The second terminal of the fifteenth transistor T15 and the control terminal of the sixteenth transistor T16 are connected to the ninth node Q9. A first terminal of the sixteenth transistor T16 receives the second clock signal CK2, and a second terminal is connected to the tenth node Q10. One plate of the third capacitor C3 is connected to the ninth node Q9, and the other plate is connected to the tenth node Q10. A control terminal of the seventeenth transistor T17 receives the second clock signal CK2, a first terminal is connected to the tenth node Q10, and a second terminal is connected to the second node Q2.

[0091] In addition, the first submodule 211 includes an eighteenth transistor T18, the control terminal of the eighteenth transistor T18 receives the first clock signal CK1, the first terminal receives the input signal STV, and the second terminal is connected to the first node Q1. Figure 16The second end of the eighteenth transistor T18 is connected to the fifth node Q5, which is connected to the first node Q1 via the protection transistor M5. The third submodule 213 includes a nineteenth transistor T19, whose control end is connected to the output end of the first submodule 211, whose first end receives the second voltage signal VG2, and whose second end is connected to the second node Q2.

[0092] Figure 17 Another timing diagram provided by the embodiment of the present invention can be used to drive Figure 16 The shift register unit provided in the embodiment. The working process of the input module 21 can be combined with Figure 16 and Figure 17 To understand. Figure 17 As shown, the operation of the shift register unit 20 includes a first period t1, a second period t2, a third period t3 and a fourth period t4 which are sequentially arranged in time.

[0093] During a first period t1, the input module 21, under the control of a high-level first clock signal CK1, turns on and writes the high-level input signal STV to the first node Q1, writes the low-level second voltage signal VG2 to the second node Q2, and writes the low-level second voltage signal VG2 to the ninth node Q9. Furthermore, under the control of a low-level second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is cut off. Specifically, the high-level first clock signal CK1 turns on the eighteenth transistor T18 in the first submodule 211, writing the high-level input signal STV to the fifth node Q5. The fifth node Q5 then writes the high-level input signal to the first node Q1 via the protection transistor M5. During this period, the output of the first submodule 211 is high, controlling the nineteenth transistor T19 in the third submodule 213 to turn on and write the low-level second voltage signal VG2 to the second node Q2. The high level at the output of the first submodule 211 also turns on the thirteenth transistor T13 in the second submodule 212. Simultaneously, the first clock signal CK1 turns on the fourteenth transistor T14. The high level of the third voltage signal VG3 written through the fourteenth transistor T14 leaks through the thirteenth transistor T13. The fifteenth transistor turns on under the control of the high level of the third voltage signal VG3. Therefore, at this moment, a low level is written to the ninth node Q9. The ninth node Q9 is at a low level, the second clock signal CK2 is at a low level, and the sixteenth and seventeenth transistors T16 and 17 are both turned off. During this period, the first node Q1 is at a high level, the second node Q2 is at a low level, the third output terminal M3 in the output module 22 is turned on, and the output terminal OUT outputs a high-level signal.

[0094] During the second time period t2, the input module 21 is closed under the control of the low-level signal of the first clock signal CK1. The first node Q1 maintains a high potential, while the second node Q2 and the ninth node Q9 maintain a low potential. Furthermore, under the control of the high-level signal of the second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is connected. Specifically, when the first clock signal CK1 is at a low level, the eighteenth transistor T18 and the fourteenth transistor T14 are turned off. The fifth node Q5 and the first node Q1 maintain a high potential. During this period, the second node Q2 and the ninth node Q9 maintain a low potential. Furthermore, the high level of the second clock signal CK2 controls the seventeenth transistor T17 to turn on, thereby connecting the path between the tenth node Q10 and the second node Q2. During this period, the first node Q1 is at a high potential, the second node Q2 is at a low potential, the third output terminal M3 of the output module 22 is turned on, and the output terminal OUT outputs a high-level signal.

[0095] During the third period t3, the input module 21 is turned on under the control of the high-level signal of the first clock signal CK1, writes the low-level input signal STV to the first node Q1, writes the high-level third voltage signal VG3 to the ninth node Q9, and writes the low-level second clock signal CK2 to the tenth node Q10 under the control of the ninth node Q9. Under the control of the low-level second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is cut off, and the second node Q2 maintains a low potential. Specifically, the high-level signal of the first clock signal CK1 controls the turning on of the eighteenth transistor T18 and the fourteenth transistor T14. The turning on of the eighteenth transistor T18 writes the low-level input signal STV to the fifth node Q5. The fifth node Q5 then writes the low-level voltage to the first node Q1 via the protection transistor M5. Simultaneously, the low-level voltage of the fifth node Q5 controls the turning off of the thirteenth transistor T13, while the fourteenth transistor T14 and the fifteenth transistor T15 turn on, writing the high-level third voltage signal VG3 to the ninth node Q9. The high level of the ninth node Q9 controls the sixteenth transistor T16 to turn on, writing the low level of the second clock signal CK2 to the tenth node Q10. The low level of the second clock signal CK2 controls the seventeenth transistor T17 to turn off, cutting off the path between the tenth node Q10 and the second node Q2. During this period, the second node Q2 is at a low potential, and the first node Q1 is at a low potential. The output terminal OUT of the output module 22 maintains the output state of the previous period and outputs a high-level signal.

[0096] During the fourth period t4, the input module 21 is closed under the control of the low-level signal of the first clock signal CK1. The first node Q1 maintains a low potential, and the ninth node Q9 maintains a high potential. Under the control of the ninth node Q9, the high potential of the second clock signal CK2 is written to the tenth node Q10. Due to the coupling effect of the third capacitor C3, the potential change of the tenth node Q10 couples the potential of the ninth node Q9 to a higher potential. Under the control of the high-level signal of the second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is connected, and a high potential is written to the second node Q2. During this period, the second node Q2 is at a high potential, the first node Q1 is at a low potential, the fourth output terminal M4 of the output module 22 is turned on, and the output terminal OUT outputs a low-level signal.

[0097] In some embodiments, Figure 18 A schematic diagram of a cascade of shift register units provided in an embodiment of the present invention is shown in FIG. Figure 18 As shown, the shift register unit 20 includes an input module 21, an output module 22, and a voltage stabilizing module 23. The output terminal OUT of the output module 22 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the i+1-th stage shift register unit 20(i+1), where i is a positive integer. That is, the signal outputted by the output terminal OUT of the output module 22 in the shift register unit 20 serves as the input signal STV received by the input module 21 in the next stage shift register unit 20.

[0098] In other embodiments, Figure 19 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown. Figure 20 Another shift register unit cascade diagram provided by an embodiment of the present invention is as follows Figure 19 As shown, the shift register unit 20 also includes a level transfer module 25, which is connected to the first node Q1 and the second node Q2, respectively. The level transfer module 25 is configured to output a high-level signal based on the voltage at the first node Q1, and to output a low-level signal based on the voltage at the second node Q2. In an application, the signal outputted from the output terminal Next of the level transfer module 25 is used for level transfer and provided to the input terminal of the next-stage shift register unit. The signal outputted from the output terminal OUT of the output module 22 is provided to the scan line to drive the pixel circuit. This can reduce the voltage drop of the scan signal outputted by the shift register unit 20, which is beneficial for improving display uniformity.

[0099] Combine Figure 20For example, the output terminal Next of the transmission module 25 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the i+1-th stage shift register unit 20(i+1), where i is a positive integer. In other words, the signal output by the output terminal Next of the transmission module 25 in the shift register unit 20 serves as the input signal STV received by the input module 21 in the next-stage shift register unit 20.

[0100] In some embodiments, Figure 21 A schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 22 Another timing diagram provided by the embodiment of the present invention can be used to drive Figure 21 Provided shift register unit. Figure 21 As shown, the shift register unit 20 includes an input module 21, an output module 22, a voltage stabilizing module 23, and a stage transfer module 25. The stage transfer module 25 includes a first output transistor M1 and a second output transistor M2. The control end of the first output transistor M1 is connected to the first node Q1, the first end receives the third voltage signal VG3, and the second end is connected to the output terminal Next of the stage transfer module 25. The control end of the second output transistor M2 is connected to the second node Q2, the first end receives the second voltage signal VG2, and the second end is connected to the output terminal Next of the stage transfer module 25. Specifically, a protection transistor M5 is connected between the first node Q1 and the output end of the input module 21. The control end of the second output transistor M2 is connected to the second node Q2 via a twelfth transistor T12. The third voltage signal VG3 provides a high-level signal, and the second voltage signal VG2 provides a low-level signal. Figure 21 A capacitor C03 is also shown, one plate of the capacitor C03 is connected to the control end of the second output tube M2, and the other plate receives the second voltage signal VG2.

[0101] The output module 22 includes a third output transistor M3 and a fourth output transistor M4. The control end of the third output transistor M3 is connected to the first node Q1, the first end receives the fourth voltage signal VG4, and the second end is connected to the output end OUT of the output module 22. The control end of the fourth output transistor M4 is connected to the second node Q2, the first end receives the fifth voltage signal VG5, and the second end is connected to the output end OUT of the output module 22. Specifically, the control end of the fourth output transistor M4 is connected to the second node Q2 via the twelfth transistor T12. The fourth voltage signal VG4 provides a high-level signal, and the fifth voltage signal VG5 provides a low-level signal.

[0102] in addition, Figure 21 In the embodiment, the input module 21 and Figure 10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Figure 1 The structure of the voltage stabilizing module 22 in the embodiments is the same and will not be described again here.

[0103] In other embodiments, Figure 23 A schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 24 Another timing diagram provided by the embodiment of the present invention can be used to drive Figure 23 Provided shift register unit. Figure 23 As shown, the shift register unit 20 includes an input module 21 , an output module 22 , a voltage stabilizing module 23 and a stage transmission module 25 . Figure 23 In the embodiment, the input module 21 and Figure 10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Figure 10 The structures of the voltage stabilizing modules 22 in the embodiments are the same.

[0104] In other embodiments, Figure 25 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 25 As shown, the shift register unit 20 includes an input module 21 , an output module 22 , a voltage stabilizing module 23 , an anti-leakage module 24 and a level transmission module 25 . Figure 23 In the embodiment, the input module 21 and Figure 10 The structure of the input module 21 in the embodiment is the same as that of the voltage stabilizing module 22. Figure 11 The structures of the voltage stabilizing modules 22 in the embodiments are the same.

[0105] In other embodiments, Figure 26 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Figure 25 As shown, the shift register unit 20 includes an input module 21 , an output module 22 , an anti-leakage module 24 and a level transfer module 25 . Figure 26 Also shown are capacitors C04 and C05.

[0106] In some embodiments, the third voltage signal VG3 and the fourth voltage signal VG5 both provide high-level signals, the third voltage signal VG3 has a voltage value of VGH1, the fourth voltage signal VG4 has a voltage value of VGH2, and VGH2 ≤ VGH1. This configuration enables the potential of the first node Q1 to more completely control the conduction of the third output transistor M3, thereby making the output terminal OUT of the output module 22 outputting a high-level enable voltage more stable.

[0107] In some embodiments, the second voltage signal VG2 and the fifth voltage signal VG5 both provide low-level signals, the second voltage signal VG2 has a voltage value of VGL1, the fifth voltage signal VG5 has a voltage value of VGL2, and VGL2 ≥ VGL1. This configuration allows the fourth output transistor M4 to be completely turned off when the output terminal OUT of the output module 22 is in a negative bias state and outputs a high level, thereby ensuring the stability of the high-level output of the output terminal OUT of the output module 22.

[0108] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 27 A schematic diagram of a display device provided for the implementation of the present invention, such as Figure 27 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device such as a mobile phone, a tablet, a television, a smart wearable product, etc.

Claims

1. A display panel, characterized in that: The display panel includes a shift register, and the shift register includes a plurality of shift register units; the shift register unit includes an input module, an output module and a voltage stabilizing module; The input module is configured to write voltages to a first node and a second node respectively based on at least an input signal and a first clock signal, and the output module is connected to the first node and the second node respectively; the output module is configured to output a high-level signal based on the voltage of the first node, and is further configured to output a low-level signal based on the voltage of the second node; The voltage stabilizing module is connected to at least the first node; during at least a portion of a period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and the first voltage signal; The operation of the shift register unit includes a first period and a second period; the first node is at a high potential during the first period and the second period; During the first period, the voltage of the first node is V1; during the second period, the voltage of the first node is V2, and V2>V1.

2. The display panel according to claim 1, wherein: The operation of the shift register unit includes m first time periods and m second time periods, where m is an integer and m≥1; In time sequence, the first time periods and the second time periods are arranged alternately, and the first first time period is earlier than the first second time period.

3. The display panel according to claim 2, wherein: During the first period, the input module writes a high potential to the first node based on a high-level signal of the first clock signal, and the voltage stabilizing module writes a low-level signal of the first voltage signal to a third node in the voltage stabilizing module under the control of the first node; During the second period, the voltage stabilizing module writes a high-level signal of the first voltage signal into the third node under the control of the first node, and raises the potential of the first node based on the potential change of the third node.

4. The display panel according to claim 1, wherein: In terms of time sequence, the first period is earlier than the second period; The length of the first time period is t01, the length of the second time period is t02, and t02>t01.

5. The display panel according to claim 4, wherein: During the first time period, the input module writes a high potential to the first node based on the high-level signal of the first clock signal, the voltage stabilizing module writes the high level of the input signal to the fourth node in the voltage stabilizing module under the control of the high-level signal of the first clock signal, and writes the low-level signal of the first voltage signal to the third node under the control of the high-level signal of the fourth node; The second period includes a first sub-segment and a second sub-segment; In the first sub-segment, the voltage stabilization module, under control of the fourth node, writes a high-level signal of the first voltage signal into the third node, raises the potential of the fourth node based on a potential change of the third node, and the voltage of the fourth node is V3. One-way conduction occurs between the fourth node and the first node, and the voltage of the fourth node is written into the first node. In the second sub-segment, the voltage stabilizing module writes the low level signal of the first voltage signal to the third node under the high potential control of the fourth node, and the voltage stabilizing module writes the voltage of the input signal to the fourth node under the high level signal control of the first clock signal. The voltage of the fourth node is V4, V4 <V3。 6. The display panel according to claim 1, wherein: The operation of the shift register unit includes a first period and a second period; the first node is at a high potential during the first period and the second period; During the first time period, the first clock signal is a high-level signal, the first voltage signal is a high-level signal, the voltage stabilizing module writes the high-level signal of the first voltage signal to the fifth node under the control of the first node, and writes the high potential of the fifth node to the first node under the control of the first clock signal; During the second time period, the first clock signal is a low-level signal and the first voltage signal is a high-level signal. Under the control of the first node, the voltage stabilization module writes the high-level signal of the first voltage signal to the fifth node, and under the control of the first clock signal, cuts off the path between the fifth node and the first node.

7. The display panel according to claim 1, wherein: The voltage stabilizing module includes a first transistor, a second transistor and a first capacitor; The control terminal of the first transistor is connected to the first node, the control terminal of the second transistor is connected to the second node, the first terminal of the first transistor receives the first voltage signal, the second terminal of the first transistor and the second terminal of the second transistor are connected to a third node, and the first terminal of the second transistor receives the second voltage signal; One plate of the first capacitor is connected to the first node, and the other plate is connected to the third node.

8. The display panel according to claim 7, wherein: The first voltage signal is a second clock signal.

9. The display panel according to claim 7, wherein: The voltage stabilizing module further includes a third transistor and a sub-input module; The control terminal of the first transistor, one plate of the first capacitor, and the control terminal of the third transistor are connected to a fourth node, the first terminal of the third transistor is connected to the fourth node, and the second terminal of the third transistor is connected to the first node; An output terminal of the sub-input module is connected to the fourth node, and the sub-input module is configured to write a voltage to the fourth node based on the input signal and the first clock signal.

10. The display panel according to claim 9, wherein: The sub-input module includes a fourth transistor and a fifth transistor; The control end of the fourth transistor receives the first clock signal, the first end receives the input signal, and the second end is connected to the sixth node. The control end of the fifth transistor receives the third voltage signal, the first end is connected to the sixth node, and the second end is connected to the fourth node.

11. The display panel according to claim 10, wherein: The voltage stabilizing module further includes a sixth transistor, wherein the control end of the sixth transistor is connected to the sixth node, the first end of the sixth transistor receives the second voltage signal, and the second end of the sixth transistor is connected to the second node.

12. The display panel according to claim 1, wherein The voltage stabilizing module includes a seventh transistor and an eighth transistor; A control terminal of the seventh transistor receives the first clock signal, a first terminal of the seventh transistor and an output terminal of the input module are connected to a fifth node, and a second terminal of the seventh transistor is connected to the first node; The control end of the eighth transistor is connected to the first node, the first end of the eighth transistor receives the first voltage signal, the first voltage signal is the input signal or a high-level signal, and the second end of the eighth transistor is connected to the fifth node.

13. The display panel according to claim 1, wherein The input module includes a first submodule, a second submodule and a third submodule; The first submodule is configured to write a voltage to the first node based on the input signal and the first clock signal; The second submodule is configured to write a high level to the second node based on at least the input signal and the first clock signal; The third submodule is configured to write a low level to the second node based on control of the output signal of the first submodule.

14. The display panel according to claim 13, wherein: The second submodule includes a ninth transistor, a tenth transistor, and a second capacitor; The control end of the ninth transistor receives the input signal, the first end of the ninth transistor receives the second voltage signal, the second end of the ninth transistor and the control end of the tenth transistor are connected to the seventh node; the first end of the tenth transistor receives the first clock signal, and the second end is connected to the second node; one plate of the second capacitor receives the first clock signal, and the other plate is connected to the seventh node.

15. The display panel according to claim 14, wherein: The ninth transistor includes a first sub-transistor and a second sub-transistor, wherein a control terminal of the first sub-transistor and a control terminal of the second sub-transistor receive the input signal, a first terminal of the first sub-transistor receives a second voltage signal, a second terminal of the first sub-transistor and a first terminal of the second sub-transistor are connected to the eighth node, and a second terminal of the second sub-transistor is connected to the seventh node; The second submodule further includes an eleventh transistor, a control end of the eleventh transistor being connected to the seventh node or the second end of the tenth transistor, a first end receiving a third voltage signal or the first clock signal, and a second end being connected to the eighth node.

16. The display panel according to claim 1, wherein The shift register unit further includes an anti-leakage module connected between the second node and the output module. The anti-leakage module is configured to be turned off under the control of the first clock signal.

17. The display panel according to claim 16, wherein: The anti-leakage module includes a twelfth transistor, wherein the control end of the twelfth transistor receives the first clock signal, the first end is connected to the second node, and the second end is connected to a control end of the output module.

18. The display panel according to claim 1, wherein The input module includes a first submodule, a second submodule and a third submodule; The first submodule is configured to write a voltage to the first node based on the input signal and the first clock signal; The second submodule is configured to write a voltage to the second node based on at least the output signal of the first submodule, the first clock signal, and the second clock signal; The third submodule is configured to write a low level to the second node based on control of the output signal of the first submodule.

19. The display panel according to claim 18, wherein: The second submodule includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The control terminal of the thirteenth transistor is connected to the output terminal of the first submodule, the first terminal receives the second voltage signal, and the second terminal is connected to the second terminal of the fourteenth transistor; the control terminal of the fourteenth transistor receives the first clock signal, the control terminal of the fifteenth transistor receives the third voltage signal, the first terminal of the fourteenth transistor receives the third voltage signal, and the second terminal is connected to the first terminal of the fifteenth transistor; the second terminal of the fifteenth transistor and the control terminal of the sixteenth transistor are connected to a ninth node; The first end of the sixteenth transistor receives the second clock signal, and the second end is connected to the tenth node; The control end of the seventeenth transistor receives the second clock signal, the first end is connected to the tenth node, and the second end is connected to the second node.

20. The display panel according to claim 13 or 18, wherein: The first submodule includes an eighteenth transistor, wherein the control terminal of the eighteenth transistor receives the first clock signal, the first terminal receives the input signal, and the second terminal is connected to the first node; And / or, the third submodule includes a nineteenth transistor, a control end of the nineteenth transistor is connected to the output end of the first submodule, a first end receives a second voltage signal, and a second end is connected to the second node.

21. The display panel according to claim 1, wherein The output end of the output module in the i-th stage shift register unit is connected to the input end of the input module in the i+1-th stage shift register unit, where i is a positive integer.

22. The display panel according to claim 1, wherein The shift register unit further includes a stage transmission module, the stage transmission module being connected to the first node and the second node respectively; the stage transmission module being configured to output a high level signal based on the voltage of the first node, and being configured to output a low level signal based on the voltage of the second node; The output end of the stage transmission module in the i-th stage shift register unit is connected to the input end of the input module in the (i+1)-th stage shift register unit, where i is a positive integer.

23. The display panel according to claim 22, wherein: The stage transmission module includes a first output tube and a second output tube, wherein the control end of the first output tube is connected to the first node, the first end receives the third voltage signal, and the second end is connected to the output end of the stage transmission module; the control end of the second output tube is connected to the second node, the first end receives the second voltage signal, and the second end is connected to the output end of the stage transmission module; The output module includes a third output tube and a fourth output tube, wherein the control end of the third output tube is connected to the first node, the first end receives the fourth voltage signal, and the second end is connected to the output end of the output module; the control end of the fourth output tube is connected to the second node, the first end receives the fifth voltage signal, and the second end is connected to the output end of the output module; wherein The third voltage signal has a voltage value of VGH1, the fourth voltage signal has a voltage value of VGH2, VGH2≤VGH1; and / or the second voltage signal has a voltage value of VGL1, the fifth voltage signal has a voltage value of VGL2, VGL2≥VGL1.

24. The display panel according to claim 1, wherein At least the transistor connected to the first node in the output module is an n-type transistor.

25. The display panel according to claim 24, wherein: All transistors in the shift register unit are n-type transistors.

26. The display panel according to claim 24, wherein: The active layer of the n-type transistor includes indium gallium zinc oxide.

27. A display device, characterized in that: A display panel comprising any one of claims 1 to 26.

Images