A BMC source selection method and system

Abstract

A BMC source selection method and system belongs to the field of time synchronization technology, including a downstream time node obtaining an ANNO message sent by each upstream time node, wherein the ANNO message includes an actual link deviation level and a port theoretical deviation level, wherein the actual link deviation level is the link accuracy between the upstream time node and the upstream time node, and the port theoretical deviation level is the device accuracy of the upstream time node itself; the downstream time node calculates the comprehensive link deviation level of each upstream time node, wherein the comprehensive link deviation level is obtained by summing the larger value of the device accuracy of the upstream time node and the device accuracy of the downstream time node with the link accuracy of the upstream time node; the downstream time node selects the time source of the upstream time node with the smallest comprehensive link deviation as the time reference source for time synchronization operation. This application introduces the concept of comprehensive link deviation into the existing BMC algorithm, and realizes synchronization path selection based on optimal device performance according to the comprehensive link deviation.

Description

Technical Field

[0001] The present application relates to the field of time synchronization technology, and in particular to a BMC source selection method and system. Background Art

[0002] 1588 time synchronization technology is used to synchronize time between network elements (NEs) and is used in mobile backhaul scenarios to ensure normal communication between 4G and 5G base stations. This technology, detailed in the IEEE 1588-2008 standard, consists of two main steps: an optimal clock source selection algorithm that compares clock quality parameters carried in Announce messages (ANNO messages) to select a source and determine port status, and a time offset calculation and time adjustment. With the iterative evolution of technology, the single-hop performance of 1588 time synchronization has been improved from the previous standard accuracy of ±30ns to the ultra-high accuracy of ±5ns. In existing networks, a large number of legacy and new devices are mixed in the network.

[0003] In a time synchronization network, a device receives Announce messages from each port and records the fields in the message that represent clock quality parameters, such as GM ID, GM priority 1, GM class, GM priority 2, step-removed, etc., to form a clock source data set. The BMC (Best Master Clock) algorithm compares the clock source data sets from each port with the local clock source data set in turn. The comparison method is as follows: Figure 1 As shown in the figure, if the GM IDs are different, GM priority1 is compared until which data set is better. The clock source corresponding to the optimal data set is the synchronization direction. If the GM IDs are the same, then Figure 2 As shown, the hop counts are compared in sequence until a decision is made on which data set is better. If all are the same, an error is reported, but this situation generally does not occur.

[0004] The existing BMC algorithm compares the static configuration parameters of the clock source when GM IDs are inconsistent. (Configured parameters are static values, while the actual performance of the device is dynamic. Configuring static parameters does not always reflect the actual performance of the device.) When GM IDs are consistent, the algorithm prioritizes the number of hops. Neither algorithm considers the actual performance of the clock source.

[0005] Take the hybrid network topology composed of PTN (Packet Transport Network) and SPN (Slicing Packet Network) as an example to illustrate. Figure 3As shown in the figure, in a simple time synchronization network, there are ultra-high-precision SPN devices with a theoretical jitter of 5ns per hop, and there are also high-precision PTN devices with a theoretical jitter of 30ns per hop. For NE7 devices, path 1 has 3 hops and path 2 has 4 hops. According to the existing BMC algorithm, the NE7 synchronization path 1 will be determined by comparing the number of hops. However, path 2 has three hops and is an ultra-high-precision device. The theoretical total jitter is 5×4=20ns, while the theoretical total jitter of path 1 is 5+30×2=65ns. In fact, the link accuracy of path 2 is higher, so NE7 synchronization path 2 is the better choice. Time performance is also affected by the clock, and the current network environment is far more complex than that of the existing network environment. Figure 3 It is much more complicated. It is often encountered that the time performance of the current synchronization path is not good enough due to clock performance issues. In reality, there are better options.

[0006] In summary, in actual application scenarios, using the existing BMC algorithm, the synchronization path selected by the device is not the path with the best performance, and the ultra-high-precision equipment is not effectively utilized. How to enable the device to select a source with better performance is an urgent problem that needs to be solved. Summary of the Invention

[0007] The present application provides a BMC source selection method and system, which can solve the technical problem in the prior art that the synchronization path selected by the existing BMC algorithm is not the path with the best performance.

[0008] In a first aspect, an embodiment of the present application provides a BMC source selection method, the method comprising:

[0009] The downstream clock node obtains the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation level and the port theoretical deviation level. The actual link deviation level is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation level is the device accuracy of the clock node itself.

[0010] The downstream clock node calculates a comprehensive link deviation level of each upstream clock node, where the comprehensive link deviation level is obtained by summing a larger value of the device accuracy of the upstream clock node and the device accuracy of the downstream clock node and the link accuracy of the upstream clock node;

[0011] The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation level as the clock reference source for clock synchronization operations.

[0012] In conjunction with the first aspect, in one embodiment, the ANNO message includes a clock source data set, and the clock source data set includes static configuration parameters, and the actual link deviation and the port theoretical deviation;

[0013] The actual link deviation and the port theoretical deviation are stored in the reserved field of the ANNO message.

[0014] In combination with the first aspect, in one embodiment, the method further includes:

[0015] When the comprehensive link deviation levels of the upstream clock nodes are the same, the downstream clock node selects a clock source of an upstream clock node as a clock reference source for clock synchronization operations according to static configuration parameters.

[0016] In conjunction with the first aspect, in one implementation, the actual link deviation level is obtained by the following steps:

[0017] The upstream clock node sends a first message to the downstream clock node, and uses the first timestamp to record the sending time of the first message;

[0018] When the downstream clock node receives the first message, it uses the second timestamp to record the reception time of the first message;

[0019] The downstream clock node sends a second message to the upstream clock node, and uses the third timestamp to record the sending time of the second message;

[0020] When the upstream clock node receives the second message, it records the reception time of the second message using the timestamp;

[0021] The actual link deviation value is calculated by combining the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, and the actual link deviation value is compared with a preset link level conversion table to obtain the corresponding actual link level.

[0022] In conjunction with the first aspect, in one embodiment, the port theoretical deviation level is obtained by the following steps:

[0023] The theoretical one-hop jitter of the upstream clock node is obtained, and the theoretical one-hop jitter is compared with a preset link level conversion table to obtain a corresponding theoretical link level, and the theoretical link level is used as the theoretical deviation of the port.

[0024] In combination with the first aspect, in one embodiment, if an ANNO message sent by an upstream clock node and received by the downstream clock node does not contain an actual link deviation level, the actual link deviation of the upstream clock node is set to a default value.

[0025] In combination with the first aspect, in one implementation, when the clock source, as an upstream clock node, sends an ANNO message to a downstream clock node, the actual link deviation level is set to a default value.

[0026] In a second aspect, an embodiment of the present application provides a BMC source selection system, the system comprising:

[0027] A data acquisition module, which is used to control the downstream clock node to obtain the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation level and the port theoretical deviation level. The actual link deviation level is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation is the device accuracy of the clock node itself;

[0028] a data processing module, configured to control a downstream clock node to calculate a comprehensive link deviation level of each upstream clock node, wherein the comprehensive link deviation level is obtained by summing the larger value of the device delay of the upstream clock node and the device accuracy of the downstream clock node with the link accuracy of the upstream clock node;

[0029] The synchronization path selection module is used to control the downstream clock node to select the clock source of the upstream clock node with the smallest comprehensive link deviation level as the clock reference source for clock synchronization operation.

[0030] In conjunction with the second aspect, in one embodiment, the data acquisition module is further configured to acquire the actual link deviation level;

[0031] The data acquisition module controls the upstream clock node to send a first message to the downstream clock node, and uses a first timestamp to record the sending time of the first message;

[0032] When the downstream clock node receives the first message, the second timestamp is used to record the reception time of the first message;

[0033] Control the downstream clock node to send a second message to the upstream clock node, and use the third timestamp to record the sending time of the second message;

[0034] When the upstream clock node receives the second message, it uses the timestamp to record the receiving time of the second message;

[0035] The data acquisition module calculates an actual link deviation value based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, and compares the actual link deviation value with a preset link level conversion table to obtain a corresponding actual link level.

[0036] In conjunction with the second aspect, in one embodiment, the data acquisition module is further used to obtain the port theoretical deviation;

[0037] The data acquisition module acquires the theoretical one-hop jitter of the upstream clock node, compares the theoretical one-hop jitter with a preset link level conversion table, obtains the corresponding theoretical link level, and uses the theoretical link level as the port theoretical deviation.

[0038] The beneficial effects of the technical solutions provided in the embodiments of the present application include:

[0039] The concept of comprehensive link deviation is introduced into the existing BMC algorithm. The comprehensive link deviation is calculated based on the theoretical port deviation and the actual link deviation. The theoretical port deviation is the time jitter caused by the device accuracy of the clock node itself, and the actual link deviation is the time jitter caused by the link accuracy between the upstream clock node and the upstream clock node. When selecting a time synchronization path, the downstream clock node takes the larger value of the device accuracy of the upstream clock node and the device accuracy of its own clock node, and sums this larger value with the actual link deviation calculated by the upstream clock node and the upstream clock node to obtain the comprehensive link deviation of the upstream clock node relative to its own clock node. The smaller the comprehensive link deviation, the smaller the comprehensive jitter of the device and link in that direction. The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation as the clock reference source for clock synchronization operations, thereby achieving synchronization path selection based on optimal device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a flow chart of the BMC source selection method in the prior art when the GM ID is consistent;

[0041] Figure 2 This is a flow chart of a BMC source selection method in the prior art when the GM IDs are inconsistent;

[0042] Figure 3 A schematic diagram of the architecture of a hybrid networking topology in the prior art;

[0043] Figure 4 This is a flow chart of an embodiment of the BMC source selection method of the present application;

[0044] Figure 5 This is a flow chart of an embodiment of the BMC source selection method of the present application;

[0045] Figure 6 This is a flow chart of a specific embodiment of the BMC source selection method of this application;

[0046] Figure 7 This is a deviation level conversion table for an embodiment of the present application;

[0047] Figure 8 This is a functional module diagram of an embodiment of the BMC source selection system of the present application. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] First, some technical terms in this application are explained to facilitate those skilled in the art to understand this application.

[0050] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0051] In a first aspect, an embodiment of the present application provides a BMC source selection method.

[0052] In one embodiment, referring to Figure 4 , Figure 4 This is a flow chart of the first embodiment of the BMC source selection method of this application. Figure 4 As shown, the BMC source selection method includes:

[0053] Step S1: The downstream clock node obtains the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation and the port theoretical deviation. The actual link deviation is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation is the device accuracy of the clock node itself.

[0054] Step S2: The downstream clock node calculates the comprehensive link deviation of each upstream clock node. The comprehensive link deviation is obtained by summing the larger value of the device accuracy of the upstream clock node and the device accuracy of the downstream clock node with the link accuracy of the upstream clock node.

[0055] Step S3: The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation as the clock reference source for clock synchronization operation.

[0056] In this embodiment, in a network system requiring high-precision time synchronization, the clock source direction is regarded as the upstream direction, and the clock nodes sequentially connected to the clock source are regarded as the downstream direction. When a clock node selects a time synchronization path, the clock node serves as the downstream clock node, and the clock nodes sequentially connected to it in the upstream direction serve as the upstream clock node and the upstream-upstream clock node, respectively.

[0057] The downstream clock node receives the ANNO messages sent by each upstream clock node and, based on each ANNO message, selects the clock source corresponding to an upstream clock node as the clock reference source for clock synchronization. The ANNO message includes the actual link deviation and the theoretical port deviation. The actual link deviation is the link accuracy between the upstream clock node and the upstream clock node, while the theoretical port deviation is the device accuracy of the clock node itself. When calculating the comprehensive link deviation of each upstream clock node, the larger of the upstream clock node's device accuracy and the downstream clock node's device accuracy is taken. This larger value is summed with the actual link deviation calculated by the upstream clock node and the upstream clock node to obtain the comprehensive link deviation of the upstream clock node relative to its own clock node. The smaller the comprehensive link deviation, the smaller the comprehensive jitter of the device and link in that direction. The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation as the clock reference source for clock synchronization, thereby achieving synchronization path selection based on optimal device performance.

[0058] In summary, the present invention proposes the concept of link deviation and incorporates link deviation into the clock source data set of the BMC algorithm. Based on the new clock source data set, the device can select a clock source with better actual performance as the synchronization clock source.

[0059] Furthermore, in one embodiment, the ANNO message includes a clock source data set, and the clock source data set includes static configuration parameters, actual link deviation, and port theoretical deviation.

[0060] The actual link deviation and the theoretical port deviation are stored in the reserved field of the ANNO message.

[0061] Furthermore, in one embodiment, the method further includes:

[0062] When the integrated link deviations of the upstream clock nodes are the same, the downstream clock node selects a clock source of an upstream clock node as a clock reference source for clock synchronization according to static configuration parameters.

[0063] In this embodiment, the comparison of the comprehensive link deviation is placed before the comparison of the GM ID, such as Figure 5 As shown, the system first compares the overall link deviation and selects a clock source based on the device's actual performance. If the deviation levels of the two clock sources are the same, the system continues to select a clock source based on the existing BMC algorithm.

[0064] The actual link deviation and theoretical port deviation are transmitted in the reserved field of the ANNO message header. Each clock node device has multiple ports that can function as slave ports or master ports at different times. The device maintains a theoretical port deviation level for each port. For example, if the jitter of an ultra-high-precision device is 5ns, and the jitter of a standard-precision device is 30ns, this translates to a theoretical port deviation level of 1 for the ultra-high-precision device and 6 for the standard-precision device. After receiving ANNO messages from the upstream clock node, the multiple ports of the downstream clock node extract the actual link deviation and theoretical port deviation from each ANNO message. The downstream clock node then calculates the combined link deviation for each upstream clock node and selects the upstream clock node with the smallest combined link deviation as the previous hop on the synchronization path. At this point, the port on the downstream clock node connected to the upstream clock node with the smallest combined link deviation is considered the slave port, and the port on the upstream clock node with the smallest combined link deviation connected to the downstream clock node is considered the master port.

[0065] In a specific embodiment, if Figure 6 As shown, at a certain moment, device 1 is the clock source, device 2 is the upstream clock node, device 3 is the upstream clock node, device 4 is the downstream clock node, and device 5 is the downstream clock node.

[0066] When selecting the reference clock source and corresponding synchronization path for time synchronization, device 4 receives an ANNO message sent by device 3. The ANNO message contains the actual link deviation A and the theoretical port deviation B. The actual link deviation is calculated after interaction between device 3 and device 2, and the theoretical port deviation B is maintained by device 3 based on its own device performance. Device 4 calculates the comprehensive link deviation C based on the ANNO message, where C = A + MAX(B, D), where D is the theoretical port deviation of device 4 (the theoretical port deviations of all ports of device 4 are the same). After calculation, it is determined that the comprehensive link deviation of device 3 is the smallest. In this case, device 4 uses device 3 as the previous hop node of the time synchronization path and uses device 3's clock source, namely device 1, as the reference clock source for device 4's time synchronization.

[0067] After device 4 selects device 3 as the previous hop node of the time synchronization path, the port on device 4 used to connect to device 3 serves as the slave port of device 4. The slave port calculates the actual link deviation C between device 3 and device 4 by interacting with device 3. When device 4 sends an ANNO message to device 5, the port that outputs the ANNO message serves as the master port of device 4. Device 4 maintains the theoretical port deviation D of the master port. The ANNO message output by device 4 contains the actual link deviation C and the theoretical port deviation D. After receiving the ANNO message, device 5 also calculates the comprehensive link deviation based on the actual link deviation C, the theoretical port deviation D, and its own theoretical port deviation to select the route and source.

[0068] Some ports on the clock node function as passive ports. These ports only receive ANNO messages and do not send any messages. After the clock source corresponding to the upstream clock node that sends the ANNO message to the passive port is determined to be the reference clock source, the passive port functions as a slave port.

[0069] Furthermore, in one embodiment, the actual link deviation is obtained by the following steps:

[0070] The upstream clock node sends a first message to the downstream clock node, and uses a first timestamp to record a sending time of the first message.

[0071] When the downstream clock node receives the first message, it uses the second timestamp to record the reception time of the first message.

[0072] The downstream clock node sends a second message to the upstream clock node, and uses the third timestamp to record the sending time of the second message.

[0073] When the upstream clock node receives the second message, it records the receiving time of the second message using the timestamp.

[0074] The actual link accuracy value is calculated by combining the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, and the actual link accuracy value is compared with the preset link level conversion table to obtain the corresponding actual link level.

[0075] In this embodiment, the first message is a sync message, and the second message is a delay_req message. Assuming that the upstream clock node serves as the master node and the upstream clock node serves as the slave node, the paths through which various messages are transmitted between the master and slave nodes are symmetrical, and the delays are equal. Then, at time t1 based on the master node's local clock, the master node sends a sync message to the slave node. At this time, the local clock based on the slave node is t1'. If a two-step method is used, the master node then sends a follow_up message to bring the timestamp t1 to the slave node. The sync message is transmitted on the link between the master and the slave with a delay of t-ms. At time t2 based on the slave node's local clock, the slave node receives the sync message. At time t3 based on the slave node's local clock, the slave node sends a delay_req message to the master node. At this time, the local clock based on the master node is t3'. The delay_req message is transmitted on the link between the master and the slave with a delay of t-sm. At time t4 based on the master's local clock, the master receives the delay-req message. The master then sends a delay_resp message with timestamp t4 to the slave. At this point, the slave now has timestamps t1, t2, t3, and t4. Assuming these times, including the link delay, are represented as unsigned integers, the following calculation yields the time difference between the master and the slave: offset = ((t2-t1)+(t3-t4)) / 2. Therefore, once the slave obtains timestamps t1, t2, t3, and t4, it can determine the time difference and path delay between the master and the slave, and can then synchronize its local clock to the master. The offset is the actual link deviation between the upstream clock node and the upstream-upstream clock node.

[0076] After selecting its slave port, the clock node will continue to calculate the actual link deviation between the slave port and the previous hop node on its synchronization path for a period of time. The peak-to-peak value of the actual link deviation during this period is taken, and the pre-configured deviation level conversion table is searched to obtain the corresponding actual link deviation level. The deviation level conversion table is as follows: Figure 7 shown.

[0077] Furthermore, in one embodiment, the port theoretical deviation is obtained by the following steps:

[0078] Obtain the theoretical jitter per hop of the upstream clock node, compare the theoretical jitter per hop with the preset link level conversion table, and obtain the corresponding theoretical link level. Use the theoretical link level as the theoretical deviation of the port.

[0079] In this embodiment, the device maintains a theoretical port deviation level for each port, with an ultra-high precision of 5ns and a normal precision of 30ns. This is equivalent to an ultra-high precision deviation level of 1 and a normal precision deviation level of 6.

[0080] Furthermore, in one embodiment, if the actual link deviation does not exist in an ANNO message sent by an upstream clock node and received by the downstream clock node, the actual link deviation of the upstream clock node is set to a default value.

[0081] In this embodiment, if the link deviation level is not obtained or the device loses lock during switching, the reserved field in the ANNO message sent by the upstream clock node is 0. In this case, the actual link deviation of the upstream clock node is the power-on default value of 255.

[0082] Furthermore, in one embodiment, when the clock source, as an upstream clock node, sends an ANNO message to a downstream clock node, the actual link deviation is set to a default value.

[0083] In this embodiment, since there is no upstream clock node upstream of the clock source, the actual link deviation in the ANNO message sent by the clock source to the downstream clock node is set to a default value.

[0084] In addition, the clock source may inform the downstream clock node that it is the clock source in other ways instead of setting the actual link deviation to the default value in the ANNO message.

[0085] In a second aspect, an embodiment of the present application further provides a BMC source selection system.

[0086] In one embodiment, referring to Figure 8 , Figure 8 This is a functional module diagram of an embodiment of the BMC source selection system of this application. Figure 8 As shown, the BMC source selection system includes:

[0087] Data acquisition module 1 is used to control the downstream clock node to obtain the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation and the port theoretical deviation. The actual link deviation is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation is the device accuracy of the clock node itself.

[0088] Data processing module 2 is used to control the downstream clock node to calculate the comprehensive link deviation of each upstream clock node. The comprehensive link deviation is obtained by summing the larger value of the device accuracy of the upstream clock node and the device accuracy of the downstream clock node with the link accuracy of the upstream clock node.

[0089] The synchronization path selection module is used to control the downstream clock node to select the clock source of the upstream clock node with the smallest comprehensive link deviation as the clock reference source for clock synchronization operation.

[0090] In this embodiment, in a network system requiring high-precision time synchronization, the clock source direction is regarded as the upstream direction, and the clock nodes sequentially connected to the clock source are regarded as the downstream direction. When a clock node selects a time synchronization path, the clock node serves as the downstream clock node, and the clock nodes sequentially connected to it in the upstream direction serve as the upstream clock node and the upstream-upstream clock node, respectively.

[0091] The downstream clock node receives the ANNO messages sent by each upstream clock node and, based on each ANNO message, selects the clock source corresponding to one of the upstream clock nodes as the clock reference source for clock synchronization. The ANNO message includes the actual link deviation level and the port theoretical deviation level. The actual link deviation level is the link accuracy between the upstream clock node and the upstream clock node, while the port theoretical deviation level is the device accuracy of the clock node itself. When calculating the comprehensive link deviation level for each upstream clock node, the larger of the upstream clock node's device accuracy and the downstream clock node's device accuracy is taken. This larger value is then summed with the actual link deviation level calculated by the upstream clock node and the upstream clock node to obtain the comprehensive link deviation level of the port time source. The smaller the comprehensive link deviation level, the smaller the comprehensive jitter of the time source in that direction. The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation as the clock reference source for clock synchronization, thereby achieving synchronization path selection based on optimal device performance.

[0092] In summary, the present invention proposes the concept of link deviation level and incorporates the link deviation level into the clock source data set of the BMC algorithm. Based on the new clock source data set, the device can select a clock source with better actual performance as the synchronization clock source.

[0093] Among them, the functional implementation of each module in the above-mentioned BMC source selection system corresponds to each step in the above-mentioned BMC source selection method embodiment, and its functions and implementation processes are not repeated here one by one.

[0094] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0095] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0096] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0097] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0098] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of the present application.

[0100] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A BMC source selection method, characterized in that: The method comprises: The downstream clock node obtains the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation level and the port theoretical deviation level. The actual link deviation level is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation level is the device accuracy of the clock node itself. The downstream clock node calculates a comprehensive link deviation level of each upstream clock node, where the comprehensive link deviation level is obtained by summing a larger value of the device accuracy of the upstream clock node and the device accuracy of the downstream clock node and the link accuracy of the upstream clock node; The downstream clock node selects the clock source of the upstream clock node with the smallest comprehensive link deviation level as the clock reference source for clock synchronization operations; When the comprehensive link deviation levels of the upstream clock nodes are the same, the downstream clock node selects a clock source of an upstream clock node as a clock reference source for clock synchronization operations according to static configuration parameters.

2. The BMC source selection method according to claim 1, wherein: The ANNO message includes a clock source data set, which includes static configuration parameters, the actual link deviation and the port theoretical deviation; The actual link deviation and the port theoretical deviation are stored in the reserved field of the ANNO message.

3. The BMC source selection method according to claim 1, wherein: The actual link deviation level is obtained by the following steps: The upstream clock node sends a first message to the downstream clock node, and uses the first timestamp to record the sending time of the first message; When the downstream clock node receives the first message, it records the reception time of the first message using the second timestamp; The downstream clock node sends a second message to the upstream clock node, and uses the third timestamp to record the sending time of the second message; When the upstream clock node receives the second message, it records the reception time of the second message using the timestamp; The actual link deviation value is calculated by combining the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, and the actual link deviation value is compared with a preset link level conversion table to obtain the corresponding actual link level.

4. The BMC source selection method according to claim 1, wherein: The theoretical deviation level of the port is obtained by the following steps: The theoretical one-hop jitter of the upstream clock node is obtained, and the theoretical one-hop jitter is compared with a preset link level conversion table to obtain a corresponding theoretical link level, and the theoretical link level is used as the theoretical deviation of the port.

5. The BMC source selection method according to claim 1, wherein: If the actual link deviation level does not exist in the ANNO message sent by an upstream clock node and received by the downstream clock node, the actual link deviation of the upstream clock node is set to a default value.

6. The BMC source selection method according to claim 1, wherein: When the clock source, acting as an upstream clock node, sends an ANNO message to a downstream clock node, it sets the actual link deviation level to the default value.

7. A BMC source selection system, characterized in that: The system comprises: A data acquisition module, which is used to control the downstream clock node to obtain the ANNO message sent by each upstream clock node. The ANNO message includes the actual link deviation level and the port theoretical deviation level. The actual link deviation level is the link accuracy between the upstream clock node and the upstream clock node, and the port theoretical deviation is the device accuracy of the clock node itself; a data processing module, configured to control a downstream clock node to calculate a comprehensive link deviation level of each upstream clock node, wherein the comprehensive link deviation level is obtained by summing the larger value of the device accuracy of the upstream clock node and the device accuracy of the downstream clock node with the link accuracy of the upstream clock node; The synchronization path selection module is used to control the downstream clock node to select the clock source of the upstream clock node with the smallest comprehensive link deviation level as the clock reference source for clock synchronization operations; when the comprehensive link deviation levels of the upstream clock nodes are the same, the downstream clock node selects the clock source of an upstream clock node as the clock reference source for clock synchronization operations based on static configuration parameters.

8. The BMC source selection system according to claim 7, wherein: The data acquisition module is further used to obtain the actual link deviation level; The data acquisition module controls the upstream clock node to send a first message to the downstream clock node, and uses a first timestamp to record the sending time of the first message; When the downstream clock node receives the first message, the second timestamp is used to record the reception time of the first message; Control the downstream clock node to send a second message to the upstream clock node, and use the third timestamp to record the sending time of the second message; When the upstream clock node receives the second message, it uses the timestamp to record the receiving time of the second message; The data acquisition module calculates an actual link deviation value based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, and compares the actual link deviation value with a preset link level conversion table to obtain a corresponding actual link level.

9. The BMC source selection system according to claim 7, wherein: The data acquisition module is also used to obtain the port theoretical deviation; The data acquisition module acquires the theoretical one-hop jitter of the upstream clock node, compares the theoretical one-hop jitter with a preset link level conversion table, obtains the corresponding theoretical link level, and uses the theoretical link level as the port theoretical deviation.

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