A high-speed storage method and device for a QKD system

Abstract

The application provides a high-speed storage method and device for a QKD system, and belongs to the technical field of communication. The method comprises the following steps: performing ping-pong processing on input data; performing bit width conversion on the ping-pong processed data, and performing frame splicing on the bit width converted data; directly inputting the frame spliced data frame into an input end of a DDR3 until the DDR3 is full of data; and after the DDR3 is full of data, triggering an upper computer to read data from the DDR3 through a preset UDP network. After the input data of the DDR3 is processed, large capacity data can be stored in the DDR3, meanwhile, the network cable can transmit external data through the UDP protocol, and the two processes are performed simultaneously without considering the frame loss problem caused by delay, so that the high speed of quantum key distribution is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a high-speed storage method and device for a QKD system. BACKGROUND

[0002] Quantum key distribution (QKD) is a communication method for transmitting quantum keys through optical fibers, and the information carrier is light, which is distributed through the BB84 protocol combined with polarization encoding.

[0003] In a quantum key distribution system, both the transmitting end and the receiving end need to encode and decode data according to photon information and interact through a classical channel. With the improvement of the rate of the quantum key distribution system, the traditional data interaction relying on a serial port cannot meet the system requirements, and the transmission through a network cable is prone to packet loss, which is also difficult to apply to a quantum key distribution system that requires basis vector comparison.

[0004] Therefore, there is an urgent need for a new technical solution to be applied to a quantum key distribution system to achieve a higher rate of quantum key distribution. SUMMARY

[0005] The present application provides a high-speed storage method and device for a QKD system to solve the defect that the data transmission method in the prior art cannot be applied to a quantum key distribution system.

[0006] In a first aspect, the present application provides a high-speed storage method for a QKD system, comprising: performing ping-pong processing on input data; performing bit width conversion on the ping-pong processed data, and performing frame splicing on the bit width converted data; directly inputting the frame spliced data frame to the input end of the DDR3 until the DDR3 is full of data; after the DDR3 is full of data, triggering the host computer to read data from the DDR3 through a preset UDP network.

[0007] According to the high-speed storage method for a QKD system provided by the present application, after the DDR3 is full of data, the host computer is triggered to read data from the DDR3 through a preset UDP network, which comprises: reading data from the DDR3, performing cross-domain conversion to convert the data under the DDR3 clock into a standard UDP protocol clock; distinguishing different data frames according to the frame header information to perform frame splitting operation on the cross-domain converted data; performing bit width conversion operation on the frame split data and transmitting it to the host computer based on the UDP protocol.

[0008] According to the high-speed storage method for a QKD system provided by the present application, it further comprises: when the data in the DDR3 is read empty, triggering a second storage mechanism to cycle in sequence.

[0009] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0010] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0011] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0012] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0013] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0014] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0015] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0016] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0017] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0018] The high-speed storage method for the QKD system provided by the application comprises the following steps: performing bit width conversion on the data after the ping-pong processing, i.e., converting 4-bit data into 64-bit data; and performing bit width conversion on the data after the frame disassembly, i.e., converting 4-bit data into 64-bit data.

[0019] In a fourth aspect, the application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the high-speed storage method for a QKD system according to any one of the above.

[0020] The high-speed storage method and device for a QKD system provided by the application can store large-capacity data in a DDR3 while transmitting data externally through a network cable via a UDP protocol, and the two operations are performed simultaneously without considering the frame loss problem caused by delay, thereby ensuring the high speed of quantum key distribution.

[0021] The application is based on a hardware architecture combining FPGA and DDR3, and realizes quantum key signal processing from a high-speed stream in combination with a cross-clock processing mode based on ping-pong processing. Meanwhile, in order to maximize the storage space, the data is converted in 4bit_64bit bit width, the cascade idea is introduced, the FIFO capacity is expanded, the data is spliced, 64 frames are spliced into 1 frame and input to the input end of the DDR3, and after the DDR3 is full of data, the overflow flag triggers the host computer of the quantum key distribution system to read the DDR3 data. Since the UDP network cable is 125M, after the DDR3 is read out, the data needs to be converted in 64bit_4bit bit width and split, and after splitting, the frame header is a frame counter, which is convenient for the host computer to receive data. This storage idea enables the receiving and transmitting ends to realize high-speed and large-capacity reading mode, and also reasonably utilizes the large-capacity storage space of the DDR3 and the appropriate data bit width. After the capacity of the DDR3 is expanded, the problem of insufficient data transmission per frame of the UDP protocol and the resulting frame loss caused by the delay of the host computer can be solved, thereby achieving the purpose of high-speed communication. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0023] Figure 1 is a flowchart of the high-speed storage method for a QKD system provided by the application;

[0024] Figure 2 is a schematic diagram of the principle of ping-pong processing provided by the application;

[0025] Figure 3 is a simulation diagram of low-speed data stream after ping-pong processing provided by the application;

[0026] Figure 4Is the simulation diagram of the input 4bit frame data stream converted to 32bit output by bit width conversion provided by the application;

[0027] Figure 5 Is the local enlarged view provided by the application;

[0028] Figure 6 Is the simulation diagram of data frame splicing provided by the application;

[0029] Figure 7 Is the structural schematic diagram of the electronic device provided by the application. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0031] It should be noted that, in the description of the embodiments of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0032] Optical fiber quantum key distribution (QKD) is a communication method for transmitting quantum keys through optical fibers, and the information carrier is light, and the key distribution is performed through the BB84 protocol combined with polarization encoding.

[0033] In the QKD system, the sending end and the receiving end need to compare the base vectors according to the classical channel, and when the system continuously works, due to the large read-write bandwidth, sufficient storage space is needed to consume the encoding and decoding data. The large-capacity DDR3 memory is adopted, and the high-speed conversion mechanism can solve the above problems. Data buffering plays a crucial role in a large data real-time acquisition system. It has multiple implementation methods: asynchronous FIFO with first-in-first-out read-write rule, no need to operate the read-write address, independent read-write clock, etc. It is widely used in cross-clock domain data acquisition and transmission systems. However, due to the fact that the on-chip FIFO capacity of the common FPGA is mostly in the MB level, it is difficult to meet the requirements of large data buffering, and the FIFO address is controlled by the internal address pointer, and cannot be determined by the address line, so the portability is poor. The memory capacity of DDR3 SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has reached the GB level, and it can completely buffer a large amount of data at the same time, so it is favored by engineers, but DDR3 cannot directly complete the data buffering by identifying the read-write enable set by the outside world like FIFO, but needs to design a complex read-write operation control module. This control module can convert the data rate and bit width, and then splice the new data frame into a giant frame to introduce it into the DDR3 input end, and then transmit it to the upper computer through the UDP protocol for subsequent processing, so as to achieve high-speed transmission without packet loss.

[0034] Double Data Rate Synchronous Dynamic Random Access Memory (DDR3 SDRAM) can transmit data at the rising edge and falling edge of the clock at the same time, and its transmission rate is twice that of SDRAM without changing the clock frequency. The DDR3 uses the MT8JTF12864HZ- DDR3 memory bar of Micron Company, which is internally configured with 8 BANKs, can obtain high-speed operation with 8n prefetch structure, and uses advanced synchronous circuits to complete reading, writing data, commands and CPU synchronization independently. 8 BANKs correspond to 3 BANK address selection lines, 14 row address lines and 10 column address lines are multiplexed, and external communication is completed through 8 groups of data lines (DQ0-DQ7), so the capacity of each memory chip is 8*2^3*2^14*2^10=128MB. The burst length of the memory bar is set to 8, each chip contains 8 data lines (DQ0-DQ7), and 8 chips are placed together, so the data bit width of each read-write operation is 512 bits, which greatly improves the read-write efficiency of DDR3.

[0035] The following will be described Figures 1-7 The high-speed storage method and device for the QKD system provided by the embodiment of the application are described.

[0036] Figure 1 is a flowchart of the high-speed storage method for a QKD system provided by the present application, as shown in Figure 1 which includes but is not limited to the following steps:

[0037] Step 101: Ping-Pong processing is performed on the input data.

[0038] Figure 2 is a schematic diagram of the principle of the Ping-Pong processing provided by the present application, as shown in Figure 2 external input data, at the rising edge of the odd frame, the data selection module sends the data into the first buffer and reads the data in the second buffer; at the falling edge of the odd frame, the data selection module switches to the second buffer; at the rising edge of the even frame, the data selection module sends the data into the second buffer and reads the data in the first buffer; at the falling edge of the even frame, the data selection module switches to the first buffer. According to the above rules, the data is cyclically read and read out, and switches back and forth. In order to achieve the conversion of data from low speed to high speed, the write clock of the double FIFO of the Ping-Pong processing is the slow clock of the input, and the read clock is selected as the high-speed clock, achieving the purpose.

[0039] Step 102: Bit width conversion is performed on the data after Ping-Pong processing, and frame splicing is performed on the data after bit width conversion.

[0040] Specifically, after the data is converted from low speed to high speed, in order to interface with the DDR3 driver, the data is first converted in bit width, from 4 bits directly to 64 bits output, a 64-bit shift register is selected for data operation, 4-bit data is input into the lowest 4 bits of the 64-bit shift register, at this time the shift register is shifted left by 4 bits, and the 4-bit data enters the lowest 4 bits of the shift register again, and the cycle is repeated, so that 64-bit conversion data can be obtained, realizing the bit width conversion operation.

[0041] After the bit width conversion operation, frame splicing operation is performed, a large-capacity FIFO is opened, the data is input into the input end of the FIFO, and the read enable of the FIFO is triggered at the falling edge of the 64th frame data valid bit to read out the spliced data frame. Since the single frame reading time of the 64-frame extension bit is long, during this period, the 65th frame enters the FIFO, and there is no empty data in the FIFO. If accurate data is to be obtained, all data needs to be read out before the 65th frame enters the FIFO. To solve this problem, the Ping-Pong processing operation mode can be used again, at this time the read and write clocks of the double FIFO are selected as the same frequency clock, the first 64 frames enter the first buffer and wait, the second buffer is read at the rising edge of the first frame, the second buffer is switched to at the falling edge of the 64th frame, the second buffer is entered at the rising edge of the 65th frame and waits, and the first buffer is read, the first buffer is switched to again at the falling edge of the 128th frame, and the cycle is repeated, achieving the purpose.

[0042] Step 103: The data frame after frame splicing is directly input to the input end of DDR3 until the DDR3 is full of data.

[0043] Step 104: After the DDR3 is full of data, the host computer triggers to read data from the DDR3 through a preset UDP network.

[0044] In order to realize high-speed storage interaction of data, the host computer needs to quickly read data after the DDR3 is full of data to facilitate the next interaction. The interaction mode between the host computer and the DDR3 adopts a gigabit UDP network mode.

[0045] The data read out by the DDR3 is first input into the FIFO, and the cross-domain conversion is performed to convert the data driven by the DDR3 clock into a 125M standard UDP protocol clock. The FIFO directly performs cross-domain conversion in a first-in-first-out mode.

[0046] The data converted by the cross-domain conversion is first subjected to splitting processing. Different frames are distinguished according to the frame header, and a dual-port RAM is selected to perform address correspondence on the frame. The RAM read enable is generated according to the address information and the valid signal information, that is, each frame of data is read to achieve the effect of frame splitting.

[0047] The data after frame splitting is subjected to 64-bit to 4-bit conversion operation, and is transmitted to the host computer through the UDP protocol. After the DDR3 data is read empty, the second storage mechanism is triggered in turn to realize the high-speed storage function of the QKD system.

[0048] As another optional embodiment, the technical solutions of the application are further described in the form of data flow.

[0049] (1) Low-speed data input

[0050] The external low-speed data is input to the system; and the output data is subjected to ping-pong processing, specifically:

[0051] On the rising edge of the odd frame, the data selection module inputs the data into the first buffer zone, and reads the data in the second buffer zone at the same time.

[0052] On the falling edge of the odd frame, the data selection module switches to the second buffer zone.

[0053] On the rising edge of the even frame, the data is input into the second buffer zone, and the data in the first buffer zone is read at the same time.

[0054] On the falling edge of the even frame, the data selection module switches back to the first buffer zone.

[0055] (2) Bit width conversion

[0056] Using 64-bit shift register, 4-bit data is moved into the lowest 4-bit of the register, every time 4-bit, until 64-bit data is formed.

[0057] (3) Frame splicing

[0058] Open a large-capacity FIFO, and send 64-bit data into the FIFO one by one.

[0059] The falling edge of the 64th frame data valid trigger FIFO read enable, read the spliced data frame.

[0060] In order to avoid the internal data not read out when the 65th frame data enters the FIFO, the ping-pong processing mode is adopted, and two FIFOs are used alternately.

[0061] The first 64 frames enter the first buffer, and the second buffer is read at the rising edge of the first frame. The second buffer is switched at the falling edge of the 64th frame.

[0062] The 65th frame enters the second buffer at the rising edge, and reads the data of the first buffer. The first buffer is switched again at the falling edge of the 128th frame, and the cycle is repeated.

[0063] (4) Data storage in DDR3

[0064] The spliced data frame is directly input to the input end of DDR3, until the DDR3 is full of data.

[0065] When the DDR3 is full of data, the host computer is triggered to read the data through the gigabit UDP network.

[0066] (5) Data readout and cross-domain conversion

[0067] After the data is read from the DDR3, it is first entered into the FIFO for cross-domain conversion, and the data under the DDR3 clock is converted into the 125M standard UDP protocol clock.

[0068] Single FIFO is used for cross-domain conversion to ensure the order and integrity of the data.

[0069] (6) Data splitting and transmission

[0070] The cross-domain converted data is first processed by splitting, and different data frames are distinguished according to the frame header information.

[0071] Dual-port RAM is selected for frame address correspondence, and RAM read enable is generated according to address information and valid signal information to read each frame of data, realizing the effect of frame splitting.

[0072] The split frame data is then operated by 64-bit to 4-bit, and is transmitted to the host computer through the UDP protocol.

[0073] (7) Cycle storage mechanism

[0074] When the DDR3 data read is empty, the second storage mechanism is triggered, and the cycle is performed in turn.

[0075] This mechanism ensures the continuous and efficient storage and transmission of data.

[0076] Further, the simulation analysis process of the present application is introduced below.

[0077] VIVADO is used for simulation analysis, and the input source end is 4-bit coded information, including 1018 data and 6 frame headers to form an orange clock as shown in Figure 4 The input data stream passes through a double asynchronous FIFO, and the write clock of the asynchronous FIFO is 125M, Figure 3 is the simulation diagram of the low-speed data stream after ping-pong processing provided by the present application, the orange is the input low-speed data stream, and since the sampling clock is 10M, it can be seen that the occupied bandwidth is very large, and the gray part is the result after ping-pong processing, and it can be seen that the data stream has been rate converted, and there is a long time gap between frames, which can be further processed.

[0078] Figure 4 is the simulation diagram of the input 4bit frame data stream converted to 32bit output by bit width conversion provided by the present application, the orange is a 25M 4bit data stream, and the data amount of each frame is 1024, and the gray is a 125M 32bit data stream, and according to the data matching rule, the number of data in each frame of the gray part is 128, Figure 5 is a local enlarged view provided by the present application, and the value of rd_data_count at the frame tail is 7F, i.e. the value is 128, and the bit width display is 32. According to the result of the frame counter, the matching output of 1024*4=128*32 is obtained, and the data conversion effect is achieved.

[0079] Since the read-write depth of DDR3 is a multiple of 256, 16 frames are spliced here, i.e. 128*32bit*16=2048*32, the depth of each frame is expanded to 2048, and the data bit width is 32, Figure 6 is the simulation diagram of data frame splicing provided by the present application, and the orange part is the input data frame, and it can be seen that the frame counter is converted every 16 times, and the output data is shown in gray, i.e. the data stream of 128*32 is converted to the data stream of 2096*32, i.e. every 16 frames are spliced into 1 frame, and the storage depth of DDR3 is expanded. According to the local enlarged view, it can be seen that the value of data_out_cnt is 2048 after the input end frame tail 128 is output, which achieves the matching purpose, so that the data capacity is expanded by 16 times.

[0080] In another aspect, the application also provides a high-speed storage device for a QKD system, comprising:

[0081] a first processing module, configured to perform ping-pong processing on input data;

[0082] a second processing module, configured to perform bit width conversion on the ping-pong processed data and frame splicing on the bit width converted data;

[0083] a third processing module, configured to directly input the frame spliced data frame to an input end of a DDR3 until the DDR3 is full of data;

[0084] a fourth processing module, configured to trigger a host computer to read data from the DDR3 through a preset UDP network after the DDR3 is full of data.

[0085] It should be noted that the high-speed storage device for a QKD system provided by the embodiment of the application can perform the high-speed storage method for a QKD system described in any of the above embodiments during specific operation, and the embodiment will not be described here.

[0086] In summary, the high-speed storage method and device for a QKD system provided by the application have the following beneficial effects compared with the prior art:

[0087] (1) The application can store large capacity data in the DDR3 after performing data processing on the input data driven by the DDR3, and the network cable can transmit data externally through the UDP protocol, both of which are performed simultaneously without considering the frame loss problem caused by delay, thereby ensuring the high speed of quantum key distribution.

[0088] (2) The application realizes quantum key signal processing from high-speed flow based on the hardware architecture combined by FPGA and DDR3 and the cross-clock processing mode based on ping-pong processing. In order to maximize the storage space, the application performs 4bit_64bit bit width conversion on the data, introduces the cascade idea, expands the FIFO capacity, splices the data, inputs 64 frames to the input end of the DDR3, and triggers the quantum key distribution system host computer to read the DDR3 data after the overflow flag of the DDR3 is full of data. Since the UDP network cable is 125M, 64bit_4bit bit width conversion and data splitting are performed after the DDR3 is read out, and the effect after splitting is that the frame header is the frame counter, which is convenient for the host computer to receive data. This storage idea enables the receiving and transmitting ends to realize high-speed and large-capacity reading mode, and also reasonably utilizes the large-capacity storage space of the DDR3 and the appropriate data bit width. After capacity expansion of the DDR3, the problem of insufficient data transmission per frame of the UDP protocol and the frame loss problem caused by delay of the host computer can be solved, and the purpose of high-speed communication is achieved.

[0089] Figure 7is a structural schematic diagram of an electronic device provided by the present application, as shown in Figure 7 The electronic device can include a processor 710, a communications interface 720, a memory 730, and a communications bus 740, wherein the processor 710, the communications interface 720, and the memory 730 complete mutual communication through the communications bus 740. The processor 710 can call logical instructions in the memory 730 to execute a high-speed storage method for a QKD system, which includes: performing ping-pong processing on input data; performing bit width conversion on the ping-pong processed data, and performing frame splicing on the bit width converted data; directly inputting the frame spliced data frame to an input end of a DDR3 until the DDR3 is full of data; after the DDR3 is full of data, triggering an upper computer to read data from the DDR3 through a preset UDP network.

[0090] In addition, the logical instructions in the memory 730 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0091] On the other hand, the present application also provides a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, and the computer program includes program instructions, when the program instructions are executed by a computer, the computer can execute the high-speed storage method for a QKD system provided by the above-mentioned embodiments, which includes: performing ping-pong processing on input data; performing bit width conversion on the ping-pong processed data, and performing frame splicing on the bit width converted data; directly inputting the frame spliced data frame to an input end of a DDR3 until the DDR3 is full of data; after the DDR3 is full of data, triggering an upper computer to read data from the DDR3 through a preset UDP network.

[0092] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements a high-speed storage method for a QKD system as provided by any of the above embodiments, the method comprising: performing ping-pong processing on input data; performing bit width conversion on the ping-pong processed data, and performing frame splicing on the bit width converted data; directly inputting the frame spliced data frame to an input end of a DDR3 until the DDR3 is full of data; after the DDR3 is full of data, triggering a host computer to read data from the DDR3 through a preset UDP network.

[0093] Those skilled in the art can clearly understand from the above description of the embodiments that each embodiment can be realized by means of software and a necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method described in each embodiment or some part of the embodiment.

[0094] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features thereof; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high-speed storage method for a QKD system, characterized by, The application relates to a high-speed storage method for a QKD system. The input data is ping-pong processed; The ping-pong processed data is subjected to bit width conversion, and the bit width converted data is subjected to frame splicing; The frame spliced data frame is directly input to the input end of a DDR3 until the DDR3 is full of data; After the DDR3 is full of data, an upper computer is triggered to read the data from the DDR3 through a preset UDP network, specifically including: The data is read out from the DDR3 and enters a first-in-first-out queue FIFO for cross-domain conversion to convert the data under the DDR3 clock into standard UDP protocol clock; Different data frames are distinguished according to frame header information to perform frame disassembling operation on the cross-domain converted data; The frame disassembled data is subjected to bit width conversion operation and is transmitted to the upper computer based on the UDP protocol; The bit width conversion of the ping-pong processed data is converting 4-bit data into 64-bit data; and the bit width conversion operation of the frame disassembled data is converting 4-bit data into 64-bit data.

2. The high-speed storage method for a QKD system according to claim 1, wherein, The application further relates to a high-speed storage method for a QKD system. The frame spliced data is subjected to bit width conversion, including:

3. The high-speed storage method for a QKD system according to claim 2, wherein, A first-in-first-out queue FIFO is created, and 64-bit data is sequentially sent into the FIFO; The falling edge of the 64th frame data valid bit triggers the read enable of the FIFO to read the spliced data frame. The input data is ping-pong processed, including: 4.The high-speed storage method for a QKD system according to claim 1, wherein, At the rising edge of an odd frame, a data selection module sends data into a first buffer and reads data in a second buffer; at the falling edge of the odd frame, the data selection module is switched to the second buffer; At the rising edge of an even frame, the data selection module sends data into the second buffer and reads data in the first buffer; at the falling edge of the even frame, the data selection module is switched to the first buffer. The 4-bit data is converted into 64-bit data, including:

5. The high-speed storage method for a QKD system according to claim 1, wherein, A 64-bit shift register is used to convert 4-bit data into 64-bit data. The application relates to a high-speed storage method for a QKD system.

6. A high-speed storage device for a QKD system, characterized by, The input data is ping-pong processed by the first processing module; The ping-pong processed data is subjected to bit width conversion, and the bit width converted data is subjected to frame splicing by the second processing module; The frame spliced data frame is directly input to the input end of a DDR3 until the DDR3 is full of data by the third processing module; After the DDR3 is full of data, the fourth processing module triggers an upper computer to read the data from the DDR3 through a preset UDP network. The computer program is executed by a processor to realize the steps of the high-speed storage method for the QKD system.

7. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to realize the steps of the high-speed storage method for the QKD system.

8. A computer program product comprising a computer program, characterized in that, ​

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