Semiconductor structure preparation method and semiconductor structure

Abstract

The present application relates to a method for preparing a semiconductor structure and a semiconductor structure. The method for preparing the semiconductor structure includes: providing a substrate; forming a stacked structure on the upper surface of the substrate, the stacked structure including a first sidewall dielectric layer, a second sidewall dielectric layer, a conductive layer, a third sidewall dielectric layer, and a fourth sidewall dielectric layer stacked in sequence from bottom to top; the first sidewall dielectric layer and the second sidewall dielectric layer have different dielectric constants; the third sidewall dielectric layer and the fourth sidewall dielectric layer have different dielectric constants; forming a plurality of channel holes in the stacked structure; forming an active pillar in each channel hole, the active pillar and the sidewall of the channel hole having a spacing; forming a wordline isolation trench in the stacked structure to obtain a plurality of spaced wordlines; the wordline surrounds the active pillar and extends along a first direction; the wordline includes a first outer sidewall, a first inner sidewall, a wordline conductive layer, a second inner sidewall, and a second outer sidewall stacked in sequence from bottom to top.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of memory technology, the miniaturization of memory devices has become a key technical issue. However, the miniaturization of memory devices is approaching the physical limit, and the related technologies are no longer applicable to advanced memories due to the short channel effect.

[0003] Vertical gate-all-around transistors with superior gate control capabilities are currently being used in next-generation advanced memories. First, vertical gate-all-around devices have strong gate control capabilities and weak short-channel effects, which can improve retention time; second, vertical gate-all-around devices have a small area, and the unit area of ​​memories using vertical gate-all-around transistors can be as small as 4F. 2 (“F” stands for size factor, which is the minimum feature size in the manufacturing process), compared to the current 6F 2 , 4F 2 The area can be reduced by about 30%.

[0004] However, existing memory cells based on vertical gate-all-around devices have problems such as low gate electric field control capability, subthreshold characteristics, and low switching ratio. Summary of the Invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor structure to address the above-mentioned problems, including:

[0006] providing a substrate;

[0007] forming a stacked structure on the upper surface of the substrate, the stacked structure comprising a first spacer dielectric layer, a second spacer dielectric layer, a conductive layer, a third spacer dielectric layer, and a fourth spacer dielectric layer stacked sequentially from bottom to top; the first spacer dielectric layer and the second spacer dielectric layer have different dielectric constants; and the third spacer dielectric layer and the fourth spacer dielectric layer have different dielectric constants;

[0008] forming a plurality of channel holes in the stacked structure;

[0009] forming an active pillar in each of the channel holes, wherein the active pillar is spaced apart from a sidewall of the channel hole;

[0010] A word line isolation trench is formed in the stacked structure to obtain a plurality of spaced word lines; the word lines surround the active pillars and extend along a first direction; the word lines include a first outer sidewall, a first inner sidewall, a word line conductive layer, a second inner sidewall, and a second outer sidewall stacked sequentially from bottom to top;

[0011] A gate dielectric layer is formed between the word line and the active pillar.

[0012] In one embodiment, the first spacer dielectric layer includes a low-k dielectric layer, the second spacer dielectric layer includes a high-k dielectric layer, the third spacer dielectric layer includes a high-k dielectric layer, and the fourth spacer dielectric layer includes a low-k dielectric layer.

[0013] In one embodiment, before forming the active pillars in the channel holes, the method further includes: forming a sacrificial layer on the sidewalls of the channel holes; and forming a gate dielectric layer between the word lines and the active pillars includes:

[0014] removing the sacrificial layer to form a sacrificial gap between the active pillar and the sidewall of the channel hole;

[0015] A gate dielectric layer is formed in the sacrificial gap.

[0016] In one embodiment, before forming the stacked structure on the upper surface of the substrate, the method further includes:

[0017] performing a doping process on the substrate;

[0018] Etching the substrate to form a plurality of spaced-apart bit line steps;

[0019] forming a protection sidewall, wherein the protection sidewall covers the top of the bit line step and extends to the sidewall of the bit line step to cover a portion of the sidewall of the bit line step;

[0020] forming a metal layer, wherein the metal layer at least covers the exposed sidewalls of the bit line step;

[0021] The resulting structure is annealed to form a buried metal silicide bit line extending along a second direction intersecting the first direction.

[0022] In one embodiment, before forming the protective spacer, the method further includes: forming an isolation dielectric layer between adjacent bit line steps and outside the bit line steps; the protective spacer is located on the isolation dielectric layer;

[0023] After forming the protective sidewalls and before forming the metal layer, the method further includes: etching back the isolation dielectric layer to form a first isolation layer, wherein the first isolation layer is spaced apart from the protective sidewalls to expose a portion of the sidewalls of the bit line step;

[0024] After forming the buried metal silicide bit line and before forming the stacked structure on the upper surface of the substrate, the method further includes: removing the protective sidewalls; forming a second isolation layer between adjacent bit line steps and outside the bit line steps, wherein the upper surface of the second isolation layer is flush with the upper surface of the bit line step;

[0025] The stacked structure covers the upper surface of the second isolation layer and the upper surface of the bit line step; the channel hole and the word line isolation groove both penetrate the stacked structure and extend to the upper surface of the bit line step.

[0026] In one embodiment, after forming a gate dielectric layer between the word line and the active pillar, the method further includes:

[0027] forming a word line isolation layer, wherein the word line isolation layer fills the word line isolation groove and covers the active pillar and the word line;

[0028] forming a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in a one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the active pillars;

[0029] A plurality of capacitors are formed, wherein the capacitors are arranged in a one-to-one correspondence with the through-hole capacitor contact structures, and the lower electrodes of the capacitors are in contact with the upper surfaces of the through-hole capacitor contact structures.

[0030] The present application also provides a semiconductor structure, comprising:

[0031] substrate;

[0032] a plurality of active pillars arranged at intervals and located on the substrate;

[0033] A plurality of spaced-apart word lines are located on the substrate, the word lines encircling the active pillars and extending along a first direction; the word lines include a first outer sidewall, a first inner sidewall, a word line conductive layer, a second inner sidewall, and a second outer sidewall stacked sequentially from bottom to top; the dielectric constant of the first outer sidewall is different from the dielectric constant of the first inner sidewall, and the dielectric constant of the second outer sidewall is different from the dielectric constant of the second inner sidewall;

[0034] The gate dielectric layer is located between the word line and the active pillar.

[0035] In one embodiment, the first outer sidewall includes a low-k dielectric layer, the first inner sidewall includes a high-k dielectric layer, the second inner sidewall includes a high-k dielectric layer, and the second outer sidewall includes a low-k dielectric layer.

[0036] In one embodiment, the substrate includes a plurality of spaced-apart bit line steps; and the semiconductor structure further includes:

[0037] a buried metal silicide bit line, located in the bit line step and spaced apart from both the upper and lower surfaces of the bit line step;

[0038] a first isolation layer covering the surface of the substrate between the bit line steps and outside the bit line steps;

[0039] a second isolation layer, located on an upper surface of the first isolation layer, wherein an upper surface of the second isolation layer is flush with an upper surface of the bit line step;

[0040] Wherein, the lower surface of the active pillar contacts the upper surface of the bit line step.

[0041] In one embodiment, the semiconductor structure further comprises:

[0042] a word line isolation layer, the word line isolation layer filling the word line isolation grooves between adjacent word lines and covering the active pillars and the word lines;

[0043] a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in a one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the active pillars;

[0044] A plurality of capacitors are provided in a one-to-one correspondence with the through-hole capacitor contact structures, and lower electrodes of the capacitors are in contact with upper surfaces of the through-hole capacitor contact structures.

[0045] The preparation method and semiconductor structure of the present application are as follows: a stacked structure is formed on the upper surface of a substrate, and then a plurality of channel holes are formed in the stacked structure, and active pillars are formed in each channel hole, with a spacing between the active pillars and the sidewalls of the channel holes, so that a gate dielectric layer is subsequently formed between the word lines and the active pillars to isolate and protect the active pillars; a word line isolation groove is formed in the stacked structure to obtain a plurality of spaced word lines, and each word line can connect the active pillars in the same row or column in series; the stacked structure includes: A first spacer dielectric layer, a second spacer dielectric layer, a conductive layer, a third spacer dielectric layer, and a fourth spacer dielectric layer are stacked in sequence. The first spacer dielectric layer and the second spacer dielectric layer have different dielectric constants, and the third spacer dielectric layer and the fourth spacer dielectric layer have different dielectric constants. This results in different dielectric constants between the first outer sidewall and the first inner sidewall of the word line, and different dielectric constants between the second outer sidewall and the second inner sidewall. This enhances the electric field control of the word line on the source / drain, improves the subthreshold characteristics, and increases the on / off ratio of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0048] Figure 2 is a schematic top view of a semiconductor structure provided in one embodiment;

[0049] Figure 3 Figure (a) shows the structure obtained in step S101 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S101 in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0050] Figure 4 A flow chart of a method for preparing a semiconductor structure before forming a stacked structure on the upper surface of a substrate provided in one embodiment;

[0051] Figure 5 Figure (a) shows the structure obtained in step S401 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S401 according to an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0052] Figure 6 Figure (a) shows the structure obtained in step S402 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a cross-sectional structure along the aa' direction, provided in an embodiment of the present invention. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0053] Figure 7 FIG. (a) shows a structure obtained by forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps in one embodiment. Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction aa' shown in FIG. (b) is a structure obtained by forming a first isolation dielectric layer between adjacent bit line steps and outside the bit line steps in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0054] Figure 8 Figure (a) shows the structure obtained in step S403 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S403 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0055] Figure 9FIG. (a) in FIG. 1 shows a step of etching back the first isolation dielectric layer to form the first isolation layer provided in an embodiment. Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', FIG. (b) is a schematic diagram of a step of etching back the first isolation dielectric layer to form a first isolation layer provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0056] Figure 10 Figure (a) shows the structure obtained in step S404 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S404 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0057] Figure 11 Figure (a) shows the structure obtained in step S405 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S405 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0058] Figure 12 FIG. (a) shows a structure obtained by forming a second isolation layer between adjacent bit line steps and outside the bit line steps in one embodiment. Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', FIG. (b) is a schematic diagram of a structure obtained by forming a second isolation layer between adjacent bit line steps and outside the bit line steps in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0059] Figure 13 Figure (a) shows the structure obtained in step S102 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S102 in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0060] Figure 14 Figure (a) shows the structure obtained in step S103 provided in one embodiment. Figure 2 (b) is a schematic diagram of the cross-sectional structure along the aa' direction, and (b) is a schematic diagram of the structure obtained in step S103 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0061] Figure 15 FIG. (a) shows a structure obtained by forming a sacrificial layer on the sidewall of each channel hole according to an embodiment. Figure 2FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', FIG. (b) is a schematic diagram of a structure obtained by forming a sacrificial layer on the sidewall of each channel hole provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0062] Figure 16 Figure (a) shows the structure obtained in step S104 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S104 in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0063] Figure 17 Figure (a) shows the structure obtained in step S105 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S105 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0064] Figure 18 FIG. (a) shows a structure obtained by removing a sacrificial layer in an embodiment to form a sacrificial gap between the active pillar and the sidewall of the channel hole. Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure in the direction of aa', ... Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0065] Figure 19 Figure (a) shows the structure obtained in step S106 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (c) is a schematic diagram of a cross-sectional structure along the aa' direction, and (d) is a schematic diagram of a cross-sectional structure along the aa' direction, Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0066] Figure 20 Figure (a) shows the structure obtained in step S107 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S107 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction;

[0067] Figure 21 Figure (a) shows the structure obtained in step S108 provided in one embodiment. Figure 2 (b) is a schematic diagram of a cross-sectional structure along the aa' direction, and (b) is a schematic diagram of a structure obtained in step S108 provided in an embodiment. Figure 2 Schematic diagram of the cross-sectional structure in the bb' direction.

[0068] Description of reference numerals:

[0069] 10. Substrate; 101. Bitline step; 102. Protective sidewall; 103. Metal layer; 104. Buried metal silicide bitline; 20. Isolation stack; 21. First isolation layer; 211. First isolation dielectric layer; 22. Second isolation layer; 30. Stack structure; 31. First sidewall dielectric layer; 32. Second sidewall dielectric layer; 33. Conductive layer; 34. Third sidewall dielectric layer; 35. Fourth sidewall dielectric layer; 301. Channel hole; 40. Active Pillar; 41, sacrificial layer; 50, word line; 51, first outer side wall; 52, first inner side wall; 53, word line conductive layer; 54, second inner side wall; 55, second outer side wall; 501, word line isolation groove; 502, sacrificial gap; 56, gate dielectric layer; 57, word line isolation layer; 60, through-hole capacitor contact structure; 61, contact dielectric layer; 62, contact conductive layer; 70, capacitor; 71, upper electrode; 72, capacitor dielectric layer; 73, lower electrode. DETAILED DESCRIPTION

[0070] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0072] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion.

[0073] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0074] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0075] With the development of memory technology, the miniaturization of memory devices has become a key technical issue. The miniaturization of DRAM (dynamic random access memory) is approaching its physical limit. Traditional MOSFETs are no longer suitable for advanced DRAM due to short-channel effects.

[0076] The vertical gate-all-around transistor with superior gate control capability will replace the traditional MOSFET in the next generation of DRAM. First, the vertical gate-all-around device has strong gate control capability and weak short channel effect, which can improve the retention time; second, the vertical gate-all-around device has a small area. The DRAM cell unit area using the vertical gate-all-around transistor can be as small as 4F. 2 (“F” stands for size factor, which is the minimum feature size in the manufacturing process), compared to the current 6F 2 , 4F 2 The area can be reduced by about 30%.

[0077] However, existing storage cells based on vertical ring-gate devices have problems such as low gate electric field control capability, subthreshold characteristics, and low switching ratio; and there is a common problem in the preparation that the bit line is difficult to heavily dope, which reduces storage performance.

[0078] Based on this, it is necessary to provide a method for preparing a semiconductor structure to address the above-mentioned problems, including:

[0079] S101: providing a substrate.

[0080] S102: forming a stacked structure on the upper surface of the substrate, the stacked structure including a first sidewall dielectric layer, a second sidewall dielectric layer, a conductive layer, a third sidewall dielectric layer, and a fourth sidewall dielectric layer stacked in sequence from bottom to top; the first sidewall dielectric layer and the second sidewall dielectric layer have different dielectric constants; and the third sidewall dielectric layer and the fourth sidewall dielectric layer have different dielectric constants.

[0081] S103: forming a plurality of channel holes in the stacked structure.

[0082] S104: forming an active pillar in each trench hole, wherein a distance exists between the active pillar and a sidewall of the trench hole.

[0083] S105: forming word line isolation trenches in the stacked structure to obtain a plurality of spaced word lines; the word lines surround the active pillars and extend along a first direction; the word lines include a first outer sidewall, a first inner sidewall, a word line conductive layer, a second inner sidewall, and a second outer sidewall stacked sequentially from bottom to top.

[0084] S106: forming a gate dielectric layer between the word lines and the active pillars.

[0085] The semiconductor structure obtained after steps S101-S104 can be referred to Figure 19 Of course, in order to facilitate understanding of the present invention, Figure 19 Some examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention are given. There may be other suitable examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention, and the present invention does not limit them here.

[0086] The method for preparing the semiconductor structure in the above embodiment is to form a stacked structure on the upper surface of the substrate, then form a plurality of channel holes in the stacked structure, and form active pillars in each channel hole, with a spacing between the active pillars and the sidewalls of the channel holes so that a gate dielectric layer is subsequently formed between the word lines and the active pillars to isolate and protect the active pillars; form word line isolation grooves in the stacked structure to obtain a plurality of spaced word lines, each word line can connect active pillars in the same row or column in series; the stacked structure includes: The first spacer dielectric layer, the second spacer dielectric layer, the conductive layer, the third spacer dielectric layer and the fourth spacer dielectric layer are stacked in sequence. The dielectric constants of the first spacer dielectric layer and the second spacer dielectric layer are different, and the dielectric constants of the third spacer dielectric layer and the fourth spacer dielectric layer are different. This ensures that the dielectric constants of the first outer sidewall and the first inner sidewall of the word line are different, and that the dielectric constants of the second outer sidewall and the second inner sidewall are different. This enhances the electric field control of the word line on the source / drain, improves the subthreshold characteristics, and increases the switching ratio of the device.

[0087] See also Figure 2 , Figure 2 The aa' direction and the bb' direction of the semiconductor structure in this application are shown.

[0088] In step S101, refer to Figure 1 Step S101 in Figure 3 , providing a substrate 10.

[0089] The material of the substrate 10 may be any suitable material, for example, at least one of the following materials: silicon (Si), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), etc., which are not limited in this embodiment.

[0090] In one embodiment, Figure 4 As shown, before forming the stacked structure on the upper surface of the substrate 10, the following steps S401 to S405 may be further included:

[0091] S401 : performing a doping process on the substrate 10 .

[0092] The resulting structure can be found in Figure 5 Before the substrate 10 is doped, the method further includes the step of performing bit line doping on the substrate 10 .

[0093] The substrate 10 may be subjected to bit line implantation, annealing and other processes to achieve bit line doping, so as to form an ohmic contact of the bit line, so as to subsequently reduce the contact resistance between the bit line and the drain terminal.

[0094] The bit line doping dose can be 0.8×10 20 cm -3 ~1.2×10 20 cm -3 For example, the bit line doping dose may be 0.8×10 20 cm -3 , 0.9×10 20 cm -3 , 1×10 20 cm -3 , 1.1×10 20 cm -3 or 1.2×10 20 cm -3 .

[0095] In one example, see Figure 5 , performing doping treatment on the substrate 10 may include: injecting carbon impurities or nitrogen impurities into the substrate 10.

[0096] Among them, combined Figure 11 After carbon impurities or nitrogen impurities are implanted into the substrate 10, during the subsequent heat treatment process, the carbon impurities or nitrogen impurities can improve the density of the substrate 10, making the film layer of the subsequently obtained buried metal silicide bit line 104 dense and the grain size smaller. The film quality of the contact interface between the buried metal silicide bit line 104 and the substrate 10 is improved, and the thermal stability of the structure is enhanced.

[0097] In the process of doping the substrate 10, the implantation energy may be 10keV to 20keV, and the implantation dose of the doping element may be 5×10 14 cm -3 ~3×10 15 cm -3 .

[0098] For example, the implantation energy may be 10keV, 12keV, 15keV, 18keV or 20keV, or other implantation energies between 10keV and 20keV, which are not limited in this embodiment. The implantation dose of the doping element is 5×10 14 cm -3 , 8×10 14 cm -3 , 1×10 15 cm -3 , 2×10 15 cm -3or 3×10 15 cm -3 , or other locations within 5×10 14 cm -3 ~3×10 15 cm -3 The injection dose between and is not limited in this embodiment.

[0099] The selection of the implantation energy and implantation dose should ensure that the energy is sufficient to well incorporate the impurities into the substrate 10 , while not excessively damaging the substrate 10 .

[0100] S402: etching the substrate 10 to form a plurality of bit line steps arranged at intervals.

[0101] The resulting structure is Figure 6 Etching the substrate 10 to form a plurality of spaced-apart bit line steps 101 may include the following steps: forming a mask layer on the upper surface of the substrate 10, the mask layer having a mask window, the mask window exposing a to-be-etched area; and etching the to-be-etched area to form a plurality of spaced-apart bit line steps 101 on the substrate 10. The mask layer may be formed on the upper surface of the substrate 10 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The mask layer may include a silicon nitride layer or a photoresist layer.

[0102] The substrate 10 may be etched using a wet etching process or a dry etching process to form a plurality of bit line steps 101 arranged at intervals.

[0103] The method for fabricating a semiconductor structure provided herein does not specifically limit the manner in which the bit line steps 101 are formed in step S402. For example, a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process can be used to form a plurality of spaced-apart bit line steps 101.

[0104] S403: forming a protective spacer 102, the protective spacer 102 covers the top of the bit line step 101, and extends to the sidewall of the bit line step 101, covering part of the sidewall of the bit line step 101. Figure 8 .

[0105] In one embodiment, before forming the protective sidewall 102, the following steps may be further included: forming a first isolation dielectric layer 211 between adjacent bit line steps 101 and outside the bit line steps 101. The resulting structure is shown in FIG. Figure 7 ; The protective sidewall 102 is located on the first isolation dielectric layer 211.

[0106] The first isolation dielectric layer 211 may be formed between adjacent bit line steps 101 and outside the bit line steps 101 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The first isolation dielectric layer 211 may include, but is not limited to, at least one of a silicon nitride layer and a silicon oxynitride layer. That is, the first isolation dielectric layer 211 may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer.

[0107] In step S403, refer to Figure 3 Step S403 in Figure 8 , forming a protection spacer 102 , the protection spacer 102 covers the top of the bit line step 101 and extends to the sidewall of the bit line step 101 , covering part of the sidewall of the bit line step 101 .

[0108] The substrate 10 may be thermally oxidized using an in-situ steam generation (ISSG) process to consume a portion of the substrate 10, thereby forming a protective spacer 102. During a subsequent annealing process, this helps control the position of the buried metal silicide bit line 104, ensuring that the formed buried metal silicide bit line 104 is located within the substrate 10. Furthermore, the protective spacer 102 may protect the upper surface and sidewalls of the substrate 10 during the annealing process. The material of the protective spacer 102 may include an oxide, which may include silicon dioxide.

[0109] In one embodiment, after forming the protective sidewall 102 and before forming the metal layer, the following steps may be further included: etching back the first isolation dielectric layer 211 to form a first isolation layer 21, with a gap between the first isolation layer 21 and the protective sidewall 102 to expose a portion of the sidewall of the bit line step 101; the resulting structure is shown in FIG. Figure 9 .

[0110] The first isolation dielectric layer 211 may be etched back using a wet etching process or a dry etching process to form a first isolation layer 21. The first isolation layer 21 may include, but is not limited to, at least one of a silicon nitride layer and a silicon oxynitride layer, that is, the first isolation layer 21 may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer.

[0111] S404 : forming a metal layer 103 , wherein the metal layer 103 at least covers the exposed sidewalls of the bit line step 101 .

[0112] The resulting structure is Figure 10. Among them, the metal layer 103 can be formed by a physical vapor deposition process or an atomic layer deposition process. The metal layer 103 at least covers the exposed sidewalls of the bit line step 101, which can mean that the metal layer 103 covers the exposed sidewalls of the bit line step 101, the surface of the protective sidewall 102 and the surface of the first isolation layer 21 away from the substrate 10; or the metal layer 103 covers the exposed sidewalls of the bit line step 101 and the surface of the protective sidewall 102; or the metal layer 103 covers the exposed sidewalls of the bit line step 101 and the surface of the first isolation layer 21 away from the substrate 10; or the metal layer 103 covers the exposed sidewalls of the bit line step 101.

[0113] S405 : performing an annealing process on the obtained structure to form a buried metal silicide bit line 104 . The buried metal silicide bit line 104 extends along a second direction intersecting the first direction.

[0114] The resulting structure is Figure 11 Furthermore, the first direction and the second direction may be perpendicular to each other.

[0115] by Figures 5 to 11 For example, for ease of understanding, the second direction may be an example of the aa' direction, and the first direction may be an example of the bb' direction.

[0116] For example, the metal layer 103 may include, but is not limited to, a cobalt layer; and the buried metal silicide bit line 104 may include, but is not limited to, a buried cobalt silicide bit line. The buried metal silicide bit line 104 can reduce the bit line's own resistance, thereby improving storage performance and thermal stability.

[0117] The annealing temperature for the resulting structure may be 650° C. to 950° C., and the annealing time may be 20 seconds to 35 seconds. The annealing temperature and time are selected to promote diffusion of metal elements in the metal layer into the substrate 10 to form the buried metal silicide bit line 104 while also ensuring that the substrate 10 is not excessively damaged.

[0118] For example, the annealing temperature of the obtained structure can be 650°C, 700°C, 750°C, 800°C, 850°C, or 950°C, or other annealing temperatures between 650°C and 950°C, which is not limited in this embodiment. The annealing time of the obtained structure can be 20 seconds, 25 seconds, 30 seconds, or 35 seconds, or other annealing time between 20 seconds and 35 seconds, which is not limited in this embodiment.

[0119] In one embodiment, see Figure 10 As shown in FIG. 2 b, the ratio of the thickness m of the metal layer 103 to the width n of the bit line step 101 is greater than or equal to 0.6.

[0120] Among them, the ratio of the thickness m of the metal layer 103 to the width n of the bit line step 101 can be greater than 0.6 or equal to 0.6, so that the exposed bit line step 101 can be completely metallized and transformed into a buried metal silicide bit line 104; while the unexposed bit line step 101 is almost unaffected; therefore, the position of the buried metal silicide bit line 104 can be precisely controlled.

[0121] Illustratively, the upper surface of the buried metal silicide bit line 104 is lower than the upper surface of the bit line step 101 , that is, the upper surface of the buried metal silicide bit line 104 is lower than the upper surface of the substrate 10 , so the substrate 10 can better isolate and protect the buried metal silicide bit line 104 .

[0122] In one embodiment, after forming the buried metal silicide bit line 104 and before forming the stacked structure on the upper surface of the substrate 10, the following steps may be further included: removing the protective sidewalls 102; forming a second isolation layer 22 between adjacent bit line steps 101 and outside the bit line steps 101; and the resulting structure is shown in FIG. Figure 12 , the upper surface of the second isolation layer 22 is flush with the upper surface of the bit line step 101; the stacked structure covers the upper surface of the second isolation layer 22 and the upper surface of the bit line step 101; the channel hole and the word line isolation groove both penetrate the stacked structure and extend to the upper surface of the bit line step 101.

[0123] The protective spacer 102 can be removed by a wet etching process or a dry etching process. A second isolation layer 22 can be formed between adjacent bit line steps 101 and outside the bit line steps 101 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The second isolation layer 22 can include an oxide layer, which can include a silicon oxide layer. Figure 12 The first isolation layer 21 and the second isolation layer 22 together form an isolation stack 20 to protect the bit line step 101 and the buried metal silicide bit line 104.

[0124] In the above embodiment, by performing a doping treatment on the substrate 10, the grain size of the metal silicide during the annealing treatment to form the buried metal silicide bit line 104 can be reduced, and the film quality of the contact interface between the metal silicide and the substrate can be improved. Therefore, the thermal stability of the buried metal silicide bit line 104 can be improved, and the junction leakage problem between the bit line and the drain end of the device can be avoided. It can also avoid the performance degradation of the metal silicide structure in the subsequent high-temperature gate oxide process and capacitor preparation process.

[0125] In step S102, refer to Figure 1 Step S102 in Figure 13A stacked structure 30 is formed on the upper surface of the substrate 10. The stacked structure 30 includes a first spacer dielectric layer 31, a second spacer dielectric layer 32, a conductive layer 33, a third spacer dielectric layer 34, and a fourth spacer dielectric layer 35 stacked in sequence from bottom to top. The first spacer dielectric layer 31 and the second spacer dielectric layer 32 have different dielectric constants. The third spacer dielectric layer 34 and the fourth spacer dielectric layer 35 have different dielectric constants.

[0126] The stacked structure 30 covers the upper surface of the second isolation layer 22 and the upper surface of the bitline step 101. A first dielectric spacer 31 is located on the upper surface of the second isolation layer 22 and the upper surface of the bitline step 101; a second dielectric spacer 32 is located on the upper surface of the first dielectric spacer 31; a conductive layer 33 is located on the upper surface of the second dielectric spacer 32; a third dielectric spacer 34 is located on the upper surface of the conductive layer 33; and a fourth dielectric spacer 35 is located on the upper surface of the third dielectric spacer 34.

[0127] In one embodiment, the first spacer dielectric layer 31 includes a low-k dielectric layer (k is the dielectric constant of the material), the second spacer dielectric layer 32 includes a high-k dielectric layer, the third spacer dielectric layer 34 includes a high-k dielectric layer, and the fourth spacer dielectric layer 35 includes a low-k dielectric layer. The conductive layer 33 may include at least one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer. That is, the conductive layer 33 may be any one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer, and may be a stacked structure 30 composed of a titanium layer and a titanium nitride layer, or a stacked structure 30 composed of two or more of a cobalt layer, a molybdenum layer, or a tungsten layer.

[0128] For example, k of the first spacer dielectric layer 31 and the fourth spacer dielectric layer 35 is less than or equal to 3.9, and k of the second spacer dielectric layer 32 and the third spacer dielectric layer 34 is greater than or equal to 3.9.

[0129] Furthermore, the k value of the first spacer dielectric layer 31 and the fourth spacer dielectric layer 35 can be the same, and the k value of the second spacer dielectric layer 32 and the third spacer dielectric layer 34 can be the same, so that the film layers of the stacked structure 30 are symmetrical and uniform, so as to obtain a stacked structure 30 with more stable performance.

[0130] In step S103, refer to Figure 1 Step S103 in Figure 14 , a plurality of channel holes 301 are formed in the stacked structure 30 .

[0131] The channel holes 301 penetrate the stacked structure 30 and extend to the upper surface of the bitline step 101; the channel holes 301 expose a portion of the upper surface of the bitline step 101. The method for forming the plurality of channel holes 301 in step S103 is not specifically limited. As an example, a self-aligned double patterning process or a self-aligned quadruple patterning process can be used to form the plurality of channel holes 301 in the stacked structure 30.

[0132] In step S104, refer to Figure 1 Step S104 in Figures 15 and 16 An active pillar 40 is formed in each channel hole 301 , and a distance exists between the active pillar 40 and the sidewall of the channel hole 301 .

[0133] Among them, see Figure 15 Before forming the active pillars 40 in each channel hole 301, the method further includes forming a sacrificial layer 41 on the sidewalls of each channel hole 301. Exemplarily, the sacrificial layer 41 can be formed on the sidewalls of each channel hole 301 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The sacrificial layer 41 can include, but is not limited to, at least one of a silicon nitride layer and a silicon oxynitride layer. That is, the sacrificial layer 41 can include a silicon nitride layer or a silicon oxynitride layer, or can include a stacked structure 30 consisting of a silicon nitride layer and a silicon oxynitride layer.

[0134] See Figure 16 In step S104, an N-type doped silicon column can be formed as an active column 40 by using an epitaxial channel growth process; the doping concentration in the active column 40 is 5×10 18 cm -3 ~1×10 19 cm -3 For example, the doping concentration in the active pillar 40 may be 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 or 1×10 19 cm -3 , or other locations within 5×10 18 cm -3 ~1×10 19 cm -3 The doping concentration between and is not limited in this embodiment.

[0135] Wherein, an epitaxial channel growth process is adopted to form an N-type doped silicon pillar as the active pillar 40 , and the thermal stability of the active pillar 40 is further improved.

[0136] In step S105, refer to Figure 1 Step S105 in Figure 17 A word line isolation trench 501 is formed in the stacked structure 30 to obtain a plurality of spaced word lines 50; the word line 50 surrounds the active pillar 40 and extends along the first direction; the word line 50 includes a first outer sidewall 51, a first inner sidewall 52, a word line conductive layer 53, a second inner sidewall 54, and a second outer sidewall 55 stacked in sequence from bottom to top.

[0137] The wordline isolation trench 501 may be formed in the stacked structure 30 by a self-aligned double patterning process or a self-aligned quadruple patterning process. The wordline isolation trench 501 penetrates the stacked structure 30 and extends to the upper surface of the bitline step 101 .

[0138] Illustratively, the first outer sidewall 51 comprises a low-k dielectric layer, the first inner sidewall 52 comprises a high-k dielectric layer, the second inner sidewall 54 comprises a high-k dielectric layer, and the second outer sidewall 55 comprises a low-k dielectric layer. The word line conductive layer 53 may comprise at least one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer. That is, the word line conductive layer 53 may be any one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer, or a tungsten layer. It may be a stacked structure 30 formed by combining a titanium layer and a titanium nitride layer, or a stacked structure 30 formed by combining two or more of a cobalt layer, a molybdenum layer, or a tungsten layer.

[0139] Among them, the high-k dielectric layer can include: at least one of: Al2O3 (aluminum oxide) layer, HfO2 (hafnium dioxide) layer and ZrO2 (zirconium dioxide) layer, that is, the first inner wall 52 and the second inner wall 54 can be any one of Al2O3 layer, HfO2 layer and ZrO2 layer, or a stacked structure 30 composed of two or more of Al2O3 layer, HfO2 layer and ZrO2 layer.

[0140] For example, k of the first outer wall 51 and the second outer wall 55 is less than or equal to 3.9, and k of the first inner wall 52 and the second inner wall 54 is greater than or equal to 3.9.

[0141] Furthermore, the k value of the first outer sidewall 51 and the second outer sidewall 55 can be the same, and the k value of the first inner sidewall 52 and the second inner sidewall 54 can be the same, so that the film layer of the bit line is symmetrical and uniform, thereby obtaining a bit line with more stable performance.

[0142] In step S106, refer to Figure 1 Step S106 in Figures 18 to 19, a gate dielectric layer 56 is formed between the word line 50 and the active pillar 40 .

[0143] In one embodiment, forming the gate dielectric layer 56 between the word line 50 and the active pillar 40 may include the following steps: removing the sacrificial layer 41 to form a sacrificial gap 502 between the active pillar 40 and the sidewall of the channel hole 301, and the resulting structure is as follows: Figure 18 As shown; a gate dielectric layer 56 is formed in the sacrificial gap 502, and the resulting structure is as shown Figure 19 shown.

[0144] The gate dielectric layer 56 is also formed on the upper surfaces of the bit lines and the active pillars 40 to isolate and protect the upper surfaces of the bit lines and the active pillars 40 .

[0145] For example, a wet etching process or a dry etching process can be used to remove the sacrificial layer 41. A physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process can be used to form a gate dielectric layer 56 in the sacrificial gap 502. The gate dielectric layer 56 can include an oxide layer, and the oxide layer can include a silicon oxide layer.

[0146] In one embodiment, after forming the gate dielectric layer 56 between the word line 50 and the active pillar 40 , the method for fabricating the semiconductor structure may further include the following steps S107 to S109 :

[0147] S107 : forming a word line isolation layer 57 . The word line isolation layer 57 fills the word line isolation trench 501 and covers the active pillar 40 and the word line 50 .

[0148] The resulting structure is Figure 20 The word line isolation layer 57 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The word line isolation layer 57 may include an oxide layer, which may be a silicon oxide layer.

[0149] S108 : forming a plurality of through-via capacitor contact structures 60 . The through-via capacitor contact structures 60 are disposed in a one-to-one correspondence with the active pillars 40 , and the lower surfaces of the through-via capacitor contact structures 60 are in contact with the active pillars 40 .

[0150] Among them, see Figure 21 , a plurality of through-hole capacitor contact structures 60 can be formed by a Damascene process.

[0151] For example, see Figure 21 The through-hole capacitor contact structure 60 may include a contact dielectric layer 61 and a contact conductive layer 62 .

[0152] The contact dielectric layer 61 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the contact dielectric layer 61 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0153] Among them, the contact conductive layer 62 can include at least one of a cobalt layer, a molybdenum layer or a tungsten layer, that is, the contact conductive layer 62 can be any one of a cobalt layer, a molybdenum layer or a tungsten layer, or it can be a stacked structure 30 composed of two or more of the cobalt layer, molybdenum layer or tungsten layer.

[0154] S109 : forming a plurality of capacitors 70 , wherein the capacitors 70 are arranged in a one-to-one correspondence with the through-hole capacitor contact structures 60 , and the lower electrodes 73 of the capacitors 70 are in contact with the upper surface of the through-hole capacitor contact structures 60 .

[0155] Among them, still refer to Figure 21 The capacitor 70 is connected to the metal silicide layer on the upper surface of the active pillar 40 through the through-hole capacitor contact structure 60.

[0156] For example, see Figure 21 The capacitor 70 may include: an upper electrode 71 , a capacitor dielectric layer 72 and a lower electrode 73 .

[0157] The upper electrode 71 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the upper electrode 71 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0158] Among them, the capacitor dielectric layer 72 includes a high-k dielectric material layer, and the high-k dielectric layer may include: at least one of: Al2O3 (aluminum oxide) layer, HfO2 (hafnium dioxide) layer and ZrO2 (zirconium dioxide) layer, that is, the capacitor dielectric layer 7272 can be any one of the Al2O3 layer, HfO2 layer and ZrO2 layer, or it can be a stacked structure 30 composed of two or more of the Al2O3 layer, HfO2 layer and ZrO2 layer.

[0159] The lower electrode 73 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the lower electrode 73 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0160] It should be understood that, although the various steps in the flow charts of the various embodiments are shown in sequence according to the instructions of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flow charts of the various embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or steps or stages in other steps.

[0161] Based on the same inventive concept, the present application also provides a semiconductor structure.

[0162] like Figure 19 As shown, the semiconductor structure may include: a substrate 10, a plurality of active pillars 40 arranged at intervals, a plurality of word lines 50 arranged at intervals and a gate dielectric layer 56; the plurality of active pillars 40 are located on the substrate 10; the plurality of word lines 50 are located on the substrate 10, the word lines 50 surround the active pillars 40 and extend along a first direction; the word lines 50 include a first outer wall 51, a first inner wall 52, a word line conductive layer 53, a second inner wall 54 and a second outer wall 55 stacked in sequence from bottom to top; the dielectric constant of the first outer wall 51 is different from the dielectric constant of the first inner wall 52, and the dielectric constant of the second outer wall 55 is different from the dielectric constant of the second inner wall 54; the gate dielectric layer 56 is located between the word lines 50 and the active pillars 40.

[0163] The substrate 10 may be made of any suitable material, for example, at least one of the following materials: silicon (Si), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), etc., which are not limited in this embodiment. The active pillars 40 may include N-type doped silicon pillars.

[0164] Exemplarily, the word line conductive layer 53 may include at least one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer or a tungsten layer, that is, the word line conductive layer 53 may be any one of a titanium layer, a titanium nitride layer, a polysilicon layer, a cobalt layer, a molybdenum layer or a tungsten layer, may be a stacked structure 30 formed by a combination of a titanium layer and a titanium nitride layer, or may be a stacked structure 30 formed by a combination of two or more of a cobalt layer, a molybdenum layer or a tungsten layer.

[0165] Exemplarily, the gate dielectric layer 56 may include an oxide layer, and the oxide layer may include a silicon oxide layer.

[0166] The semiconductor structure in the above embodiment is formed by forming a stacked structure 30 on the upper surface of the substrate 10, and then forming a plurality of channel holes 301 in the stacked structure 30, and forming an active pillar 40 in each channel hole 301, with a gap between the active pillar 40 and the sidewall of the channel hole 301, so that a gate dielectric layer 56 is subsequently formed between the word line 50 and the active pillar 40 to isolate and protect the active pillar 40; forming a word line isolation groove 501 in the stacked structure 30 to obtain a plurality of spaced word lines 50, each word line 50 can connect the active pillars 40 in the same row or column in series; the stacked structure 30 includes a plurality of word lines 50 arranged at intervals, and a plurality of word lines 50 can be connected in series to form a plurality of word lines 50 arranged at intervals, and a plurality of word lines 50 can be connected in series to form a plurality of word lines 50 in the same row or column; the stacked structure 30 includes ... The first spacer dielectric layer 31, the second spacer dielectric layer 32, the conductive layer 33, the third spacer dielectric layer 34, and the fourth spacer dielectric layer 35 are sequentially stacked thereon. The first spacer dielectric layer 31 and the second spacer dielectric layer 32 have different dielectric constants, and the third spacer dielectric layer 34 and the fourth spacer dielectric layer 35 have different dielectric constants. This results in different dielectric constants between the first outer sidewall 51 and the first inner sidewall 52 of the word line 50, and different dielectric constants between the second outer sidewall 55 and the second inner sidewall 54. This enhances the electric field control of the word line 50 on the source / drain, improves the subthreshold characteristics, and increases the switching ratio of the device.

[0167] In one embodiment, the first outer sidewall 51 includes a low-k dielectric layer (k is the dielectric constant of the material), the first inner sidewall 52 includes a high-k dielectric layer, the second inner sidewall 54 includes a high-k dielectric layer, and the second outer sidewall 55 includes a low-k dielectric layer.

[0168] Among them, the high-k dielectric layer can include: at least one of: Al2O3 (aluminum oxide) layer, HfO2 (hafnium dioxide) layer and ZrO2 (zirconium dioxide) layer, that is, the first inner wall 52 and the second inner wall 54 can be any one of Al2O3 layer, HfO2 layer and ZrO2 layer, or a stacked structure 30 composed of two or more of Al2O3 layer, HfO2 layer and ZrO2 layer.

[0169] For example, k of the first outer wall 51 and the second outer wall 55 is less than or equal to 3.9, and k of the first inner wall 52 and the second inner wall 54 is greater than or equal to 3.9.

[0170] Furthermore, the k value of the first outer sidewall 51 and the second outer sidewall 55 can be the same, and the k value of the first inner sidewall 52 and the second inner sidewall 54 can be the same, so that the film layer of the bit line is symmetrical and uniform, thereby obtaining a bit line with more stable performance.

[0171] In one embodiment, still referring to Figure 19The substrate 10 includes a plurality of spaced-apart bit line steps 101; the semiconductor structure further includes: a buried metal silicide bit line 104, a first isolation layer 21, and a second isolation layer 22; the buried metal silicide bit line 104 is located within the bit line step 101, and is spaced apart from both the upper and lower surfaces of the bit line step 101; the first isolation layer 21 covers the surface of the substrate 10 between the bit line steps 101 and outside the bit line steps 101; the second isolation layer 22 is located on the upper surface of the first isolation layer 21, and the upper surface of the second isolation layer 22 is flush with the upper surface of the bit line step 101; wherein the lower surface of the active pillar 40 is in contact with the upper surface of the bit line step 101.

[0172] The first isolation layer 21 and the second isolation layer 22 together form an isolation stack 20 to protect the bit line step 101 and the buried metal silicide bit line 104 .

[0173] Exemplarily, the first isolation layer 21 may include, but is not limited to, at least one of a silicon nitride layer and a silicon oxynitride layer. That is, the first isolation layer 21 may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer. The second isolation layer 22 may include an oxide layer, which may include a silicon oxide layer.

[0174] In one embodiment, Figure 21 As shown, the semiconductor structure also includes: a word line isolation layer 57, a plurality of through-hole capacitor contact structures 60 and a plurality of capacitors 70; the word line isolation layer 57 fills the word line isolation groove 501 between adjacent word lines 50, and covers the active pillars 40 and the word lines 50; the through-hole capacitor contact structure 60 is arranged in a one-to-one correspondence with the active pillars 40, and the lower surface of the through-hole capacitor contact structure 60 is in contact with the active pillars 40; the capacitor 70 is arranged in a one-to-one correspondence with the through-hole capacitor contact structure 60, and the lower electrode 73 of the capacitor 70 is in contact with the upper surface of the through-hole capacitor contact structure 60.

[0175] For example, see Figure 21 The through-hole capacitor contact structure 60 may include a contact dielectric layer 61 and a contact conductive layer 62 .

[0176] The contact dielectric layer 61 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the contact dielectric layer 61 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0177] Among them, the contact conductive layer 62 can include at least one of a cobalt layer, a molybdenum layer or a tungsten layer, that is, the contact conductive layer 62 can be any one of a cobalt layer, a molybdenum layer or a tungsten layer, or it can be a stacked structure 30 composed of two or more of the cobalt layer, molybdenum layer or tungsten layer.

[0178] For example, see Figure 21 The capacitor 70 may include: an upper electrode 71 , a capacitor dielectric layer 72 and a lower electrode 73 .

[0179] The upper electrode 71 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the upper electrode 71 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0180] Among them, the capacitor dielectric layer 72 includes a high-k dielectric material layer, and the high-k dielectric layer may include: at least one of: Al2O3 (aluminum oxide) layer, HfO2 (hafnium dioxide) layer and ZrO2 (zirconium dioxide) layer, that is, the capacitor dielectric layer 7272 can be any one of the Al2O3 layer, HfO2 layer and ZrO2 layer, or it can be a stacked structure 30 composed of two or more of the Al2O3 layer, HfO2 layer and ZrO2 layer.

[0181] The lower electrode 73 may include at least one of a TiN (titanium nitride) layer and a TaN (tantalum nitride) layer, that is, the lower electrode 73 may include either a TiN layer or a TaN layer, or may be a stacked structure 30 composed of a TiN layer and a TaN layer.

[0182] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0183] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the upper surface of the substrate, the stacked structure comprising a first spacer dielectric layer, a second spacer dielectric layer, a conductive layer, a third spacer dielectric layer, and a fourth spacer dielectric layer stacked sequentially from bottom to top; the first spacer dielectric layer and the second spacer dielectric layer have different dielectric constants; and the third spacer dielectric layer and the fourth spacer dielectric layer have different dielectric constants; forming a plurality of channel holes in the stacked structure; forming an active pillar in each of the channel holes, wherein the active pillar is spaced apart from a sidewall of the channel hole; A word line isolation trench is formed in the stacked structure to obtain a plurality of spaced word lines; the word lines surround the active pillars and extend along a first direction; the word lines include a first outer sidewall, a first inner sidewall, a word line conductive layer, a second inner sidewall, and a second outer sidewall stacked sequentially from bottom to top; A gate dielectric layer is formed between the word line and the active pillar.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The first spacer dielectric layer includes a low-k dielectric layer, the second spacer dielectric layer includes a high-k dielectric layer, the third spacer dielectric layer includes a high-k dielectric layer, and the fourth spacer dielectric layer includes a low-k dielectric layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the active pillar in each of the channel holes, the method further includes: forming a sacrificial layer on the sidewall of each of the channel holes; Forming a gate dielectric layer between the word line and the active pillar includes: removing the sacrificial layer to form a sacrificial gap between the active pillar and the sidewall of the channel hole; A gate dielectric layer is formed in the sacrificial gap.

4. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the stacked structure on the upper surface of the substrate, the method further includes: performing a doping process on the substrate; Etching the substrate to form a plurality of spaced-apart bit line steps; forming a protection sidewall, wherein the protection sidewall covers the top of the bit line step and extends to the sidewall of the bit line step to cover a portion of the sidewall of the bit line step; forming a metal layer, wherein the metal layer at least covers the exposed sidewalls of the bit line step; The resulting structure is annealed to form a buried metal silicide bit line extending along a second direction intersecting the first direction.

5. The method for preparing a semiconductor structure according to claim 4, wherein: Before forming the protective sidewalls, the method further includes: forming an isolation dielectric layer between adjacent bit line steps and outside the bit line steps; the protective sidewalls are located on the isolation dielectric layer; After forming the protective sidewalls and before forming the metal layer, the method further includes: etching back the isolation dielectric layer to form a first isolation layer, wherein the first isolation layer is spaced apart from the protective sidewalls to expose a portion of the sidewalls of the bit line step; After forming the buried metal silicide bit line and before forming the stacked structure on the upper surface of the substrate, the method further includes: removing the protective sidewalls; forming a second isolation layer between adjacent bit line steps and outside the bit line steps, wherein the upper surface of the second isolation layer is flush with the upper surface of the bit line step; The stacked structure covers the upper surface of the second isolation layer and the upper surface of the bit line step; the channel hole and the word line isolation groove both penetrate the stacked structure and extend to the upper surface of the bit line step.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: After forming a gate dielectric layer between the word line and the active pillar, the method further includes: forming a word line isolation layer, wherein the word line isolation layer fills the word line isolation groove and covers the active pillar and the word line; forming a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in a one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the active pillars; A plurality of capacitors are formed, wherein the capacitors are arranged in a one-to-one correspondence with the through-hole capacitor contact structures, and the lower electrodes of the capacitors are in contact with the upper surfaces of the through-hole capacitor contact structures.

7. A semiconductor structure, characterized in that include: substrate; a plurality of active pillars arranged at intervals and located on the substrate; A plurality of spaced-apart word lines are located on the substrate, the word lines encircling the active pillars and extending along a first direction; the word lines include a first outer sidewall, a first inner sidewall, a word line conductive layer, a second inner sidewall, and a second outer sidewall stacked sequentially from bottom to top; the dielectric constant of the first outer sidewall is different from the dielectric constant of the first inner sidewall, and the dielectric constant of the second outer sidewall is different from the dielectric constant of the second inner sidewall; The gate dielectric layer is located between the word line and the active pillar.

8. The semiconductor structure according to claim 7, wherein: The first outer sidewall includes a low-k dielectric layer, the first inner sidewall includes a high-k dielectric layer, the second inner sidewall includes a high-k dielectric layer, and the second outer sidewall includes a low-k dielectric layer.

9. The semiconductor structure according to claim 7, wherein: The substrate includes a plurality of bit line steps arranged at intervals; the semiconductor structure further includes: a buried metal silicide bit line, located in the bit line step and spaced apart from both the upper and lower surfaces of the bit line step; a first isolation layer covering the surface of the substrate between the bit line steps and outside the bit line steps; a second isolation layer, located on an upper surface of the first isolation layer, wherein an upper surface of the second isolation layer is flush with an upper surface of the bit line step; Wherein, the lower surface of the active pillar contacts the upper surface of the bit line step.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that The semiconductor structure further comprises: a word line isolation layer, the word line isolation layer filling the word line isolation grooves between adjacent word lines and covering the active pillars and the word lines; a plurality of through-hole capacitor contact structures, wherein the through-hole capacitor contact structures are arranged in a one-to-one correspondence with the active pillars, and the lower surfaces of the through-hole capacitor contact structures are in contact with the active pillars; A plurality of capacitors are provided in a one-to-one correspondence with the through-hole capacitor contact structures, and lower electrodes of the capacitors are in contact with upper surfaces of the through-hole capacitor contact structures.

Images