Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises an array substrate, and the array substrate comprises a substrate; the array substrate comprises a first type of transistor and a second type of transistor, the first type of transistor comprises a first active layer, the second type of transistor comprises a second active layer, and the second active layer is located on the side, away from the substrate, of the first active layer; wherein the first active layer and the second active layer are both oxide semiconductor active layers. By adopting the technical method provided by the embodiment of the invention, the positions of the first active layer and the second active layer are adjusted, so that the position relationship between the first type of transistors and the second type of transistors in the array substrate is adjusted, and the total occupied space of the transistors in the array substrate can be reduced; the display panel with higher pixel density can be realized by saving space, so that the overall display effect of the display panel is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. In particular, the application of VR / AR scenes requires more detailed display images and narrower display frames to improve visual experience. However, due to problems such as device size, high-resolution display panels are difficult to achieve in the existing technology, affecting the overall effect of the display panel. Summary of the invention

[0003] An embodiment of the present invention provides a display panel and a display device. By adjusting the positions of a first active layer and a second active layer, and then adjusting the positional relationship between a first type of transistor and a second type of transistor in an array substrate, the overall occupied space of transistors in the array substrate can be reduced, the resolution of the display panel can be effectively improved, and the overall display effect of the display panel can be enhanced.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, wherein the display panel includes an array substrate, wherein the array substrate includes:

[0005] substrate;

[0006] The array substrate includes a first type of transistor and a second type of transistor, the first type of transistor includes a first active layer, the second type of transistor includes a second active layer, and the second active layer is located on a side of the first active layer away from the substrate;

[0007] Wherein, the first active layer and the second active layer are both oxide semiconductor active layers.

[0008] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in any one of the first aspect.

[0009] An embodiment of the present invention provides a display panel, which includes an array substrate, wherein the display substrate includes a substrate and a first type of transistor and a second type of transistor located on one side of the substrate; wherein the first type of transistor includes a first active layer, and the second type of transistor includes a second active layer, and the second active layer is located on a side of the first active layer away from the substrate, that is, the first active layer and the second active layer are arranged in different layers; further, the first active layer and the second active layer are both oxide semiconductor active layers, that is, the first type of transistor and the second type of transistor are oxide transistors; the display panel provided by the embodiment of the present invention can reduce the overall occupied space of the transistors in the array substrate by adjusting the positions of the active layers in the first type of transistor and the second type of transistor, and is conducive to realizing a display panel with a higher pixel density by saving space, thereby improving the overall display effect of the display panel.

[0010] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required to describe the embodiments. Obviously, the drawings introduced are only drawings of a part of the embodiments to be described in the present invention, rather than all the drawings. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic diagram of a partial structure of a first array substrate provided by an embodiment of the present invention;

[0014] Figure 3 yes Figure 2 A schematic cross-sectional view along the section line A-A';

[0015] Figure 4 yes Figure 2 A schematic cross-sectional view along the section line BB';

[0016] Figure 5 is a partial structural schematic diagram of a second array substrate provided by an embodiment of the present invention;

[0017] Figure 6 yes Figure 5 A schematic cross-sectional view along the section line C-C';

[0018] Figure 7is a partial structural schematic diagram of a third array substrate provided by an embodiment of the present invention;

[0019] Figure 8 yes Figure 7 A schematic cross-sectional view along the section line D-D';

[0020] Fig. 9 is a schematic structural diagram of a first type transistor and a second type transistor provided by an embodiment of the present invention;

[0021] Fig.10 is a schematic structural diagram of a second first-type transistor and a second-type transistor provided in an embodiment of the present invention;

[0022] Fig.11 is a schematic structural diagram of a third first-type transistor and a second-type transistor provided by an embodiment of the present invention;

[0023] Fig.12 yes Figure 7 A schematic cross-sectional view along the section line E-E';

[0024] Fig.13 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0025] Fig.14 The embodiment of the present invention provides a Fig.13 The timing of the signal of the pixel driving circuit shown in the embodiment;

[0026] Fig.15 is a schematic diagram of a film layer of a pixel driving circuit provided by an embodiment of the present invention;

[0027] Fig.16 yes Fig.15 Schematic diagram of the membrane layer in the first part;

[0028] Fig.17 yes Fig.15 Schematic diagram of the membrane layer in the second part;

[0029] Fig.18 yes Fig.15 Schematic diagram of the membrane layer in the third part;

[0030] Fig.19 yes Fig.15 Schematic diagram of the membrane layer in the fourth part;

[0031] Fig. 20 yes Fig.15 Schematic diagram of stacking of the first to fourth parts;

[0032] Fig.21 yes Fig.15Schematic diagram of the membrane layer in the fifth part;

[0033] Fig. 22 yes Fig.15 Schematic diagram of the membrane layer in the sixth part;

[0034] Fig.23 yes Fig.15 Schematic diagram of the membrane layer in the seventh part;

[0035] Fig.24 yes Fig.15 Schematic diagram of the membrane layer in the eighth part;

[0036] Fig.25 yes Fig.15 A schematic diagram of the stacking of the first to eighth parts;

[0037] Fig.26 yes Fig.15 Schematic diagram of the membrane layer in the ninth part;

[0038] Fig. 27 yes Fig.15 Schematic diagram of the membrane layer in the tenth part;

[0039] Fig.28 yes Fig.15 A schematic cross-sectional view along the section line F-F';

[0040] Fig.29 is a partial structural diagram of a shift register provided by an embodiment of the present invention;

[0041] Fig.30 yes Fig.29 A schematic cross-sectional view along the section line G-G';

[0042] Fig.31 yes Fig.29 A schematic cross-sectional view along the section line H-H';

[0043] Fig.32 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a system, product or device comprising a series of units is not necessarily limited to those steps or units clearly listed, but may include other units that are not clearly listed or inherent to these products or devices.

[0046] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a partial structural diagram of a first array substrate provided by an embodiment of the present invention, Figure 3 yes Figure 2 A schematic cross-sectional view along the section line A-A', Figure 4 yes Figure 2 A schematic cross-sectional view along the section line B-B', Figure 5 is a partial structural diagram of a second array substrate provided by an embodiment of the present invention, Figure 6 yes Figure 5 A schematic cross-sectional view along the section line C-C', Figure 7 is a partial structural diagram of a third array substrate provided by an embodiment of the present invention, Figure 8 yes Figure 7 A schematic cross-sectional view along the section line D-D', Fig. 9 is a schematic structural diagram of a first type transistor and a second type transistor provided by an embodiment of the present invention, Fig.10 is a schematic diagram of the structure of a second first type transistor and a second type transistor provided by an embodiment of the present invention, with reference to Figures 1 to 10 As shown, an embodiment of the present invention provides a display panel 10, which includes an array substrate 100, and the array substrate 100 includes: a substrate 200, a first type of transistor 310 and a second type of transistor 320. The first type of transistor 310 includes a first active layer 311, and the second type of transistor 320 includes a second active layer 321, and the second active layer 321 is located on a side of the first active layer 311 away from the substrate 200; wherein the first active layer 311 and the second active layer 321 are both oxide semiconductor active layers.

[0047] The display panel 10 includes an array substrate 100, and the array substrate 100 is provided with a pixel driving circuit 100A at the display area AA and a shift register 100B at the non-display area NA. The shift register 100B is electrically connected to the pixel driving circuit 100A and is used to provide a scanning signal. The pixel driving circuit 100A transmits the driving signal to the light-emitting element 100C under the control of the corresponding scanning signal, and is used to drive the light-emitting element 100C to emit light and display, thereby achieving the overall display effect of the display panel 10. In particular, whether in the pixel driving circuit 100A or in the shift register 100B, a plurality of transistors are included on one side of the substrate 200. By adjusting the setting position of the transistors in the array substrate 100, the compactness of the device setting in the display panel 10 can be ensured, more space can be saved, and it is beneficial to realize the miniaturization setting of the display panel 10, or provide more setting space for the light-emitting element 100C, improve the pixel density of the display panel 10, and thus ensure a better display effect of the display panel 10.

[0048] Specifically, refer to Figures 1 to 10 As shown, the array substrate 100 includes a first type of transistor 310 and a second type of transistor 320, the first type of transistor 310 includes a first active layer 311, and the second type of transistor 320 includes a second active layer 321, wherein the first active layer 311 and the second active layer 321 are both oxide semiconductor active layers, which can be understood as the first type of transistor 310 and the second type of transistor 320 are both oxide transistors (Indium Gallium Zinc Oxide, IGZO). The advantage of the low leakage current of the oxide transistor is that when the transistor in the driving circuit 100A in the array substrate 100 can include an oxide transistor, the oxide transistor can reduce the influence of the leakage current on the gate potential of the driving transistor, thereby stabilizing the gate voltage of the driving transistor, improving the working stability of the driving transistor, and then ensuring the stability of the driving current, which is conducive to the display panel 10 of the embodiment of the present invention being able to ensure the uniformity of the luminous brightness of the light-emitting element. Similarly, when the transistor in the shift register 100B in the array substrate 100 can also include an oxide transistor, the working stability of the shift register can be guaranteed, and then the overall display effect of the display panel 10 can also be improved.

[0049] Furthermore, the transistors provided in the driving circuit 100A at the array substrate 100 in the display panel 10 are oxide transistors. Combining the advantages of oxide transistors and utilizing the characteristic of small leakage current, the potential of the gate of the driving transistor can be maintained for a long time when the display panel 10 displays a value, thereby improving the flickering phenomenon and enhancing the display effect of the display panel 10. Furthermore, if the transistors in the display panel 10 are all oxide transistors, and at least some of the oxide transistors are stacked, the space occupied by the driving circuit 100A in the display panel 10 can be saved, and more driving circuits 100A and light-emitting elements can be provided in the display panel 10, thereby improving the pixel density and ensuring that the display panel 10 can display the picture more delicately, that is, enhancing the user's visual experience of the display panel 10. Similarly, the shift registers 100B in the display panel 10 can also all be oxide transistors. In particular, when the display panel 10 is realizing low-frequency driving display, the display time of one frame of picture is longer, and the time that the potential of the driving transistor needs to be maintained is also longer. If the transistor connected to the gate of the driving transistor is a low-temperature polysilicon transistor, the leakage current of the transistor connected to the gate of the driving transistor may have a greater impact on the potential of the gate of the driving transistor due to the large off-state leakage current of the low-temperature polysilicon transistor, thereby causing obvious flicker.

[0050] Furthermore, the positions of the first active layer 311 and the second active layer 321 can be adjusted to achieve the position adjustment of the first type transistor 310 and the second type transistor 320, thereby reducing the overall occupied space of the transistors in the array substrate 100. Figures 2 to 8 As shown, the first active layer 311 and the second active layer 321 are arranged in different layers, and the second active layer 321 is located on a side of the first active layer 311 away from the substrate 200. Figure 2 , Figure 5 and Figure 7 It is shown that when the first active layer 311 and the second active layer 321 are arranged in different layers, the first type of transistor 310 and the second type of transistor 320 can have different relative arrangement positions. Therefore, compared with the arrangement of two active layers in the same layer, the structural space occupancy under the same film layer can be reduced.

[0051] Exemplary, reference Figures 2 to 4 As shown, the orthographic projection of the first active layer 311 onto the substrate 200 may not overlap with the orthographic projection of the second active layer 321 onto the substrate 200; Figures 4 to 8 As shown, the orthographic projection of the first active layer 311 onto the substrate 200 and the orthographic projection of the second active layer 321 onto the substrate 200 may overlap, reflecting the flexibility of the different layer settings of the first active layer 311 and the second active layer 321. Fig. 9 and Fig.10It is used to show that when the first type of transistor 310 and the second type of transistor 320 are arranged in different layers of the first active layer 311 and the second active layer 321, the two types of transistors have different relative arrangements. Further, the relative arrangement relationship of the first active layer 311 and the second active layer 321 in the display panel 10 provided by the embodiment of the present invention can be as follows Figure 2 , Figure 5 and Figure 7 As shown in any one or more of the above, it is reflected that the arrangement of the first type of transistor 310 and the second type of transistor 320 is diverse. The display panel 10 can be adjusted in different arrangement modes according to the requirements of the transistor arrangement positions in the pixel driving circuit 100A and the shift register 100B, thereby saving the occupied space of the transistor while ensuring the display effect of the display panel 10, which is beneficial to realize the miniaturization of the display panel 10, or provide more arrangement space for the light-emitting element 100C, improve the pixel density of the display panel 10, and thus ensure a better display effect of the display panel 10.

[0052] In summary, an embodiment of the present invention provides a display panel, wherein the array substrate of the display panel includes a first type of transistor and a second type of transistor; wherein the first active layer of the first type of transistor and the second active layer of the second type of transistor are arranged in different layers; further, the first active layer and the second active layer are both oxide semiconductor active layers, that is, the first type of transistor and the second type of transistor are oxide transistors; the display panel provided by the embodiment of the present invention can reduce the overall occupied space of the transistors in the array substrate by adjusting the positions of the active layers in the first type of transistor and the second type of transistor, and saving space is conducive to realizing a display panel with a higher pixel density, thereby improving the overall display effect of the display panel.

[0053] Continue to refer Figures 2 to 6 , Fig. 9 As shown, the first active layer 311 includes a first channel 311 a , and the second active layer 321 includes a second channel 321 a . In a direction perpendicular to the plane where the substrate 200 is located, the first channel 311 a and the second channel 321 a do not overlap.

[0054] The transistor includes an active layer, a gate and a source and drain electrode, wherein the active layer includes a channel overlapping with the gate, and a source region and a drain region doped with ions, wherein the source electrode is electrically connected to the source region, and the drain electrode is electrically connected to the drain region. Figures 2 to 6 As shown, the first type of transistor 310 includes a first active layer 311 and a first gate 312 (in a direction perpendicular to the plane where the substrate 200 is located, Figures 2 to 6In the example of the first type transistor 310, the first gate 312 is provided on both sides of the first active layer 311, wherein the region in the first active layer 311 that overlaps with the first gate 312 is the first channel 311a, that is, in the first active layer 311, the region where the orthographic projection of the first active layer 311 onto the substrate 200 overlaps with the orthographic projection of the first gate 312 onto the substrate 200 is the first channel 311a. Similarly, referring to Figures 2 to 6 As shown, the second type transistor 320 includes a second active layer 321 and a second gate 322 (in a direction perpendicular to the plane where the substrate 200 is located, Figures 2 to 6 In the figure, the second gate 322 is provided on both sides of the second active layer 321 in the second type transistor 320 as an example for explanation), wherein the area in the second active layer 321 where the second gate 322 overlaps is the second channel 321a, that is, in the second active layer 321, the area where the orthographic projection of the second active layer 321 onto the substrate 200 overlaps with the orthographic projection of the second gate 322 onto the substrate 200 is the second channel 321a.

[0055] For further reference, Figures 2 to 6 As shown, the first active layer 311 and the second active layer 321 are arranged in different layers, so the first channel 311a located on the first active layer 311 and the second channel 321a located on the second active layer 321 are also arranged in different layers. Fig. 9 As shown, the first channel 311a and the second channel 321a are arranged in different layers, which can reflect the different layer arrangement of the first type transistor 310 and the second type transistor 320. Not arranging the first active layer 311 and the second active layer 321 in the same film layer can save more space for the film layer where the first active layer 311 and the film layer where the second active layer 321 are located, and provide more arrangement space for the remaining structures and wirings in the display panel 10. The overall occupied space of the transistors in the array substrate is reduced, or it can be beneficial to realize a display panel with a higher pixel density by saving space, thereby improving the overall display effect of the display panel.

[0056] For further reference, Figures 2 to 6 , Fig. 9 As shown, along the direction perpendicular to the plane where the substrate 200 is located, the first channel 311a and the second channel 321a do not overlap, which can be understood as the orthographic projection of the first channel 311a onto the substrate 200 and the orthographic projection of the second channel 321a onto the substrate 200 do not overlap, that is, when the first active layer 311 and the second active layer 321 are arranged in different layers, the first type of transistor 310 and the second type of transistor 320 can be as shown in FIG. Figures 2 to 6 , Fig. 9 As shown, the staggered arrangement reflects a configuration method of the first type transistor 310 and the second type transistor 320 .

[0057] Fig.11 is a schematic diagram of the structure of the third first type transistor and the second type transistor provided in an embodiment of the present invention, and further reference is made to Figure 7 , Figure 8 , Fig.10 and Fig.11 As shown, the first active layer 311 includes a first channel 311 a , and the second active layer 321 includes a second channel 321 a . In a direction perpendicular to the plane where the substrate 200 is located, the first channel 311 a and the second channel 321 a overlap.

[0058] Specifically, refer to Figure 7 and Figure 8 As shown, the first type transistor 310 includes a first active layer 311 and a first gate 312, wherein the region in the first active layer 311 that overlaps with the first gate 312 is a first channel 311a, that is, in the first active layer 311, the region where the orthographic projection of the first active layer 311 onto the substrate 200 overlaps with the orthographic projection of the first gate 312 onto the substrate 200 is the first channel 311a. Similarly, referring to Figure 7 and Figure 8 As shown, the second type of transistor 320 includes a second active layer 321 and a second gate 322, wherein the region in the second active layer 321 that overlaps with the second gate 322 is a second channel 321a, that is, in the second active layer 321, the region where the orthographic projection of the second active layer 321 onto the substrate 200 overlaps with the orthographic projection of the second gate 322 onto the substrate 200 is the second channel 321a.

[0059] For further reference, Figure 7 and Figure 8 As shown, the first active layer 311 and the second active layer 321 are arranged in different layers, so the first channel 311a located on the first active layer 311 and the second channel 321a located on the second active layer 321 are also arranged in different layers. Fig.10As shown, the first channel 311a and the second channel 321a are arranged in different layers, which can reflect the different layer arrangement of the first type transistor 310 and the second type transistor 320. The first active layer 311 and the second active layer 321 are not arranged at the same film layer, but the first channel 311a and the second channel 321a are arranged in an overlapping manner, which can be understood as the first active layer 311 and the second active layer 321 are arranged in a stacked manner, and the projection of the stacked film layer structure onto the substrate 200 overlaps, so the space occupied by the first active layer 311 on the substrate 200 and the space occupied by the second active layer 321 on the substrate 200 overlap, and then the space occupied by the first active layer 311 and the second active layer 321 in the projection direction of the substrate 200 is reduced, providing more space for the arrangement of the remaining structures and wirings in the display panel 10. Reducing the overall occupied space of the transistors in the array substrate, or saving space can be conducive to realizing a display panel with a higher pixel density, thereby improving the overall display effect of the display panel.

[0060] For further reference, Figure 7 , Figure 8 , Fig.10 and Fig.11 As shown, along the direction perpendicular to the plane where the substrate 200 is located, the first channel 311a and the second channel 321a overlap, which can be understood as the orthographic projection of the first channel 311a onto the substrate 200 overlaps with the orthographic projection of the second channel 321a onto the substrate 200. Figure 7 , Figure 8 and Fig.10 2. It is shown that the first channel 311a and the second channel 321a substantially overlap in a direction perpendicular to the plane where the substrate 200 is located, that is, in a direction perpendicular to the plane where the substrate 200 is located, the first channel 311a and the second channel 321a completely overlap; in other embodiments, refer to Fig.11 As shown, the first channel 311a and the second channel 321a may also only partially overlap in the direction perpendicular to the plane where the substrate 200 is located. It should be noted that, in the direction perpendicular to the plane where the substrate 200 is located, the degree of overlap between the first channel 311a and the second channel 321a is also related to the area of ​​the first channel 311a and the second channel 321a.

[0061] When the first active layer 311 and the second active layer 321 are arranged in different layers, along the direction perpendicular to the plane where the substrate 200 is located, the first channel 311a and the second channel 321a overlap, and the first type transistor 310 and the second type transistor 320 can be as follows: Figure 7 , Figure 8 , Fig.10 and Fig.11As shown, the first type of transistor 310 and the second type of transistor 320 are stacked, which reflects the different settings of the first type of transistor 310 and the second type of transistor 320. In addition, the stacked first type of transistor 310 and the second type of transistor 320 can better reduce the occupied space of multiple transistors in the vertical direction of the array substrate 100, or reduce the occupied space in the direction perpendicular to the thickness of the display panel 10, that is, better reduce the overall occupied space of the transistors in the array substrate; it can also save space to achieve a display panel with a higher pixel density, thereby improving the overall display effect of the display panel.

[0062] Continue to refer Figures 2 to 4 , Fig. 9 As shown, the first type transistor 310 includes a first gate 312, and the second type transistor 320 includes a second gate 322; along a direction perpendicular to the plane where the substrate 200 is located, the first gate 312 and the second gate 322 do not overlap, and the first active layer 311 and the second active layer 321 do not overlap.

[0063] Among them, Figures 2 to 4 As shown, the first type transistor 310 includes a first active layer 311 and a first gate 312, and the second type transistor 322 includes a second active layer 321 and a second gate 322, wherein along a direction perpendicular to the plane where the substrate 200 is located, the first active layer 311 and the second active layer 321 do not overlap, and the first gate 312 and the second gate 322 do not overlap. This can also be understood as follows: Figure 2 As shown, the corresponding gates and active layers in the first type of transistor 310 and the second type of transistor 320 are independently set areas, and there is no overlapping part, that is, the orthographic projection of the first gate 312 onto the substrate 200 does not overlap with the orthographic projection of the second gate 322 onto the substrate 200, and the orthographic projection of the first active layer 311 onto the substrate 200 does not overlap with the orthographic projection of the second active layer 321 onto the substrate 200.

[0064] Further, such as Figure 2 As shown, in the case where the first active layer 311 and the second active layer 321 are arranged in different layers, the first active layer 311 and the second active layer 321 are arranged in a staggered manner, and the first gate 321 and the second gate 322 are also arranged in a staggered manner, which embodies a configuration method of the first type transistor 310 and the second type transistor 320. When the first type transistor 310 and the second type transistor 320 adopt this configuration method, interference between the signal transmitted in the first type transistor 310 and the signal transmitted in the second type transistor 320 can also be avoided, thereby ensuring the stability of signal transmission in the display panel 10.

[0065] Continue to refer Figure 5 and Figure 6As shown, the first type of transistor 310 includes a first gate 312, and the second type of transistor 320 includes a second gate 322; along a direction perpendicular to the plane where the substrate 200 is located, the first gate 312 and the second gate 322 have no overlap, the first active layer 311 and the second channel 321a overlap, and the second active layer 321 and the first channel 311a overlap.

[0066] Among them, Figure 5 and Figure 6 As shown, the first type transistor 310 includes a first active layer 311 and a first gate 312, and the second type transistor 322 includes a second active layer 321 and a second gate 322, wherein along a direction perpendicular to the plane where the substrate 200 is located, the first gate 312 and the second gate 322 do not overlap. This can also be understood as follows, Figure 5 As shown, the corresponding gates in the first type transistor 310 and the second type transistor 320 are independently set areas, and there is no overlapping part, that is, the orthographic projection of the first gate 312 to the substrate 200 does not overlap with the orthographic projection of the second gate 322 to the substrate 200. As for the first active layer 311 and the second active layer 321, refer to Figure 5 and Figure 6 As shown, the orthographic projection of the first active layer 311 onto the substrate 200 overlaps with the orthographic projection of the second channel 321a onto the substrate 200, and the orthographic projection of the second active layer 321 onto the substrate 200 overlaps with the orthographic projection of the first channel 311a onto the substrate 200. It can be understood that when the first active layer 311 includes the first channel 311a, its orthographic projection onto the substrate 200 overlaps with the orthographic projection of the second channel 321a onto the substrate 200. Similarly, when the second active layer 321 includes the second channel 321a, its orthographic projection onto the substrate 200 overlaps with the orthographic projection of the first channel 311a onto the substrate 200.

[0067] In other words, the first active layer 311 and the second active layer 321 are located at different film layers, but their orthographic projections onto the substrate 200 overlap, and the two are arranged in a superimposed manner, and the overlapping region of the first active layer 311 and the second active layer 321 has an overlapping region with the first gate 312 and an overlapping region with the second gate 322. Further, as Figure 5As shown, in the case where the first active layer 311 and the second active layer 321 are arranged in different layers, the first active layer 311 and the second active layer 321 are arranged to overlap in the vertical direction of the plane where the display panel 10 is located, but the first gate 321 and the second gate 322 are arranged in a staggered manner, which reflects another arrangement of the first type transistor 310 and the second type transistor 320. When the first type transistor 310 and the second type transistor 320 adopt this arrangement, the space occupied by the first active layer 311 and the second active layer 321 as a whole becomes smaller, which can better reduce the overall occupied space of the transistors in the array substrate; it can also save space to achieve a display panel with a higher pixel density, thereby improving the overall display effect of the display panel.

[0068] In general, reference Figures 2 to 11 As shown, the first type of transistor 310 and the second type of transistor 320 have various settings. In the array substrate 200, the pixel driving circuit or shift register including the first type of transistor 310 and the second type of transistor 320 can adaptively adopt one or more of the settings of the above transistors according to the extension of the metal wiring, the length of the wiring and the cross-sectional area, so as to achieve an overall space saving effect.

[0069] Continue to refer Figures 2 to 11 As shown, the array substrate 100 further includes a first insulating layer 410, a second insulating layer 420 and a source-drain metal layer 430, the first insulating layer 410 is located between the first active layer 311 and the second active layer 321, the second insulating layer 420 is located on a side of the second active layer 321 away from the first active layer 311, the source-drain metal layer 430 is located on a side of the second insulating layer 420 away from the second active layer 321; the source-drain metal layer includes a first source 431, a first drain 432, a second source 433 and a second drain 434, the first insulating layer 410 is located between the first active layer 311 and the second active layer 321, the second insulating layer 420 is located on a side of the second active layer 321 away from the first active layer 311, the source-drain metal layer 430 includes a first source 431, a first drain 432, a second source 433 and a second drain 434, the first insulating layer 410 is located between the first active layer 311 and the second active layer 321, the second insulating layer 420 is located on a side of the second active layer 321 away from the second active layer 321, the source-drain metal layer ... A source electrode 431 is connected to the second active layer 321 through a first through hole 421 set in the second insulating layer 420, a first drain electrode 432 is connected to the second active layer 321 through a second through hole 422 set in the second insulating layer 420, a second source electrode 433 is connected to the first active layer 311 through a third through hole 411 set in the second insulating layer 420 and the first insulating layer 410, and a second drain electrode 434 is connected to the first active layer 311 through a fourth through hole 412 set in the second insulating layer 420 and the first insulating layer 410.

[0070] The array substrate 100 includes a plurality of insulating layers and metal layers stacked together. Figures 2 to 11As shown, the insulating layer includes a first insulating layer 410, a second insulating layer 420 and a source-drain metal layer 430, wherein the first insulating layer 410 is located between the first active layer 311 and the second active layer 321, and the second active layer 420 is located on a side of the second active layer 321 away from the first active layer 311. Figures 1 to 11 As shown, a plurality of insulating layers are included between the first active layer 311 and the second active layer 321, so the first insulating layer 410 may include a plurality of insulating layers. For example, the first insulating layer 410 may include an interlayer insulating layer and a gate insulating layer, etc. The number of insulating layers in the first insulating layer 410 may be adaptively adjusted according to different display panels 10, and the embodiment of the present invention does not specifically limit this.

[0071] Further, the array substrate 100 includes a source-drain metal layer 430, which may correspond to the reference Figures 9 to 11 As shown, the source-drain metal layer 430 is located on a side of the second insulating layer 420 away from the second active layer 321. The source-drain metal layer 430 includes a first source 431, a first drain 432, a second source 433, and a second drain 434, wherein the first source 431 is electrically connected to the second active layer 321 of the second type transistor 320, and the first drain 432 is electrically connected to the second active layer 321 of the second type transistor 320, that is, the first source 431 and the first drain 432 are the source and drain of the second type transistor 320; similarly, the second source 433 is electrically connected to the first active layer 311 of the first type transistor 310, and the second drain 434 is electrically connected to the first active layer 311 of the first type transistor 310, that is, the second source 433 and the second drain 434 are the source and drain of the first type transistor 320.

[0072] Specifically, refer to Figures 9 to 11 As shown, the array substrate 100 includes a first through hole 421 and a second through hole 422, and the first through hole 421 and the second through hole 422 penetrate the second insulating layer 420. In the second type transistor 320, the first source 431 is connected to the second active layer 321 through the first through hole 421, and the first drain 432 is connected to the second active layer 321 through the second through hole 422, thereby realizing the electrical connection relationship between the first source 431 and the first drain 432 and the second active layer 321. Further, refer to Figures 9 to 11 As shown, the array substrate 100 further includes a third through hole 411 and a fourth through hole 412, wherein the first through hole 411 and the fourth through hole 412 penetrate the first insulating layer 410 and the second insulating layer 420. In the first type transistor 310, the second source 433 is connected to the first active layer 311 through the third through hole 411, and the second drain 434 is connected to the first active layer 311 through the fourth through hole 412, thereby realizing the electrical connection relationship between the second source 433 and the second drain 434 and the first active layer 311.

[0073] Specifically, since the first source 431, the first drain 432, the second source 433 and the second drain 434 are all located on the side of the second insulating layer 420 away from the second active layer 321, that is, the first source 431, the first drain 432, the second source 433 and the second drain 434 are all arranged in the same layer, and the first active layer 311 and the second active layer 321 are arranged in different layers, in order to ensure the electrical connection between the first source 431 and the first drain 432 and the second active layer 321, and the electrical connection between the second source 433 and the second drain 434 and the first active layer 311, the first insulating layer 410 and the second insulating layer 420 are designed with vias. The first source electrode 431 and the first drain electrode 432 include the second insulating layer 420 between them and the second active layer 321, so the first through hole 421 and the second through hole 422 only penetrate the second insulating layer 420; the second source electrode 433 and the second drain electrode 434 include the first insulating layer 410 and the second insulating layer 420 between them and the first insulating layer 311, so the third through hole 411 and the fourth through hole 412 penetrate the first insulating layer 410 and the second insulating layer 420.

[0074] Continue to refer Figures 2 to 11 As shown, the first gate 312 includes a first sub-gate 312a and a second sub-gate 312b, the first sub-gate 312a is located on the side of the first active layer 311 close to the substrate 200, and the second sub-gate 312b is located on the side of the first active layer 311 away from the substrate 200; the second gate 322 includes a third sub-gate 322a and a fourth sub-gate 322b, the third sub-gate 322a is located on the side of the second active layer 321 close to the substrate 200, and the fourth sub-gate 322b is located on the side of the second active layer 321 away from the substrate 200.

[0075] Specifically, refer to Figures 2 to 11 As shown, in the first type transistor 310, the first gate 312 may include a first sub-gate 312a and a second sub-gate 312b, and the first sub-gate 312a and the second sub-gate 312b are located on both sides of the first active layer 311, that is, the first type transistor 310 is a top-bottom double-gate structure, which ensures that the first type transistor 310 can have a good response to the control signal. Among them, the first sub-gate 312a is located on the side of the first active layer 311 close to the substrate 200, and the second sub-gate 312b is located on the side of the first active layer 311 away from the substrate 200. Similarly, refer to Figures 2 to 11 As shown, in the second type transistor 320, the second gate 322 may include a third sub-gate 322a and a fourth sub-gate 322b, and the third sub-gate 322a and the fourth sub-gate 322b are located on both sides of the second active layer 321, that is, the second type transistor 320 is also a top-bottom double-gate structure, ensuring that the second type transistor 320 can have a better response to the control signal, thereby ensuring the stable transmission of the signal in the display panel 10, thereby ensuring a better display effect of the display panel 10.

[0076] Fig.12 yes Figure 7 A schematic cross-sectional view along the section line E-E', see Figures 1 to 12 As shown, the display panel 10 also includes an insulating layer located between the first sub-gate 312a and the first active layer 311, between the first active layer 311 and the second sub-gate 312b, between the third sub-gate 322a and the second active layer 321, and between the second active layer 321 and the fourth sub-gate 322b. The first sub-gate 312a and the second sub-gate 312b are connected via a fifth through hole 451 disposed in the insulating layer between the first sub-gate 312a and the second sub-gate 312b, and the third sub-gate 322a and the fourth sub-gate 322b are connected via a sixth through hole 452 disposed in the insulating layer between the third sub-gate 322a and the fourth sub-gate 322b.

[0077] When both the first type transistor 310 and the second type transistor 320 are top-bottom dual-gate transistors, Figures 2 to 12 As shown, there is an insulating layer between the first sub-gate 312a and the first active layer 311, there is an insulating layer between the first active layer 311 and the second sub-gate 312b, there is an insulating layer between the third sub-gate 322a and the second active layer 321, and there is an insulating layer between the second active layer 321 and the fourth sub-gate 322b, which is used to ensure that the signals transmitted between the first sub-gate 312a, the second sub-gate 312b, the first active layer 311, the third sub-gate 322a, the fourth sub-gate 322b and the second active layer 321 have stability and reliability.

[0078] For further reference, Figures 2 to 12 , specific reference Figure 2 and Figure 3 As shown, the first sub-gate 312a and the second sub-gate 312b are connected through a fifth through hole 451 disposed in the insulating layer between the first sub-gate 312a and the second sub-gate 312b, and the first sub-gate 312a and the second sub-gate 312b transmit the same control signal for controlling the conduction or shutoff of the first type transistor 310. Similarly, referring to Figures 2 to 12 , specific reference Figure 7 and Fig.12 As shown, the third sub-gate 322a and the fourth sub-gate 322b are connected through a sixth through hole 452 arranged in the insulating layer between the third sub-gate 322a and the fourth sub-gate 322b, and the third sub-gate 322a and the fourth sub-gate 322b transmit the same control signal for controlling the conduction or shutdown of the second type transistor 320.

[0079] It should be noted that Figure 2 , Figure 5 and Figure 7In the embodiment, the specific arrangement positions of the fifth through hole 451 and the sixth through hole 452 can be adaptively adjusted according to different display panels 10, and the embodiment of the present invention does not specifically limit this.

[0080] Fig.13 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present invention. Figure 1 and Fig.13 As shown, the array substrate 100 includes a display area AA and a pixel driving circuit 100A located in the display area AA. The pixel driving circuit 100A includes a first type of transistor 310 and a second type of transistor 320 .

[0081] Among them, reference Figure 1 As shown, the display panel 10 includes a display area AA, in which the display area AA includes a pixel driving circuit 100A and a light-emitting element 100C electrically connected to the pixel driving circuit 100A. The pixel driving circuit 100A drives the light-emitting element 100C to perform light-emitting display, thereby realizing the display function of the display panel 10.

[0082] Furthermore, the pixel driving circuit 100A includes a plurality of transistors, that is, the pixel driving circuit 100A has various configuration modes. For example, refer to Fig.13 As shown, the pixel driving circuit 100A is illustrated as "6T1C", where "T" represents a transistor and "C" represents a capacitor. In different display panels 10, the pixel driving circuit 100A may also be "7T1C" or "8T1C", etc. The number of transistors in the pixel driving circuit 100A may be adaptively adjusted according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0083] Among them, when the pixel driving circuit 100A includes multiple transistors, the pixel driving circuit 100A may include a first type of transistor 310 and a second type of transistor 320. By adjusting the structural positions of the active layer and the gate in the first type of transistor 310 and the second type of transistor 320, the overall occupied space of the pixel driving circuit 100A in the array substrate can be reduced. Saving space is conducive to achieving a display panel 10 with a higher pixel density, thereby improving the overall display effect of the display panel 10.

[0084] Fig.14 The embodiment of the present invention provides a Fig.13 The timing of the signal of the pixel driving circuit shown in the embodiment is as follows. Figure 1 , Fig.13 and Fig.14As shown, the pixel driving circuit 100A includes a driving transistor T3, a data writing transistor T2, an initialization transistor T5, a threshold compensation transistor T4, a first light-emitting control transistor T1, a second light-emitting control transistor T6 and a storage capacitor Cst; the control end of the driving transistor T3 is electrically connected to the first node N1, the first end of the driving transistor T3 is electrically connected to the second node N2, and the second end of the driving transistor T3 is electrically connected to the third node N3; the control end of the first light-emitting control transistor T1 is electrically connected to the first light-emitting control signal line em2, the first end of the first light-emitting control transistor T1 is electrically connected to the first voltage end PVDD, and the second end of the first light-emitting control transistor T1 is electrically connected to the second node N2; the control end of the threshold compensation transistor T4 is electrically connected to the first scanning signal line sn2, the first end of the threshold compensation transistor T4 is electrically connected to the second node N2, and the threshold compensation transistor T4 is electrically connected to the third node N3. The second end of the data write transistor T2 is electrically connected to the first node N1; the first end of the storage capacitor Cst is electrically connected to the first node N1, and the second end of the storage capacitor Cst is electrically connected to the fourth node N4; the control end of the initialization transistor T5 is electrically connected to the first scanning signal line sn2, the first end of the initialization transistor T5 is electrically connected to the fourth node N4, and the second end of the initialization transistor T5 is electrically connected to the initialization voltage signal line Vini; the control end of the data write transistor T2 is electrically connected to the second scanning signal line sn1, the first end of the data write transistor T2 is electrically connected to the data line Data, and the second end of the data write transistor T2 is electrically connected to the third node N3; the control end of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control signal line em1, the first end of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second end of the second light-emitting control transistor T6 is electrically connected to the fourth node N4.

[0085] Specifically, the pixel driving circuit 100A may be configured in various ways, and thus the display panel 10 may be configured in various ways. Fig.13 and Fig.14 As shown, the pixel driving circuit 100A is illustrated by taking “6T1C” as an example. Fig.13 As shown, the pixel circuit 100 may include a driving transistor T3, a data writing transistor T2, an initialization transistor T5, a threshold compensation transistor T4, a first light emission control transistor T1, a second light emission control transistor T6 and a storage capacitor Cst. The transistors in the pixel driving circuit 100A may be oxide transistors.

[0086] Specifically, for the timing operation process of the pixel driving circuit 100A, refer to Fig.13 and Fig.14For example, the first scanning signal line sn2 connected to the control end of the initialization transistor T5 can control the on and off of the initialization transistor T5, and when the initialization transistor T5 is turned on, the reset signal in the initialization voltage signal line Vini connected to the input end of the initialization transistor T5 is written to the gate of the driving transistor T3 to reset the first node N1. The storage capacitor Cst is set to ensure the stability of the potential of the first node N1. The second scanning signal line sn1 connected to the control end of the data writing transistor T2 can control the on and off of the data writing transistor T2, and when the data writing transistor T2 is turned on, the data signal on the data line Data is written to the first electrode of the driving transistor T3. The first scanning signal line sn2 connected to the control end of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and when the threshold compensation transistor T4 is turned on, the threshold voltage compensation of the driving transistor T3 is performed. The first light-emitting control signal line em2 connected to the control end of the first light-emitting control transistor T1 and the second light-emitting control signal line em1 connected to the control end of the second light-emitting control transistor T6 can control the on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, and write the power signal transmitted by the first voltage terminal PVDD to the light-emitting element 100C when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, thereby realizing the display and light emission of the light-emitting element 100C. Specifically, refer to Fig.14 As shown, a frame time of the display panel 10 includes at least an initialization writing stage P1, a data writing stage P2 and a light emitting stage P3. In the initialization stage P1, the initialization transistor T5 is turned on under the control of the first scanning signal line sn2, and the reset signal in the initialization voltage signal line Vini is written into the first node N1 electrically connected to the gate of the driving transistor T3 to initialize the gate of the driving transistor T3. At the same time, since the threshold compensation transistor T4 is turned on, the reset signal in the initialization voltage signal line Vini is simultaneously written into the second end of the second light emitting control transistor T6, that is, the N4 node, so that the light emitting element 100c can be reset. In the data writing stage P2, the data writing transistor T2 is turned on under the control of the second scanning signal line sn1, and the threshold compensation transistor T4 is turned on under the control of the first scanning signal line sn2, so that the data signal is sequentially written into the gate of the driving transistor T3 through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4. In the light-emitting stage P3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on under the control of the first light-emitting control signal line em2 and the second light-emitting control signal line em1 respectively, so that the driving transistor T3 generates a driving current that can be transmitted to the anode of the light-emitting element 100C, thereby driving the light-emitting element 100C to emit light.

[0087] Fig.15is a schematic diagram of a film layer of a pixel driving circuit provided by an embodiment of the present invention, Fig.16 yes Fig.15 Schematic diagram of the membrane layer in the first part, Fig.17 yes Fig.15 Schematic diagram of the membrane layer in the second part, Fig.18 yes Fig.15 Schematic diagram of the membrane layer in the third part, Fig.19 yes Fig.15 Schematic diagram of the membrane layer in the fourth part, Fig. 20 yes Fig.15 The schematic diagram of the stacking of the first to fourth parts, Fig.21 yes Fig.15 Schematic diagram of the membrane layer in the fifth part, Fig. 22 yes Fig.15 Schematic diagram of the membrane layer in the sixth part, Fig.23 yes Fig.15 Schematic diagram of the membrane layer in the seventh part, Fig.24 yes Fig.15 Schematic diagram of the membrane layer in the eighth part, Fig.25 yes Fig.15 The schematic diagram of the stacking of the first to eighth parts, Fig.26 yes Fig.15 Schematic diagram of the membrane layer in the ninth part, Fig. 27 yes Fig.15 The membrane layer diagram of the tenth part is shown in Figure 1. Figures 13 to 27 As shown, the display panel 10 is formed by overlapping multiple film layers. Fig.15 As shown, Fig.15 The film structure of the pixel driving circuit 100A shown in FIG. 1 may correspond to Fig.13 The pixel driving circuit 100A provided. Specifically, refer to Figures 16 to 27 As shown, the film structure of the pixel driving circuit 100 may include insulating layers 610 to 6100 and film layers related to the pixel driving circuit 100A located on the insulating layers, which are sequentially arranged from the substrate 200 to the light-emitting side of the display panel 10 . Figures 15 to 27 And combined with Figures 2 to 12As shown, the insulating layer 610 is an insulating layer on the side of the first active layer 311 close to the substrate 200, and the first sub-gate 312a can be set on the insulating layer 610; the first active layer 311 can be set on the side of the insulating layer 620 away from the substrate 200; the insulating layer 630 is set between the first active layer 311 and the second sub-gate 312b, and the second sub-gate 312b is set on the side of the insulating layer 640 away from the substrate 200; the third sub-gate 322a is set on the side of the insulating layer 620 away from the substrate 200, the insulating layer 660 is set between the third sub-gate 322a and the second active layer 321, the second active layer 321 is located on the side of the insulating layer 670 away from the substrate 200, the fourth sub-gate 322b is set on the side of the insulating layer 680 away from the substrate 200, and the side of the fourth sub-gate 322b away from the substrate 200 also includes insulating layers 690 and 6100, wherein the source and drain metal layer 430 is set on the side of the insulating layer 6100 away from the substrate 200. The film layer structure of the specific pixel driving circuit 100A can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and any of the above film layers can include at least one sublayer, which is not specifically limited in the embodiment of the present invention.

[0088] refer to Figures 1 to 27 As shown, the driving transistor T3, the first light emission control transistor T1 and the second light emission control transistor T2 are first type transistors 310, and the data writing transistor T2, the threshold compensation transistor T4 and the initialization transistor T5 are second type transistors.

[0089] The pixel driving circuit 100A of the display panel 10 includes a first type of transistor 310 and a second type of transistor 320 , which are used to ensure that the pixel driving circuit 100A occupies a smaller space in the array substrate 100 and improve the overall display effect of the display panel 10 .

[0090] The driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 in the pixel driving circuit 100A may be a first type transistor 310, and the active layer corresponding to the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 is a first active layer 311, which may be arranged on a side of the insulating layer 620 away from the substrate 200, and the corresponding active layer may refer to Fig.17As shown. The data writing transistor T2, the threshold compensation transistor T4 and the initialization transistor T5 in the pixel driving circuit 100A can be the second type of transistors, and the active layer corresponding to the data writing transistor T2, the threshold compensation transistor T4 and the initialization transistor T5 is the second active layer 321, which can be arranged on the side of the insulating layer 670 away from the substrate 200. While satisfying that the transistors in the pixel driving circuit 100A are all oxide transistors, adjusting the different layers of the active layers corresponding to different transistors in the pixel driving circuit 100A can ensure the display stability of the display panel 10, and can also compress the size of the pixel driving circuit 100A, which can save more space; further, it can also increase the pixel density and improve the display effect of the display panel 10.

[0091] Continue to refer Figures 15 to 27 As shown, the pixel driving circuit 100A includes a first pixel driving circuit 100A1 and a second pixel driving circuit 100A2, and the first pixel circuit 100A1 and the second pixel circuit 100A2 are arranged in an axisymmetric manner.

[0092] Specifically, the pixel driving circuit 100A includes a first pixel driving circuit 100A1 and a second pixel driving circuit 100A2. Figures 15 to 27 As shown, the first pixel circuit 100A1 and the second pixel circuit 100A2 are arranged axially symmetrically, and thus the transistors in the first pixel circuit 100A1 are arranged symmetrically with the transistors in the second pixel circuit 100A2. By arranging the first pixel driving circuit 100A1 and the second pixel driving circuit 100A2, the arrangement space of the transistors provided by the array substrate 100 in the display panel 10 can be better utilized, and the regularity of the display panel 10 can also be improved.

[0093] Fig.28 yes Fig.15 A schematic cross-sectional view along the section line F-F', see Figures 1 to 28As shown, along the direction perpendicular to the plane where the substrate 200 is located, the channel of the first light-emitting control transistor T1 and the channel of the threshold compensation transistor T4 overlap; the array substrate 100 further includes a first insulating layer 410, a second insulating layer 420 and a source-drain metal layer 430, the first insulating layer 410 is located between the first active layer 311 and the second active layer 321, the second insulating layer 420 is located on the side of the second active layer 321 away from the first active layer 311, and the source-drain metal layer 430 is located on the side of the second insulating layer 420 away from the second active layer 321; the source-drain metal layer 430 includes a source of the first light-emitting control transistor T1 and a source wiring 440 of the threshold compensation transistor T4, the source of the first light-emitting control transistor T1 is connected to the source wiring 440 by a first insulating layer 410 disposed on the second active layer 311. The seventh through hole 510 of the second insulating layer 420 and the first insulating layer 410 is connected to the active layer of the source region of the first light-emitting control transistor T1, the active layer of the drain region of the first light-emitting control transistor T1 is connected to the active layer of the drain region of the threshold compensation transistor T4 through the eighth through hole 520 set in the first insulating layer 410, the first end 441 of the source wiring 440 of the threshold compensation transistor T4 (the source of the threshold compensation transistor T4) is connected to the second active layer 312 through the ninth through hole 530 set in the second insulating layer 420, and the second end 442 of the source wiring 440 of the threshold compensation transistor T4 is connected to the gate of the driving transistor T3 through the tenth through hole 540 set in the second insulating layer 420 and the first insulating layer 410.

[0094] Specifically, refer to Fig.15 , Fig.17 and Fig.28 As shown, the first light emission control transistor T1 is a first type transistor 310, and the active layer corresponding to the first light emission control transistor T1 (i.e., the first active layer 311 in the first type transistor 310) and the channel corresponding to the active layer of the first light emission control transistor T1 (i.e., the first channel 311a in the first type transistor 310) can be shown in the film layer diagram. Fig.15 , Fig.23 and Fig.28 As shown, the threshold compensation transistor T4 is a second type of transistor 320, and the active layer corresponding to the threshold compensation transistor T4 (i.e., the second active layer 321 in the second type of transistor 320) can be shown in the film layer diagram, and the channel corresponding to the active layer of the threshold compensation transistor T4 (i.e., the second channel 321a in the second type of transistor 320) is shown. Fig.15 and Fig.28As shown, the channel of the first light emission control transistor T1 and the channel of the threshold compensation transistor T4 overlap, that is, the orthographic projection of the channel of the first light emission control transistor T1 onto the substrate 200 and the orthographic projection of the channel of the threshold compensation transistor T4 onto the substrate 200 have an overlapping area. It can also be understood that the first light emission control transistor T1 and the threshold compensation transistor T4 are arranged to overlap up and down along the thickness direction of the substrate 200.

[0095] For further reference, Figures 15 to 28 As shown, the source-drain metal layer 430 is located on the side of the insulating layer 6100 away from the substrate 200, and the source-drain metal layer 430 includes the source wiring and the drain wiring of the transistor in the pixel driving circuit 100A. Figures 15 to 28 As shown, specific reference Fig.26 and Fig.28 As shown, the source of the first light emission control transistor T1 is connected to the source region of the first light emission control transistor T1 (reference Fig.28 The active layer connection of 311b) is used to electrically connect the first light emission control transistor T1 to the first voltage terminal PVDD, and transmit the positive power supply signal to the pixel driving circuit 100A through the first light emission control transistor T1. Figures 15 to 28 As shown, specific reference Fig. 22 and Fig.28 As shown, the drain region of the first light emitting control transistor T1 (reference Fig.28 The active layer of the transistor 311c shown in FIG. 311c is connected to the drain region of the threshold compensation transistor T4 (reference Fig.28 Active layer connections 321c) are shown.

[0096] For further reference, Figures 15 to 28 As shown, specific reference Fig.26 and Fig.28 As shown, the first end of the source of the threshold compensation transistor T4 is connected to the second active layer 312 through the ninth through hole 530, that is, the source of the threshold compensation transistor T4 is electrically connected to the active layer corresponding to the threshold compensation transistor T4 through the ninth through hole 530, specifically to the source region of the threshold compensation transistor T4 (reference Fig.28 321b) is electrically connected as shown. Further, reference Figures 15 to 28 As shown, specific reference Fig.15 and Fig.26 As shown, the second end 442 of the source of the threshold compensation transistor T4 is connected to the gate of the driving transistor T3 (reference Fig.28 312d) connection shown, reference Fig.28 The channel 311 a of the middle driving transistor T3 is electrically connected to the second terminal 442 of the source of the threshold compensation transistor T4 .

[0097] By describing the positions of the active layer, source and drain in the first light emission control transistor T1 and the threshold compensation transistor T4, the different-layer arrangement relationship of the first light emission control transistor T1 and the threshold compensation transistor T4 is reflected, or the relative position relationship of the first light emission control transistor T1 and the threshold compensation transistor T4 can be referred to. Figure 7 and Figure 8 Further, the relative position relationship between the first light emitting control transistor T1 and the initialization transistor T5 can be referred to Figure 5 and Figure 6 Further, the relative position relationship between the first light emission control transistor T1 and the second light emission control transistor T2 can be referred to Figures 2 to 4 As shown. Thus, in the pixel driving circuit 100A, the relative arrangement of the first type of transistor 310 and the second type of transistor 320 is diverse. By combining different similar arrangement methods, the occupied space of the pixel driving circuit 100A in the array substrate 100 can be further reduced. By saving space, it is conducive to realizing a display panel 10 with a higher pixel density, thereby improving the overall display effect of the display panel 10.

[0098] Continue to refer Fig.15 , Fig.16 , Figures 19 to 21 , Fig.24 and Fig.25 As shown, on the plane where the substrate 200 is located, the first light-emitting control signal line em2 and the first scanning signal line sn2 extend in the same direction and at least partially overlap; and in the direction perpendicular to the substrate 200, the channel of the first light-emitting control transistor T1 and the channel of the threshold compensation transistor T4 are overlapped.

[0099] Specifically, the first light emitting control signal line em2 electrically connected to the control end of the first light emitting control transistor T1 and the first scanning signal line sn2 electrically connected to the control end of the threshold compensation transistor T4 extend in the same direction. Fig.15 , Fig.16 , Figures 19 to 21 , Fig.24 and Fig.25 As shown, the first light-emitting control signal line em2 and the first scanning signal line sn2 both extend in the horizontal direction of the figure. Further, the first light-emitting control signal line em2 provides a control signal for the first light-emitting control transistor T1, and the first light-emitting control signal line em2 overlaps with the active layer of the first light-emitting control transistor T1 in the channel of the first light-emitting control transistor T1. The first scanning signal line sn2 provides a control signal for the threshold compensation transistor T4, and the first scanning signal line sn2 overlaps with the active layer of the threshold compensation transistor T4 in the channel of the threshold compensation transistor T4.

[0100] Further, the first light emission control transistor T1 is a first type transistor 310, and the threshold compensation transistor T4 is a second type transistor 320. In a direction perpendicular to the substrate 200, the channel of the first light emission control transistor T1 and the channel of the threshold compensation transistor T4 are overlapped, thereby reflecting the stacking arrangement of the first light emission control transistor T1 and the threshold compensation transistor T4. Specifically, the relative position relationship between the first light emission control transistor T1 and the threshold compensation transistor T4 can be referred to. Figure 7 and Figure 8 shown.

[0101] Continue to refer Fig.15 , Fig.16 , Figures 19 to 21 , Fig.24 and Fig.25 As shown, on the plane where the substrate 200 is located, the second light emitting control signal line em1 and the second scanning signal line sn1 extend in the same direction and at least partially overlap.

[0102] Specifically, the second light emitting control signal line em1 electrically connected to the control end of the second light emitting control transistor T6 and the second scanning signal line sn1 electrically connected to the control end of the data writing transistor T2 extend in the same direction and have a partial overlap area. Fig.15 , Fig.16 , Figures 19 to 21 , Fig.24 and Fig.25 As shown, the second light-emitting control signal line em1 and the second scanning signal line sn1 both extend in the horizontal direction of the figure. Further, the second light-emitting control signal line em1 provides a control signal for the second light-emitting control transistor T6, and the second light-emitting control signal line em1 overlaps with the active layer of the second light-emitting control transistor T6, which is the channel of the second light-emitting control transistor T6. The second scanning signal line sn1 provides a control signal for the data writing transistor T2, and the second scanning signal line sn1 overlaps with the active layer of the data writing transistor T2, which is the channel of the data writing transistor T2.

[0103] Further, the second light-emitting control transistor T6 is a first-type transistor 310, and the data-writing transistor T2 is a second-type transistor 320. The second light-emitting control signal line em1 for providing a control signal to the second light-emitting control transistor T6 and the second scanning signal line sn1 for providing a control signal to the data-writing transistor T2 have the same extension direction, but the channel of the second light-emitting control transistor T6 and the channel of the data-writing transistor T2 do not overlap, thereby reflecting a setting method of the second light-emitting control transistor T2 and the data-writing transistor T2. Specifically, the relative position relationship between the second light-emitting control transistor T2 and the data-writing transistor T2 can be referred to. Figure 4 and Figure 5 shown.

[0104] Fig.29 is a partial structural diagram of a shift register provided by an embodiment of the present invention, Fig.30 yes Fig.29 A schematic cross-sectional view along the section line G-G', Fig.31 yes Fig.29 A schematic cross-sectional view of the section line H-H', see Figure 1 , Figure 29 to Figure 31 As shown, the array substrate 100 also includes a non-display area NA, which includes a plurality of shift registers 100B arranged in cascade, and the shift register 100B includes a first transistor 100B1 and a second transistor 100B2, wherein the first transistor 100B1 is a first type transistor 310, and the second transistor 100B2 is a second type transistor 320.

[0105] Among them, reference Figure 1 As shown, the display panel 10 includes a display area AA and a non-display area NA, and the display area AA includes a light-emitting element 100C and a pixel driving circuit 100A connected to the light-emitting element 100C, etc., for realizing the display function of the display panel 10. The non-display area NA includes a plurality of shift registers 100B, and the shift registers 100B are electrically connected to the pixel driving circuit 100A of the display area AA, and are used to provide relevant signals to the pixel driving circuit 100A, such as providing a scanning signal to the pixel driving circuit 100A, or providing a light-emitting control signal to the pixel driving circuit 100A. Among them, the non-display area NA surrounds at least part of the display area AA, and the embodiment of the present invention does not make specific restrictions based on the specific positions of the display area AA and the non-display area NA. For the plurality of cascaded shift registers 100B set in the non-display area NA, they can be set on one side of the display area AA, or on both sides of the display area AA. Based on the specific setting position and setting number of the shift registers 100B, they can be adaptively adjusted according to different display panels 10, and the embodiment of the present invention does not make specific restrictions on this.

[0106] Furthermore, the shift register 100B of the display panel 10 includes multiple transistors, and the shift register 100B can be "12T3C" or "8T2C", etc. The setting number of transistors and capacitors in the shift register 100B can be adjusted according to the difference in the output signal of the shift register 100B, or adaptively adjusted according to the specific needs of the display panel 10. The embodiment of the present invention does not make specific limitations on this.

[0107] Specifically, the shift register 100B includes a first transistor 100B1 and a second transistor 100B2, wherein the first transistor 100B1 is a first type transistor 310, and the second transistor 100B2 is a second type transistor 320. The transistors in the shift register 100B are oxide transistors, which can effectively avoid leakage of the shift register 100B and improve the working stability of the shift register 100B. The transistors in the shift register 100B include a first type transistor 310 and a second type transistor 320. In combination with the setting positions of the first type transistor 310 and the second type transistor 320, it is used to ensure that the space occupied by the shift register 100B in the array substrate 100 is relatively small, which is beneficial to reducing the space occupied by the non-display area NA in the display panel 10, realizing a narrow frame design, and improving the proportion of the display area AA, thereby improving the overall display effect of the display panel 10.

[0108] Continue to refer Figure 1 , Figure 29 to Figure 31 As shown, along a direction perpendicular to the plane where the substrate 200 is located, the first transistor 100B1 and the second transistor 100B2 overlap.

[0109] For further reference, Figure 29 to Figure 31 As shown, the first transistor 100B1 is a first type transistor 310, and the second transistor 100B2 is a second type transistor 320, wherein the first active layer 311 of the first type transistor 310 and the second active layer 321 of the second transistor 320 are arranged in different layers, and the active layer of the first transistor 100B1 and the active layer of the second transistor 100B2 are also arranged in different layers.

[0110] For further reference, Fig.29 and Fig.31 As shown, the orthographic projection of the first transistor 100B1 onto the substrate 200 overlaps with the orthographic projection of the second transistor 100B2 onto the substrate 200, that is, the first transistor 100B1 and the second transistor 100B2 are stacked, which can further reduce the space occupied by the transistors in the shift register 100B, thereby reducing the space occupied by the non-display area NA in the display panel 10, increasing the space occupied by the display area AA, and thereby improving the overall display effect of the display panel 10.

[0111] For details, please refer to Figure 1 , Figure 29 to Figure 31 As shown, the first transistor 100B1 includes a third gate 100B12 and a third active layer 100B11, and the second transistor 100B2 includes a fourth gate 100B22 and a fourth active layer 100B21; along a direction perpendicular to the plane where the substrate 22 is located, the third gate 100B12 and the fourth gate 100B22 do not overlap, and the third active layer 100B11 and the fourth active layer 100B21 overlap.

[0112] Among them, reference Figure 29 to Figure 31 As shown, the first transistor 100B1 includes a third gate 100B12 and a third active layer 100B11. The figure takes the first transistor 100B1 including two third gates 100B12 located on both sides of the third active layer 100B11, that is, the first transistor 100B1 is a top-bottom double-gate transistor for example. The second transistor 100B2 includes a fourth gate 100B22 and a fourth active layer 100B21. The figure takes the second transistor 100B2 including two fourth gates 100B22 located on both sides of the fourth active layer 100B21, that is, the second transistor 100B2 is a top-bottom double-gate transistor for example. It should be noted that Fig.29 A partial schematic diagram of a film layer of the shift register 100B is shown. The specific film layer structure of the shift register 100B can be adaptively adjusted according to different display panels 10 , and the embodiment of the present invention does not specifically limit this.

[0113] Specifically, refer to Figure 29 to Figure 31 As shown, along the direction perpendicular to the plane where the substrate 200 is located, the third gate 100B12 and the fourth gate 100B22 do not overlap. This can also be understood as follows: Fig.31 As shown, the corresponding gates in the first transistor 100B1 and the second transistor 100B2 are independently set areas without any overlapping parts, that is, the orthographic projection of the third gate 100B12 onto the substrate 200 does not overlap with the orthographic projection of the fourth gate 100B22 onto the substrate 200.

[0114] The orthographic projections of the third active layer 100B11 and the fourth active layer 100B21 arranged in different layers onto the substrate 200 overlap. In other words, the third active layer 100B11 and the fourth active layer 100B21 are located at different film layers, but their orthographic projections onto the substrate 200 overlap. The two are arranged to overlap, and the overlapping region of the third active layer 100B11 and the fourth active layer 100B21 overlaps with the third gate 100B12 and with the fourth gate 100B22. Further, as Fig.30 As shown, referring to region k1 and region K3, when the third active layer 100B11 and the fourth active layer 100B21 are arranged in different layers, the third active layer 100B11 and the fourth active layer 100B21 are arranged overlapping in the thickness direction of the display panel 10, but the third gate 100B12 and the fourth gate 100B22 are arranged in a staggered manner, which reflects a setting method of the first transistor 100B1 and the second transistor 100B2 in the shift register 100B, which can better reduce the overall occupied space of the transistors in the array substrate, thereby improving the overall display effect of the display panel.

[0115] Continue to refer Figure 1 , Figure 29 to Figure 31 As shown, the first transistor 100B1 includes a third gate 100B12 and a third active layer 100B11, and the second transistor 100B2 includes a fourth gate 100B22 and a fourth active layer 100B21; along a direction perpendicular to the plane where the substrate 200 is located, the third gate 100B12 and the fourth gate 100B22 overlap, and the third active layer 100B11 and the fourth active layer 100B21 overlap.

[0116] Specifically, refer to Figure 29 to Figure 31 As shown, along the direction perpendicular to the plane where the substrate 200 is located, the third gate 100B12 and the fourth gate 100B22 overlap. This can also be understood as follows: Fig.31 As shown, the corresponding gates of the first transistor 100B1 and the second transistor 100B2 are arranged to overlap, that is, the orthographic projection of the third gate 100B12 onto the substrate 200 overlaps with the orthographic projection of the fourth gate 100B22 onto the substrate 200 .

[0117] The orthographic projections of the third active layer 100B11 and the fourth active layer 100B21 arranged in different layers onto the substrate 200 also overlap. In other words, the third active layer 100B11 and the fourth active layer 100B21 are located at different film layers, but their orthographic projections onto the substrate 200 overlap. The two are arranged to overlap, and the overlapping region of the third active layer 100B11 and the fourth active layer 100B21 overlaps with the third gate 100B12 and with the fourth gate 100B22. Further, as Fig.30 As shown, with reference to area k1 and area K2, when the third active layer 100B11 and the fourth active layer 100B21 are arranged in different layers, the third active layer 100B11 and the fourth active layer 100B21 are arranged overlapping in the thickness direction of the display panel 10, and the third gate 100B12 and the fourth gate 100B22 are also arranged overlapping, which reflects another arrangement method of the first transistor 100B1 and the second transistor 100B2 in the shift register 100B, which can better reduce the overall occupied space of the transistors in the array substrate, thereby improving the overall display effect of the display panel.

[0118] Continue to refer Figure 1 As shown, the display panel 10 further includes a light emitting element 100C, which is electrically connected to the pixel driving circuit 100A; a plurality of light emitting elements 100C form a pixel unit, and a pixel density of the pixel unit is greater than or equal to 1000 pixels per inch.

[0119] Among them, reference Figure 1As shown, the display panel 10C includes a plurality of light-emitting elements 100C, which emit light and display under the drive of the pixel driving circuit 100A, thereby realizing the display function of the display panel 10. Among them, the light-emitting elements 100C may include light-emitting elements 100C of different colors, such as red light-emitting elements, blue light-emitting elements, and green light-emitting elements, etc., thereby realizing the color display effect of the display panel 10. Further, the plurality of light-emitting elements 100C form a pixel unit, and the pixel unit can be understood as the minimum repeating unit of the plurality of light-emitting elements 100C in the display panel 10.

[0120] The transistors in the array substrate 100 in the display panel 10 provided in the embodiment of the present invention include a first type of transistor 310 and a second type of transistor 320, and both the first type of transistor 310 and the second type of transistor 320 are oxide transistors, thereby ensuring that the pixel driving circuit 100A or the shift register 100B in the display panel 10 have the advantages of oxide transistors. Further, the active layers of the first type of transistor 310 and the second type of transistor 320 are arranged in different layers, that is, the array substrate 100 can save the space occupied by the transistor in the array substrate 100 by adjusting the relative positions of the first type of transistor 310 and the second type of transistor 320, and can improve the pixel density of the display panel 10, thereby ensuring a better display effect of the display panel 10. Further, a higher pixel density, that is, a higher resolution, can be used in an AR display device and a VR display device to improve the display effect.

[0121] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.32 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.32 As shown, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided in the embodiment of the present invention has the corresponding beneficial effects in the above embodiments, which will not be repeated here. The display device 1 can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch, an AR display device, a VR display device, etc.) and a vehicle-mounted display device.

[0122] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes an array substrate, and the array substrate includes: substrate; The array substrate includes a first type of transistor and a second type of transistor, the first type of transistor includes a first active layer, the second type of transistor includes a second active layer, and the second active layer is located on a side of the first active layer away from the substrate; Wherein, the first active layer and the second active layer are both oxide semiconductor active layers.

2. The display panel according to claim 1, characterized in that: The first active layer includes a first channel, and the second active layer includes a second channel. In a direction perpendicular to a plane where the substrate is located, the first channel and the second channel do not overlap.

3. The display panel according to claim 1, characterized in that: The first active layer includes a first channel, and the second active layer includes a second channel. The first channel and the second channel overlap along a direction perpendicular to a plane where the substrate is located.

4. The display panel according to claim 2, characterized in that: The first type of transistor includes a first gate, and the second type of transistor includes a second gate; Along a direction perpendicular to a plane where the substrate is located, the first gate and the second gate do not overlap, and the first active layer and the second active layer do not overlap.

5. The display panel according to claim 2, characterized in that: The first type of transistor includes a first gate, and the second type of transistor includes a second gate; Along a direction perpendicular to a plane where the substrate is located, the first gate and the second gate do not overlap, the first active layer and the second channel overlap, and the second active layer and the first channel overlap.

6. The display panel according to claim 1, characterized in that: The array substrate further comprises a first insulating layer, a second insulating layer and a source-drain metal layer, wherein the first insulating layer is located between the first active layer and the second active layer, the second insulating layer is located on a side of the second active layer away from the first active layer, and the source-drain metal layer is located on a side of the second insulating layer away from the second active layer; The source-drain metal layer includes a first source, a first drain, a second source and a second drain, the first source is connected to the second active layer through a first through hole set in the second insulating layer, the first drain is connected to the second active layer through a second through hole set in the second insulating layer, the second source is connected to the first active layer through a third through hole set in the second insulating layer and the first insulating layer, and the second drain is connected to the first active layer through a fourth through hole set in the second insulating layer and the first insulating layer.

7. The display panel according to claim 4 or 5, characterized in that: The first gate includes a first sub-gate and a second sub-gate, the first sub-gate is located on a side of the first active layer close to the substrate, and the second sub-gate is located on a side of the first active layer away from the substrate; The second gate includes a third sub-gate and a fourth sub-gate, the third sub-gate is located on a side of the second active layer close to the substrate, and the fourth sub-gate is located on a side of the second active layer away from the substrate.

8. The display panel according to claim 7, characterized in that: It also includes an insulating layer located between the first sub-gate and the first active layer, between the first active layer and the second sub-gate, between the third sub-gate and the second active layer, and between the second active layer and the fourth sub-gate, the first sub-gate and the second sub-gate are connected via a fifth through hole arranged in the insulating layer between the first sub-gate and the second sub-gate, and the third sub-gate and the fourth sub-gate are connected via a sixth through hole arranged in the insulating layer between the third sub-gate and the fourth sub-gate.

9. The display panel according to claim 1, characterized in that: The array substrate includes a display area and a pixel driving circuit located in the display area, wherein the pixel driving circuit includes the first type of transistors and the second type of transistors.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit includes a driving transistor, a data writing transistor, an initialization transistor, a threshold compensation transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor; The control terminal of the driving transistor is electrically connected to the first node, the first terminal of the driving transistor is electrically connected to the second node, and the second terminal of the driving transistor is electrically connected to the third node; The control end of the first light emission control transistor is electrically connected to the first light emission control signal line, the first end of the first light emission control transistor is electrically connected to the first voltage end, and the second end of the first light emission control transistor is electrically connected to the second node; The control end of the threshold compensation transistor is electrically connected to the first scan signal line, the first end of the threshold compensation transistor is electrically connected to the second node, and the second end of the threshold compensation transistor is electrically connected to the first node; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the fourth node; The control end of the initialization transistor is electrically connected to the first scan signal line, the first end of the initialization transistor is electrically connected to the fourth node, and the second end of the initialization transistor is electrically connected to the initialization voltage signal line; The control end of the data writing transistor is electrically connected to the second scanning signal line, the first end of the data writing transistor is electrically connected to the data line, and the second end of the data writing transistor is electrically connected to the third node; The control end of the second light emission control transistor is electrically connected to the second light emission control signal line, the first end of the second light emission control transistor is electrically connected to the third node, and the second end of the second light emission control transistor is electrically connected to the fourth node.

11. The display panel according to claim 10, characterized in that: The driving transistor, the first light emission control transistor, and the second light emission control transistor are transistors of the first type, and the data writing transistor, the threshold compensation transistor, and the initialization transistor are transistors of the second type.

12. The display panel according to claim 11, characterized in that: Along a direction perpendicular to the plane where the substrate is located, a channel of the first light emission control transistor overlaps with a channel of the threshold compensation transistor; The array substrate further comprises a first insulating layer, a second insulating layer and a source-drain metal layer, wherein the first insulating layer is located between the first active layer and the second active layer, the second insulating layer is located on a side of the second active layer away from the first active layer, and the source-drain metal layer is located on a side of the second insulating layer away from the second active layer; The source-drain metal layer includes a first light-emitting control transistor source and a threshold compensation transistor source wiring, the first light-emitting control transistor source is connected to the active layer of the first light-emitting control transistor source region through a seventh through hole provided in the second insulating layer and the first insulating layer, the active layer of the first light-emitting control transistor drain region is connected to the active layer of the threshold compensation transistor drain region through an eighth through hole provided in the first insulating layer, the first end of the threshold compensation transistor source wiring is connected to the second active layer through a ninth through hole provided in the second insulating layer, and the second end of the threshold compensation transistor source wiring is connected to the gate of the driving transistor through a tenth through hole provided in the second insulating layer and the first insulating layer.

13. The display panel according to claim 11, characterized in that: On the plane where the substrate is located, the first light-emitting control signal line and the first scanning signal line extend in the same direction and at least partially overlap; and in a direction perpendicular to the substrate, the channel of the first light-emitting control transistor and the channel of the threshold compensation transistor are overlapped.

14. The display panel according to claim 11, characterized in that: On a plane where the substrate is located, the second light emitting control signal line and the second scanning signal line extend in the same direction and at least partially overlap.

15. The display panel according to claim 9, characterized in that: The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit, and the first pixel circuit and the second pixel circuit are arranged in an axisymmetric manner.

16. The display panel according to claim 1, characterized in that: The array substrate further includes a non-display area, the non-display area includes a plurality of shift registers arranged in cascade, the shift register includes a first transistor and a second transistor, wherein the first transistor is the first type of transistor, and the second transistor is the second type of transistor.

17. The display panel according to claim 16, characterized in that: Along a direction perpendicular to a plane where the substrate is located, the first transistor and the second transistor overlap.

18. The display panel according to claim 17, characterized in that: The first transistor includes a third gate and a third active layer, and the second transistor includes a fourth gate and a fourth active layer; Along a direction perpendicular to the plane where the substrate is located, the third gate and the fourth gate do not overlap, and the third active layer and the fourth active layer overlap.

19. The display panel according to claim 17, characterized in that: The first transistor includes a third gate and a third active layer, and the second transistor includes a fourth gate and a fourth active layer; Along a direction perpendicular to the plane where the substrate is located, the third gate overlaps with the fourth gate, and the third active layer overlaps with the fourth active layer.

20. The display panel according to claim 9, characterized in that: Also includes a light emitting element, the light emitting element is electrically connected to the pixel driving circuit; A plurality of the light emitting elements form a pixel unit, and a pixel density of the pixel unit is greater than or equal to 1000 pixels per inch.

21. A display device, characterized in that: A display panel comprising any one of claims 1 to 20.

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